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[PATCH 2/6] hw/pci-bridge/cxl_upstream: Provide x-speed and x-width properties.

Jonathan Cameron via posted 6 patches 2 months, 1 week ago
[PATCH 2/6] hw/pci-bridge/cxl_upstream: Provide x-speed and x-width properties.
Posted by Jonathan Cameron via 2 months, 1 week ago 
Copied from gen_pcie_root_port.c
Drop the previous code that ensured a valid value in s->width, s->speed
as now a default is provided so this will always be set.

Note this changes the default settings but it is unlikely to have a negative
effect on software as will only affect ports with now downstream device.
All other ports will use the settings from that device.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 hw/pci-bridge/cxl_downstream.c | 23 ++++++++++-------------
 1 file changed, 10 insertions(+), 13 deletions(-)

diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c
index 4b42984360..c347ac06f3 100644
--- a/hw/pci-bridge/cxl_downstream.c
+++ b/hw/pci-bridge/cxl_downstream.c
@@ -13,6 +13,8 @@
 #include "hw/pci/msi.h"
 #include "hw/pci/pcie.h"
 #include "hw/pci/pcie_port.h"
+#include "hw/qdev-properties.h"
+#include "hw/qdev-properties-system.h"
 #include "hw/cxl/cxl.h"
 #include "qapi/error.h"
 
@@ -210,24 +212,20 @@ static void cxl_dsp_exitfn(PCIDevice *d)
     pci_bridge_exitfn(d);
 }
 
-static void cxl_dsp_instance_post_init(Object *obj)
-{
-    PCIESlot *s = PCIE_SLOT(obj);
-
-    if (!s->speed) {
-        s->speed = QEMU_PCI_EXP_LNK_2_5GT;
-    }
-
-    if (!s->width) {
-        s->width = QEMU_PCI_EXP_LNK_X1;
-    }
-}
+static Property cxl_dsp_props[] = {
+    DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot,
+                                speed, PCIE_LINK_SPEED_64),
+    DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
+                                width, PCIE_LINK_WIDTH_16),
+    DEFINE_PROP_END_OF_LIST()
+};
 
 static void cxl_dsp_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
     PCIDeviceClass *k = PCI_DEVICE_CLASS(oc);
 
+    device_class_set_props(dc, cxl_dsp_props);
     k->config_write = cxl_dsp_config_write;
     k->realize = cxl_dsp_realize;
     k->exit = cxl_dsp_exitfn;
@@ -243,7 +241,6 @@ static const TypeInfo cxl_dsp_info = {
     .name = TYPE_CXL_DSP,
     .instance_size = sizeof(CXLDownstreamPort),
     .parent = TYPE_PCIE_SLOT,
-    .instance_post_init = cxl_dsp_instance_post_init,
     .class_init = cxl_dsp_class_init,
     .interfaces = (InterfaceInfo[]) {
         { INTERFACE_PCIE_DEVICE },
-- 
2.43.0
Re: [PATCH 2/6] hw/pci-bridge/cxl_upstream: Provide x-speed and x-width properties.
Posted by Fan Ni 3 weeks, 4 days ago 
On Mon, Sep 16, 2024 at 06:35:14PM +0100, Jonathan Cameron wrote:
> Copied from gen_pcie_root_port.c
> Drop the previous code that ensured a valid value in s->width, s->speed
> as now a default is provided so this will always be set.
> 
> Note this changes the default settings but it is unlikely to have a negative
> effect on software as will only affect ports with now downstream device.
> All other ports will use the settings from that device.
> 
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
>  hw/pci-bridge/cxl_downstream.c | 23 ++++++++++-------------
>  1 file changed, 10 insertions(+), 13 deletions(-)
> 
> diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c
> index 4b42984360..c347ac06f3 100644
> --- a/hw/pci-bridge/cxl_downstream.c
> +++ b/hw/pci-bridge/cxl_downstream.c
> @@ -13,6 +13,8 @@
>  #include "hw/pci/msi.h"
>  #include "hw/pci/pcie.h"
>  #include "hw/pci/pcie_port.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/qdev-properties-system.h"
>  #include "hw/cxl/cxl.h"
>  #include "qapi/error.h"
>  
> @@ -210,24 +212,20 @@ static void cxl_dsp_exitfn(PCIDevice *d)
>      pci_bridge_exitfn(d);
>  }
>  
> -static void cxl_dsp_instance_post_init(Object *obj)
> -{
> -    PCIESlot *s = PCIE_SLOT(obj);
> -
> -    if (!s->speed) {
> -        s->speed = QEMU_PCI_EXP_LNK_2_5GT;
> -    }
> -
> -    if (!s->width) {
> -        s->width = QEMU_PCI_EXP_LNK_X1;
> -    }
> -}
> +static Property cxl_dsp_props[] = {
> +    DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot,
> +                                speed, PCIE_LINK_SPEED_64),
> +    DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
> +                                width, PCIE_LINK_WIDTH_16),

Not sure why. For the root port, we use PCIE_LINK_WIDTH_32, and here it is
PCIE_LINK_WIDTH_16?

Fan

> +    DEFINE_PROP_END_OF_LIST()
> +};
>  
>  static void cxl_dsp_class_init(ObjectClass *oc, void *data)
>  {
>      DeviceClass *dc = DEVICE_CLASS(oc);
>      PCIDeviceClass *k = PCI_DEVICE_CLASS(oc);
>  
> +    device_class_set_props(dc, cxl_dsp_props);
>      k->config_write = cxl_dsp_config_write;
>      k->realize = cxl_dsp_realize;
>      k->exit = cxl_dsp_exitfn;
> @@ -243,7 +241,6 @@ static const TypeInfo cxl_dsp_info = {
>      .name = TYPE_CXL_DSP,
>      .instance_size = sizeof(CXLDownstreamPort),
>      .parent = TYPE_PCIE_SLOT,
> -    .instance_post_init = cxl_dsp_instance_post_init,
>      .class_init = cxl_dsp_class_init,
>      .interfaces = (InterfaceInfo[]) {
>          { INTERFACE_PCIE_DEVICE },
> -- 
> 2.43.0
> 

-- 
Fan Ni
Re: [PATCH 2/6] hw/pci-bridge/cxl_upstream: Provide x-speed and x-width properties.
Posted by Jonathan Cameron via 3 weeks, 3 days ago 
On Tue, 29 Oct 2024 09:37:59 -0700
Fan Ni <nifan.cxl@gmail.com> wrote:

> On Mon, Sep 16, 2024 at 06:35:14PM +0100, Jonathan Cameron wrote:
> > Copied from gen_pcie_root_port.c
> > Drop the previous code that ensured a valid value in s->width, s->speed
> > as now a default is provided so this will always be set.
> > 
> > Note this changes the default settings but it is unlikely to have a negative
> > effect on software as will only affect ports with now downstream device.
> > All other ports will use the settings from that device.
> > 
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > ---
> >  hw/pci-bridge/cxl_downstream.c | 23 ++++++++++-------------
> >  1 file changed, 10 insertions(+), 13 deletions(-)
> > 
> > diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c
> > index 4b42984360..c347ac06f3 100644
> > --- a/hw/pci-bridge/cxl_downstream.c
> > +++ b/hw/pci-bridge/cxl_downstream.c
> > @@ -13,6 +13,8 @@
> >  #include "hw/pci/msi.h"
> >  #include "hw/pci/pcie.h"
> >  #include "hw/pci/pcie_port.h"
> > +#include "hw/qdev-properties.h"
> > +#include "hw/qdev-properties-system.h"
> >  #include "hw/cxl/cxl.h"
> >  #include "qapi/error.h"
> >  
> > @@ -210,24 +212,20 @@ static void cxl_dsp_exitfn(PCIDevice *d)
> >      pci_bridge_exitfn(d);
> >  }
> >  
> > -static void cxl_dsp_instance_post_init(Object *obj)
> > -{
> > -    PCIESlot *s = PCIE_SLOT(obj);
> > -
> > -    if (!s->speed) {
> > -        s->speed = QEMU_PCI_EXP_LNK_2_5GT;
> > -    }
> > -
> > -    if (!s->width) {
> > -        s->width = QEMU_PCI_EXP_LNK_X1;
> > -    }
> > -}
> > +static Property cxl_dsp_props[] = {
> > +    DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot,
> > +                                speed, PCIE_LINK_SPEED_64),
> > +    DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
> > +                                width, PCIE_LINK_WIDTH_16),  
> 
> Not sure why. For the root port, we use PCIE_LINK_WIDTH_32, and here it is
> PCIE_LINK_WIDTH_16?

Random choice. There is no obvious default to choose.

I'm fine changing them to another choice if that makes more sense.

Jonathan


> 
> Fan
> 
> > +    DEFINE_PROP_END_OF_LIST()
> > +};
> >  
> >  static void cxl_dsp_class_init(ObjectClass *oc, void *data)
> >  {
> >      DeviceClass *dc = DEVICE_CLASS(oc);
> >      PCIDeviceClass *k = PCI_DEVICE_CLASS(oc);
> >  
> > +    device_class_set_props(dc, cxl_dsp_props);
> >      k->config_write = cxl_dsp_config_write;
> >      k->realize = cxl_dsp_realize;
> >      k->exit = cxl_dsp_exitfn;
> > @@ -243,7 +241,6 @@ static const TypeInfo cxl_dsp_info = {
> >      .name = TYPE_CXL_DSP,
> >      .instance_size = sizeof(CXLDownstreamPort),
> >      .parent = TYPE_PCIE_SLOT,
> > -    .instance_post_init = cxl_dsp_instance_post_init,
> >      .class_init = cxl_dsp_class_init,
> >      .interfaces = (InterfaceInfo[]) {
> >          { INTERFACE_PCIE_DEVICE },
> > -- 
> > 2.43.0
> >   
>

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