| 1 | The following changes since commit 63731c346f071a77e1bb1789bef1ac9d592b6d4f: | 1 | First arm pullreq of the cycle; this is mostly my softfloat NaN |
|---|---|---|---|
| 2 | handling series. (Lots more in my to-review queue, but I don't | ||
| 3 | like pullreqs growing too close to a hundred patches at a time :-)) | ||
| 2 | 4 | ||
| 3 | Merge tag 'pull-loongarch-20240912' of https://gitlab.com/gaosong/qemu into staging (2024-09-13 11:38:15 +0100) | 5 | thanks |
| 6 | -- PMM | ||
| 7 | |||
| 8 | The following changes since commit 97f2796a3736ed37a1b85dc1c76a6c45b829dd17: | ||
| 9 | |||
| 10 | Open 10.0 development tree (2024-12-10 17:41:17 +0000) | ||
| 4 | 11 | ||
| 5 | are available in the Git repository at: | 12 | are available in the Git repository at: |
| 6 | 13 | ||
| 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240913 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241211 |
| 8 | 15 | ||
| 9 | for you to fetch changes up to 110684c9a69a02cbabfbddcd3afa921826ad565c: | 16 | for you to fetch changes up to 1abe28d519239eea5cf9620bb13149423e5665f8: |
| 10 | 17 | ||
| 11 | hw/intc/arm_gic: fix spurious level triggered interrupts (2024-09-13 15:31:50 +0100) | 18 | MAINTAINERS: Add correct email address for Vikram Garhwal (2024-12-11 15:31:09 +0000) |
| 12 | 19 | ||
| 13 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
| 14 | target-arm queue: | 21 | target-arm queue: |
| 15 | * s390: convert s390 virtio-ccw and CPU to three-phase reset | 22 | * hw/net/lan9118: Extract PHY model, reuse with imx_fec, fix bugs |
| 16 | * reset: remove now-unused device_class_set_parent_reset() | 23 | * fpu: Make muladd NaN handling runtime-selected, not compile-time |
| 17 | * reset: introduce device_class_set_legacy_reset() | 24 | * fpu: Make default NaN pattern runtime-selected, not compile-time |
| 18 | * reset: remove unneeded transitional machinery | 25 | * fpu: Minor NaN-related cleanups |
| 19 | * kvm: Use 'unsigned long' for request argument in functions wrapping ioctl() | 26 | * MAINTAINERS: email address updates |
| 20 | * hvf: arm: Implement and use hvf_get_physical_address_range | ||
| 21 | so VMs can have larger-than-36-bit IPA spaces when the host | ||
| 22 | supports this | ||
| 23 | * target/arm/tcg: refine cache descriptions with a wrapper | ||
| 24 | * hw/net/can/xlnx-versal-canfd: fix various bugs | ||
| 25 | * MAINTAINERS: update versal, CAN maintainer entries | ||
| 26 | * hw/intc/arm_gic: fix spurious level triggered interrupts | ||
| 27 | 27 | ||
| 28 | ---------------------------------------------------------------- | 28 | ---------------------------------------------------------------- |
| 29 | Alireza Sanaee (1): | 29 | Bernhard Beschow (5): |
| 30 | target/arm/tcg: refine cache descriptions with a wrapper | 30 | hw/net/lan9118: Extract lan9118_phy |
| 31 | hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations | ||
| 32 | hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register | ||
| 33 | hw/net/lan9118_phy: Reuse MII constants | ||
| 34 | hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement | ||
| 31 | 35 | ||
| 32 | Danny Canter (3): | 36 | Leif Lindholm (1): |
| 33 | hw/boards: Add hvf_get_physical_address_range to MachineClass | 37 | MAINTAINERS: update email address for Leif Lindholm |
| 34 | hvf: Split up hv_vm_create logic per arch | ||
| 35 | hvf: arm: Implement and use hvf_get_physical_address_range | ||
| 36 | 38 | ||
| 37 | Doug Brown (7): | 39 | Peter Maydell (54): |
| 38 | hw/net/can/xlnx-versal-canfd: Fix interrupt level | 40 | fpu: handle raising Invalid for infzero in pick_nan_muladd |
| 39 | hw/net/can/xlnx-versal-canfd: Fix CAN FD flag check | 41 | fpu: Check for default_nan_mode before calling pickNaNMulAdd |
| 40 | hw/net/can/xlnx-versal-canfd: Translate CAN ID registers | 42 | softfloat: Allow runtime choice of inf * 0 + NaN result |
| 41 | hw/net/can/xlnx-versal-canfd: Handle flags correctly | 43 | tests/fp: Explicitly set inf-zero-nan rule |
| 42 | hw/net/can/xlnx-versal-canfd: Fix byte ordering | 44 | target/arm: Set FloatInfZeroNaNRule explicitly |
| 43 | hw/net/can/xlnx-versal-canfd: Simplify DLC conversions | 45 | target/s390: Set FloatInfZeroNaNRule explicitly |
| 44 | hw/net/can/xlnx-versal-canfd: Fix FIFO issues | 46 | target/ppc: Set FloatInfZeroNaNRule explicitly |
| 47 | target/mips: Set FloatInfZeroNaNRule explicitly | ||
| 48 | target/sparc: Set FloatInfZeroNaNRule explicitly | ||
| 49 | target/xtensa: Set FloatInfZeroNaNRule explicitly | ||
| 50 | target/x86: Set FloatInfZeroNaNRule explicitly | ||
| 51 | target/loongarch: Set FloatInfZeroNaNRule explicitly | ||
| 52 | target/hppa: Set FloatInfZeroNaNRule explicitly | ||
| 53 | softfloat: Pass have_snan to pickNaNMulAdd | ||
| 54 | softfloat: Allow runtime choice of NaN propagation for muladd | ||
| 55 | tests/fp: Explicitly set 3-NaN propagation rule | ||
| 56 | target/arm: Set Float3NaNPropRule explicitly | ||
| 57 | target/loongarch: Set Float3NaNPropRule explicitly | ||
| 58 | target/ppc: Set Float3NaNPropRule explicitly | ||
| 59 | target/s390x: Set Float3NaNPropRule explicitly | ||
| 60 | target/sparc: Set Float3NaNPropRule explicitly | ||
| 61 | target/mips: Set Float3NaNPropRule explicitly | ||
| 62 | target/xtensa: Set Float3NaNPropRule explicitly | ||
| 63 | target/i386: Set Float3NaNPropRule explicitly | ||
| 64 | target/hppa: Set Float3NaNPropRule explicitly | ||
| 65 | fpu: Remove use_first_nan field from float_status | ||
| 66 | target/m68k: Don't pass NULL float_status to floatx80_default_nan() | ||
| 67 | softfloat: Create floatx80 default NaN from parts64_default_nan | ||
| 68 | target/loongarch: Use normal float_status in fclass_s and fclass_d helpers | ||
| 69 | target/m68k: In frem helper, initialize local float_status from env->fp_status | ||
| 70 | target/m68k: Init local float_status from env fp_status in gdb get/set reg | ||
| 71 | target/sparc: Initialize local scratch float_status from env->fp_status | ||
| 72 | target/ppc: Use env->fp_status in helper_compute_fprf functions | ||
| 73 | fpu: Allow runtime choice of default NaN value | ||
| 74 | tests/fp: Set default NaN pattern explicitly | ||
| 75 | target/microblaze: Set default NaN pattern explicitly | ||
| 76 | target/i386: Set default NaN pattern explicitly | ||
| 77 | target/hppa: Set default NaN pattern explicitly | ||
| 78 | target/alpha: Set default NaN pattern explicitly | ||
| 79 | target/arm: Set default NaN pattern explicitly | ||
| 80 | target/loongarch: Set default NaN pattern explicitly | ||
| 81 | target/m68k: Set default NaN pattern explicitly | ||
| 82 | target/mips: Set default NaN pattern explicitly | ||
| 83 | target/openrisc: Set default NaN pattern explicitly | ||
| 84 | target/ppc: Set default NaN pattern explicitly | ||
| 85 | target/sh4: Set default NaN pattern explicitly | ||
| 86 | target/rx: Set default NaN pattern explicitly | ||
| 87 | target/s390x: Set default NaN pattern explicitly | ||
| 88 | target/sparc: Set default NaN pattern explicitly | ||
| 89 | target/xtensa: Set default NaN pattern explicitly | ||
| 90 | target/hexagon: Set default NaN pattern explicitly | ||
| 91 | target/riscv: Set default NaN pattern explicitly | ||
| 92 | target/tricore: Set default NaN pattern explicitly | ||
| 93 | fpu: Remove default handling for dnan_pattern | ||
| 45 | 94 | ||
| 46 | Francisco Iglesias (3): | 95 | Richard Henderson (11): |
| 47 | MAINTAINERS: Remove Vikram Garhwal as maintainer | 96 | target/arm: Copy entire float_status in is_ebf |
| 48 | MAINTAINERS: Update Xilinx Versal OSPI maintainer's email address | 97 | softfloat: Inline pickNaNMulAdd |
| 49 | MAINTAINERS: Add my-self as CAN maintainer | 98 | softfloat: Use goto for default nan case in pick_nan_muladd |
| 99 | softfloat: Remove which from parts_pick_nan_muladd | ||
| 100 | softfloat: Pad array size in pick_nan_muladd | ||
| 101 | softfloat: Move propagateFloatx80NaN to softfloat.c | ||
| 102 | softfloat: Use parts_pick_nan in propagateFloatx80NaN | ||
| 103 | softfloat: Inline pickNaN | ||
| 104 | softfloat: Share code between parts_pick_nan cases | ||
| 105 | softfloat: Sink frac_cmp in parts_pick_nan until needed | ||
| 106 | softfloat: Replace WHICH with RET in parts_pick_nan | ||
| 50 | 107 | ||
| 51 | Jan Klötzke (1): | 108 | Vikram Garhwal (1): |
| 52 | hw/intc/arm_gic: fix spurious level triggered interrupts | 109 | MAINTAINERS: Add correct email address for Vikram Garhwal |
| 53 | 110 | ||
| 54 | Johannes Stoelp (1): | 111 | MAINTAINERS | 4 +- |
| 55 | kvm: Use 'unsigned long' for request argument in functions wrapping ioctl() | 112 | include/fpu/softfloat-helpers.h | 38 +++- |
| 56 | 113 | include/fpu/softfloat-types.h | 89 +++++++- | |
| 57 | Peter Maydell (11): | 114 | include/hw/net/imx_fec.h | 9 +- |
| 58 | hw/s390/ccw-device: Convert to three-phase reset | 115 | include/hw/net/lan9118_phy.h | 37 ++++ |
| 59 | hw/s390/virtio-ccw: Convert to three-phase reset | 116 | include/hw/net/mii.h | 6 + |
| 60 | target/s390: Convert CPU to Resettable interface | 117 | target/mips/fpu_helper.h | 20 ++ |
| 61 | hw: Remove device_class_set_parent_reset() | 118 | target/sparc/helper.h | 4 +- |
| 62 | target/alpha, hppa: Remove unused parent_reset fields | 119 | fpu/softfloat.c | 19 ++ |
| 63 | hw: Define new device_class_set_legacy_reset() | 120 | hw/net/imx_fec.c | 146 ++------------ |
| 64 | hw: Use device_class_set_legacy_reset() instead of opencoding | 121 | hw/net/lan9118.c | 137 ++----------- |
| 65 | hw: Rename DeviceClass::reset field to legacy_reset | 122 | hw/net/lan9118_phy.c | 222 ++++++++++++++++++++ |
| 66 | hw: Remove device_phases_reset() | 123 | linux-user/arm/nwfpe/fpa11.c | 5 + |
| 67 | hw/core/qdev: Simplify legacy_reset handling | 124 | target/alpha/cpu.c | 2 + |
| 68 | hw/core/resettable: Remove transitional_function machinery | 125 | target/arm/cpu.c | 10 + |
| 69 | 126 | target/arm/tcg/vec_helper.c | 20 +- | |
| 70 | MAINTAINERS | 5 +- | 127 | target/hexagon/cpu.c | 2 + |
| 71 | docs/devel/reset.rst | 10 ++ | 128 | target/hppa/fpu_helper.c | 12 ++ |
| 72 | scripts/coccinelle/device-reset.cocci | 30 ++++++ | 129 | target/i386/tcg/fpu_helper.c | 12 ++ |
| 73 | hw/s390x/virtio-ccw.h | 2 +- | 130 | target/loongarch/tcg/fpu_helper.c | 14 +- |
| 74 | include/hw/boards.h | 5 + | 131 | target/m68k/cpu.c | 14 +- |
| 75 | include/hw/qdev-core.h | 33 +++--- | 132 | target/m68k/fpu_helper.c | 6 +- |
| 76 | include/hw/resettable.h | 15 +-- | 133 | target/m68k/helper.c | 6 +- |
| 77 | include/sysemu/hvf_int.h | 1 + | 134 | target/microblaze/cpu.c | 2 + |
| 78 | include/sysemu/kvm.h | 8 +- | 135 | target/mips/msa.c | 10 + |
| 79 | include/sysemu/kvm_int.h | 17 +++- | 136 | target/openrisc/cpu.c | 2 + |
| 80 | target/alpha/cpu.h | 2 - | 137 | target/ppc/cpu_init.c | 19 ++ |
| 81 | target/arm/cpu-features.h | 50 +++++++++ | 138 | target/ppc/fpu_helper.c | 3 +- |
| 82 | target/arm/hvf_arm.h | 19 ++++ | 139 | target/riscv/cpu.c | 2 + |
| 83 | target/arm/internals.h | 19 ++++ | 140 | target/rx/cpu.c | 2 + |
| 84 | target/hppa/cpu.h | 2 - | 141 | target/s390x/cpu.c | 5 + |
| 85 | target/s390x/cpu.h | 21 +--- | 142 | target/sh4/cpu.c | 2 + |
| 86 | accel/hvf/hvf-accel-ops.c | 16 ++- | 143 | target/sparc/cpu.c | 6 + |
| 87 | accel/kvm/kvm-all.c | 8 +- | 144 | target/sparc/fop_helper.c | 8 +- |
| 88 | hw/acpi/erst.c | 2 +- | 145 | target/sparc/translate.c | 4 +- |
| 89 | hw/acpi/piix4.c | 2 +- | 146 | target/tricore/helper.c | 2 + |
| 90 | hw/adc/aspeed_adc.c | 2 +- | 147 | target/xtensa/cpu.c | 4 + |
| 91 | hw/adc/max111x.c | 2 +- | 148 | target/xtensa/fpu_helper.c | 3 +- |
| 92 | hw/adc/stm32f2xx_adc.c | 2 +- | 149 | tests/fp/fp-bench.c | 7 + |
| 93 | hw/adc/zynq-xadc.c | 2 +- | 150 | tests/fp/fp-test-log2.c | 1 + |
| 94 | hw/arm/armsse.c | 2 +- | 151 | tests/fp/fp-test.c | 7 + |
| 95 | hw/arm/highbank.c | 2 +- | 152 | fpu/softfloat-parts.c.inc | 152 +++++++++++--- |
| 96 | hw/arm/musicpal.c | 6 +- | 153 | fpu/softfloat-specialize.c.inc | 412 ++------------------------------------ |
| 97 | hw/arm/pxa2xx.c | 4 +- | 154 | .mailmap | 5 +- |
| 98 | hw/arm/strongarm.c | 4 +- | 155 | hw/net/Kconfig | 5 + |
| 99 | hw/arm/virt.c | 38 ++++++- | 156 | hw/net/meson.build | 1 + |
| 100 | hw/audio/ac97.c | 2 +- | 157 | hw/net/trace-events | 10 +- |
| 101 | hw/audio/cs4231.c | 2 +- | 158 | 47 files changed, 778 insertions(+), 730 deletions(-) |
| 102 | hw/audio/cs4231a.c | 2 +- | 159 | create mode 100644 include/hw/net/lan9118_phy.h |
| 103 | hw/audio/es1370.c | 2 +- | 160 | create mode 100644 hw/net/lan9118_phy.c |
| 104 | hw/audio/hda-codec.c | 2 +- | ||
| 105 | hw/audio/intel-hda.c | 2 +- | ||
| 106 | hw/audio/marvell_88w8618.c | 2 +- | ||
| 107 | hw/audio/pl041.c | 2 +- | ||
| 108 | hw/audio/via-ac97.c | 2 +- | ||
| 109 | hw/block/fdc-isa.c | 2 +- | ||
| 110 | hw/block/fdc-sysbus.c | 2 +- | ||
| 111 | hw/block/m25p80.c | 2 +- | ||
| 112 | hw/block/nand.c | 2 +- | ||
| 113 | hw/block/onenand.c | 2 +- | ||
| 114 | hw/block/pflash_cfi01.c | 2 +- | ||
| 115 | hw/block/pflash_cfi02.c | 2 +- | ||
| 116 | hw/block/swim.c | 2 +- | ||
| 117 | hw/char/avr_usart.c | 2 +- | ||
| 118 | hw/char/cmsdk-apb-uart.c | 2 +- | ||
| 119 | hw/char/digic-uart.c | 2 +- | ||
| 120 | hw/char/escc.c | 2 +- | ||
| 121 | hw/char/etraxfs_ser.c | 2 +- | ||
| 122 | hw/char/exynos4210_uart.c | 2 +- | ||
| 123 | hw/char/goldfish_tty.c | 2 +- | ||
| 124 | hw/char/grlib_apbuart.c | 2 +- | ||
| 125 | hw/char/ibex_uart.c | 2 +- | ||
| 126 | hw/char/imx_serial.c | 2 +- | ||
| 127 | hw/char/mcf_uart.c | 2 +- | ||
| 128 | hw/char/mchp_pfsoc_mmuart.c | 2 +- | ||
| 129 | hw/char/nrf51_uart.c | 2 +- | ||
| 130 | hw/char/pl011.c | 2 +- | ||
| 131 | hw/char/renesas_sci.c | 2 +- | ||
| 132 | hw/char/sclpconsole-lm.c | 2 +- | ||
| 133 | hw/char/sclpconsole.c | 2 +- | ||
| 134 | hw/char/sh_serial.c | 2 +- | ||
| 135 | hw/char/shakti_uart.c | 2 +- | ||
| 136 | hw/char/stm32f2xx_usart.c | 2 +- | ||
| 137 | hw/char/xilinx_uartlite.c | 2 +- | ||
| 138 | hw/core/or-irq.c | 2 +- | ||
| 139 | hw/core/qdev.c | 97 +++++------------- | ||
| 140 | hw/core/resettable.c | 24 +---- | ||
| 141 | hw/cxl/switch-mailbox-cci.c | 2 +- | ||
| 142 | hw/display/artist.c | 2 +- | ||
| 143 | hw/display/ati.c | 2 +- | ||
| 144 | hw/display/bcm2835_fb.c | 2 +- | ||
| 145 | hw/display/cg3.c | 2 +- | ||
| 146 | hw/display/dpcd.c | 2 +- | ||
| 147 | hw/display/exynos4210_fimd.c | 2 +- | ||
| 148 | hw/display/g364fb.c | 2 +- | ||
| 149 | hw/display/i2c-ddc.c | 2 +- | ||
| 150 | hw/display/jazz_led.c | 2 +- | ||
| 151 | hw/display/macfb.c | 4 +- | ||
| 152 | hw/display/qxl.c | 2 +- | ||
| 153 | hw/display/sii9022.c | 2 +- | ||
| 154 | hw/display/sm501.c | 4 +- | ||
| 155 | hw/display/tcx.c | 2 +- | ||
| 156 | hw/display/vga-isa.c | 2 +- | ||
| 157 | hw/display/vga-mmio.c | 2 +- | ||
| 158 | hw/display/vga-pci.c | 2 +- | ||
| 159 | hw/display/vmware_vga.c | 2 +- | ||
| 160 | hw/display/xlnx_dp.c | 2 +- | ||
| 161 | hw/dma/bcm2835_dma.c | 2 +- | ||
| 162 | hw/dma/i8257.c | 2 +- | ||
| 163 | hw/dma/pl080.c | 2 +- | ||
| 164 | hw/dma/pl330.c | 2 +- | ||
| 165 | hw/dma/rc4030.c | 2 +- | ||
| 166 | hw/dma/sparc32_dma.c | 2 +- | ||
| 167 | hw/dma/xilinx_axidma.c | 2 +- | ||
| 168 | hw/dma/xlnx-zdma.c | 2 +- | ||
| 169 | hw/dma/xlnx-zynq-devcfg.c | 2 +- | ||
| 170 | hw/dma/xlnx_csu_dma.c | 2 +- | ||
| 171 | hw/dma/xlnx_dpdma.c | 2 +- | ||
| 172 | hw/fsi/aspeed_apb2opb.c | 2 +- | ||
| 173 | hw/fsi/fsi-master.c | 2 +- | ||
| 174 | hw/fsi/fsi.c | 2 +- | ||
| 175 | hw/fsi/lbus.c | 2 +- | ||
| 176 | hw/gpio/aspeed_gpio.c | 2 +- | ||
| 177 | hw/gpio/bcm2835_gpio.c | 2 +- | ||
| 178 | hw/gpio/bcm2838_gpio.c | 2 +- | ||
| 179 | hw/gpio/gpio_key.c | 2 +- | ||
| 180 | hw/gpio/imx_gpio.c | 2 +- | ||
| 181 | hw/gpio/max7310.c | 2 +- | ||
| 182 | hw/gpio/mpc8xxx.c | 2 +- | ||
| 183 | hw/gpio/nrf51_gpio.c | 2 +- | ||
| 184 | hw/gpio/omap_gpio.c | 4 +- | ||
| 185 | hw/gpio/pca9552.c | 2 +- | ||
| 186 | hw/gpio/pca9554.c | 2 +- | ||
| 187 | hw/gpio/pcf8574.c | 2 +- | ||
| 188 | hw/gpio/sifive_gpio.c | 2 +- | ||
| 189 | hw/hyperv/hyperv.c | 2 +- | ||
| 190 | hw/hyperv/vmbus.c | 2 +- | ||
| 191 | hw/i2c/aspeed_i2c.c | 4 +- | ||
| 192 | hw/i2c/bcm2835_i2c.c | 2 +- | ||
| 193 | hw/i2c/exynos4210_i2c.c | 2 +- | ||
| 194 | hw/i2c/imx_i2c.c | 2 +- | ||
| 195 | hw/i2c/microbit_i2c.c | 2 +- | ||
| 196 | hw/i2c/mpc_i2c.c | 2 +- | ||
| 197 | hw/i2c/omap_i2c.c | 2 +- | ||
| 198 | hw/i2c/ppc4xx_i2c.c | 2 +- | ||
| 199 | hw/i2c/smbus_eeprom.c | 2 +- | ||
| 200 | hw/i386/amd_iommu.c | 2 +- | ||
| 201 | hw/i386/intel_iommu.c | 2 +- | ||
| 202 | hw/i386/kvm/i8254.c | 2 +- | ||
| 203 | hw/i386/kvm/i8259.c | 2 +- | ||
| 204 | hw/i386/kvm/ioapic.c | 2 +- | ||
| 205 | hw/i386/kvm/xen_overlay.c | 2 +- | ||
| 206 | hw/i386/port92.c | 2 +- | ||
| 207 | hw/i386/vapic.c | 2 +- | ||
| 208 | hw/i386/vmmouse.c | 2 +- | ||
| 209 | hw/i386/xen/xen_platform.c | 2 +- | ||
| 210 | hw/ide/ahci.c | 2 +- | ||
| 211 | hw/ide/cmd646.c | 2 +- | ||
| 212 | hw/ide/ich.c | 2 +- | ||
| 213 | hw/ide/isa.c | 2 +- | ||
| 214 | hw/ide/macio.c | 2 +- | ||
| 215 | hw/ide/microdrive.c | 2 +- | ||
| 216 | hw/ide/mmio.c | 2 +- | ||
| 217 | hw/ide/piix.c | 4 +- | ||
| 218 | hw/ide/sii3112.c | 2 +- | ||
| 219 | hw/ide/via.c | 2 +- | ||
| 220 | hw/input/adb-kbd.c | 2 +- | ||
| 221 | hw/input/adb-mouse.c | 2 +- | ||
| 222 | hw/input/lm832x.c | 2 +- | ||
| 223 | hw/input/pckbd.c | 4 +- | ||
| 224 | hw/intc/allwinner-a10-pic.c | 2 +- | ||
| 225 | hw/intc/apic_common.c | 2 +- | ||
| 226 | hw/intc/arm_gic.c | 11 +- | ||
| 227 | hw/intc/armv7m_nvic.c | 2 +- | ||
| 228 | hw/intc/aspeed_intc.c | 2 +- | ||
| 229 | hw/intc/aspeed_vic.c | 2 +- | ||
| 230 | hw/intc/bcm2835_ic.c | 2 +- | ||
| 231 | hw/intc/bcm2836_control.c | 2 +- | ||
| 232 | hw/intc/exynos4210_combiner.c | 2 +- | ||
| 233 | hw/intc/goldfish_pic.c | 2 +- | ||
| 234 | hw/intc/grlib_irqmp.c | 2 +- | ||
| 235 | hw/intc/heathrow_pic.c | 2 +- | ||
| 236 | hw/intc/i8259.c | 2 +- | ||
| 237 | hw/intc/imx_avic.c | 2 +- | ||
| 238 | hw/intc/imx_gpcv2.c | 2 +- | ||
| 239 | hw/intc/ioapic.c | 2 +- | ||
| 240 | hw/intc/loongarch_extioi.c | 2 +- | ||
| 241 | hw/intc/loongarch_pch_pic.c | 2 +- | ||
| 242 | hw/intc/m68k_irqc.c | 2 +- | ||
| 243 | hw/intc/omap_intc.c | 4 +- | ||
| 244 | hw/intc/openpic.c | 2 +- | ||
| 245 | hw/intc/openpic_kvm.c | 2 +- | ||
| 246 | hw/intc/pl190.c | 2 +- | ||
| 247 | hw/intc/ppc-uic.c | 2 +- | ||
| 248 | hw/intc/s390_flic.c | 2 +- | ||
| 249 | hw/intc/s390_flic_kvm.c | 2 +- | ||
| 250 | hw/intc/sifive_plic.c | 2 +- | ||
| 251 | hw/intc/slavio_intctl.c | 2 +- | ||
| 252 | hw/intc/xlnx-pmu-iomod-intc.c | 2 +- | ||
| 253 | hw/intc/xlnx-zynqmp-ipi.c | 2 +- | ||
| 254 | hw/isa/lpc_ich9.c | 2 +- | ||
| 255 | hw/isa/pc87312.c | 2 +- | ||
| 256 | hw/isa/piix.c | 2 +- | ||
| 257 | hw/isa/vt82c686.c | 10 +- | ||
| 258 | hw/m68k/mcf5206.c | 2 +- | ||
| 259 | hw/m68k/mcf_intc.c | 2 +- | ||
| 260 | hw/m68k/next-cube.c | 2 +- | ||
| 261 | hw/m68k/next-kbd.c | 2 +- | ||
| 262 | hw/mem/cxl_type3.c | 2 +- | ||
| 263 | hw/misc/a9scu.c | 2 +- | ||
| 264 | hw/misc/allwinner-cpucfg.c | 2 +- | ||
| 265 | hw/misc/allwinner-h3-ccu.c | 2 +- | ||
| 266 | hw/misc/allwinner-h3-dramc.c | 2 +- | ||
| 267 | hw/misc/allwinner-h3-sysctrl.c | 2 +- | ||
| 268 | hw/misc/allwinner-r40-ccu.c | 2 +- | ||
| 269 | hw/misc/allwinner-r40-dramc.c | 2 +- | ||
| 270 | hw/misc/allwinner-sid.c | 2 +- | ||
| 271 | hw/misc/allwinner-sramc.c | 2 +- | ||
| 272 | hw/misc/applesmc.c | 2 +- | ||
| 273 | hw/misc/arm_l2x0.c | 2 +- | ||
| 274 | hw/misc/arm_sysctl.c | 2 +- | ||
| 275 | hw/misc/armsse-cpu-pwrctrl.c | 2 +- | ||
| 276 | hw/misc/armsse-mhu.c | 2 +- | ||
| 277 | hw/misc/aspeed_hace.c | 2 +- | ||
| 278 | hw/misc/aspeed_i3c.c | 4 +- | ||
| 279 | hw/misc/aspeed_lpc.c | 2 +- | ||
| 280 | hw/misc/aspeed_peci.c | 2 +- | ||
| 281 | hw/misc/aspeed_sbc.c | 2 +- | ||
| 282 | hw/misc/aspeed_scu.c | 10 +- | ||
| 283 | hw/misc/aspeed_sdmc.c | 4 +- | ||
| 284 | hw/misc/aspeed_xdma.c | 2 +- | ||
| 285 | hw/misc/avr_power.c | 2 +- | ||
| 286 | hw/misc/bcm2835_cprman.c | 8 +- | ||
| 287 | hw/misc/bcm2835_mbox.c | 2 +- | ||
| 288 | hw/misc/bcm2835_mphi.c | 2 +- | ||
| 289 | hw/misc/bcm2835_powermgt.c | 2 +- | ||
| 290 | hw/misc/bcm2835_rng.c | 2 +- | ||
| 291 | hw/misc/bcm2835_thermal.c | 2 +- | ||
| 292 | hw/misc/eccmemctl.c | 2 +- | ||
| 293 | hw/misc/exynos4210_clk.c | 2 +- | ||
| 294 | hw/misc/exynos4210_pmu.c | 2 +- | ||
| 295 | hw/misc/exynos4210_rng.c | 2 +- | ||
| 296 | hw/misc/imx25_ccm.c | 2 +- | ||
| 297 | hw/misc/imx31_ccm.c | 2 +- | ||
| 298 | hw/misc/imx6_ccm.c | 2 +- | ||
| 299 | hw/misc/imx6_src.c | 2 +- | ||
| 300 | hw/misc/imx6ul_ccm.c | 2 +- | ||
| 301 | hw/misc/imx7_ccm.c | 4 +- | ||
| 302 | hw/misc/imx7_snvs.c | 2 +- | ||
| 303 | hw/misc/imx7_src.c | 2 +- | ||
| 304 | hw/misc/imx_rngc.c | 2 +- | ||
| 305 | hw/misc/iotkit-secctl.c | 2 +- | ||
| 306 | hw/misc/iotkit-sysctl.c | 2 +- | ||
| 307 | hw/misc/ivshmem.c | 2 +- | ||
| 308 | hw/misc/lasi.c | 2 +- | ||
| 309 | hw/misc/led.c | 2 +- | ||
| 310 | hw/misc/macio/cuda.c | 2 +- | ||
| 311 | hw/misc/macio/gpio.c | 2 +- | ||
| 312 | hw/misc/macio/mac_dbdma.c | 2 +- | ||
| 313 | hw/misc/macio/pmu.c | 2 +- | ||
| 314 | hw/misc/mips_cmgcr.c | 2 +- | ||
| 315 | hw/misc/mips_cpc.c | 2 +- | ||
| 316 | hw/misc/mips_itu.c | 2 +- | ||
| 317 | hw/misc/mps2-fpgaio.c | 2 +- | ||
| 318 | hw/misc/mps2-scc.c | 2 +- | ||
| 319 | hw/misc/msf2-sysreg.c | 2 +- | ||
| 320 | hw/misc/nrf51_rng.c | 2 +- | ||
| 321 | hw/misc/pci-testdev.c | 2 +- | ||
| 322 | hw/misc/sifive_e_aon.c | 2 +- | ||
| 323 | hw/misc/sifive_u_prci.c | 2 +- | ||
| 324 | hw/misc/slavio_misc.c | 2 +- | ||
| 325 | hw/misc/stm32f2xx_syscfg.c | 2 +- | ||
| 326 | hw/misc/stm32f4xx_exti.c | 2 +- | ||
| 327 | hw/misc/stm32f4xx_syscfg.c | 2 +- | ||
| 328 | hw/misc/tz-mpc.c | 2 +- | ||
| 329 | hw/misc/tz-msc.c | 2 +- | ||
| 330 | hw/misc/tz-ppc.c | 2 +- | ||
| 331 | hw/misc/virt_ctrl.c | 2 +- | ||
| 332 | hw/misc/xlnx-versal-cfu.c | 2 +- | ||
| 333 | hw/net/allwinner-sun8i-emac.c | 2 +- | ||
| 334 | hw/net/allwinner_emac.c | 2 +- | ||
| 335 | hw/net/cadence_gem.c | 2 +- | ||
| 336 | hw/net/can/can_kvaser_pci.c | 2 +- | ||
| 337 | hw/net/can/can_mioe3680_pci.c | 2 +- | ||
| 338 | hw/net/can/can_pcm3680_pci.c | 2 +- | ||
| 339 | hw/net/can/ctucan_pci.c | 2 +- | ||
| 340 | hw/net/can/xlnx-versal-canfd.c | 185 ++++++++++++++-------------------- | ||
| 341 | hw/net/dp8393x.c | 2 +- | ||
| 342 | hw/net/etraxfs_eth.c | 2 +- | ||
| 343 | hw/net/fsl_etsec/etsec.c | 2 +- | ||
| 344 | hw/net/ftgmac100.c | 4 +- | ||
| 345 | hw/net/imx_fec.c | 2 +- | ||
| 346 | hw/net/lan9118.c | 2 +- | ||
| 347 | hw/net/lance.c | 2 +- | ||
| 348 | hw/net/lasi_i82596.c | 2 +- | ||
| 349 | hw/net/mcf_fec.c | 2 +- | ||
| 350 | hw/net/mipsnet.c | 2 +- | ||
| 351 | hw/net/msf2-emac.c | 2 +- | ||
| 352 | hw/net/npcm7xx_emc.c | 2 +- | ||
| 353 | hw/net/npcm_gmac.c | 2 +- | ||
| 354 | hw/net/opencores_eth.c | 2 +- | ||
| 355 | hw/net/pcnet-pci.c | 2 +- | ||
| 356 | hw/net/rocker/rocker.c | 2 +- | ||
| 357 | hw/net/rtl8139.c | 2 +- | ||
| 358 | hw/net/smc91c111.c | 2 +- | ||
| 359 | hw/net/stellaris_enet.c | 2 +- | ||
| 360 | hw/net/sungem.c | 2 +- | ||
| 361 | hw/net/sunhme.c | 2 +- | ||
| 362 | hw/net/tulip.c | 2 +- | ||
| 363 | hw/net/vmxnet3.c | 2 +- | ||
| 364 | hw/net/xilinx_axienet.c | 2 +- | ||
| 365 | hw/net/xilinx_ethlite.c | 2 +- | ||
| 366 | hw/nvme/ctrl.c | 2 +- | ||
| 367 | hw/nvram/eeprom_at24c.c | 2 +- | ||
| 368 | hw/nvram/fw_cfg.c | 2 +- | ||
| 369 | hw/nvram/mac_nvram.c | 2 +- | ||
| 370 | hw/nvram/nrf51_nvm.c | 2 +- | ||
| 371 | hw/pci-bridge/cxl_downstream.c | 2 +- | ||
| 372 | hw/pci-bridge/cxl_upstream.c | 2 +- | ||
| 373 | hw/pci-bridge/i82801b11.c | 2 +- | ||
| 374 | hw/pci-bridge/pci_bridge_dev.c | 2 +- | ||
| 375 | hw/pci-bridge/pci_expander_bridge.c | 2 +- | ||
| 376 | hw/pci-bridge/pcie_pci_bridge.c | 2 +- | ||
| 377 | hw/pci-bridge/simba.c | 2 +- | ||
| 378 | hw/pci-bridge/xio3130_downstream.c | 2 +- | ||
| 379 | hw/pci-bridge/xio3130_upstream.c | 2 +- | ||
| 380 | hw/pci-host/astro.c | 4 +- | ||
| 381 | hw/pci-host/designware.c | 2 +- | ||
| 382 | hw/pci-host/dino.c | 2 +- | ||
| 383 | hw/pci-host/gt64120.c | 2 +- | ||
| 384 | hw/pci-host/mv64361.c | 2 +- | ||
| 385 | hw/pci-host/ppc440_pcix.c | 2 +- | ||
| 386 | hw/pci-host/q35.c | 2 +- | ||
| 387 | hw/pci-host/sabre.c | 2 +- | ||
| 388 | hw/pci-host/versatile.c | 2 +- | ||
| 389 | hw/pci-host/xilinx-pcie.c | 2 +- | ||
| 390 | hw/ppc/pnv_psi.c | 4 +- | ||
| 391 | hw/ppc/ppc405_boards.c | 2 +- | ||
| 392 | hw/ppc/ppc405_uc.c | 12 +-- | ||
| 393 | hw/ppc/ppc4xx_devs.c | 6 +- | ||
| 394 | hw/ppc/ppc4xx_sdram.c | 4 +- | ||
| 395 | hw/ppc/ppce500_spin.c | 2 +- | ||
| 396 | hw/ppc/spapr_cpu_core.c | 2 +- | ||
| 397 | hw/ppc/spapr_iommu.c | 2 +- | ||
| 398 | hw/ppc/spapr_pci.c | 2 +- | ||
| 399 | hw/ppc/spapr_vio.c | 2 +- | ||
| 400 | hw/remote/proxy.c | 2 +- | ||
| 401 | hw/rtc/allwinner-rtc.c | 2 +- | ||
| 402 | hw/rtc/aspeed_rtc.c | 2 +- | ||
| 403 | hw/rtc/ds1338.c | 2 +- | ||
| 404 | hw/rtc/exynos4210_rtc.c | 2 +- | ||
| 405 | hw/rtc/goldfish_rtc.c | 2 +- | ||
| 406 | hw/rtc/ls7a_rtc.c | 2 +- | ||
| 407 | hw/rtc/m48t59-isa.c | 2 +- | ||
| 408 | hw/rtc/m48t59.c | 2 +- | ||
| 409 | hw/rtc/xlnx-zynqmp-rtc.c | 2 +- | ||
| 410 | hw/s390x/ccw-device.c | 7 +- | ||
| 411 | hw/s390x/event-facility.c | 2 +- | ||
| 412 | hw/s390x/ipl.c | 2 +- | ||
| 413 | hw/s390x/s390-pci-bus.c | 4 +- | ||
| 414 | hw/s390x/sclpquiesce.c | 2 +- | ||
| 415 | hw/s390x/virtio-ccw.c | 13 ++- | ||
| 416 | hw/scsi/esp-pci.c | 2 +- | ||
| 417 | hw/scsi/esp.c | 2 +- | ||
| 418 | hw/scsi/lsi53c895a.c | 2 +- | ||
| 419 | hw/scsi/megasas.c | 2 +- | ||
| 420 | hw/scsi/mptsas.c | 2 +- | ||
| 421 | hw/scsi/scsi-disk.c | 2 +- | ||
| 422 | hw/scsi/scsi-generic.c | 2 +- | ||
| 423 | hw/scsi/vmw_pvscsi.c | 2 +- | ||
| 424 | hw/sd/allwinner-sdhost.c | 2 +- | ||
| 425 | hw/sd/aspeed_sdhci.c | 2 +- | ||
| 426 | hw/sd/bcm2835_sdhost.c | 2 +- | ||
| 427 | hw/sd/cadence_sdhci.c | 2 +- | ||
| 428 | hw/sd/npcm7xx_sdhci.c | 2 +- | ||
| 429 | hw/sd/pl181.c | 2 +- | ||
| 430 | hw/sd/pxa2xx_mmci.c | 2 +- | ||
| 431 | hw/sd/sd.c | 2 +- | ||
| 432 | hw/sd/sdhci.c | 2 +- | ||
| 433 | hw/sd/ssi-sd.c | 2 +- | ||
| 434 | hw/sensor/dps310.c | 2 +- | ||
| 435 | hw/sensor/emc141x.c | 2 +- | ||
| 436 | hw/sensor/lsm303dlhc_mag.c | 2 +- | ||
| 437 | hw/sparc/sun4m_iommu.c | 2 +- | ||
| 438 | hw/sparc64/sun4u_iommu.c | 2 +- | ||
| 439 | hw/ssi/aspeed_smc.c | 2 +- | ||
| 440 | hw/ssi/bcm2835_spi.c | 2 +- | ||
| 441 | hw/ssi/ibex_spi_host.c | 2 +- | ||
| 442 | hw/ssi/imx_spi.c | 2 +- | ||
| 443 | hw/ssi/mss-spi.c | 2 +- | ||
| 444 | hw/ssi/pl022.c | 2 +- | ||
| 445 | hw/ssi/pnv_spi.c | 2 +- | ||
| 446 | hw/ssi/sifive_spi.c | 2 +- | ||
| 447 | hw/ssi/stm32f2xx_spi.c | 2 +- | ||
| 448 | hw/ssi/xilinx_spi.c | 2 +- | ||
| 449 | hw/ssi/xilinx_spips.c | 4 +- | ||
| 450 | hw/ssi/xlnx-versal-ospi.c | 2 +- | ||
| 451 | hw/timer/a9gtimer.c | 2 +- | ||
| 452 | hw/timer/allwinner-a10-pit.c | 2 +- | ||
| 453 | hw/timer/arm_mptimer.c | 2 +- | ||
| 454 | hw/timer/armv7m_systick.c | 2 +- | ||
| 455 | hw/timer/aspeed_timer.c | 2 +- | ||
| 456 | hw/timer/avr_timer16.c | 2 +- | ||
| 457 | hw/timer/bcm2835_systmr.c | 2 +- | ||
| 458 | hw/timer/cmsdk-apb-dualtimer.c | 2 +- | ||
| 459 | hw/timer/cmsdk-apb-timer.c | 2 +- | ||
| 460 | hw/timer/digic-timer.c | 2 +- | ||
| 461 | hw/timer/exynos4210_mct.c | 2 +- | ||
| 462 | hw/timer/exynos4210_pwm.c | 2 +- | ||
| 463 | hw/timer/grlib_gptimer.c | 2 +- | ||
| 464 | hw/timer/hpet.c | 2 +- | ||
| 465 | hw/timer/i8254.c | 2 +- | ||
| 466 | hw/timer/ibex_timer.c | 2 +- | ||
| 467 | hw/timer/imx_epit.c | 2 +- | ||
| 468 | hw/timer/imx_gpt.c | 2 +- | ||
| 469 | hw/timer/nrf51_timer.c | 2 +- | ||
| 470 | hw/timer/renesas_cmt.c | 2 +- | ||
| 471 | hw/timer/renesas_tmr.c | 2 +- | ||
| 472 | hw/timer/sifive_pwm.c | 2 +- | ||
| 473 | hw/timer/slavio_timer.c | 2 +- | ||
| 474 | hw/timer/sse-counter.c | 2 +- | ||
| 475 | hw/timer/sse-timer.c | 2 +- | ||
| 476 | hw/timer/stm32f2xx_timer.c | 2 +- | ||
| 477 | hw/tpm/tpm_tis_i2c.c | 2 +- | ||
| 478 | hw/tpm/tpm_tis_isa.c | 2 +- | ||
| 479 | hw/tpm/tpm_tis_sysbus.c | 2 +- | ||
| 480 | hw/tricore/tricore_testdevice.c | 2 +- | ||
| 481 | hw/usb/hcd-dwc3.c | 2 +- | ||
| 482 | hw/usb/hcd-ehci-pci.c | 2 +- | ||
| 483 | hw/usb/hcd-ehci-sysbus.c | 2 +- | ||
| 484 | hw/usb/hcd-ohci-pci.c | 2 +- | ||
| 485 | hw/usb/hcd-ohci-sysbus.c | 2 +- | ||
| 486 | hw/usb/hcd-uhci.c | 2 +- | ||
| 487 | hw/usb/hcd-xhci-pci.c | 2 +- | ||
| 488 | hw/usb/hcd-xhci-sysbus.c | 2 +- | ||
| 489 | hw/usb/hcd-xhci.c | 2 +- | ||
| 490 | hw/usb/imx-usb-phy.c | 2 +- | ||
| 491 | hw/usb/tusb6010.c | 2 +- | ||
| 492 | hw/vfio/ap.c | 2 +- | ||
| 493 | hw/vfio/ccw.c | 2 +- | ||
| 494 | hw/vfio/pci.c | 2 +- | ||
| 495 | hw/virtio/virtio-mmio.c | 2 +- | ||
| 496 | hw/watchdog/cmsdk-apb-watchdog.c | 2 +- | ||
| 497 | hw/watchdog/sbsa_gwdt.c | 2 +- | ||
| 498 | hw/watchdog/wdt_aspeed.c | 2 +- | ||
| 499 | hw/watchdog/wdt_diag288.c | 2 +- | ||
| 500 | hw/watchdog/wdt_i6300esb.c | 2 +- | ||
| 501 | hw/watchdog/wdt_ib700.c | 2 +- | ||
| 502 | hw/watchdog/wdt_imx2.c | 2 +- | ||
| 503 | target/arm/cpu64.c | 19 ++-- | ||
| 504 | target/arm/hvf/hvf.c | 63 ++++++++++++ | ||
| 505 | target/arm/ptw.c | 15 +++ | ||
| 506 | target/arm/tcg/cpu64.c | 108 ++++++++++---------- | ||
| 507 | target/i386/hvf/hvf.c | 5 + | ||
| 508 | target/i386/kvm/kvm.c | 3 +- | ||
| 509 | target/s390x/cpu.c | 38 ++++--- | ||
| 510 | target/s390x/sigp.c | 8 +- | ||
| 511 | accel/kvm/trace-events | 8 +- | ||
| 512 | 442 files changed, 977 insertions(+), 820 deletions(-) | ||
| 513 | create mode 100644 scripts/coccinelle/device-reset.cocci | ||
| 514 | diff view generated by jsdifflib |
| 1 | From: Francisco Iglesias <francisco.iglesias@amd.com> | 1 | From: Bernhard Beschow <shentey@gmail.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com> | 3 | A very similar implementation of the same device exists in imx_fec. Prepare for |
| 4 | Message-id: 20240906181645.40359-4-francisco.iglesias@amd.com | 4 | a common implementation by extracting a device model into its own files. |
| 5 | |||
| 6 | Some migration state has been moved into the new device model which breaks | ||
| 7 | migration compatibility for the following machines: | ||
| 8 | * smdkc210 | ||
| 9 | * realview-* | ||
| 10 | * vexpress-* | ||
| 11 | * kzm | ||
| 12 | * mps2-* | ||
| 13 | |||
| 14 | While breaking migration ABI, fix the size of the MII registers to be 16 bit, | ||
| 15 | as defined by IEEE 802.3u. | ||
| 16 | |||
| 17 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> | ||
| 18 | Tested-by: Guenter Roeck <linux@roeck-us.net> | ||
| 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 20 | Message-id: 20241102125724.532843-2-shentey@gmail.com | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | --- | 22 | --- |
| 8 | MAINTAINERS | 1 + | 23 | include/hw/net/lan9118_phy.h | 37 ++++++++ |
| 9 | 1 file changed, 1 insertion(+) | 24 | hw/net/lan9118.c | 137 +++++----------------------- |
| 25 | hw/net/lan9118_phy.c | 169 +++++++++++++++++++++++++++++++++++ | ||
| 26 | hw/net/Kconfig | 4 + | ||
| 27 | hw/net/meson.build | 1 + | ||
| 28 | 5 files changed, 233 insertions(+), 115 deletions(-) | ||
| 29 | create mode 100644 include/hw/net/lan9118_phy.h | ||
| 30 | create mode 100644 hw/net/lan9118_phy.c | ||
| 10 | 31 | ||
| 11 | diff --git a/MAINTAINERS b/MAINTAINERS | 32 | diff --git a/include/hw/net/lan9118_phy.h b/include/hw/net/lan9118_phy.h |
| 33 | new file mode 100644 | ||
| 34 | index XXXXXXX..XXXXXXX | ||
| 35 | --- /dev/null | ||
| 36 | +++ b/include/hw/net/lan9118_phy.h | ||
| 37 | @@ -XXX,XX +XXX,XX @@ | ||
| 38 | +/* | ||
| 39 | + * SMSC LAN9118 PHY emulation | ||
| 40 | + * | ||
| 41 | + * Copyright (c) 2009 CodeSourcery, LLC. | ||
| 42 | + * Written by Paul Brook | ||
| 43 | + * | ||
| 44 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
| 45 | + * See the COPYING file in the top-level directory. | ||
| 46 | + */ | ||
| 47 | + | ||
| 48 | +#ifndef HW_NET_LAN9118_PHY_H | ||
| 49 | +#define HW_NET_LAN9118_PHY_H | ||
| 50 | + | ||
| 51 | +#include "qom/object.h" | ||
| 52 | +#include "hw/sysbus.h" | ||
| 53 | + | ||
| 54 | +#define TYPE_LAN9118_PHY "lan9118-phy" | ||
| 55 | +OBJECT_DECLARE_SIMPLE_TYPE(Lan9118PhyState, LAN9118_PHY) | ||
| 56 | + | ||
| 57 | +typedef struct Lan9118PhyState { | ||
| 58 | + SysBusDevice parent_obj; | ||
| 59 | + | ||
| 60 | + uint16_t status; | ||
| 61 | + uint16_t control; | ||
| 62 | + uint16_t advertise; | ||
| 63 | + uint16_t ints; | ||
| 64 | + uint16_t int_mask; | ||
| 65 | + qemu_irq irq; | ||
| 66 | + bool link_down; | ||
| 67 | +} Lan9118PhyState; | ||
| 68 | + | ||
| 69 | +void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down); | ||
| 70 | +void lan9118_phy_reset(Lan9118PhyState *s); | ||
| 71 | +uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg); | ||
| 72 | +void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val); | ||
| 73 | + | ||
| 74 | +#endif | ||
| 75 | diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c | ||
| 12 | index XXXXXXX..XXXXXXX 100644 | 76 | index XXXXXXX..XXXXXXX 100644 |
| 13 | --- a/MAINTAINERS | 77 | --- a/hw/net/lan9118.c |
| 14 | +++ b/MAINTAINERS | 78 | +++ b/hw/net/lan9118.c |
| 15 | @@ -XXX,XX +XXX,XX @@ F: include/hw/rx/ | 79 | @@ -XXX,XX +XXX,XX @@ |
| 16 | 80 | #include "net/net.h" | |
| 17 | CAN bus subsystem and hardware | 81 | #include "net/eth.h" |
| 18 | M: Pavel Pisa <pisa@cmp.felk.cvut.cz> | 82 | #include "hw/irq.h" |
| 19 | +M: Francisco Iglesias <francisco.iglesias@amd.com> | 83 | +#include "hw/net/lan9118_phy.h" |
| 20 | S: Maintained | 84 | #include "hw/net/lan9118.h" |
| 21 | W: https://canbus.pages.fel.cvut.cz/ | 85 | #include "hw/ptimer.h" |
| 22 | F: net/can/* | 86 | #include "hw/qdev-properties.h" |
| 87 | @@ -XXX,XX +XXX,XX @@ do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0) | ||
| 88 | #define MAC_CR_RXEN 0x00000004 | ||
| 89 | #define MAC_CR_RESERVED 0x7f404213 | ||
| 90 | |||
| 91 | -#define PHY_INT_ENERGYON 0x80 | ||
| 92 | -#define PHY_INT_AUTONEG_COMPLETE 0x40 | ||
| 93 | -#define PHY_INT_FAULT 0x20 | ||
| 94 | -#define PHY_INT_DOWN 0x10 | ||
| 95 | -#define PHY_INT_AUTONEG_LP 0x08 | ||
| 96 | -#define PHY_INT_PARFAULT 0x04 | ||
| 97 | -#define PHY_INT_AUTONEG_PAGE 0x02 | ||
| 98 | - | ||
| 99 | #define GPT_TIMER_EN 0x20000000 | ||
| 100 | |||
| 101 | /* | ||
| 102 | @@ -XXX,XX +XXX,XX @@ struct lan9118_state { | ||
| 103 | uint32_t mac_mii_data; | ||
| 104 | uint32_t mac_flow; | ||
| 105 | |||
| 106 | - uint32_t phy_status; | ||
| 107 | - uint32_t phy_control; | ||
| 108 | - uint32_t phy_advertise; | ||
| 109 | - uint32_t phy_int; | ||
| 110 | - uint32_t phy_int_mask; | ||
| 111 | + Lan9118PhyState mii; | ||
| 112 | + IRQState mii_irq; | ||
| 113 | |||
| 114 | int32_t eeprom_writable; | ||
| 115 | uint8_t eeprom[128]; | ||
| 116 | @@ -XXX,XX +XXX,XX @@ struct lan9118_state { | ||
| 117 | |||
| 118 | static const VMStateDescription vmstate_lan9118 = { | ||
| 119 | .name = "lan9118", | ||
| 120 | - .version_id = 2, | ||
| 121 | - .minimum_version_id = 1, | ||
| 122 | + .version_id = 3, | ||
| 123 | + .minimum_version_id = 3, | ||
| 124 | .fields = (const VMStateField[]) { | ||
| 125 | VMSTATE_PTIMER(timer, lan9118_state), | ||
| 126 | VMSTATE_UINT32(irq_cfg, lan9118_state), | ||
| 127 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118 = { | ||
| 128 | VMSTATE_UINT32(mac_mii_acc, lan9118_state), | ||
| 129 | VMSTATE_UINT32(mac_mii_data, lan9118_state), | ||
| 130 | VMSTATE_UINT32(mac_flow, lan9118_state), | ||
| 131 | - VMSTATE_UINT32(phy_status, lan9118_state), | ||
| 132 | - VMSTATE_UINT32(phy_control, lan9118_state), | ||
| 133 | - VMSTATE_UINT32(phy_advertise, lan9118_state), | ||
| 134 | - VMSTATE_UINT32(phy_int, lan9118_state), | ||
| 135 | - VMSTATE_UINT32(phy_int_mask, lan9118_state), | ||
| 136 | VMSTATE_INT32(eeprom_writable, lan9118_state), | ||
| 137 | VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128), | ||
| 138 | VMSTATE_INT32(tx_fifo_size, lan9118_state), | ||
| 139 | @@ -XXX,XX +XXX,XX @@ static void lan9118_reload_eeprom(lan9118_state *s) | ||
| 140 | lan9118_mac_changed(s); | ||
| 141 | } | ||
| 142 | |||
| 143 | -static void phy_update_irq(lan9118_state *s) | ||
| 144 | +static void lan9118_update_irq(void *opaque, int n, int level) | ||
| 145 | { | ||
| 146 | - if (s->phy_int & s->phy_int_mask) { | ||
| 147 | + lan9118_state *s = opaque; | ||
| 148 | + | ||
| 149 | + if (level) { | ||
| 150 | s->int_sts |= PHY_INT; | ||
| 151 | } else { | ||
| 152 | s->int_sts &= ~PHY_INT; | ||
| 153 | @@ -XXX,XX +XXX,XX @@ static void phy_update_irq(lan9118_state *s) | ||
| 154 | lan9118_update(s); | ||
| 155 | } | ||
| 156 | |||
| 157 | -static void phy_update_link(lan9118_state *s) | ||
| 158 | -{ | ||
| 159 | - /* Autonegotiation status mirrors link status. */ | ||
| 160 | - if (qemu_get_queue(s->nic)->link_down) { | ||
| 161 | - s->phy_status &= ~0x0024; | ||
| 162 | - s->phy_int |= PHY_INT_DOWN; | ||
| 163 | - } else { | ||
| 164 | - s->phy_status |= 0x0024; | ||
| 165 | - s->phy_int |= PHY_INT_ENERGYON; | ||
| 166 | - s->phy_int |= PHY_INT_AUTONEG_COMPLETE; | ||
| 167 | - } | ||
| 168 | - phy_update_irq(s); | ||
| 169 | -} | ||
| 170 | - | ||
| 171 | static void lan9118_set_link(NetClientState *nc) | ||
| 172 | { | ||
| 173 | - phy_update_link(qemu_get_nic_opaque(nc)); | ||
| 174 | -} | ||
| 175 | - | ||
| 176 | -static void phy_reset(lan9118_state *s) | ||
| 177 | -{ | ||
| 178 | - s->phy_status = 0x7809; | ||
| 179 | - s->phy_control = 0x3000; | ||
| 180 | - s->phy_advertise = 0x01e1; | ||
| 181 | - s->phy_int_mask = 0; | ||
| 182 | - s->phy_int = 0; | ||
| 183 | - phy_update_link(s); | ||
| 184 | + lan9118_phy_update_link(&LAN9118(qemu_get_nic_opaque(nc))->mii, | ||
| 185 | + nc->link_down); | ||
| 186 | } | ||
| 187 | |||
| 188 | static void lan9118_reset(DeviceState *d) | ||
| 189 | @@ -XXX,XX +XXX,XX @@ static void lan9118_reset(DeviceState *d) | ||
| 190 | s->read_word_n = 0; | ||
| 191 | s->write_word_n = 0; | ||
| 192 | |||
| 193 | - phy_reset(s); | ||
| 194 | - | ||
| 195 | s->eeprom_writable = 0; | ||
| 196 | lan9118_reload_eeprom(s); | ||
| 197 | } | ||
| 198 | @@ -XXX,XX +XXX,XX @@ static void do_tx_packet(lan9118_state *s) | ||
| 199 | uint32_t status; | ||
| 200 | |||
| 201 | /* FIXME: Honor TX disable, and allow queueing of packets. */ | ||
| 202 | - if (s->phy_control & 0x4000) { | ||
| 203 | + if (s->mii.control & 0x4000) { | ||
| 204 | /* This assumes the receive routine doesn't touch the VLANClient. */ | ||
| 205 | qemu_receive_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len); | ||
| 206 | } else { | ||
| 207 | @@ -XXX,XX +XXX,XX @@ static void tx_fifo_push(lan9118_state *s, uint32_t val) | ||
| 208 | } | ||
| 209 | } | ||
| 210 | |||
| 211 | -static uint32_t do_phy_read(lan9118_state *s, int reg) | ||
| 212 | -{ | ||
| 213 | - uint32_t val; | ||
| 214 | - | ||
| 215 | - switch (reg) { | ||
| 216 | - case 0: /* Basic Control */ | ||
| 217 | - return s->phy_control; | ||
| 218 | - case 1: /* Basic Status */ | ||
| 219 | - return s->phy_status; | ||
| 220 | - case 2: /* ID1 */ | ||
| 221 | - return 0x0007; | ||
| 222 | - case 3: /* ID2 */ | ||
| 223 | - return 0xc0d1; | ||
| 224 | - case 4: /* Auto-neg advertisement */ | ||
| 225 | - return s->phy_advertise; | ||
| 226 | - case 5: /* Auto-neg Link Partner Ability */ | ||
| 227 | - return 0x0f71; | ||
| 228 | - case 6: /* Auto-neg Expansion */ | ||
| 229 | - return 1; | ||
| 230 | - /* TODO 17, 18, 27, 29, 30, 31 */ | ||
| 231 | - case 29: /* Interrupt source. */ | ||
| 232 | - val = s->phy_int; | ||
| 233 | - s->phy_int = 0; | ||
| 234 | - phy_update_irq(s); | ||
| 235 | - return val; | ||
| 236 | - case 30: /* Interrupt mask */ | ||
| 237 | - return s->phy_int_mask; | ||
| 238 | - default: | ||
| 239 | - qemu_log_mask(LOG_GUEST_ERROR, | ||
| 240 | - "do_phy_read: PHY read reg %d\n", reg); | ||
| 241 | - return 0; | ||
| 242 | - } | ||
| 243 | -} | ||
| 244 | - | ||
| 245 | -static void do_phy_write(lan9118_state *s, int reg, uint32_t val) | ||
| 246 | -{ | ||
| 247 | - switch (reg) { | ||
| 248 | - case 0: /* Basic Control */ | ||
| 249 | - if (val & 0x8000) { | ||
| 250 | - phy_reset(s); | ||
| 251 | - break; | ||
| 252 | - } | ||
| 253 | - s->phy_control = val & 0x7980; | ||
| 254 | - /* Complete autonegotiation immediately. */ | ||
| 255 | - if (val & 0x1000) { | ||
| 256 | - s->phy_status |= 0x0020; | ||
| 257 | - } | ||
| 258 | - break; | ||
| 259 | - case 4: /* Auto-neg advertisement */ | ||
| 260 | - s->phy_advertise = (val & 0x2d7f) | 0x80; | ||
| 261 | - break; | ||
| 262 | - /* TODO 17, 18, 27, 31 */ | ||
| 263 | - case 30: /* Interrupt mask */ | ||
| 264 | - s->phy_int_mask = val & 0xff; | ||
| 265 | - phy_update_irq(s); | ||
| 266 | - break; | ||
| 267 | - default: | ||
| 268 | - qemu_log_mask(LOG_GUEST_ERROR, | ||
| 269 | - "do_phy_write: PHY write reg %d = 0x%04x\n", reg, val); | ||
| 270 | - } | ||
| 271 | -} | ||
| 272 | - | ||
| 273 | static void do_mac_write(lan9118_state *s, int reg, uint32_t val) | ||
| 274 | { | ||
| 275 | switch (reg) { | ||
| 276 | @@ -XXX,XX +XXX,XX @@ static void do_mac_write(lan9118_state *s, int reg, uint32_t val) | ||
| 277 | if (val & 2) { | ||
| 278 | DPRINTF("PHY write %d = 0x%04x\n", | ||
| 279 | (val >> 6) & 0x1f, s->mac_mii_data); | ||
| 280 | - do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data); | ||
| 281 | + lan9118_phy_write(&s->mii, (val >> 6) & 0x1f, s->mac_mii_data); | ||
| 282 | } else { | ||
| 283 | - s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f); | ||
| 284 | + s->mac_mii_data = lan9118_phy_read(&s->mii, (val >> 6) & 0x1f); | ||
| 285 | DPRINTF("PHY read %d = 0x%04x\n", | ||
| 286 | (val >> 6) & 0x1f, s->mac_mii_data); | ||
| 287 | } | ||
| 288 | @@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset, | ||
| 289 | break; | ||
| 290 | case CSR_PMT_CTRL: | ||
| 291 | if (val & 0x400) { | ||
| 292 | - phy_reset(s); | ||
| 293 | + lan9118_phy_reset(&s->mii); | ||
| 294 | } | ||
| 295 | s->pmt_ctrl &= ~0x34e; | ||
| 296 | s->pmt_ctrl |= (val & 0x34e); | ||
| 297 | @@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp) | ||
| 298 | const MemoryRegionOps *mem_ops = | ||
| 299 | s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops; | ||
| 300 | |||
| 301 | + qemu_init_irq(&s->mii_irq, lan9118_update_irq, s, 0); | ||
| 302 | + object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY); | ||
| 303 | + if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) { | ||
| 304 | + return; | ||
| 305 | + } | ||
| 306 | + qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq); | ||
| 307 | + | ||
| 308 | memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s, | ||
| 309 | "lan9118-mmio", 0x100); | ||
| 310 | sysbus_init_mmio(sbd, &s->mmio); | ||
| 311 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c | ||
| 312 | new file mode 100644 | ||
| 313 | index XXXXXXX..XXXXXXX | ||
| 314 | --- /dev/null | ||
| 315 | +++ b/hw/net/lan9118_phy.c | ||
| 316 | @@ -XXX,XX +XXX,XX @@ | ||
| 317 | +/* | ||
| 318 | + * SMSC LAN9118 PHY emulation | ||
| 319 | + * | ||
| 320 | + * Copyright (c) 2009 CodeSourcery, LLC. | ||
| 321 | + * Written by Paul Brook | ||
| 322 | + * | ||
| 323 | + * This code is licensed under the GNU GPL v2 | ||
| 324 | + * | ||
| 325 | + * Contributions after 2012-01-13 are licensed under the terms of the | ||
| 326 | + * GNU GPL, version 2 or (at your option) any later version. | ||
| 327 | + */ | ||
| 328 | + | ||
| 329 | +#include "qemu/osdep.h" | ||
| 330 | +#include "hw/net/lan9118_phy.h" | ||
| 331 | +#include "hw/irq.h" | ||
| 332 | +#include "hw/resettable.h" | ||
| 333 | +#include "migration/vmstate.h" | ||
| 334 | +#include "qemu/log.h" | ||
| 335 | + | ||
| 336 | +#define PHY_INT_ENERGYON (1 << 7) | ||
| 337 | +#define PHY_INT_AUTONEG_COMPLETE (1 << 6) | ||
| 338 | +#define PHY_INT_FAULT (1 << 5) | ||
| 339 | +#define PHY_INT_DOWN (1 << 4) | ||
| 340 | +#define PHY_INT_AUTONEG_LP (1 << 3) | ||
| 341 | +#define PHY_INT_PARFAULT (1 << 2) | ||
| 342 | +#define PHY_INT_AUTONEG_PAGE (1 << 1) | ||
| 343 | + | ||
| 344 | +static void lan9118_phy_update_irq(Lan9118PhyState *s) | ||
| 345 | +{ | ||
| 346 | + qemu_set_irq(s->irq, !!(s->ints & s->int_mask)); | ||
| 347 | +} | ||
| 348 | + | ||
| 349 | +uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) | ||
| 350 | +{ | ||
| 351 | + uint16_t val; | ||
| 352 | + | ||
| 353 | + switch (reg) { | ||
| 354 | + case 0: /* Basic Control */ | ||
| 355 | + return s->control; | ||
| 356 | + case 1: /* Basic Status */ | ||
| 357 | + return s->status; | ||
| 358 | + case 2: /* ID1 */ | ||
| 359 | + return 0x0007; | ||
| 360 | + case 3: /* ID2 */ | ||
| 361 | + return 0xc0d1; | ||
| 362 | + case 4: /* Auto-neg advertisement */ | ||
| 363 | + return s->advertise; | ||
| 364 | + case 5: /* Auto-neg Link Partner Ability */ | ||
| 365 | + return 0x0f71; | ||
| 366 | + case 6: /* Auto-neg Expansion */ | ||
| 367 | + return 1; | ||
| 368 | + /* TODO 17, 18, 27, 29, 30, 31 */ | ||
| 369 | + case 29: /* Interrupt source. */ | ||
| 370 | + val = s->ints; | ||
| 371 | + s->ints = 0; | ||
| 372 | + lan9118_phy_update_irq(s); | ||
| 373 | + return val; | ||
| 374 | + case 30: /* Interrupt mask */ | ||
| 375 | + return s->int_mask; | ||
| 376 | + default: | ||
| 377 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
| 378 | + "lan9118_phy_read: PHY read reg %d\n", reg); | ||
| 379 | + return 0; | ||
| 380 | + } | ||
| 381 | +} | ||
| 382 | + | ||
| 383 | +void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) | ||
| 384 | +{ | ||
| 385 | + switch (reg) { | ||
| 386 | + case 0: /* Basic Control */ | ||
| 387 | + if (val & 0x8000) { | ||
| 388 | + lan9118_phy_reset(s); | ||
| 389 | + break; | ||
| 390 | + } | ||
| 391 | + s->control = val & 0x7980; | ||
| 392 | + /* Complete autonegotiation immediately. */ | ||
| 393 | + if (val & 0x1000) { | ||
| 394 | + s->status |= 0x0020; | ||
| 395 | + } | ||
| 396 | + break; | ||
| 397 | + case 4: /* Auto-neg advertisement */ | ||
| 398 | + s->advertise = (val & 0x2d7f) | 0x80; | ||
| 399 | + break; | ||
| 400 | + /* TODO 17, 18, 27, 31 */ | ||
| 401 | + case 30: /* Interrupt mask */ | ||
| 402 | + s->int_mask = val & 0xff; | ||
| 403 | + lan9118_phy_update_irq(s); | ||
| 404 | + break; | ||
| 405 | + default: | ||
| 406 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
| 407 | + "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val); | ||
| 408 | + } | ||
| 409 | +} | ||
| 410 | + | ||
| 411 | +void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) | ||
| 412 | +{ | ||
| 413 | + s->link_down = link_down; | ||
| 414 | + | ||
| 415 | + /* Autonegotiation status mirrors link status. */ | ||
| 416 | + if (link_down) { | ||
| 417 | + s->status &= ~0x0024; | ||
| 418 | + s->ints |= PHY_INT_DOWN; | ||
| 419 | + } else { | ||
| 420 | + s->status |= 0x0024; | ||
| 421 | + s->ints |= PHY_INT_ENERGYON; | ||
| 422 | + s->ints |= PHY_INT_AUTONEG_COMPLETE; | ||
| 423 | + } | ||
| 424 | + lan9118_phy_update_irq(s); | ||
| 425 | +} | ||
| 426 | + | ||
| 427 | +void lan9118_phy_reset(Lan9118PhyState *s) | ||
| 428 | +{ | ||
| 429 | + s->control = 0x3000; | ||
| 430 | + s->status = 0x7809; | ||
| 431 | + s->advertise = 0x01e1; | ||
| 432 | + s->int_mask = 0; | ||
| 433 | + s->ints = 0; | ||
| 434 | + lan9118_phy_update_link(s, s->link_down); | ||
| 435 | +} | ||
| 436 | + | ||
| 437 | +static void lan9118_phy_reset_hold(Object *obj, ResetType type) | ||
| 438 | +{ | ||
| 439 | + Lan9118PhyState *s = LAN9118_PHY(obj); | ||
| 440 | + | ||
| 441 | + lan9118_phy_reset(s); | ||
| 442 | +} | ||
| 443 | + | ||
| 444 | +static void lan9118_phy_init(Object *obj) | ||
| 445 | +{ | ||
| 446 | + Lan9118PhyState *s = LAN9118_PHY(obj); | ||
| 447 | + | ||
| 448 | + qdev_init_gpio_out(DEVICE(s), &s->irq, 1); | ||
| 449 | +} | ||
| 450 | + | ||
| 451 | +static const VMStateDescription vmstate_lan9118_phy = { | ||
| 452 | + .name = "lan9118-phy", | ||
| 453 | + .version_id = 1, | ||
| 454 | + .minimum_version_id = 1, | ||
| 455 | + .fields = (const VMStateField[]) { | ||
| 456 | + VMSTATE_UINT16(control, Lan9118PhyState), | ||
| 457 | + VMSTATE_UINT16(status, Lan9118PhyState), | ||
| 458 | + VMSTATE_UINT16(advertise, Lan9118PhyState), | ||
| 459 | + VMSTATE_UINT16(ints, Lan9118PhyState), | ||
| 460 | + VMSTATE_UINT16(int_mask, Lan9118PhyState), | ||
| 461 | + VMSTATE_BOOL(link_down, Lan9118PhyState), | ||
| 462 | + VMSTATE_END_OF_LIST() | ||
| 463 | + } | ||
| 464 | +}; | ||
| 465 | + | ||
| 466 | +static void lan9118_phy_class_init(ObjectClass *klass, void *data) | ||
| 467 | +{ | ||
| 468 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
| 469 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 470 | + | ||
| 471 | + rc->phases.hold = lan9118_phy_reset_hold; | ||
| 472 | + dc->vmsd = &vmstate_lan9118_phy; | ||
| 473 | +} | ||
| 474 | + | ||
| 475 | +static const TypeInfo types[] = { | ||
| 476 | + { | ||
| 477 | + .name = TYPE_LAN9118_PHY, | ||
| 478 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
| 479 | + .instance_size = sizeof(Lan9118PhyState), | ||
| 480 | + .instance_init = lan9118_phy_init, | ||
| 481 | + .class_init = lan9118_phy_class_init, | ||
| 482 | + } | ||
| 483 | +}; | ||
| 484 | + | ||
| 485 | +DEFINE_TYPES(types) | ||
| 486 | diff --git a/hw/net/Kconfig b/hw/net/Kconfig | ||
| 487 | index XXXXXXX..XXXXXXX 100644 | ||
| 488 | --- a/hw/net/Kconfig | ||
| 489 | +++ b/hw/net/Kconfig | ||
| 490 | @@ -XXX,XX +XXX,XX @@ config VMXNET3_PCI | ||
| 491 | config SMC91C111 | ||
| 492 | bool | ||
| 493 | |||
| 494 | +config LAN9118_PHY | ||
| 495 | + bool | ||
| 496 | + | ||
| 497 | config LAN9118 | ||
| 498 | bool | ||
| 499 | + select LAN9118_PHY | ||
| 500 | select PTIMER | ||
| 501 | |||
| 502 | config NE2000_ISA | ||
| 503 | diff --git a/hw/net/meson.build b/hw/net/meson.build | ||
| 504 | index XXXXXXX..XXXXXXX 100644 | ||
| 505 | --- a/hw/net/meson.build | ||
| 506 | +++ b/hw/net/meson.build | ||
| 507 | @@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_VMXNET3_PCI', if_true: files('vmxnet3.c')) | ||
| 508 | |||
| 509 | system_ss.add(when: 'CONFIG_SMC91C111', if_true: files('smc91c111.c')) | ||
| 510 | system_ss.add(when: 'CONFIG_LAN9118', if_true: files('lan9118.c')) | ||
| 511 | +system_ss.add(when: 'CONFIG_LAN9118_PHY', if_true: files('lan9118_phy.c')) | ||
| 512 | system_ss.add(when: 'CONFIG_NE2000_ISA', if_true: files('ne2000-isa.c')) | ||
| 513 | system_ss.add(when: 'CONFIG_OPENCORES_ETH', if_true: files('opencores_eth.c')) | ||
| 514 | system_ss.add(when: 'CONFIG_XGMAC', if_true: files('xgmac.c')) | ||
| 23 | -- | 515 | -- |
| 24 | 2.34.1 | 516 | 2.34.1 | diff view generated by jsdifflib |
| 1 | Use device_class_set_legacy_reset() instead of opencoding an | 1 | From: Bernhard Beschow <shentey@gmail.com> |
|---|---|---|---|
| 2 | assignment to DeviceClass::reset. This change was produced | ||
| 3 | with: | ||
| 4 | spatch --macro-file scripts/cocci-macro-file.h \ | ||
| 5 | --sp-file scripts/coccinelle/device-reset.cocci \ | ||
| 6 | --keep-comments --smpl-spacing --in-place --dir hw | ||
| 7 | 2 | ||
| 3 | imx_fec models the same PHY as lan9118_phy. The code is almost the same with | ||
| 4 | imx_fec having more logging and tracing. Merge these improvements into | ||
| 5 | lan9118_phy and reuse in imx_fec to fix the code duplication. | ||
| 6 | |||
| 7 | Some migration state how resides in the new device model which breaks migration | ||
| 8 | compatibility for the following machines: | ||
| 9 | * imx25-pdk | ||
| 10 | * sabrelite | ||
| 11 | * mcimx7d-sabre | ||
| 12 | * mcimx6ul-evk | ||
| 13 | |||
| 14 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> | ||
| 15 | Tested-by: Guenter Roeck <linux@roeck-us.net> | ||
| 16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 17 | Message-id: 20241102125724.532843-3-shentey@gmail.com | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 10 | Message-id: 20240830145812.1967042-8-peter.maydell@linaro.org | ||
| 11 | --- | 19 | --- |
| 12 | hw/acpi/erst.c | 2 +- | 20 | include/hw/net/imx_fec.h | 9 ++- |
| 13 | hw/acpi/piix4.c | 2 +- | 21 | hw/net/imx_fec.c | 146 ++++----------------------------------- |
| 14 | hw/adc/aspeed_adc.c | 2 +- | 22 | hw/net/lan9118_phy.c | 82 ++++++++++++++++------ |
| 15 | hw/adc/max111x.c | 2 +- | 23 | hw/net/Kconfig | 1 + |
| 16 | hw/adc/stm32f2xx_adc.c | 2 +- | 24 | hw/net/trace-events | 10 +-- |
| 17 | hw/adc/zynq-xadc.c | 2 +- | 25 | 5 files changed, 85 insertions(+), 163 deletions(-) |
| 18 | hw/arm/armsse.c | 2 +- | ||
| 19 | hw/arm/highbank.c | 2 +- | ||
| 20 | hw/arm/musicpal.c | 6 +++--- | ||
| 21 | hw/arm/pxa2xx.c | 4 ++-- | ||
| 22 | hw/arm/strongarm.c | 4 ++-- | ||
| 23 | hw/audio/ac97.c | 2 +- | ||
| 24 | hw/audio/cs4231.c | 2 +- | ||
| 25 | hw/audio/cs4231a.c | 2 +- | ||
| 26 | hw/audio/es1370.c | 2 +- | ||
| 27 | hw/audio/hda-codec.c | 2 +- | ||
| 28 | hw/audio/intel-hda.c | 2 +- | ||
| 29 | hw/audio/marvell_88w8618.c | 2 +- | ||
| 30 | hw/audio/pl041.c | 2 +- | ||
| 31 | hw/audio/via-ac97.c | 2 +- | ||
| 32 | hw/block/fdc-isa.c | 2 +- | ||
| 33 | hw/block/fdc-sysbus.c | 2 +- | ||
| 34 | hw/block/m25p80.c | 2 +- | ||
| 35 | hw/block/nand.c | 2 +- | ||
| 36 | hw/block/onenand.c | 2 +- | ||
| 37 | hw/block/pflash_cfi01.c | 2 +- | ||
| 38 | hw/block/pflash_cfi02.c | 2 +- | ||
| 39 | hw/block/swim.c | 2 +- | ||
| 40 | hw/char/avr_usart.c | 2 +- | ||
| 41 | hw/char/cmsdk-apb-uart.c | 2 +- | ||
| 42 | hw/char/digic-uart.c | 2 +- | ||
| 43 | hw/char/escc.c | 2 +- | ||
| 44 | hw/char/etraxfs_ser.c | 2 +- | ||
| 45 | hw/char/exynos4210_uart.c | 2 +- | ||
| 46 | hw/char/goldfish_tty.c | 2 +- | ||
| 47 | hw/char/grlib_apbuart.c | 2 +- | ||
| 48 | hw/char/ibex_uart.c | 2 +- | ||
| 49 | hw/char/imx_serial.c | 2 +- | ||
| 50 | hw/char/mcf_uart.c | 2 +- | ||
| 51 | hw/char/mchp_pfsoc_mmuart.c | 2 +- | ||
| 52 | hw/char/nrf51_uart.c | 2 +- | ||
| 53 | hw/char/pl011.c | 2 +- | ||
| 54 | hw/char/renesas_sci.c | 2 +- | ||
| 55 | hw/char/sclpconsole-lm.c | 2 +- | ||
| 56 | hw/char/sclpconsole.c | 2 +- | ||
| 57 | hw/char/sh_serial.c | 2 +- | ||
| 58 | hw/char/shakti_uart.c | 2 +- | ||
| 59 | hw/char/stm32f2xx_usart.c | 2 +- | ||
| 60 | hw/char/xilinx_uartlite.c | 2 +- | ||
| 61 | hw/core/or-irq.c | 2 +- | ||
| 62 | hw/core/qdev.c | 2 +- | ||
| 63 | hw/cxl/switch-mailbox-cci.c | 2 +- | ||
| 64 | hw/display/artist.c | 2 +- | ||
| 65 | hw/display/ati.c | 2 +- | ||
| 66 | hw/display/bcm2835_fb.c | 2 +- | ||
| 67 | hw/display/cg3.c | 2 +- | ||
| 68 | hw/display/dpcd.c | 2 +- | ||
| 69 | hw/display/exynos4210_fimd.c | 2 +- | ||
| 70 | hw/display/g364fb.c | 2 +- | ||
| 71 | hw/display/i2c-ddc.c | 2 +- | ||
| 72 | hw/display/jazz_led.c | 2 +- | ||
| 73 | hw/display/macfb.c | 4 ++-- | ||
| 74 | hw/display/qxl.c | 2 +- | ||
| 75 | hw/display/sii9022.c | 2 +- | ||
| 76 | hw/display/sm501.c | 4 ++-- | ||
| 77 | hw/display/tcx.c | 2 +- | ||
| 78 | hw/display/vga-isa.c | 2 +- | ||
| 79 | hw/display/vga-mmio.c | 2 +- | ||
| 80 | hw/display/vga-pci.c | 2 +- | ||
| 81 | hw/display/vmware_vga.c | 2 +- | ||
| 82 | hw/display/xlnx_dp.c | 2 +- | ||
| 83 | hw/dma/bcm2835_dma.c | 2 +- | ||
| 84 | hw/dma/i8257.c | 2 +- | ||
| 85 | hw/dma/pl080.c | 2 +- | ||
| 86 | hw/dma/pl330.c | 2 +- | ||
| 87 | hw/dma/rc4030.c | 2 +- | ||
| 88 | hw/dma/sparc32_dma.c | 2 +- | ||
| 89 | hw/dma/xilinx_axidma.c | 2 +- | ||
| 90 | hw/dma/xlnx-zdma.c | 2 +- | ||
| 91 | hw/dma/xlnx-zynq-devcfg.c | 2 +- | ||
| 92 | hw/dma/xlnx_csu_dma.c | 2 +- | ||
| 93 | hw/dma/xlnx_dpdma.c | 2 +- | ||
| 94 | hw/fsi/aspeed_apb2opb.c | 2 +- | ||
| 95 | hw/fsi/fsi-master.c | 2 +- | ||
| 96 | hw/fsi/fsi.c | 2 +- | ||
| 97 | hw/fsi/lbus.c | 2 +- | ||
| 98 | hw/gpio/aspeed_gpio.c | 2 +- | ||
| 99 | hw/gpio/bcm2835_gpio.c | 2 +- | ||
| 100 | hw/gpio/bcm2838_gpio.c | 2 +- | ||
| 101 | hw/gpio/gpio_key.c | 2 +- | ||
| 102 | hw/gpio/imx_gpio.c | 2 +- | ||
| 103 | hw/gpio/max7310.c | 2 +- | ||
| 104 | hw/gpio/mpc8xxx.c | 2 +- | ||
| 105 | hw/gpio/nrf51_gpio.c | 2 +- | ||
| 106 | hw/gpio/omap_gpio.c | 4 ++-- | ||
| 107 | hw/gpio/pca9552.c | 2 +- | ||
| 108 | hw/gpio/pca9554.c | 2 +- | ||
| 109 | hw/gpio/pcf8574.c | 2 +- | ||
| 110 | hw/gpio/sifive_gpio.c | 2 +- | ||
| 111 | hw/hyperv/hyperv.c | 2 +- | ||
| 112 | hw/hyperv/vmbus.c | 2 +- | ||
| 113 | hw/i2c/aspeed_i2c.c | 4 ++-- | ||
| 114 | hw/i2c/bcm2835_i2c.c | 2 +- | ||
| 115 | hw/i2c/exynos4210_i2c.c | 2 +- | ||
| 116 | hw/i2c/imx_i2c.c | 2 +- | ||
| 117 | hw/i2c/microbit_i2c.c | 2 +- | ||
| 118 | hw/i2c/mpc_i2c.c | 2 +- | ||
| 119 | hw/i2c/omap_i2c.c | 2 +- | ||
| 120 | hw/i2c/ppc4xx_i2c.c | 2 +- | ||
| 121 | hw/i2c/smbus_eeprom.c | 2 +- | ||
| 122 | hw/i386/amd_iommu.c | 2 +- | ||
| 123 | hw/i386/intel_iommu.c | 2 +- | ||
| 124 | hw/i386/kvm/i8254.c | 2 +- | ||
| 125 | hw/i386/kvm/i8259.c | 2 +- | ||
| 126 | hw/i386/kvm/ioapic.c | 2 +- | ||
| 127 | hw/i386/kvm/xen_overlay.c | 2 +- | ||
| 128 | hw/i386/port92.c | 2 +- | ||
| 129 | hw/i386/vapic.c | 2 +- | ||
| 130 | hw/i386/vmmouse.c | 2 +- | ||
| 131 | hw/i386/xen/xen_platform.c | 2 +- | ||
| 132 | hw/ide/ahci.c | 2 +- | ||
| 133 | hw/ide/cmd646.c | 2 +- | ||
| 134 | hw/ide/ich.c | 2 +- | ||
| 135 | hw/ide/isa.c | 2 +- | ||
| 136 | hw/ide/macio.c | 2 +- | ||
| 137 | hw/ide/microdrive.c | 2 +- | ||
| 138 | hw/ide/mmio.c | 2 +- | ||
| 139 | hw/ide/piix.c | 4 ++-- | ||
| 140 | hw/ide/sii3112.c | 2 +- | ||
| 141 | hw/ide/via.c | 2 +- | ||
| 142 | hw/input/adb-kbd.c | 2 +- | ||
| 143 | hw/input/adb-mouse.c | 2 +- | ||
| 144 | hw/input/lm832x.c | 2 +- | ||
| 145 | hw/input/pckbd.c | 4 ++-- | ||
| 146 | hw/intc/allwinner-a10-pic.c | 2 +- | ||
| 147 | hw/intc/apic_common.c | 2 +- | ||
| 148 | hw/intc/armv7m_nvic.c | 2 +- | ||
| 149 | hw/intc/aspeed_intc.c | 2 +- | ||
| 150 | hw/intc/aspeed_vic.c | 2 +- | ||
| 151 | hw/intc/bcm2835_ic.c | 2 +- | ||
| 152 | hw/intc/bcm2836_control.c | 2 +- | ||
| 153 | hw/intc/exynos4210_combiner.c | 2 +- | ||
| 154 | hw/intc/goldfish_pic.c | 2 +- | ||
| 155 | hw/intc/grlib_irqmp.c | 2 +- | ||
| 156 | hw/intc/heathrow_pic.c | 2 +- | ||
| 157 | hw/intc/i8259.c | 2 +- | ||
| 158 | hw/intc/imx_avic.c | 2 +- | ||
| 159 | hw/intc/imx_gpcv2.c | 2 +- | ||
| 160 | hw/intc/ioapic.c | 2 +- | ||
| 161 | hw/intc/loongarch_extioi.c | 2 +- | ||
| 162 | hw/intc/loongarch_pch_pic.c | 2 +- | ||
| 163 | hw/intc/m68k_irqc.c | 2 +- | ||
| 164 | hw/intc/omap_intc.c | 4 ++-- | ||
| 165 | hw/intc/openpic.c | 2 +- | ||
| 166 | hw/intc/openpic_kvm.c | 2 +- | ||
| 167 | hw/intc/pl190.c | 2 +- | ||
| 168 | hw/intc/ppc-uic.c | 2 +- | ||
| 169 | hw/intc/s390_flic.c | 2 +- | ||
| 170 | hw/intc/s390_flic_kvm.c | 2 +- | ||
| 171 | hw/intc/sifive_plic.c | 2 +- | ||
| 172 | hw/intc/slavio_intctl.c | 2 +- | ||
| 173 | hw/intc/xlnx-pmu-iomod-intc.c | 2 +- | ||
| 174 | hw/intc/xlnx-zynqmp-ipi.c | 2 +- | ||
| 175 | hw/isa/lpc_ich9.c | 2 +- | ||
| 176 | hw/isa/pc87312.c | 2 +- | ||
| 177 | hw/isa/piix.c | 2 +- | ||
| 178 | hw/isa/vt82c686.c | 10 +++++----- | ||
| 179 | hw/m68k/mcf5206.c | 2 +- | ||
| 180 | hw/m68k/mcf_intc.c | 2 +- | ||
| 181 | hw/m68k/next-cube.c | 2 +- | ||
| 182 | hw/m68k/next-kbd.c | 2 +- | ||
| 183 | hw/mem/cxl_type3.c | 2 +- | ||
| 184 | hw/misc/a9scu.c | 2 +- | ||
| 185 | hw/misc/allwinner-cpucfg.c | 2 +- | ||
| 186 | hw/misc/allwinner-h3-ccu.c | 2 +- | ||
| 187 | hw/misc/allwinner-h3-dramc.c | 2 +- | ||
| 188 | hw/misc/allwinner-h3-sysctrl.c | 2 +- | ||
| 189 | hw/misc/allwinner-r40-ccu.c | 2 +- | ||
| 190 | hw/misc/allwinner-r40-dramc.c | 2 +- | ||
| 191 | hw/misc/allwinner-sid.c | 2 +- | ||
| 192 | hw/misc/allwinner-sramc.c | 2 +- | ||
| 193 | hw/misc/applesmc.c | 2 +- | ||
| 194 | hw/misc/arm_l2x0.c | 2 +- | ||
| 195 | hw/misc/arm_sysctl.c | 2 +- | ||
| 196 | hw/misc/armsse-cpu-pwrctrl.c | 2 +- | ||
| 197 | hw/misc/armsse-mhu.c | 2 +- | ||
| 198 | hw/misc/aspeed_hace.c | 2 +- | ||
| 199 | hw/misc/aspeed_i3c.c | 4 ++-- | ||
| 200 | hw/misc/aspeed_lpc.c | 2 +- | ||
| 201 | hw/misc/aspeed_peci.c | 2 +- | ||
| 202 | hw/misc/aspeed_sbc.c | 2 +- | ||
| 203 | hw/misc/aspeed_scu.c | 10 +++++----- | ||
| 204 | hw/misc/aspeed_sdmc.c | 4 ++-- | ||
| 205 | hw/misc/aspeed_xdma.c | 2 +- | ||
| 206 | hw/misc/avr_power.c | 2 +- | ||
| 207 | hw/misc/bcm2835_cprman.c | 8 ++++---- | ||
| 208 | hw/misc/bcm2835_mbox.c | 2 +- | ||
| 209 | hw/misc/bcm2835_mphi.c | 2 +- | ||
| 210 | hw/misc/bcm2835_powermgt.c | 2 +- | ||
| 211 | hw/misc/bcm2835_rng.c | 2 +- | ||
| 212 | hw/misc/bcm2835_thermal.c | 2 +- | ||
| 213 | hw/misc/eccmemctl.c | 2 +- | ||
| 214 | hw/misc/exynos4210_clk.c | 2 +- | ||
| 215 | hw/misc/exynos4210_pmu.c | 2 +- | ||
| 216 | hw/misc/exynos4210_rng.c | 2 +- | ||
| 217 | hw/misc/imx25_ccm.c | 2 +- | ||
| 218 | hw/misc/imx31_ccm.c | 2 +- | ||
| 219 | hw/misc/imx6_ccm.c | 2 +- | ||
| 220 | hw/misc/imx6_src.c | 2 +- | ||
| 221 | hw/misc/imx6ul_ccm.c | 2 +- | ||
| 222 | hw/misc/imx7_ccm.c | 4 ++-- | ||
| 223 | hw/misc/imx7_snvs.c | 2 +- | ||
| 224 | hw/misc/imx7_src.c | 2 +- | ||
| 225 | hw/misc/imx_rngc.c | 2 +- | ||
| 226 | hw/misc/iotkit-secctl.c | 2 +- | ||
| 227 | hw/misc/iotkit-sysctl.c | 2 +- | ||
| 228 | hw/misc/ivshmem.c | 2 +- | ||
| 229 | hw/misc/lasi.c | 2 +- | ||
| 230 | hw/misc/led.c | 2 +- | ||
| 231 | hw/misc/macio/cuda.c | 2 +- | ||
| 232 | hw/misc/macio/gpio.c | 2 +- | ||
| 233 | hw/misc/macio/mac_dbdma.c | 2 +- | ||
| 234 | hw/misc/macio/pmu.c | 2 +- | ||
| 235 | hw/misc/mips_cmgcr.c | 2 +- | ||
| 236 | hw/misc/mips_cpc.c | 2 +- | ||
| 237 | hw/misc/mips_itu.c | 2 +- | ||
| 238 | hw/misc/mps2-fpgaio.c | 2 +- | ||
| 239 | hw/misc/mps2-scc.c | 2 +- | ||
| 240 | hw/misc/msf2-sysreg.c | 2 +- | ||
| 241 | hw/misc/nrf51_rng.c | 2 +- | ||
| 242 | hw/misc/pci-testdev.c | 2 +- | ||
| 243 | hw/misc/sifive_e_aon.c | 2 +- | ||
| 244 | hw/misc/sifive_u_prci.c | 2 +- | ||
| 245 | hw/misc/slavio_misc.c | 2 +- | ||
| 246 | hw/misc/stm32f2xx_syscfg.c | 2 +- | ||
| 247 | hw/misc/stm32f4xx_exti.c | 2 +- | ||
| 248 | hw/misc/stm32f4xx_syscfg.c | 2 +- | ||
| 249 | hw/misc/tz-mpc.c | 2 +- | ||
| 250 | hw/misc/tz-msc.c | 2 +- | ||
| 251 | hw/misc/tz-ppc.c | 2 +- | ||
| 252 | hw/misc/virt_ctrl.c | 2 +- | ||
| 253 | hw/misc/xlnx-versal-cfu.c | 2 +- | ||
| 254 | hw/net/allwinner-sun8i-emac.c | 2 +- | ||
| 255 | hw/net/allwinner_emac.c | 2 +- | ||
| 256 | hw/net/cadence_gem.c | 2 +- | ||
| 257 | hw/net/can/can_kvaser_pci.c | 2 +- | ||
| 258 | hw/net/can/can_mioe3680_pci.c | 2 +- | ||
| 259 | hw/net/can/can_pcm3680_pci.c | 2 +- | ||
| 260 | hw/net/can/ctucan_pci.c | 2 +- | ||
| 261 | hw/net/can/xlnx-versal-canfd.c | 2 +- | ||
| 262 | hw/net/dp8393x.c | 2 +- | ||
| 263 | hw/net/etraxfs_eth.c | 2 +- | ||
| 264 | hw/net/fsl_etsec/etsec.c | 2 +- | ||
| 265 | hw/net/ftgmac100.c | 4 ++-- | ||
| 266 | hw/net/imx_fec.c | 2 +- | ||
| 267 | hw/net/lan9118.c | 2 +- | ||
| 268 | hw/net/lance.c | 2 +- | ||
| 269 | hw/net/lasi_i82596.c | 2 +- | ||
| 270 | hw/net/mcf_fec.c | 2 +- | ||
| 271 | hw/net/mipsnet.c | 2 +- | ||
| 272 | hw/net/msf2-emac.c | 2 +- | ||
| 273 | hw/net/npcm7xx_emc.c | 2 +- | ||
| 274 | hw/net/npcm_gmac.c | 2 +- | ||
| 275 | hw/net/opencores_eth.c | 2 +- | ||
| 276 | hw/net/pcnet-pci.c | 2 +- | ||
| 277 | hw/net/rocker/rocker.c | 2 +- | ||
| 278 | hw/net/rtl8139.c | 2 +- | ||
| 279 | hw/net/smc91c111.c | 2 +- | ||
| 280 | hw/net/stellaris_enet.c | 2 +- | ||
| 281 | hw/net/sungem.c | 2 +- | ||
| 282 | hw/net/sunhme.c | 2 +- | ||
| 283 | hw/net/tulip.c | 2 +- | ||
| 284 | hw/net/vmxnet3.c | 2 +- | ||
| 285 | hw/net/xilinx_axienet.c | 2 +- | ||
| 286 | hw/net/xilinx_ethlite.c | 2 +- | ||
| 287 | hw/nvme/ctrl.c | 2 +- | ||
| 288 | hw/nvram/eeprom_at24c.c | 2 +- | ||
| 289 | hw/nvram/fw_cfg.c | 2 +- | ||
| 290 | hw/nvram/mac_nvram.c | 2 +- | ||
| 291 | hw/nvram/nrf51_nvm.c | 2 +- | ||
| 292 | hw/pci-bridge/cxl_downstream.c | 2 +- | ||
| 293 | hw/pci-bridge/cxl_upstream.c | 2 +- | ||
| 294 | hw/pci-bridge/i82801b11.c | 2 +- | ||
| 295 | hw/pci-bridge/pci_bridge_dev.c | 2 +- | ||
| 296 | hw/pci-bridge/pci_expander_bridge.c | 2 +- | ||
| 297 | hw/pci-bridge/pcie_pci_bridge.c | 2 +- | ||
| 298 | hw/pci-bridge/simba.c | 2 +- | ||
| 299 | hw/pci-bridge/xio3130_downstream.c | 2 +- | ||
| 300 | hw/pci-bridge/xio3130_upstream.c | 2 +- | ||
| 301 | hw/pci-host/astro.c | 4 ++-- | ||
| 302 | hw/pci-host/designware.c | 2 +- | ||
| 303 | hw/pci-host/dino.c | 2 +- | ||
| 304 | hw/pci-host/gt64120.c | 2 +- | ||
| 305 | hw/pci-host/mv64361.c | 2 +- | ||
| 306 | hw/pci-host/ppc440_pcix.c | 2 +- | ||
| 307 | hw/pci-host/q35.c | 2 +- | ||
| 308 | hw/pci-host/sabre.c | 2 +- | ||
| 309 | hw/pci-host/versatile.c | 2 +- | ||
| 310 | hw/pci-host/xilinx-pcie.c | 2 +- | ||
| 311 | hw/ppc/pnv_psi.c | 4 ++-- | ||
| 312 | hw/ppc/ppc405_boards.c | 2 +- | ||
| 313 | hw/ppc/ppc405_uc.c | 12 ++++++------ | ||
| 314 | hw/ppc/ppc4xx_devs.c | 6 +++--- | ||
| 315 | hw/ppc/ppc4xx_sdram.c | 4 ++-- | ||
| 316 | hw/ppc/ppce500_spin.c | 2 +- | ||
| 317 | hw/ppc/spapr_cpu_core.c | 2 +- | ||
| 318 | hw/ppc/spapr_iommu.c | 2 +- | ||
| 319 | hw/ppc/spapr_pci.c | 2 +- | ||
| 320 | hw/ppc/spapr_vio.c | 2 +- | ||
| 321 | hw/remote/proxy.c | 2 +- | ||
| 322 | hw/rtc/allwinner-rtc.c | 2 +- | ||
| 323 | hw/rtc/aspeed_rtc.c | 2 +- | ||
| 324 | hw/rtc/ds1338.c | 2 +- | ||
| 325 | hw/rtc/exynos4210_rtc.c | 2 +- | ||
| 326 | hw/rtc/goldfish_rtc.c | 2 +- | ||
| 327 | hw/rtc/ls7a_rtc.c | 2 +- | ||
| 328 | hw/rtc/m48t59-isa.c | 2 +- | ||
| 329 | hw/rtc/m48t59.c | 2 +- | ||
| 330 | hw/rtc/xlnx-zynqmp-rtc.c | 2 +- | ||
| 331 | hw/s390x/event-facility.c | 2 +- | ||
| 332 | hw/s390x/ipl.c | 2 +- | ||
| 333 | hw/s390x/s390-pci-bus.c | 4 ++-- | ||
| 334 | hw/s390x/sclpquiesce.c | 2 +- | ||
| 335 | hw/scsi/esp-pci.c | 2 +- | ||
| 336 | hw/scsi/esp.c | 2 +- | ||
| 337 | hw/scsi/lsi53c895a.c | 2 +- | ||
| 338 | hw/scsi/megasas.c | 2 +- | ||
| 339 | hw/scsi/mptsas.c | 2 +- | ||
| 340 | hw/scsi/scsi-disk.c | 2 +- | ||
| 341 | hw/scsi/scsi-generic.c | 2 +- | ||
| 342 | hw/scsi/vmw_pvscsi.c | 2 +- | ||
| 343 | hw/sd/allwinner-sdhost.c | 2 +- | ||
| 344 | hw/sd/aspeed_sdhci.c | 2 +- | ||
| 345 | hw/sd/bcm2835_sdhost.c | 2 +- | ||
| 346 | hw/sd/cadence_sdhci.c | 2 +- | ||
| 347 | hw/sd/npcm7xx_sdhci.c | 2 +- | ||
| 348 | hw/sd/pl181.c | 2 +- | ||
| 349 | hw/sd/pxa2xx_mmci.c | 2 +- | ||
| 350 | hw/sd/sd.c | 2 +- | ||
| 351 | hw/sd/sdhci.c | 2 +- | ||
| 352 | hw/sd/ssi-sd.c | 2 +- | ||
| 353 | hw/sensor/dps310.c | 2 +- | ||
| 354 | hw/sensor/emc141x.c | 2 +- | ||
| 355 | hw/sensor/lsm303dlhc_mag.c | 2 +- | ||
| 356 | hw/sparc/sun4m_iommu.c | 2 +- | ||
| 357 | hw/sparc64/sun4u_iommu.c | 2 +- | ||
| 358 | hw/ssi/aspeed_smc.c | 2 +- | ||
| 359 | hw/ssi/bcm2835_spi.c | 2 +- | ||
| 360 | hw/ssi/ibex_spi_host.c | 2 +- | ||
| 361 | hw/ssi/imx_spi.c | 2 +- | ||
| 362 | hw/ssi/mss-spi.c | 2 +- | ||
| 363 | hw/ssi/pl022.c | 2 +- | ||
| 364 | hw/ssi/pnv_spi.c | 2 +- | ||
| 365 | hw/ssi/sifive_spi.c | 2 +- | ||
| 366 | hw/ssi/stm32f2xx_spi.c | 2 +- | ||
| 367 | hw/ssi/xilinx_spi.c | 2 +- | ||
| 368 | hw/ssi/xilinx_spips.c | 4 ++-- | ||
| 369 | hw/ssi/xlnx-versal-ospi.c | 2 +- | ||
| 370 | hw/timer/a9gtimer.c | 2 +- | ||
| 371 | hw/timer/allwinner-a10-pit.c | 2 +- | ||
| 372 | hw/timer/arm_mptimer.c | 2 +- | ||
| 373 | hw/timer/armv7m_systick.c | 2 +- | ||
| 374 | hw/timer/aspeed_timer.c | 2 +- | ||
| 375 | hw/timer/avr_timer16.c | 2 +- | ||
| 376 | hw/timer/bcm2835_systmr.c | 2 +- | ||
| 377 | hw/timer/cmsdk-apb-dualtimer.c | 2 +- | ||
| 378 | hw/timer/cmsdk-apb-timer.c | 2 +- | ||
| 379 | hw/timer/digic-timer.c | 2 +- | ||
| 380 | hw/timer/exynos4210_mct.c | 2 +- | ||
| 381 | hw/timer/exynos4210_pwm.c | 2 +- | ||
| 382 | hw/timer/grlib_gptimer.c | 2 +- | ||
| 383 | hw/timer/hpet.c | 2 +- | ||
| 384 | hw/timer/i8254.c | 2 +- | ||
| 385 | hw/timer/ibex_timer.c | 2 +- | ||
| 386 | hw/timer/imx_epit.c | 2 +- | ||
| 387 | hw/timer/imx_gpt.c | 2 +- | ||
| 388 | hw/timer/nrf51_timer.c | 2 +- | ||
| 389 | hw/timer/renesas_cmt.c | 2 +- | ||
| 390 | hw/timer/renesas_tmr.c | 2 +- | ||
| 391 | hw/timer/sifive_pwm.c | 2 +- | ||
| 392 | hw/timer/slavio_timer.c | 2 +- | ||
| 393 | hw/timer/sse-counter.c | 2 +- | ||
| 394 | hw/timer/sse-timer.c | 2 +- | ||
| 395 | hw/timer/stm32f2xx_timer.c | 2 +- | ||
| 396 | hw/tpm/tpm_tis_i2c.c | 2 +- | ||
| 397 | hw/tpm/tpm_tis_isa.c | 2 +- | ||
| 398 | hw/tpm/tpm_tis_sysbus.c | 2 +- | ||
| 399 | hw/tricore/tricore_testdevice.c | 2 +- | ||
| 400 | hw/usb/hcd-dwc3.c | 2 +- | ||
| 401 | hw/usb/hcd-ehci-pci.c | 2 +- | ||
| 402 | hw/usb/hcd-ehci-sysbus.c | 2 +- | ||
| 403 | hw/usb/hcd-ohci-pci.c | 2 +- | ||
| 404 | hw/usb/hcd-ohci-sysbus.c | 2 +- | ||
| 405 | hw/usb/hcd-uhci.c | 2 +- | ||
| 406 | hw/usb/hcd-xhci-pci.c | 2 +- | ||
| 407 | hw/usb/hcd-xhci-sysbus.c | 2 +- | ||
| 408 | hw/usb/hcd-xhci.c | 2 +- | ||
| 409 | hw/usb/imx-usb-phy.c | 2 +- | ||
| 410 | hw/usb/tusb6010.c | 2 +- | ||
| 411 | hw/vfio/ap.c | 2 +- | ||
| 412 | hw/vfio/ccw.c | 2 +- | ||
| 413 | hw/vfio/pci.c | 2 +- | ||
| 414 | hw/virtio/virtio-mmio.c | 2 +- | ||
| 415 | hw/watchdog/cmsdk-apb-watchdog.c | 2 +- | ||
| 416 | hw/watchdog/sbsa_gwdt.c | 2 +- | ||
| 417 | hw/watchdog/wdt_aspeed.c | 2 +- | ||
| 418 | hw/watchdog/wdt_diag288.c | 2 +- | ||
| 419 | hw/watchdog/wdt_i6300esb.c | 2 +- | ||
| 420 | hw/watchdog/wdt_ib700.c | 2 +- | ||
| 421 | hw/watchdog/wdt_imx2.c | 2 +- | ||
| 422 | 410 files changed, 448 insertions(+), 448 deletions(-) | ||
| 423 | 26 | ||
| 424 | diff --git a/hw/acpi/erst.c b/hw/acpi/erst.c | 27 | diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h |
| 425 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
| 426 | --- a/hw/acpi/erst.c | 29 | --- a/include/hw/net/imx_fec.h |
| 427 | +++ b/hw/acpi/erst.c | 30 | +++ b/include/hw/net/imx_fec.h |
| 428 | @@ -XXX,XX +XXX,XX @@ static void erst_class_init(ObjectClass *klass, void *data) | 31 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXFECState, IMX_FEC) |
| 429 | k->device_id = PCI_DEVICE_ID_REDHAT_ACPI_ERST; | 32 | #define TYPE_IMX_ENET "imx.enet" |
| 430 | k->revision = 0x00; | 33 | |
| 431 | k->class_id = PCI_CLASS_OTHERS; | 34 | #include "hw/sysbus.h" |
| 432 | - dc->reset = erst_reset; | 35 | +#include "hw/net/lan9118_phy.h" |
| 433 | + device_class_set_legacy_reset(dc, erst_reset); | 36 | +#include "hw/irq.h" |
| 434 | dc->vmsd = &erst_vmstate; | 37 | #include "net/net.h" |
| 435 | dc->user_creatable = true; | 38 | |
| 436 | dc->hotpluggable = false; | 39 | #define ENET_EIR 1 |
| 437 | diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c | 40 | @@ -XXX,XX +XXX,XX @@ struct IMXFECState { |
| 438 | index XXXXXXX..XXXXXXX 100644 | 41 | uint32_t tx_descriptor[ENET_TX_RING_NUM]; |
| 439 | --- a/hw/acpi/piix4.c | 42 | uint32_t tx_ring_num; |
| 440 | +++ b/hw/acpi/piix4.c | 43 | |
| 441 | @@ -XXX,XX +XXX,XX @@ static void piix4_pm_class_init(ObjectClass *klass, void *data) | 44 | - uint32_t phy_status; |
| 442 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; | 45 | - uint32_t phy_control; |
| 443 | k->revision = 0x03; | 46 | - uint32_t phy_advertise; |
| 444 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | 47 | - uint32_t phy_int; |
| 445 | - dc->reset = piix4_pm_reset; | 48 | - uint32_t phy_int_mask; |
| 446 | + device_class_set_legacy_reset(dc, piix4_pm_reset); | 49 | + Lan9118PhyState mii; |
| 447 | dc->desc = "PM"; | 50 | + IRQState mii_irq; |
| 448 | dc->vmsd = &vmstate_acpi; | 51 | uint32_t phy_num; |
| 449 | device_class_set_props(dc, piix4_pm_properties); | 52 | bool phy_connected; |
| 450 | diff --git a/hw/adc/aspeed_adc.c b/hw/adc/aspeed_adc.c | 53 | struct IMXFECState *phy_consumer; |
| 451 | index XXXXXXX..XXXXXXX 100644 | ||
| 452 | --- a/hw/adc/aspeed_adc.c | ||
| 453 | +++ b/hw/adc/aspeed_adc.c | ||
| 454 | @@ -XXX,XX +XXX,XX @@ static void aspeed_adc_engine_class_init(ObjectClass *klass, void *data) | ||
| 455 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 456 | |||
| 457 | dc->realize = aspeed_adc_engine_realize; | ||
| 458 | - dc->reset = aspeed_adc_engine_reset; | ||
| 459 | + device_class_set_legacy_reset(dc, aspeed_adc_engine_reset); | ||
| 460 | device_class_set_props(dc, aspeed_adc_engine_properties); | ||
| 461 | dc->desc = "Aspeed Analog-to-Digital Engine"; | ||
| 462 | dc->vmsd = &vmstate_aspeed_adc_engine; | ||
| 463 | diff --git a/hw/adc/max111x.c b/hw/adc/max111x.c | ||
| 464 | index XXXXXXX..XXXXXXX 100644 | ||
| 465 | --- a/hw/adc/max111x.c | ||
| 466 | +++ b/hw/adc/max111x.c | ||
| 467 | @@ -XXX,XX +XXX,XX @@ static void max111x_class_init(ObjectClass *klass, void *data) | ||
| 468 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 469 | |||
| 470 | k->transfer = max111x_transfer; | ||
| 471 | - dc->reset = max111x_reset; | ||
| 472 | + device_class_set_legacy_reset(dc, max111x_reset); | ||
| 473 | dc->vmsd = &vmstate_max111x; | ||
| 474 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 475 | } | ||
| 476 | diff --git a/hw/adc/stm32f2xx_adc.c b/hw/adc/stm32f2xx_adc.c | ||
| 477 | index XXXXXXX..XXXXXXX 100644 | ||
| 478 | --- a/hw/adc/stm32f2xx_adc.c | ||
| 479 | +++ b/hw/adc/stm32f2xx_adc.c | ||
| 480 | @@ -XXX,XX +XXX,XX @@ static void stm32f2xx_adc_class_init(ObjectClass *klass, void *data) | ||
| 481 | { | ||
| 482 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 483 | |||
| 484 | - dc->reset = stm32f2xx_adc_reset; | ||
| 485 | + device_class_set_legacy_reset(dc, stm32f2xx_adc_reset); | ||
| 486 | dc->vmsd = &vmstate_stm32f2xx_adc; | ||
| 487 | } | ||
| 488 | |||
| 489 | diff --git a/hw/adc/zynq-xadc.c b/hw/adc/zynq-xadc.c | ||
| 490 | index XXXXXXX..XXXXXXX 100644 | ||
| 491 | --- a/hw/adc/zynq-xadc.c | ||
| 492 | +++ b/hw/adc/zynq-xadc.c | ||
| 493 | @@ -XXX,XX +XXX,XX @@ static void zynq_xadc_class_init(ObjectClass *klass, void *data) | ||
| 494 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 495 | |||
| 496 | dc->vmsd = &vmstate_zynq_xadc; | ||
| 497 | - dc->reset = zynq_xadc_reset; | ||
| 498 | + device_class_set_legacy_reset(dc, zynq_xadc_reset); | ||
| 499 | } | ||
| 500 | |||
| 501 | static const TypeInfo zynq_xadc_info = { | ||
| 502 | diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c | ||
| 503 | index XXXXXXX..XXXXXXX 100644 | ||
| 504 | --- a/hw/arm/armsse.c | ||
| 505 | +++ b/hw/arm/armsse.c | ||
| 506 | @@ -XXX,XX +XXX,XX @@ static void armsse_class_init(ObjectClass *klass, void *data) | ||
| 507 | dc->realize = armsse_realize; | ||
| 508 | dc->vmsd = &armsse_vmstate; | ||
| 509 | device_class_set_props(dc, info->props); | ||
| 510 | - dc->reset = armsse_reset; | ||
| 511 | + device_class_set_legacy_reset(dc, armsse_reset); | ||
| 512 | iic->check = armsse_idau_check; | ||
| 513 | asc->info = info; | ||
| 514 | } | ||
| 515 | diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c | ||
| 516 | index XXXXXXX..XXXXXXX 100644 | ||
| 517 | --- a/hw/arm/highbank.c | ||
| 518 | +++ b/hw/arm/highbank.c | ||
| 519 | @@ -XXX,XX +XXX,XX @@ static void highbank_regs_class_init(ObjectClass *klass, void *data) | ||
| 520 | |||
| 521 | dc->desc = "Calxeda Highbank registers"; | ||
| 522 | dc->vmsd = &vmstate_highbank_regs; | ||
| 523 | - dc->reset = highbank_regs_reset; | ||
| 524 | + device_class_set_legacy_reset(dc, highbank_regs_reset); | ||
| 525 | } | ||
| 526 | |||
| 527 | static const TypeInfo highbank_regs_info = { | ||
| 528 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c | ||
| 529 | index XXXXXXX..XXXXXXX 100644 | ||
| 530 | --- a/hw/arm/musicpal.c | ||
| 531 | +++ b/hw/arm/musicpal.c | ||
| 532 | @@ -XXX,XX +XXX,XX @@ static void mv88w8618_pic_class_init(ObjectClass *klass, void *data) | ||
| 533 | { | ||
| 534 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 535 | |||
| 536 | - dc->reset = mv88w8618_pic_reset; | ||
| 537 | + device_class_set_legacy_reset(dc, mv88w8618_pic_reset); | ||
| 538 | dc->vmsd = &mv88w8618_pic_vmsd; | ||
| 539 | } | ||
| 540 | |||
| 541 | @@ -XXX,XX +XXX,XX @@ static void mv88w8618_pit_class_init(ObjectClass *klass, void *data) | ||
| 542 | { | ||
| 543 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 544 | |||
| 545 | - dc->reset = mv88w8618_pit_reset; | ||
| 546 | + device_class_set_legacy_reset(dc, mv88w8618_pit_reset); | ||
| 547 | dc->vmsd = &mv88w8618_pit_vmsd; | ||
| 548 | } | ||
| 549 | |||
| 550 | @@ -XXX,XX +XXX,XX @@ static void musicpal_gpio_class_init(ObjectClass *klass, void *data) | ||
| 551 | { | ||
| 552 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 553 | |||
| 554 | - dc->reset = musicpal_gpio_reset; | ||
| 555 | + device_class_set_legacy_reset(dc, musicpal_gpio_reset); | ||
| 556 | dc->vmsd = &musicpal_gpio_vmsd; | ||
| 557 | } | ||
| 558 | |||
| 559 | diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c | ||
| 560 | index XXXXXXX..XXXXXXX 100644 | ||
| 561 | --- a/hw/arm/pxa2xx.c | ||
| 562 | +++ b/hw/arm/pxa2xx.c | ||
| 563 | @@ -XXX,XX +XXX,XX @@ static void pxa2xx_fir_class_init(ObjectClass *klass, void *data) | ||
| 564 | dc->realize = pxa2xx_fir_realize; | ||
| 565 | dc->vmsd = &pxa2xx_fir_vmsd; | ||
| 566 | device_class_set_props(dc, pxa2xx_fir_properties); | ||
| 567 | - dc->reset = pxa2xx_fir_reset; | ||
| 568 | + device_class_set_legacy_reset(dc, pxa2xx_fir_reset); | ||
| 569 | } | ||
| 570 | |||
| 571 | static const TypeInfo pxa2xx_fir_info = { | ||
| 572 | @@ -XXX,XX +XXX,XX @@ static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data) | ||
| 573 | { | ||
| 574 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 575 | |||
| 576 | - dc->reset = pxa2xx_ssp_reset; | ||
| 577 | + device_class_set_legacy_reset(dc, pxa2xx_ssp_reset); | ||
| 578 | dc->vmsd = &vmstate_pxa2xx_ssp; | ||
| 579 | } | ||
| 580 | |||
| 581 | diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c | ||
| 582 | index XXXXXXX..XXXXXXX 100644 | ||
| 583 | --- a/hw/arm/strongarm.c | ||
| 584 | +++ b/hw/arm/strongarm.c | ||
| 585 | @@ -XXX,XX +XXX,XX @@ static void strongarm_uart_class_init(ObjectClass *klass, void *data) | ||
| 586 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 587 | |||
| 588 | dc->desc = "StrongARM UART controller"; | ||
| 589 | - dc->reset = strongarm_uart_reset; | ||
| 590 | + device_class_set_legacy_reset(dc, strongarm_uart_reset); | ||
| 591 | dc->vmsd = &vmstate_strongarm_uart_regs; | ||
| 592 | device_class_set_props(dc, strongarm_uart_properties); | ||
| 593 | dc->realize = strongarm_uart_realize; | ||
| 594 | @@ -XXX,XX +XXX,XX @@ static void strongarm_ssp_class_init(ObjectClass *klass, void *data) | ||
| 595 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 596 | |||
| 597 | dc->desc = "StrongARM SSP controller"; | ||
| 598 | - dc->reset = strongarm_ssp_reset; | ||
| 599 | + device_class_set_legacy_reset(dc, strongarm_ssp_reset); | ||
| 600 | dc->vmsd = &vmstate_strongarm_ssp_regs; | ||
| 601 | } | ||
| 602 | |||
| 603 | diff --git a/hw/audio/ac97.c b/hw/audio/ac97.c | ||
| 604 | index XXXXXXX..XXXXXXX 100644 | ||
| 605 | --- a/hw/audio/ac97.c | ||
| 606 | +++ b/hw/audio/ac97.c | ||
| 607 | @@ -XXX,XX +XXX,XX @@ static void ac97_class_init(ObjectClass *klass, void *data) | ||
| 608 | dc->desc = "Intel 82801AA AC97 Audio"; | ||
| 609 | dc->vmsd = &vmstate_ac97; | ||
| 610 | device_class_set_props(dc, ac97_properties); | ||
| 611 | - dc->reset = ac97_on_reset; | ||
| 612 | + device_class_set_legacy_reset(dc, ac97_on_reset); | ||
| 613 | } | ||
| 614 | |||
| 615 | static const TypeInfo ac97_info = { | ||
| 616 | diff --git a/hw/audio/cs4231.c b/hw/audio/cs4231.c | ||
| 617 | index XXXXXXX..XXXXXXX 100644 | ||
| 618 | --- a/hw/audio/cs4231.c | ||
| 619 | +++ b/hw/audio/cs4231.c | ||
| 620 | @@ -XXX,XX +XXX,XX @@ static void cs4231_class_init(ObjectClass *klass, void *data) | ||
| 621 | { | ||
| 622 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 623 | |||
| 624 | - dc->reset = cs_reset; | ||
| 625 | + device_class_set_legacy_reset(dc, cs_reset); | ||
| 626 | dc->vmsd = &vmstate_cs4231; | ||
| 627 | } | ||
| 628 | |||
| 629 | diff --git a/hw/audio/cs4231a.c b/hw/audio/cs4231a.c | ||
| 630 | index XXXXXXX..XXXXXXX 100644 | ||
| 631 | --- a/hw/audio/cs4231a.c | ||
| 632 | +++ b/hw/audio/cs4231a.c | ||
| 633 | @@ -XXX,XX +XXX,XX @@ static void cs4231a_class_initfn (ObjectClass *klass, void *data) | ||
| 634 | DeviceClass *dc = DEVICE_CLASS (klass); | ||
| 635 | |||
| 636 | dc->realize = cs4231a_realizefn; | ||
| 637 | - dc->reset = cs4231a_reset; | ||
| 638 | + device_class_set_legacy_reset(dc, cs4231a_reset); | ||
| 639 | set_bit(DEVICE_CATEGORY_SOUND, dc->categories); | ||
| 640 | dc->desc = "Crystal Semiconductor CS4231A"; | ||
| 641 | dc->vmsd = &vmstate_cs4231a; | ||
| 642 | diff --git a/hw/audio/es1370.c b/hw/audio/es1370.c | ||
| 643 | index XXXXXXX..XXXXXXX 100644 | ||
| 644 | --- a/hw/audio/es1370.c | ||
| 645 | +++ b/hw/audio/es1370.c | ||
| 646 | @@ -XXX,XX +XXX,XX @@ static void es1370_class_init (ObjectClass *klass, void *data) | ||
| 647 | set_bit(DEVICE_CATEGORY_SOUND, dc->categories); | ||
| 648 | dc->desc = "ENSONIQ AudioPCI ES1370"; | ||
| 649 | dc->vmsd = &vmstate_es1370; | ||
| 650 | - dc->reset = es1370_on_reset; | ||
| 651 | + device_class_set_legacy_reset(dc, es1370_on_reset); | ||
| 652 | device_class_set_props(dc, es1370_properties); | ||
| 653 | } | ||
| 654 | |||
| 655 | diff --git a/hw/audio/hda-codec.c b/hw/audio/hda-codec.c | ||
| 656 | index XXXXXXX..XXXXXXX 100644 | ||
| 657 | --- a/hw/audio/hda-codec.c | ||
| 658 | +++ b/hw/audio/hda-codec.c | ||
| 659 | @@ -XXX,XX +XXX,XX @@ static void hda_audio_base_class_init(ObjectClass *klass, void *data) | ||
| 660 | k->command = hda_audio_command; | ||
| 661 | k->stream = hda_audio_stream; | ||
| 662 | set_bit(DEVICE_CATEGORY_SOUND, dc->categories); | ||
| 663 | - dc->reset = hda_audio_reset; | ||
| 664 | + device_class_set_legacy_reset(dc, hda_audio_reset); | ||
| 665 | dc->vmsd = &vmstate_hda_audio; | ||
| 666 | device_class_set_props(dc, hda_audio_properties); | ||
| 667 | } | ||
| 668 | diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c | ||
| 669 | index XXXXXXX..XXXXXXX 100644 | ||
| 670 | --- a/hw/audio/intel-hda.c | ||
| 671 | +++ b/hw/audio/intel-hda.c | ||
| 672 | @@ -XXX,XX +XXX,XX @@ static void intel_hda_class_init(ObjectClass *klass, void *data) | ||
| 673 | k->exit = intel_hda_exit; | ||
| 674 | k->vendor_id = PCI_VENDOR_ID_INTEL; | ||
| 675 | k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO; | ||
| 676 | - dc->reset = intel_hda_reset; | ||
| 677 | + device_class_set_legacy_reset(dc, intel_hda_reset); | ||
| 678 | dc->vmsd = &vmstate_intel_hda; | ||
| 679 | device_class_set_props(dc, intel_hda_properties); | ||
| 680 | } | ||
| 681 | diff --git a/hw/audio/marvell_88w8618.c b/hw/audio/marvell_88w8618.c | ||
| 682 | index XXXXXXX..XXXXXXX 100644 | ||
| 683 | --- a/hw/audio/marvell_88w8618.c | ||
| 684 | +++ b/hw/audio/marvell_88w8618.c | ||
| 685 | @@ -XXX,XX +XXX,XX @@ static void mv88w8618_audio_class_init(ObjectClass *klass, void *data) | ||
| 686 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 687 | |||
| 688 | dc->realize = mv88w8618_audio_realize; | ||
| 689 | - dc->reset = mv88w8618_audio_reset; | ||
| 690 | + device_class_set_legacy_reset(dc, mv88w8618_audio_reset); | ||
| 691 | dc->vmsd = &mv88w8618_audio_vmsd; | ||
| 692 | dc->user_creatable = false; | ||
| 693 | } | ||
| 694 | diff --git a/hw/audio/pl041.c b/hw/audio/pl041.c | ||
| 695 | index XXXXXXX..XXXXXXX 100644 | ||
| 696 | --- a/hw/audio/pl041.c | ||
| 697 | +++ b/hw/audio/pl041.c | ||
| 698 | @@ -XXX,XX +XXX,XX @@ static void pl041_device_class_init(ObjectClass *klass, void *data) | ||
| 699 | |||
| 700 | dc->realize = pl041_realize; | ||
| 701 | set_bit(DEVICE_CATEGORY_SOUND, dc->categories); | ||
| 702 | - dc->reset = pl041_device_reset; | ||
| 703 | + device_class_set_legacy_reset(dc, pl041_device_reset); | ||
| 704 | dc->vmsd = &vmstate_pl041; | ||
| 705 | device_class_set_props(dc, pl041_device_properties); | ||
| 706 | } | ||
| 707 | diff --git a/hw/audio/via-ac97.c b/hw/audio/via-ac97.c | ||
| 708 | index XXXXXXX..XXXXXXX 100644 | ||
| 709 | --- a/hw/audio/via-ac97.c | ||
| 710 | +++ b/hw/audio/via-ac97.c | ||
| 711 | @@ -XXX,XX +XXX,XX @@ static void via_ac97_class_init(ObjectClass *klass, void *data) | ||
| 712 | device_class_set_props(dc, via_ac97_properties); | ||
| 713 | set_bit(DEVICE_CATEGORY_SOUND, dc->categories); | ||
| 714 | dc->desc = "VIA AC97"; | ||
| 715 | - dc->reset = via_ac97_reset; | ||
| 716 | + device_class_set_legacy_reset(dc, via_ac97_reset); | ||
| 717 | /* Reason: Part of a south bridge chip */ | ||
| 718 | dc->user_creatable = false; | ||
| 719 | } | ||
| 720 | diff --git a/hw/block/fdc-isa.c b/hw/block/fdc-isa.c | ||
| 721 | index XXXXXXX..XXXXXXX 100644 | ||
| 722 | --- a/hw/block/fdc-isa.c | ||
| 723 | +++ b/hw/block/fdc-isa.c | ||
| 724 | @@ -XXX,XX +XXX,XX @@ static void isabus_fdc_class_init(ObjectClass *klass, void *data) | ||
| 725 | dc->desc = "virtual floppy controller"; | ||
| 726 | dc->realize = isabus_fdc_realize; | ||
| 727 | dc->fw_name = "fdc"; | ||
| 728 | - dc->reset = fdctrl_external_reset_isa; | ||
| 729 | + device_class_set_legacy_reset(dc, fdctrl_external_reset_isa); | ||
| 730 | dc->vmsd = &vmstate_isa_fdc; | ||
| 731 | adevc->build_dev_aml = build_fdc_aml; | ||
| 732 | device_class_set_props(dc, isa_fdc_properties); | ||
| 733 | diff --git a/hw/block/fdc-sysbus.c b/hw/block/fdc-sysbus.c | ||
| 734 | index XXXXXXX..XXXXXXX 100644 | ||
| 735 | --- a/hw/block/fdc-sysbus.c | ||
| 736 | +++ b/hw/block/fdc-sysbus.c | ||
| 737 | @@ -XXX,XX +XXX,XX @@ static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data) | ||
| 738 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 739 | |||
| 740 | dc->realize = sysbus_fdc_realize; | ||
| 741 | - dc->reset = fdctrl_external_reset_sysbus; | ||
| 742 | + device_class_set_legacy_reset(dc, fdctrl_external_reset_sysbus); | ||
| 743 | dc->vmsd = &vmstate_sysbus_fdc; | ||
| 744 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | ||
| 745 | } | ||
| 746 | diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c | ||
| 747 | index XXXXXXX..XXXXXXX 100644 | ||
| 748 | --- a/hw/block/m25p80.c | ||
| 749 | +++ b/hw/block/m25p80.c | ||
| 750 | @@ -XXX,XX +XXX,XX @@ static void m25p80_class_init(ObjectClass *klass, void *data) | ||
| 751 | k->cs_polarity = SSI_CS_LOW; | ||
| 752 | dc->vmsd = &vmstate_m25p80; | ||
| 753 | device_class_set_props(dc, m25p80_properties); | ||
| 754 | - dc->reset = m25p80_reset; | ||
| 755 | + device_class_set_legacy_reset(dc, m25p80_reset); | ||
| 756 | mc->pi = data; | ||
| 757 | } | ||
| 758 | |||
| 759 | diff --git a/hw/block/nand.c b/hw/block/nand.c | ||
| 760 | index XXXXXXX..XXXXXXX 100644 | ||
| 761 | --- a/hw/block/nand.c | ||
| 762 | +++ b/hw/block/nand.c | ||
| 763 | @@ -XXX,XX +XXX,XX @@ static void nand_class_init(ObjectClass *klass, void *data) | ||
| 764 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 765 | |||
| 766 | dc->realize = nand_realize; | ||
| 767 | - dc->reset = nand_reset; | ||
| 768 | + device_class_set_legacy_reset(dc, nand_reset); | ||
| 769 | dc->vmsd = &vmstate_nand; | ||
| 770 | device_class_set_props(dc, nand_properties); | ||
| 771 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | ||
| 772 | diff --git a/hw/block/onenand.c b/hw/block/onenand.c | ||
| 773 | index XXXXXXX..XXXXXXX 100644 | ||
| 774 | --- a/hw/block/onenand.c | ||
| 775 | +++ b/hw/block/onenand.c | ||
| 776 | @@ -XXX,XX +XXX,XX @@ static void onenand_class_init(ObjectClass *klass, void *data) | ||
| 777 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 778 | |||
| 779 | dc->realize = onenand_realize; | ||
| 780 | - dc->reset = onenand_system_reset; | ||
| 781 | + device_class_set_legacy_reset(dc, onenand_system_reset); | ||
| 782 | device_class_set_props(dc, onenand_properties); | ||
| 783 | } | ||
| 784 | |||
| 785 | diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c | ||
| 786 | index XXXXXXX..XXXXXXX 100644 | ||
| 787 | --- a/hw/block/pflash_cfi01.c | ||
| 788 | +++ b/hw/block/pflash_cfi01.c | ||
| 789 | @@ -XXX,XX +XXX,XX @@ static void pflash_cfi01_class_init(ObjectClass *klass, void *data) | ||
| 790 | { | ||
| 791 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 792 | |||
| 793 | - dc->reset = pflash_cfi01_system_reset; | ||
| 794 | + device_class_set_legacy_reset(dc, pflash_cfi01_system_reset); | ||
| 795 | dc->realize = pflash_cfi01_realize; | ||
| 796 | device_class_set_props(dc, pflash_cfi01_properties); | ||
| 797 | dc->vmsd = &vmstate_pflash; | ||
| 798 | diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c | ||
| 799 | index XXXXXXX..XXXXXXX 100644 | ||
| 800 | --- a/hw/block/pflash_cfi02.c | ||
| 801 | +++ b/hw/block/pflash_cfi02.c | ||
| 802 | @@ -XXX,XX +XXX,XX @@ static void pflash_cfi02_class_init(ObjectClass *klass, void *data) | ||
| 803 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 804 | |||
| 805 | dc->realize = pflash_cfi02_realize; | ||
| 806 | - dc->reset = pflash_cfi02_reset; | ||
| 807 | + device_class_set_legacy_reset(dc, pflash_cfi02_reset); | ||
| 808 | dc->unrealize = pflash_cfi02_unrealize; | ||
| 809 | device_class_set_props(dc, pflash_cfi02_properties); | ||
| 810 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | ||
| 811 | diff --git a/hw/block/swim.c b/hw/block/swim.c | ||
| 812 | index XXXXXXX..XXXXXXX 100644 | ||
| 813 | --- a/hw/block/swim.c | ||
| 814 | +++ b/hw/block/swim.c | ||
| 815 | @@ -XXX,XX +XXX,XX @@ static void sysbus_swim_class_init(ObjectClass *oc, void *data) | ||
| 816 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 817 | |||
| 818 | dc->realize = sysbus_swim_realize; | ||
| 819 | - dc->reset = sysbus_swim_reset; | ||
| 820 | + device_class_set_legacy_reset(dc, sysbus_swim_reset); | ||
| 821 | dc->vmsd = &vmstate_sysbus_swim; | ||
| 822 | } | ||
| 823 | |||
| 824 | diff --git a/hw/char/avr_usart.c b/hw/char/avr_usart.c | ||
| 825 | index XXXXXXX..XXXXXXX 100644 | ||
| 826 | --- a/hw/char/avr_usart.c | ||
| 827 | +++ b/hw/char/avr_usart.c | ||
| 828 | @@ -XXX,XX +XXX,XX @@ static void avr_usart_class_init(ObjectClass *klass, void *data) | ||
| 829 | { | ||
| 830 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 831 | |||
| 832 | - dc->reset = avr_usart_reset; | ||
| 833 | + device_class_set_legacy_reset(dc, avr_usart_reset); | ||
| 834 | device_class_set_props(dc, avr_usart_properties); | ||
| 835 | dc->realize = avr_usart_realize; | ||
| 836 | } | ||
| 837 | diff --git a/hw/char/cmsdk-apb-uart.c b/hw/char/cmsdk-apb-uart.c | ||
| 838 | index XXXXXXX..XXXXXXX 100644 | ||
| 839 | --- a/hw/char/cmsdk-apb-uart.c | ||
| 840 | +++ b/hw/char/cmsdk-apb-uart.c | ||
| 841 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_uart_class_init(ObjectClass *klass, void *data) | ||
| 842 | |||
| 843 | dc->realize = cmsdk_apb_uart_realize; | ||
| 844 | dc->vmsd = &cmsdk_apb_uart_vmstate; | ||
| 845 | - dc->reset = cmsdk_apb_uart_reset; | ||
| 846 | + device_class_set_legacy_reset(dc, cmsdk_apb_uart_reset); | ||
| 847 | device_class_set_props(dc, cmsdk_apb_uart_properties); | ||
| 848 | } | ||
| 849 | |||
| 850 | diff --git a/hw/char/digic-uart.c b/hw/char/digic-uart.c | ||
| 851 | index XXXXXXX..XXXXXXX 100644 | ||
| 852 | --- a/hw/char/digic-uart.c | ||
| 853 | +++ b/hw/char/digic-uart.c | ||
| 854 | @@ -XXX,XX +XXX,XX @@ static void digic_uart_class_init(ObjectClass *klass, void *data) | ||
| 855 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 856 | |||
| 857 | dc->realize = digic_uart_realize; | ||
| 858 | - dc->reset = digic_uart_reset; | ||
| 859 | + device_class_set_legacy_reset(dc, digic_uart_reset); | ||
| 860 | dc->vmsd = &vmstate_digic_uart; | ||
| 861 | device_class_set_props(dc, digic_uart_properties); | ||
| 862 | } | ||
| 863 | diff --git a/hw/char/escc.c b/hw/char/escc.c | ||
| 864 | index XXXXXXX..XXXXXXX 100644 | ||
| 865 | --- a/hw/char/escc.c | ||
| 866 | +++ b/hw/char/escc.c | ||
| 867 | @@ -XXX,XX +XXX,XX @@ static void escc_class_init(ObjectClass *klass, void *data) | ||
| 868 | { | ||
| 869 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 870 | |||
| 871 | - dc->reset = escc_reset; | ||
| 872 | + device_class_set_legacy_reset(dc, escc_reset); | ||
| 873 | dc->realize = escc_realize; | ||
| 874 | dc->vmsd = &vmstate_escc; | ||
| 875 | device_class_set_props(dc, escc_properties); | ||
| 876 | diff --git a/hw/char/etraxfs_ser.c b/hw/char/etraxfs_ser.c | ||
| 877 | index XXXXXXX..XXXXXXX 100644 | ||
| 878 | --- a/hw/char/etraxfs_ser.c | ||
| 879 | +++ b/hw/char/etraxfs_ser.c | ||
| 880 | @@ -XXX,XX +XXX,XX @@ static void etraxfs_ser_class_init(ObjectClass *klass, void *data) | ||
| 881 | { | ||
| 882 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 883 | |||
| 884 | - dc->reset = etraxfs_ser_reset; | ||
| 885 | + device_class_set_legacy_reset(dc, etraxfs_ser_reset); | ||
| 886 | device_class_set_props(dc, etraxfs_ser_properties); | ||
| 887 | dc->realize = etraxfs_ser_realize; | ||
| 888 | } | ||
| 889 | diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c | ||
| 890 | index XXXXXXX..XXXXXXX 100644 | ||
| 891 | --- a/hw/char/exynos4210_uart.c | ||
| 892 | +++ b/hw/char/exynos4210_uart.c | ||
| 893 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_uart_class_init(ObjectClass *klass, void *data) | ||
| 894 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 895 | |||
| 896 | dc->realize = exynos4210_uart_realize; | ||
| 897 | - dc->reset = exynos4210_uart_reset; | ||
| 898 | + device_class_set_legacy_reset(dc, exynos4210_uart_reset); | ||
| 899 | device_class_set_props(dc, exynos4210_uart_properties); | ||
| 900 | dc->vmsd = &vmstate_exynos4210_uart; | ||
| 901 | } | ||
| 902 | diff --git a/hw/char/goldfish_tty.c b/hw/char/goldfish_tty.c | ||
| 903 | index XXXXXXX..XXXXXXX 100644 | ||
| 904 | --- a/hw/char/goldfish_tty.c | ||
| 905 | +++ b/hw/char/goldfish_tty.c | ||
| 906 | @@ -XXX,XX +XXX,XX @@ static void goldfish_tty_class_init(ObjectClass *oc, void *data) | ||
| 907 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 908 | |||
| 909 | device_class_set_props(dc, goldfish_tty_properties); | ||
| 910 | - dc->reset = goldfish_tty_reset; | ||
| 911 | + device_class_set_legacy_reset(dc, goldfish_tty_reset); | ||
| 912 | dc->realize = goldfish_tty_realize; | ||
| 913 | dc->unrealize = goldfish_tty_unrealize; | ||
| 914 | dc->vmsd = &vmstate_goldfish_tty; | ||
| 915 | diff --git a/hw/char/grlib_apbuart.c b/hw/char/grlib_apbuart.c | ||
| 916 | index XXXXXXX..XXXXXXX 100644 | ||
| 917 | --- a/hw/char/grlib_apbuart.c | ||
| 918 | +++ b/hw/char/grlib_apbuart.c | ||
| 919 | @@ -XXX,XX +XXX,XX @@ static void grlib_apbuart_class_init(ObjectClass *klass, void *data) | ||
| 920 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 921 | |||
| 922 | dc->realize = grlib_apbuart_realize; | ||
| 923 | - dc->reset = grlib_apbuart_reset; | ||
| 924 | + device_class_set_legacy_reset(dc, grlib_apbuart_reset); | ||
| 925 | device_class_set_props(dc, grlib_apbuart_properties); | ||
| 926 | } | ||
| 927 | |||
| 928 | diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c | ||
| 929 | index XXXXXXX..XXXXXXX 100644 | ||
| 930 | --- a/hw/char/ibex_uart.c | ||
| 931 | +++ b/hw/char/ibex_uart.c | ||
| 932 | @@ -XXX,XX +XXX,XX @@ static void ibex_uart_class_init(ObjectClass *klass, void *data) | ||
| 933 | { | ||
| 934 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 935 | |||
| 936 | - dc->reset = ibex_uart_reset; | ||
| 937 | + device_class_set_legacy_reset(dc, ibex_uart_reset); | ||
| 938 | dc->realize = ibex_uart_realize; | ||
| 939 | dc->vmsd = &vmstate_ibex_uart; | ||
| 940 | device_class_set_props(dc, ibex_uart_properties); | ||
| 941 | diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c | ||
| 942 | index XXXXXXX..XXXXXXX 100644 | ||
| 943 | --- a/hw/char/imx_serial.c | ||
| 944 | +++ b/hw/char/imx_serial.c | ||
| 945 | @@ -XXX,XX +XXX,XX @@ static void imx_serial_class_init(ObjectClass *klass, void *data) | ||
| 946 | |||
| 947 | dc->realize = imx_serial_realize; | ||
| 948 | dc->vmsd = &vmstate_imx_serial; | ||
| 949 | - dc->reset = imx_serial_reset_at_boot; | ||
| 950 | + device_class_set_legacy_reset(dc, imx_serial_reset_at_boot); | ||
| 951 | set_bit(DEVICE_CATEGORY_INPUT, dc->categories); | ||
| 952 | dc->desc = "i.MX series UART"; | ||
| 953 | device_class_set_props(dc, imx_serial_properties); | ||
| 954 | diff --git a/hw/char/mcf_uart.c b/hw/char/mcf_uart.c | ||
| 955 | index XXXXXXX..XXXXXXX 100644 | ||
| 956 | --- a/hw/char/mcf_uart.c | ||
| 957 | +++ b/hw/char/mcf_uart.c | ||
| 958 | @@ -XXX,XX +XXX,XX @@ static void mcf_uart_class_init(ObjectClass *oc, void *data) | ||
| 959 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 960 | |||
| 961 | dc->realize = mcf_uart_realize; | ||
| 962 | - dc->reset = mcf_uart_reset; | ||
| 963 | + device_class_set_legacy_reset(dc, mcf_uart_reset); | ||
| 964 | device_class_set_props(dc, mcf_uart_properties); | ||
| 965 | set_bit(DEVICE_CATEGORY_INPUT, dc->categories); | ||
| 966 | } | ||
| 967 | diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c | ||
| 968 | index XXXXXXX..XXXXXXX 100644 | ||
| 969 | --- a/hw/char/mchp_pfsoc_mmuart.c | ||
| 970 | +++ b/hw/char/mchp_pfsoc_mmuart.c | ||
| 971 | @@ -XXX,XX +XXX,XX @@ static void mchp_pfsoc_mmuart_class_init(ObjectClass *oc, void *data) | ||
| 972 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 973 | |||
| 974 | dc->realize = mchp_pfsoc_mmuart_realize; | ||
| 975 | - dc->reset = mchp_pfsoc_mmuart_reset; | ||
| 976 | + device_class_set_legacy_reset(dc, mchp_pfsoc_mmuart_reset); | ||
| 977 | dc->vmsd = &mchp_pfsoc_mmuart_vmstate; | ||
| 978 | set_bit(DEVICE_CATEGORY_INPUT, dc->categories); | ||
| 979 | } | ||
| 980 | diff --git a/hw/char/nrf51_uart.c b/hw/char/nrf51_uart.c | ||
| 981 | index XXXXXXX..XXXXXXX 100644 | ||
| 982 | --- a/hw/char/nrf51_uart.c | ||
| 983 | +++ b/hw/char/nrf51_uart.c | ||
| 984 | @@ -XXX,XX +XXX,XX @@ static void nrf51_uart_class_init(ObjectClass *klass, void *data) | ||
| 985 | { | ||
| 986 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 987 | |||
| 988 | - dc->reset = nrf51_uart_reset; | ||
| 989 | + device_class_set_legacy_reset(dc, nrf51_uart_reset); | ||
| 990 | dc->realize = nrf51_uart_realize; | ||
| 991 | device_class_set_props(dc, nrf51_uart_properties); | ||
| 992 | dc->vmsd = &nrf51_uart_vmstate; | ||
| 993 | diff --git a/hw/char/pl011.c b/hw/char/pl011.c | ||
| 994 | index XXXXXXX..XXXXXXX 100644 | ||
| 995 | --- a/hw/char/pl011.c | ||
| 996 | +++ b/hw/char/pl011.c | ||
| 997 | @@ -XXX,XX +XXX,XX @@ static void pl011_class_init(ObjectClass *oc, void *data) | ||
| 998 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 999 | |||
| 1000 | dc->realize = pl011_realize; | ||
| 1001 | - dc->reset = pl011_reset; | ||
| 1002 | + device_class_set_legacy_reset(dc, pl011_reset); | ||
| 1003 | dc->vmsd = &vmstate_pl011; | ||
| 1004 | device_class_set_props(dc, pl011_properties); | ||
| 1005 | } | ||
| 1006 | diff --git a/hw/char/renesas_sci.c b/hw/char/renesas_sci.c | ||
| 1007 | index XXXXXXX..XXXXXXX 100644 | ||
| 1008 | --- a/hw/char/renesas_sci.c | ||
| 1009 | +++ b/hw/char/renesas_sci.c | ||
| 1010 | @@ -XXX,XX +XXX,XX @@ static void rsci_class_init(ObjectClass *klass, void *data) | ||
| 1011 | |||
| 1012 | dc->realize = rsci_realize; | ||
| 1013 | dc->vmsd = &vmstate_rsci; | ||
| 1014 | - dc->reset = rsci_reset; | ||
| 1015 | + device_class_set_legacy_reset(dc, rsci_reset); | ||
| 1016 | device_class_set_props(dc, rsci_properties); | ||
| 1017 | } | ||
| 1018 | |||
| 1019 | diff --git a/hw/char/sclpconsole-lm.c b/hw/char/sclpconsole-lm.c | ||
| 1020 | index XXXXXXX..XXXXXXX 100644 | ||
| 1021 | --- a/hw/char/sclpconsole-lm.c | ||
| 1022 | +++ b/hw/char/sclpconsole-lm.c | ||
| 1023 | @@ -XXX,XX +XXX,XX @@ static void console_class_init(ObjectClass *klass, void *data) | ||
| 1024 | SCLPEventClass *ec = SCLP_EVENT_CLASS(klass); | ||
| 1025 | |||
| 1026 | device_class_set_props(dc, console_properties); | ||
| 1027 | - dc->reset = console_reset; | ||
| 1028 | + device_class_set_legacy_reset(dc, console_reset); | ||
| 1029 | dc->vmsd = &vmstate_sclplmconsole; | ||
| 1030 | ec->init = console_init; | ||
| 1031 | ec->get_send_mask = send_mask; | ||
| 1032 | diff --git a/hw/char/sclpconsole.c b/hw/char/sclpconsole.c | ||
| 1033 | index XXXXXXX..XXXXXXX 100644 | ||
| 1034 | --- a/hw/char/sclpconsole.c | ||
| 1035 | +++ b/hw/char/sclpconsole.c | ||
| 1036 | @@ -XXX,XX +XXX,XX @@ static void console_class_init(ObjectClass *klass, void *data) | ||
| 1037 | SCLPEventClass *ec = SCLP_EVENT_CLASS(klass); | ||
| 1038 | |||
| 1039 | device_class_set_props(dc, console_properties); | ||
| 1040 | - dc->reset = console_reset; | ||
| 1041 | + device_class_set_legacy_reset(dc, console_reset); | ||
| 1042 | dc->vmsd = &vmstate_sclpconsole; | ||
| 1043 | ec->init = console_init; | ||
| 1044 | ec->get_send_mask = send_mask; | ||
| 1045 | diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c | ||
| 1046 | index XXXXXXX..XXXXXXX 100644 | ||
| 1047 | --- a/hw/char/sh_serial.c | ||
| 1048 | +++ b/hw/char/sh_serial.c | ||
| 1049 | @@ -XXX,XX +XXX,XX @@ static void sh_serial_class_init(ObjectClass *oc, void *data) | ||
| 1050 | |||
| 1051 | device_class_set_props(dc, sh_serial_properties); | ||
| 1052 | dc->realize = sh_serial_realize; | ||
| 1053 | - dc->reset = sh_serial_reset; | ||
| 1054 | + device_class_set_legacy_reset(dc, sh_serial_reset); | ||
| 1055 | /* Reason: part of SuperH CPU/SoC, needs to be wired up */ | ||
| 1056 | dc->user_creatable = false; | ||
| 1057 | } | ||
| 1058 | diff --git a/hw/char/shakti_uart.c b/hw/char/shakti_uart.c | ||
| 1059 | index XXXXXXX..XXXXXXX 100644 | ||
| 1060 | --- a/hw/char/shakti_uart.c | ||
| 1061 | +++ b/hw/char/shakti_uart.c | ||
| 1062 | @@ -XXX,XX +XXX,XX @@ static Property shakti_uart_properties[] = { | ||
| 1063 | static void shakti_uart_class_init(ObjectClass *klass, void *data) | ||
| 1064 | { | ||
| 1065 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1066 | - dc->reset = shakti_uart_reset; | ||
| 1067 | + device_class_set_legacy_reset(dc, shakti_uart_reset); | ||
| 1068 | dc->realize = shakti_uart_realize; | ||
| 1069 | device_class_set_props(dc, shakti_uart_properties); | ||
| 1070 | set_bit(DEVICE_CATEGORY_INPUT, dc->categories); | ||
| 1071 | diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c | ||
| 1072 | index XXXXXXX..XXXXXXX 100644 | ||
| 1073 | --- a/hw/char/stm32f2xx_usart.c | ||
| 1074 | +++ b/hw/char/stm32f2xx_usart.c | ||
| 1075 | @@ -XXX,XX +XXX,XX @@ static void stm32f2xx_usart_class_init(ObjectClass *klass, void *data) | ||
| 1076 | { | ||
| 1077 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1078 | |||
| 1079 | - dc->reset = stm32f2xx_usart_reset; | ||
| 1080 | + device_class_set_legacy_reset(dc, stm32f2xx_usart_reset); | ||
| 1081 | device_class_set_props(dc, stm32f2xx_usart_properties); | ||
| 1082 | dc->realize = stm32f2xx_usart_realize; | ||
| 1083 | } | ||
| 1084 | diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c | ||
| 1085 | index XXXXXXX..XXXXXXX 100644 | ||
| 1086 | --- a/hw/char/xilinx_uartlite.c | ||
| 1087 | +++ b/hw/char/xilinx_uartlite.c | ||
| 1088 | @@ -XXX,XX +XXX,XX @@ static void xilinx_uartlite_class_init(ObjectClass *klass, void *data) | ||
| 1089 | { | ||
| 1090 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1091 | |||
| 1092 | - dc->reset = xilinx_uartlite_reset; | ||
| 1093 | + device_class_set_legacy_reset(dc, xilinx_uartlite_reset); | ||
| 1094 | dc->realize = xilinx_uartlite_realize; | ||
| 1095 | device_class_set_props(dc, xilinx_uartlite_properties); | ||
| 1096 | } | ||
| 1097 | diff --git a/hw/core/or-irq.c b/hw/core/or-irq.c | ||
| 1098 | index XXXXXXX..XXXXXXX 100644 | ||
| 1099 | --- a/hw/core/or-irq.c | ||
| 1100 | +++ b/hw/core/or-irq.c | ||
| 1101 | @@ -XXX,XX +XXX,XX @@ static void or_irq_class_init(ObjectClass *klass, void *data) | ||
| 1102 | { | ||
| 1103 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1104 | |||
| 1105 | - dc->reset = or_irq_reset; | ||
| 1106 | + device_class_set_legacy_reset(dc, or_irq_reset); | ||
| 1107 | device_class_set_props(dc, or_irq_properties); | ||
| 1108 | dc->realize = or_irq_realize; | ||
| 1109 | dc->vmsd = &vmstate_or_irq; | ||
| 1110 | diff --git a/hw/core/qdev.c b/hw/core/qdev.c | ||
| 1111 | index XXXXXXX..XXXXXXX 100644 | ||
| 1112 | --- a/hw/core/qdev.c | ||
| 1113 | +++ b/hw/core/qdev.c | ||
| 1114 | @@ -XXX,XX +XXX,XX @@ static void device_class_init(ObjectClass *class, void *data) | ||
| 1115 | * will be registered as the parent reset method and effectively call | ||
| 1116 | * parent reset phases. | ||
| 1117 | */ | ||
| 1118 | - dc->reset = device_phases_reset; | ||
| 1119 | + device_class_set_legacy_reset(dc, device_phases_reset); | ||
| 1120 | rc->get_transitional_function = device_get_transitional_reset; | ||
| 1121 | |||
| 1122 | object_class_property_add_bool(class, "realized", | ||
| 1123 | diff --git a/hw/cxl/switch-mailbox-cci.c b/hw/cxl/switch-mailbox-cci.c | ||
| 1124 | index XXXXXXX..XXXXXXX 100644 | ||
| 1125 | --- a/hw/cxl/switch-mailbox-cci.c | ||
| 1126 | +++ b/hw/cxl/switch-mailbox-cci.c | ||
| 1127 | @@ -XXX,XX +XXX,XX @@ static void cswmbcci_class_init(ObjectClass *oc, void *data) | ||
| 1128 | pc->device_id = 0xa123; | ||
| 1129 | pc->revision = 0; | ||
| 1130 | dc->desc = "CXL Switch Mailbox CCI"; | ||
| 1131 | - dc->reset = cswmbcci_reset; | ||
| 1132 | + device_class_set_legacy_reset(dc, cswmbcci_reset); | ||
| 1133 | device_class_set_props(dc, cxl_switch_cci_props); | ||
| 1134 | } | ||
| 1135 | |||
| 1136 | diff --git a/hw/display/artist.c b/hw/display/artist.c | ||
| 1137 | index XXXXXXX..XXXXXXX 100644 | ||
| 1138 | --- a/hw/display/artist.c | ||
| 1139 | +++ b/hw/display/artist.c | ||
| 1140 | @@ -XXX,XX +XXX,XX @@ static void artist_class_init(ObjectClass *klass, void *data) | ||
| 1141 | |||
| 1142 | dc->realize = artist_realizefn; | ||
| 1143 | dc->vmsd = &vmstate_artist; | ||
| 1144 | - dc->reset = artist_reset; | ||
| 1145 | + device_class_set_legacy_reset(dc, artist_reset); | ||
| 1146 | device_class_set_props(dc, artist_properties); | ||
| 1147 | } | ||
| 1148 | |||
| 1149 | diff --git a/hw/display/ati.c b/hw/display/ati.c | ||
| 1150 | index XXXXXXX..XXXXXXX 100644 | ||
| 1151 | --- a/hw/display/ati.c | ||
| 1152 | +++ b/hw/display/ati.c | ||
| 1153 | @@ -XXX,XX +XXX,XX @@ static void ati_vga_class_init(ObjectClass *klass, void *data) | ||
| 1154 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1155 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | ||
| 1156 | |||
| 1157 | - dc->reset = ati_vga_reset; | ||
| 1158 | + device_class_set_legacy_reset(dc, ati_vga_reset); | ||
| 1159 | device_class_set_props(dc, ati_vga_properties); | ||
| 1160 | dc->hotpluggable = false; | ||
| 1161 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); | ||
| 1162 | diff --git a/hw/display/bcm2835_fb.c b/hw/display/bcm2835_fb.c | ||
| 1163 | index XXXXXXX..XXXXXXX 100644 | ||
| 1164 | --- a/hw/display/bcm2835_fb.c | ||
| 1165 | +++ b/hw/display/bcm2835_fb.c | ||
| 1166 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_fb_class_init(ObjectClass *klass, void *data) | ||
| 1167 | |||
| 1168 | device_class_set_props(dc, bcm2835_fb_props); | ||
| 1169 | dc->realize = bcm2835_fb_realize; | ||
| 1170 | - dc->reset = bcm2835_fb_reset; | ||
| 1171 | + device_class_set_legacy_reset(dc, bcm2835_fb_reset); | ||
| 1172 | dc->vmsd = &vmstate_bcm2835_fb; | ||
| 1173 | } | ||
| 1174 | |||
| 1175 | diff --git a/hw/display/cg3.c b/hw/display/cg3.c | ||
| 1176 | index XXXXXXX..XXXXXXX 100644 | ||
| 1177 | --- a/hw/display/cg3.c | ||
| 1178 | +++ b/hw/display/cg3.c | ||
| 1179 | @@ -XXX,XX +XXX,XX @@ static void cg3_class_init(ObjectClass *klass, void *data) | ||
| 1180 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1181 | |||
| 1182 | dc->realize = cg3_realizefn; | ||
| 1183 | - dc->reset = cg3_reset; | ||
| 1184 | + device_class_set_legacy_reset(dc, cg3_reset); | ||
| 1185 | dc->vmsd = &vmstate_cg3; | ||
| 1186 | device_class_set_props(dc, cg3_properties); | ||
| 1187 | } | ||
| 1188 | diff --git a/hw/display/dpcd.c b/hw/display/dpcd.c | ||
| 1189 | index XXXXXXX..XXXXXXX 100644 | ||
| 1190 | --- a/hw/display/dpcd.c | ||
| 1191 | +++ b/hw/display/dpcd.c | ||
| 1192 | @@ -XXX,XX +XXX,XX @@ static void dpcd_class_init(ObjectClass *oc, void *data) | ||
| 1193 | { | ||
| 1194 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 1195 | |||
| 1196 | - dc->reset = dpcd_reset; | ||
| 1197 | + device_class_set_legacy_reset(dc, dpcd_reset); | ||
| 1198 | dc->vmsd = &vmstate_dpcd; | ||
| 1199 | } | ||
| 1200 | |||
| 1201 | diff --git a/hw/display/exynos4210_fimd.c b/hw/display/exynos4210_fimd.c | ||
| 1202 | index XXXXXXX..XXXXXXX 100644 | ||
| 1203 | --- a/hw/display/exynos4210_fimd.c | ||
| 1204 | +++ b/hw/display/exynos4210_fimd.c | ||
| 1205 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_fimd_class_init(ObjectClass *klass, void *data) | ||
| 1206 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1207 | |||
| 1208 | dc->vmsd = &exynos4210_fimd_vmstate; | ||
| 1209 | - dc->reset = exynos4210_fimd_reset; | ||
| 1210 | + device_class_set_legacy_reset(dc, exynos4210_fimd_reset); | ||
| 1211 | dc->realize = exynos4210_fimd_realize; | ||
| 1212 | device_class_set_props(dc, exynos4210_fimd_properties); | ||
| 1213 | } | ||
| 1214 | diff --git a/hw/display/g364fb.c b/hw/display/g364fb.c | ||
| 1215 | index XXXXXXX..XXXXXXX 100644 | ||
| 1216 | --- a/hw/display/g364fb.c | ||
| 1217 | +++ b/hw/display/g364fb.c | ||
| 1218 | @@ -XXX,XX +XXX,XX @@ static void g364fb_sysbus_class_init(ObjectClass *klass, void *data) | ||
| 1219 | dc->realize = g364fb_sysbus_realize; | ||
| 1220 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); | ||
| 1221 | dc->desc = "G364 framebuffer"; | ||
| 1222 | - dc->reset = g364fb_sysbus_reset; | ||
| 1223 | + device_class_set_legacy_reset(dc, g364fb_sysbus_reset); | ||
| 1224 | dc->vmsd = &vmstate_g364fb_sysbus; | ||
| 1225 | device_class_set_props(dc, g364fb_sysbus_properties); | ||
| 1226 | } | ||
| 1227 | diff --git a/hw/display/i2c-ddc.c b/hw/display/i2c-ddc.c | ||
| 1228 | index XXXXXXX..XXXXXXX 100644 | ||
| 1229 | --- a/hw/display/i2c-ddc.c | ||
| 1230 | +++ b/hw/display/i2c-ddc.c | ||
| 1231 | @@ -XXX,XX +XXX,XX @@ static void i2c_ddc_class_init(ObjectClass *oc, void *data) | ||
| 1232 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 1233 | I2CSlaveClass *isc = I2C_SLAVE_CLASS(oc); | ||
| 1234 | |||
| 1235 | - dc->reset = i2c_ddc_reset; | ||
| 1236 | + device_class_set_legacy_reset(dc, i2c_ddc_reset); | ||
| 1237 | dc->vmsd = &vmstate_i2c_ddc; | ||
| 1238 | device_class_set_props(dc, i2c_ddc_properties); | ||
| 1239 | isc->event = i2c_ddc_event; | ||
| 1240 | diff --git a/hw/display/jazz_led.c b/hw/display/jazz_led.c | ||
| 1241 | index XXXXXXX..XXXXXXX 100644 | ||
| 1242 | --- a/hw/display/jazz_led.c | ||
| 1243 | +++ b/hw/display/jazz_led.c | ||
| 1244 | @@ -XXX,XX +XXX,XX @@ static void jazz_led_class_init(ObjectClass *klass, void *data) | ||
| 1245 | |||
| 1246 | dc->desc = "Jazz LED display", | ||
| 1247 | dc->vmsd = &vmstate_jazz_led; | ||
| 1248 | - dc->reset = jazz_led_reset; | ||
| 1249 | + device_class_set_legacy_reset(dc, jazz_led_reset); | ||
| 1250 | dc->realize = jazz_led_realize; | ||
| 1251 | } | ||
| 1252 | |||
| 1253 | diff --git a/hw/display/macfb.c b/hw/display/macfb.c | ||
| 1254 | index XXXXXXX..XXXXXXX 100644 | ||
| 1255 | --- a/hw/display/macfb.c | ||
| 1256 | +++ b/hw/display/macfb.c | ||
| 1257 | @@ -XXX,XX +XXX,XX @@ static void macfb_sysbus_class_init(ObjectClass *klass, void *data) | ||
| 1258 | |||
| 1259 | dc->realize = macfb_sysbus_realize; | ||
| 1260 | dc->desc = "SysBus Macintosh framebuffer"; | ||
| 1261 | - dc->reset = macfb_sysbus_reset; | ||
| 1262 | + device_class_set_legacy_reset(dc, macfb_sysbus_reset); | ||
| 1263 | dc->vmsd = &vmstate_macfb_sysbus; | ||
| 1264 | device_class_set_props(dc, macfb_sysbus_properties); | ||
| 1265 | } | ||
| 1266 | @@ -XXX,XX +XXX,XX @@ static void macfb_nubus_class_init(ObjectClass *klass, void *data) | ||
| 1267 | device_class_set_parent_unrealize(dc, macfb_nubus_unrealize, | ||
| 1268 | &ndc->parent_unrealize); | ||
| 1269 | dc->desc = "Nubus Macintosh framebuffer"; | ||
| 1270 | - dc->reset = macfb_nubus_reset; | ||
| 1271 | + device_class_set_legacy_reset(dc, macfb_nubus_reset); | ||
| 1272 | dc->vmsd = &vmstate_macfb_nubus; | ||
| 1273 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); | ||
| 1274 | device_class_set_props(dc, macfb_nubus_properties); | ||
| 1275 | diff --git a/hw/display/qxl.c b/hw/display/qxl.c | ||
| 1276 | index XXXXXXX..XXXXXXX 100644 | ||
| 1277 | --- a/hw/display/qxl.c | ||
| 1278 | +++ b/hw/display/qxl.c | ||
| 1279 | @@ -XXX,XX +XXX,XX @@ static void qxl_pci_class_init(ObjectClass *klass, void *data) | ||
| 1280 | k->vendor_id = REDHAT_PCI_VENDOR_ID; | ||
| 1281 | k->device_id = QXL_DEVICE_ID_STABLE; | ||
| 1282 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); | ||
| 1283 | - dc->reset = qxl_reset_handler; | ||
| 1284 | + device_class_set_legacy_reset(dc, qxl_reset_handler); | ||
| 1285 | dc->vmsd = &qxl_vmstate; | ||
| 1286 | device_class_set_props(dc, qxl_properties); | ||
| 1287 | } | ||
| 1288 | diff --git a/hw/display/sii9022.c b/hw/display/sii9022.c | ||
| 1289 | index XXXXXXX..XXXXXXX 100644 | ||
| 1290 | --- a/hw/display/sii9022.c | ||
| 1291 | +++ b/hw/display/sii9022.c | ||
| 1292 | @@ -XXX,XX +XXX,XX @@ static void sii9022_class_init(ObjectClass *klass, void *data) | ||
| 1293 | k->event = sii9022_event; | ||
| 1294 | k->recv = sii9022_rx; | ||
| 1295 | k->send = sii9022_tx; | ||
| 1296 | - dc->reset = sii9022_reset; | ||
| 1297 | + device_class_set_legacy_reset(dc, sii9022_reset); | ||
| 1298 | dc->realize = sii9022_realize; | ||
| 1299 | dc->vmsd = &vmstate_sii9022; | ||
| 1300 | } | ||
| 1301 | diff --git a/hw/display/sm501.c b/hw/display/sm501.c | ||
| 1302 | index XXXXXXX..XXXXXXX 100644 | ||
| 1303 | --- a/hw/display/sm501.c | ||
| 1304 | +++ b/hw/display/sm501.c | ||
| 1305 | @@ -XXX,XX +XXX,XX @@ static void sm501_sysbus_class_init(ObjectClass *klass, void *data) | ||
| 1306 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); | ||
| 1307 | dc->desc = "SM501 Multimedia Companion"; | ||
| 1308 | device_class_set_props(dc, sm501_sysbus_properties); | ||
| 1309 | - dc->reset = sm501_reset_sysbus; | ||
| 1310 | + device_class_set_legacy_reset(dc, sm501_reset_sysbus); | ||
| 1311 | dc->vmsd = &vmstate_sm501_sysbus; | ||
| 1312 | } | ||
| 1313 | |||
| 1314 | @@ -XXX,XX +XXX,XX @@ static void sm501_pci_class_init(ObjectClass *klass, void *data) | ||
| 1315 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); | ||
| 1316 | dc->desc = "SM501 Display Controller"; | ||
| 1317 | device_class_set_props(dc, sm501_pci_properties); | ||
| 1318 | - dc->reset = sm501_reset_pci; | ||
| 1319 | + device_class_set_legacy_reset(dc, sm501_reset_pci); | ||
| 1320 | dc->hotpluggable = false; | ||
| 1321 | dc->vmsd = &vmstate_sm501_pci; | ||
| 1322 | } | ||
| 1323 | diff --git a/hw/display/tcx.c b/hw/display/tcx.c | ||
| 1324 | index XXXXXXX..XXXXXXX 100644 | ||
| 1325 | --- a/hw/display/tcx.c | ||
| 1326 | +++ b/hw/display/tcx.c | ||
| 1327 | @@ -XXX,XX +XXX,XX @@ static void tcx_class_init(ObjectClass *klass, void *data) | ||
| 1328 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1329 | |||
| 1330 | dc->realize = tcx_realizefn; | ||
| 1331 | - dc->reset = tcx_reset; | ||
| 1332 | + device_class_set_legacy_reset(dc, tcx_reset); | ||
| 1333 | dc->vmsd = &vmstate_tcx; | ||
| 1334 | device_class_set_props(dc, tcx_properties); | ||
| 1335 | } | ||
| 1336 | diff --git a/hw/display/vga-isa.c b/hw/display/vga-isa.c | ||
| 1337 | index XXXXXXX..XXXXXXX 100644 | ||
| 1338 | --- a/hw/display/vga-isa.c | ||
| 1339 | +++ b/hw/display/vga-isa.c | ||
| 1340 | @@ -XXX,XX +XXX,XX @@ static void vga_isa_class_initfn(ObjectClass *klass, void *data) | ||
| 1341 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1342 | |||
| 1343 | dc->realize = vga_isa_realizefn; | ||
| 1344 | - dc->reset = vga_isa_reset; | ||
| 1345 | + device_class_set_legacy_reset(dc, vga_isa_reset); | ||
| 1346 | dc->vmsd = &vmstate_vga_common; | ||
| 1347 | device_class_set_props(dc, vga_isa_properties); | ||
| 1348 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); | ||
| 1349 | diff --git a/hw/display/vga-mmio.c b/hw/display/vga-mmio.c | ||
| 1350 | index XXXXXXX..XXXXXXX 100644 | ||
| 1351 | --- a/hw/display/vga-mmio.c | ||
| 1352 | +++ b/hw/display/vga-mmio.c | ||
| 1353 | @@ -XXX,XX +XXX,XX @@ static void vga_mmio_class_initfn(ObjectClass *klass, void *data) | ||
| 1354 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1355 | |||
| 1356 | dc->realize = vga_mmio_realizefn; | ||
| 1357 | - dc->reset = vga_mmio_reset; | ||
| 1358 | + device_class_set_legacy_reset(dc, vga_mmio_reset); | ||
| 1359 | dc->vmsd = &vmstate_vga_common; | ||
| 1360 | device_class_set_props(dc, vga_mmio_properties); | ||
| 1361 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); | ||
| 1362 | diff --git a/hw/display/vga-pci.c b/hw/display/vga-pci.c | ||
| 1363 | index XXXXXXX..XXXXXXX 100644 | ||
| 1364 | --- a/hw/display/vga-pci.c | ||
| 1365 | +++ b/hw/display/vga-pci.c | ||
| 1366 | @@ -XXX,XX +XXX,XX @@ static void secondary_class_init(ObjectClass *klass, void *data) | ||
| 1367 | k->exit = pci_secondary_vga_exit; | ||
| 1368 | k->class_id = PCI_CLASS_DISPLAY_OTHER; | ||
| 1369 | device_class_set_props(dc, secondary_pci_properties); | ||
| 1370 | - dc->reset = pci_secondary_vga_reset; | ||
| 1371 | + device_class_set_legacy_reset(dc, pci_secondary_vga_reset); | ||
| 1372 | } | ||
| 1373 | |||
| 1374 | static const TypeInfo vga_info = { | ||
| 1375 | diff --git a/hw/display/vmware_vga.c b/hw/display/vmware_vga.c | ||
| 1376 | index XXXXXXX..XXXXXXX 100644 | ||
| 1377 | --- a/hw/display/vmware_vga.c | ||
| 1378 | +++ b/hw/display/vmware_vga.c | ||
| 1379 | @@ -XXX,XX +XXX,XX @@ static void vmsvga_class_init(ObjectClass *klass, void *data) | ||
| 1380 | k->class_id = PCI_CLASS_DISPLAY_VGA; | ||
| 1381 | k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE; | ||
| 1382 | k->subsystem_id = SVGA_PCI_DEVICE_ID; | ||
| 1383 | - dc->reset = vmsvga_reset; | ||
| 1384 | + device_class_set_legacy_reset(dc, vmsvga_reset); | ||
| 1385 | dc->vmsd = &vmstate_vmware_vga; | ||
| 1386 | device_class_set_props(dc, vga_vmware_properties); | ||
| 1387 | dc->hotpluggable = false; | ||
| 1388 | diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c | ||
| 1389 | index XXXXXXX..XXXXXXX 100644 | ||
| 1390 | --- a/hw/display/xlnx_dp.c | ||
| 1391 | +++ b/hw/display/xlnx_dp.c | ||
| 1392 | @@ -XXX,XX +XXX,XX @@ static void xlnx_dp_class_init(ObjectClass *oc, void *data) | ||
| 1393 | |||
| 1394 | dc->realize = xlnx_dp_realize; | ||
| 1395 | dc->vmsd = &vmstate_dp; | ||
| 1396 | - dc->reset = xlnx_dp_reset; | ||
| 1397 | + device_class_set_legacy_reset(dc, xlnx_dp_reset); | ||
| 1398 | device_class_set_props(dc, xlnx_dp_device_properties); | ||
| 1399 | } | ||
| 1400 | |||
| 1401 | diff --git a/hw/dma/bcm2835_dma.c b/hw/dma/bcm2835_dma.c | ||
| 1402 | index XXXXXXX..XXXXXXX 100644 | ||
| 1403 | --- a/hw/dma/bcm2835_dma.c | ||
| 1404 | +++ b/hw/dma/bcm2835_dma.c | ||
| 1405 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_dma_class_init(ObjectClass *klass, void *data) | ||
| 1406 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1407 | |||
| 1408 | dc->realize = bcm2835_dma_realize; | ||
| 1409 | - dc->reset = bcm2835_dma_reset; | ||
| 1410 | + device_class_set_legacy_reset(dc, bcm2835_dma_reset); | ||
| 1411 | dc->vmsd = &vmstate_bcm2835_dma; | ||
| 1412 | } | ||
| 1413 | |||
| 1414 | diff --git a/hw/dma/i8257.c b/hw/dma/i8257.c | ||
| 1415 | index XXXXXXX..XXXXXXX 100644 | ||
| 1416 | --- a/hw/dma/i8257.c | ||
| 1417 | +++ b/hw/dma/i8257.c | ||
| 1418 | @@ -XXX,XX +XXX,XX @@ static void i8257_class_init(ObjectClass *klass, void *data) | ||
| 1419 | IsaDmaClass *idc = ISADMA_CLASS(klass); | ||
| 1420 | |||
| 1421 | dc->realize = i8257_realize; | ||
| 1422 | - dc->reset = i8257_reset; | ||
| 1423 | + device_class_set_legacy_reset(dc, i8257_reset); | ||
| 1424 | dc->vmsd = &vmstate_i8257; | ||
| 1425 | device_class_set_props(dc, i8257_properties); | ||
| 1426 | |||
| 1427 | diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c | ||
| 1428 | index XXXXXXX..XXXXXXX 100644 | ||
| 1429 | --- a/hw/dma/pl080.c | ||
| 1430 | +++ b/hw/dma/pl080.c | ||
| 1431 | @@ -XXX,XX +XXX,XX @@ static void pl080_class_init(ObjectClass *oc, void *data) | ||
| 1432 | dc->vmsd = &vmstate_pl080; | ||
| 1433 | dc->realize = pl080_realize; | ||
| 1434 | device_class_set_props(dc, pl080_properties); | ||
| 1435 | - dc->reset = pl080_reset; | ||
| 1436 | + device_class_set_legacy_reset(dc, pl080_reset); | ||
| 1437 | } | ||
| 1438 | |||
| 1439 | static const TypeInfo pl080_info = { | ||
| 1440 | diff --git a/hw/dma/pl330.c b/hw/dma/pl330.c | ||
| 1441 | index XXXXXXX..XXXXXXX 100644 | ||
| 1442 | --- a/hw/dma/pl330.c | ||
| 1443 | +++ b/hw/dma/pl330.c | ||
| 1444 | @@ -XXX,XX +XXX,XX @@ static void pl330_class_init(ObjectClass *klass, void *data) | ||
| 1445 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1446 | |||
| 1447 | dc->realize = pl330_realize; | ||
| 1448 | - dc->reset = pl330_reset; | ||
| 1449 | + device_class_set_legacy_reset(dc, pl330_reset); | ||
| 1450 | device_class_set_props(dc, pl330_properties); | ||
| 1451 | dc->vmsd = &vmstate_pl330; | ||
| 1452 | } | ||
| 1453 | diff --git a/hw/dma/rc4030.c b/hw/dma/rc4030.c | ||
| 1454 | index XXXXXXX..XXXXXXX 100644 | ||
| 1455 | --- a/hw/dma/rc4030.c | ||
| 1456 | +++ b/hw/dma/rc4030.c | ||
| 1457 | @@ -XXX,XX +XXX,XX @@ static void rc4030_class_init(ObjectClass *klass, void *class_data) | ||
| 1458 | |||
| 1459 | dc->realize = rc4030_realize; | ||
| 1460 | dc->unrealize = rc4030_unrealize; | ||
| 1461 | - dc->reset = rc4030_reset; | ||
| 1462 | + device_class_set_legacy_reset(dc, rc4030_reset); | ||
| 1463 | dc->vmsd = &vmstate_rc4030; | ||
| 1464 | } | ||
| 1465 | |||
| 1466 | diff --git a/hw/dma/sparc32_dma.c b/hw/dma/sparc32_dma.c | ||
| 1467 | index XXXXXXX..XXXXXXX 100644 | ||
| 1468 | --- a/hw/dma/sparc32_dma.c | ||
| 1469 | +++ b/hw/dma/sparc32_dma.c | ||
| 1470 | @@ -XXX,XX +XXX,XX @@ static void sparc32_dma_device_class_init(ObjectClass *klass, void *data) | ||
| 1471 | { | ||
| 1472 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1473 | |||
| 1474 | - dc->reset = sparc32_dma_device_reset; | ||
| 1475 | + device_class_set_legacy_reset(dc, sparc32_dma_device_reset); | ||
| 1476 | dc->vmsd = &vmstate_sparc32_dma_device; | ||
| 1477 | } | ||
| 1478 | |||
| 1479 | diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c | ||
| 1480 | index XXXXXXX..XXXXXXX 100644 | ||
| 1481 | --- a/hw/dma/xilinx_axidma.c | ||
| 1482 | +++ b/hw/dma/xilinx_axidma.c | ||
| 1483 | @@ -XXX,XX +XXX,XX @@ static void axidma_class_init(ObjectClass *klass, void *data) | ||
| 1484 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1485 | |||
| 1486 | dc->realize = xilinx_axidma_realize; | ||
| 1487 | - dc->reset = xilinx_axidma_reset; | ||
| 1488 | + device_class_set_legacy_reset(dc, xilinx_axidma_reset); | ||
| 1489 | device_class_set_props(dc, axidma_properties); | ||
| 1490 | } | ||
| 1491 | |||
| 1492 | diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c | ||
| 1493 | index XXXXXXX..XXXXXXX 100644 | ||
| 1494 | --- a/hw/dma/xlnx-zdma.c | ||
| 1495 | +++ b/hw/dma/xlnx-zdma.c | ||
| 1496 | @@ -XXX,XX +XXX,XX @@ static void zdma_class_init(ObjectClass *klass, void *data) | ||
| 1497 | { | ||
| 1498 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1499 | |||
| 1500 | - dc->reset = zdma_reset; | ||
| 1501 | + device_class_set_legacy_reset(dc, zdma_reset); | ||
| 1502 | dc->realize = zdma_realize; | ||
| 1503 | device_class_set_props(dc, zdma_props); | ||
| 1504 | dc->vmsd = &vmstate_zdma; | ||
| 1505 | diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c | ||
| 1506 | index XXXXXXX..XXXXXXX 100644 | ||
| 1507 | --- a/hw/dma/xlnx-zynq-devcfg.c | ||
| 1508 | +++ b/hw/dma/xlnx-zynq-devcfg.c | ||
| 1509 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynq_devcfg_class_init(ObjectClass *klass, void *data) | ||
| 1510 | { | ||
| 1511 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1512 | |||
| 1513 | - dc->reset = xlnx_zynq_devcfg_reset; | ||
| 1514 | + device_class_set_legacy_reset(dc, xlnx_zynq_devcfg_reset); | ||
| 1515 | dc->vmsd = &vmstate_xlnx_zynq_devcfg; | ||
| 1516 | } | ||
| 1517 | |||
| 1518 | diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c | ||
| 1519 | index XXXXXXX..XXXXXXX 100644 | ||
| 1520 | --- a/hw/dma/xlnx_csu_dma.c | ||
| 1521 | +++ b/hw/dma/xlnx_csu_dma.c | ||
| 1522 | @@ -XXX,XX +XXX,XX @@ static void xlnx_csu_dma_class_init(ObjectClass *klass, void *data) | ||
| 1523 | StreamSinkClass *ssc = STREAM_SINK_CLASS(klass); | ||
| 1524 | XlnxCSUDMAClass *xcdc = XLNX_CSU_DMA_CLASS(klass); | ||
| 1525 | |||
| 1526 | - dc->reset = xlnx_csu_dma_reset; | ||
| 1527 | + device_class_set_legacy_reset(dc, xlnx_csu_dma_reset); | ||
| 1528 | dc->realize = xlnx_csu_dma_realize; | ||
| 1529 | dc->vmsd = &vmstate_xlnx_csu_dma; | ||
| 1530 | device_class_set_props(dc, xlnx_csu_dma_properties); | ||
| 1531 | diff --git a/hw/dma/xlnx_dpdma.c b/hw/dma/xlnx_dpdma.c | ||
| 1532 | index XXXXXXX..XXXXXXX 100644 | ||
| 1533 | --- a/hw/dma/xlnx_dpdma.c | ||
| 1534 | +++ b/hw/dma/xlnx_dpdma.c | ||
| 1535 | @@ -XXX,XX +XXX,XX @@ static void xlnx_dpdma_class_init(ObjectClass *oc, void *data) | ||
| 1536 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 1537 | |||
| 1538 | dc->vmsd = &vmstate_xlnx_dpdma; | ||
| 1539 | - dc->reset = xlnx_dpdma_reset; | ||
| 1540 | + device_class_set_legacy_reset(dc, xlnx_dpdma_reset); | ||
| 1541 | } | ||
| 1542 | |||
| 1543 | static const TypeInfo xlnx_dpdma_info = { | ||
| 1544 | diff --git a/hw/fsi/aspeed_apb2opb.c b/hw/fsi/aspeed_apb2opb.c | ||
| 1545 | index XXXXXXX..XXXXXXX 100644 | ||
| 1546 | --- a/hw/fsi/aspeed_apb2opb.c | ||
| 1547 | +++ b/hw/fsi/aspeed_apb2opb.c | ||
| 1548 | @@ -XXX,XX +XXX,XX @@ static void fsi_aspeed_apb2opb_class_init(ObjectClass *klass, void *data) | ||
| 1549 | |||
| 1550 | dc->desc = "ASPEED APB2OPB Bridge"; | ||
| 1551 | dc->realize = fsi_aspeed_apb2opb_realize; | ||
| 1552 | - dc->reset = fsi_aspeed_apb2opb_reset; | ||
| 1553 | + device_class_set_legacy_reset(dc, fsi_aspeed_apb2opb_reset); | ||
| 1554 | } | ||
| 1555 | |||
| 1556 | static const TypeInfo aspeed_apb2opb_info = { | ||
| 1557 | diff --git a/hw/fsi/fsi-master.c b/hw/fsi/fsi-master.c | ||
| 1558 | index XXXXXXX..XXXXXXX 100644 | ||
| 1559 | --- a/hw/fsi/fsi-master.c | ||
| 1560 | +++ b/hw/fsi/fsi-master.c | ||
| 1561 | @@ -XXX,XX +XXX,XX @@ static void fsi_master_class_init(ObjectClass *klass, void *data) | ||
| 1562 | dc->bus_type = TYPE_OP_BUS; | ||
| 1563 | dc->desc = "FSI Master"; | ||
| 1564 | dc->realize = fsi_master_realize; | ||
| 1565 | - dc->reset = fsi_master_reset; | ||
| 1566 | + device_class_set_legacy_reset(dc, fsi_master_reset); | ||
| 1567 | } | ||
| 1568 | |||
| 1569 | static const TypeInfo fsi_master_info = { | ||
| 1570 | diff --git a/hw/fsi/fsi.c b/hw/fsi/fsi.c | ||
| 1571 | index XXXXXXX..XXXXXXX 100644 | ||
| 1572 | --- a/hw/fsi/fsi.c | ||
| 1573 | +++ b/hw/fsi/fsi.c | ||
| 1574 | @@ -XXX,XX +XXX,XX @@ static void fsi_slave_class_init(ObjectClass *klass, void *data) | ||
| 1575 | |||
| 1576 | dc->bus_type = TYPE_FSI_BUS; | ||
| 1577 | dc->desc = "FSI Slave"; | ||
| 1578 | - dc->reset = fsi_slave_reset; | ||
| 1579 | + device_class_set_legacy_reset(dc, fsi_slave_reset); | ||
| 1580 | } | ||
| 1581 | |||
| 1582 | static const TypeInfo fsi_slave_info = { | ||
| 1583 | diff --git a/hw/fsi/lbus.c b/hw/fsi/lbus.c | ||
| 1584 | index XXXXXXX..XXXXXXX 100644 | ||
| 1585 | --- a/hw/fsi/lbus.c | ||
| 1586 | +++ b/hw/fsi/lbus.c | ||
| 1587 | @@ -XXX,XX +XXX,XX @@ static void fsi_scratchpad_class_init(ObjectClass *klass, void *data) | ||
| 1588 | |||
| 1589 | dc->bus_type = TYPE_FSI_LBUS; | ||
| 1590 | dc->realize = fsi_scratchpad_realize; | ||
| 1591 | - dc->reset = fsi_scratchpad_reset; | ||
| 1592 | + device_class_set_legacy_reset(dc, fsi_scratchpad_reset); | ||
| 1593 | } | ||
| 1594 | |||
| 1595 | static const TypeInfo fsi_scratchpad_info = { | ||
| 1596 | diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c | ||
| 1597 | index XXXXXXX..XXXXXXX 100644 | ||
| 1598 | --- a/hw/gpio/aspeed_gpio.c | ||
| 1599 | +++ b/hw/gpio/aspeed_gpio.c | ||
| 1600 | @@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_class_init(ObjectClass *klass, void *data) | ||
| 1601 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1602 | |||
| 1603 | dc->realize = aspeed_gpio_realize; | ||
| 1604 | - dc->reset = aspeed_gpio_reset; | ||
| 1605 | + device_class_set_legacy_reset(dc, aspeed_gpio_reset); | ||
| 1606 | dc->desc = "Aspeed GPIO Controller"; | ||
| 1607 | dc->vmsd = &vmstate_aspeed_gpio; | ||
| 1608 | } | ||
| 1609 | diff --git a/hw/gpio/bcm2835_gpio.c b/hw/gpio/bcm2835_gpio.c | ||
| 1610 | index XXXXXXX..XXXXXXX 100644 | ||
| 1611 | --- a/hw/gpio/bcm2835_gpio.c | ||
| 1612 | +++ b/hw/gpio/bcm2835_gpio.c | ||
| 1613 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_gpio_class_init(ObjectClass *klass, void *data) | ||
| 1614 | |||
| 1615 | dc->vmsd = &vmstate_bcm2835_gpio; | ||
| 1616 | dc->realize = &bcm2835_gpio_realize; | ||
| 1617 | - dc->reset = &bcm2835_gpio_reset; | ||
| 1618 | + device_class_set_legacy_reset(dc, bcm2835_gpio_reset); | ||
| 1619 | } | ||
| 1620 | |||
| 1621 | static const TypeInfo bcm2835_gpio_info = { | ||
| 1622 | diff --git a/hw/gpio/bcm2838_gpio.c b/hw/gpio/bcm2838_gpio.c | ||
| 1623 | index XXXXXXX..XXXXXXX 100644 | ||
| 1624 | --- a/hw/gpio/bcm2838_gpio.c | ||
| 1625 | +++ b/hw/gpio/bcm2838_gpio.c | ||
| 1626 | @@ -XXX,XX +XXX,XX @@ static void bcm2838_gpio_class_init(ObjectClass *klass, void *data) | ||
| 1627 | |||
| 1628 | dc->vmsd = &vmstate_bcm2838_gpio; | ||
| 1629 | dc->realize = &bcm2838_gpio_realize; | ||
| 1630 | - dc->reset = &bcm2838_gpio_reset; | ||
| 1631 | + device_class_set_legacy_reset(dc, bcm2838_gpio_reset); | ||
| 1632 | } | ||
| 1633 | |||
| 1634 | static const TypeInfo bcm2838_gpio_info = { | ||
| 1635 | diff --git a/hw/gpio/gpio_key.c b/hw/gpio/gpio_key.c | ||
| 1636 | index XXXXXXX..XXXXXXX 100644 | ||
| 1637 | --- a/hw/gpio/gpio_key.c | ||
| 1638 | +++ b/hw/gpio/gpio_key.c | ||
| 1639 | @@ -XXX,XX +XXX,XX @@ static void gpio_key_class_init(ObjectClass *klass, void *data) | ||
| 1640 | |||
| 1641 | dc->realize = gpio_key_realize; | ||
| 1642 | dc->vmsd = &vmstate_gpio_key; | ||
| 1643 | - dc->reset = &gpio_key_reset; | ||
| 1644 | + device_class_set_legacy_reset(dc, gpio_key_reset); | ||
| 1645 | } | ||
| 1646 | |||
| 1647 | static const TypeInfo gpio_key_info = { | ||
| 1648 | diff --git a/hw/gpio/imx_gpio.c b/hw/gpio/imx_gpio.c | ||
| 1649 | index XXXXXXX..XXXXXXX 100644 | ||
| 1650 | --- a/hw/gpio/imx_gpio.c | ||
| 1651 | +++ b/hw/gpio/imx_gpio.c | ||
| 1652 | @@ -XXX,XX +XXX,XX @@ static void imx_gpio_class_init(ObjectClass *klass, void *data) | ||
| 1653 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1654 | |||
| 1655 | dc->realize = imx_gpio_realize; | ||
| 1656 | - dc->reset = imx_gpio_reset; | ||
| 1657 | + device_class_set_legacy_reset(dc, imx_gpio_reset); | ||
| 1658 | device_class_set_props(dc, imx_gpio_properties); | ||
| 1659 | dc->vmsd = &vmstate_imx_gpio; | ||
| 1660 | dc->desc = "i.MX GPIO controller"; | ||
| 1661 | diff --git a/hw/gpio/max7310.c b/hw/gpio/max7310.c | ||
| 1662 | index XXXXXXX..XXXXXXX 100644 | ||
| 1663 | --- a/hw/gpio/max7310.c | ||
| 1664 | +++ b/hw/gpio/max7310.c | ||
| 1665 | @@ -XXX,XX +XXX,XX @@ static void max7310_class_init(ObjectClass *klass, void *data) | ||
| 1666 | k->event = max7310_event; | ||
| 1667 | k->recv = max7310_rx; | ||
| 1668 | k->send = max7310_tx; | ||
| 1669 | - dc->reset = max7310_reset; | ||
| 1670 | + device_class_set_legacy_reset(dc, max7310_reset); | ||
| 1671 | dc->vmsd = &vmstate_max7310; | ||
| 1672 | } | ||
| 1673 | |||
| 1674 | diff --git a/hw/gpio/mpc8xxx.c b/hw/gpio/mpc8xxx.c | ||
| 1675 | index XXXXXXX..XXXXXXX 100644 | ||
| 1676 | --- a/hw/gpio/mpc8xxx.c | ||
| 1677 | +++ b/hw/gpio/mpc8xxx.c | ||
| 1678 | @@ -XXX,XX +XXX,XX @@ static void mpc8xxx_gpio_class_init(ObjectClass *klass, void *data) | ||
| 1679 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1680 | |||
| 1681 | dc->vmsd = &vmstate_mpc8xxx_gpio; | ||
| 1682 | - dc->reset = mpc8xxx_gpio_reset; | ||
| 1683 | + device_class_set_legacy_reset(dc, mpc8xxx_gpio_reset); | ||
| 1684 | } | ||
| 1685 | |||
| 1686 | static const TypeInfo mpc8xxx_gpio_info = { | ||
| 1687 | diff --git a/hw/gpio/nrf51_gpio.c b/hw/gpio/nrf51_gpio.c | ||
| 1688 | index XXXXXXX..XXXXXXX 100644 | ||
| 1689 | --- a/hw/gpio/nrf51_gpio.c | ||
| 1690 | +++ b/hw/gpio/nrf51_gpio.c | ||
| 1691 | @@ -XXX,XX +XXX,XX @@ static void nrf51_gpio_class_init(ObjectClass *klass, void *data) | ||
| 1692 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1693 | |||
| 1694 | dc->vmsd = &vmstate_nrf51_gpio; | ||
| 1695 | - dc->reset = nrf51_gpio_reset; | ||
| 1696 | + device_class_set_legacy_reset(dc, nrf51_gpio_reset); | ||
| 1697 | dc->desc = "nRF51 GPIO"; | ||
| 1698 | } | ||
| 1699 | |||
| 1700 | diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c | ||
| 1701 | index XXXXXXX..XXXXXXX 100644 | ||
| 1702 | --- a/hw/gpio/omap_gpio.c | ||
| 1703 | +++ b/hw/gpio/omap_gpio.c | ||
| 1704 | @@ -XXX,XX +XXX,XX @@ static void omap_gpio_class_init(ObjectClass *klass, void *data) | ||
| 1705 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1706 | |||
| 1707 | dc->realize = omap_gpio_realize; | ||
| 1708 | - dc->reset = omap_gpif_reset; | ||
| 1709 | + device_class_set_legacy_reset(dc, omap_gpif_reset); | ||
| 1710 | device_class_set_props(dc, omap_gpio_properties); | ||
| 1711 | /* Reason: pointer property "clk" */ | ||
| 1712 | dc->user_creatable = false; | ||
| 1713 | @@ -XXX,XX +XXX,XX @@ static void omap2_gpio_class_init(ObjectClass *klass, void *data) | ||
| 1714 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1715 | |||
| 1716 | dc->realize = omap2_gpio_realize; | ||
| 1717 | - dc->reset = omap2_gpif_reset; | ||
| 1718 | + device_class_set_legacy_reset(dc, omap2_gpif_reset); | ||
| 1719 | device_class_set_props(dc, omap2_gpio_properties); | ||
| 1720 | /* Reason: pointer properties "iclk", "fclk0", ..., "fclk5" */ | ||
| 1721 | dc->user_creatable = false; | ||
| 1722 | diff --git a/hw/gpio/pca9552.c b/hw/gpio/pca9552.c | ||
| 1723 | index XXXXXXX..XXXXXXX 100644 | ||
| 1724 | --- a/hw/gpio/pca9552.c | ||
| 1725 | +++ b/hw/gpio/pca9552.c | ||
| 1726 | @@ -XXX,XX +XXX,XX @@ static void pca9552_class_init(ObjectClass *oc, void *data) | ||
| 1727 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 1728 | PCA955xClass *pc = PCA955X_CLASS(oc); | ||
| 1729 | |||
| 1730 | - dc->reset = pca9552_reset; | ||
| 1731 | + device_class_set_legacy_reset(dc, pca9552_reset); | ||
| 1732 | dc->vmsd = &pca9552_vmstate; | ||
| 1733 | pc->max_reg = PCA9552_LS3; | ||
| 1734 | pc->pin_count = 16; | ||
| 1735 | diff --git a/hw/gpio/pca9554.c b/hw/gpio/pca9554.c | ||
| 1736 | index XXXXXXX..XXXXXXX 100644 | ||
| 1737 | --- a/hw/gpio/pca9554.c | ||
| 1738 | +++ b/hw/gpio/pca9554.c | ||
| 1739 | @@ -XXX,XX +XXX,XX @@ static void pca9554_class_init(ObjectClass *klass, void *data) | ||
| 1740 | k->recv = pca9554_recv; | ||
| 1741 | k->send = pca9554_send; | ||
| 1742 | dc->realize = pca9554_realize; | ||
| 1743 | - dc->reset = pca9554_reset; | ||
| 1744 | + device_class_set_legacy_reset(dc, pca9554_reset); | ||
| 1745 | dc->vmsd = &pca9554_vmstate; | ||
| 1746 | device_class_set_props(dc, pca9554_properties); | ||
| 1747 | } | ||
| 1748 | diff --git a/hw/gpio/pcf8574.c b/hw/gpio/pcf8574.c | ||
| 1749 | index XXXXXXX..XXXXXXX 100644 | ||
| 1750 | --- a/hw/gpio/pcf8574.c | ||
| 1751 | +++ b/hw/gpio/pcf8574.c | ||
| 1752 | @@ -XXX,XX +XXX,XX @@ static void pcf8574_class_init(ObjectClass *klass, void *data) | ||
| 1753 | k->recv = pcf8574_rx; | ||
| 1754 | k->send = pcf8574_tx; | ||
| 1755 | dc->realize = pcf8574_realize; | ||
| 1756 | - dc->reset = pcf8574_reset; | ||
| 1757 | + device_class_set_legacy_reset(dc, pcf8574_reset); | ||
| 1758 | dc->vmsd = &vmstate_pcf8574; | ||
| 1759 | } | ||
| 1760 | |||
| 1761 | diff --git a/hw/gpio/sifive_gpio.c b/hw/gpio/sifive_gpio.c | ||
| 1762 | index XXXXXXX..XXXXXXX 100644 | ||
| 1763 | --- a/hw/gpio/sifive_gpio.c | ||
| 1764 | +++ b/hw/gpio/sifive_gpio.c | ||
| 1765 | @@ -XXX,XX +XXX,XX @@ static void sifive_gpio_class_init(ObjectClass *klass, void *data) | ||
| 1766 | device_class_set_props(dc, sifive_gpio_properties); | ||
| 1767 | dc->vmsd = &vmstate_sifive_gpio; | ||
| 1768 | dc->realize = sifive_gpio_realize; | ||
| 1769 | - dc->reset = sifive_gpio_reset; | ||
| 1770 | + device_class_set_legacy_reset(dc, sifive_gpio_reset); | ||
| 1771 | dc->desc = "SiFive GPIO"; | ||
| 1772 | } | ||
| 1773 | |||
| 1774 | diff --git a/hw/hyperv/hyperv.c b/hw/hyperv/hyperv.c | ||
| 1775 | index XXXXXXX..XXXXXXX 100644 | ||
| 1776 | --- a/hw/hyperv/hyperv.c | ||
| 1777 | +++ b/hw/hyperv/hyperv.c | ||
| 1778 | @@ -XXX,XX +XXX,XX @@ static void synic_class_init(ObjectClass *klass, void *data) | ||
| 1779 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1780 | |||
| 1781 | dc->realize = synic_realize; | ||
| 1782 | - dc->reset = synic_reset; | ||
| 1783 | + device_class_set_legacy_reset(dc, synic_reset); | ||
| 1784 | dc->user_creatable = false; | ||
| 1785 | } | ||
| 1786 | |||
| 1787 | diff --git a/hw/hyperv/vmbus.c b/hw/hyperv/vmbus.c | ||
| 1788 | index XXXXXXX..XXXXXXX 100644 | ||
| 1789 | --- a/hw/hyperv/vmbus.c | ||
| 1790 | +++ b/hw/hyperv/vmbus.c | ||
| 1791 | @@ -XXX,XX +XXX,XX @@ static void vmbus_dev_class_init(ObjectClass *klass, void *data) | ||
| 1792 | kdev->bus_type = TYPE_VMBUS; | ||
| 1793 | kdev->realize = vmbus_dev_realize; | ||
| 1794 | kdev->unrealize = vmbus_dev_unrealize; | ||
| 1795 | - kdev->reset = vmbus_dev_reset; | ||
| 1796 | + device_class_set_legacy_reset(kdev, vmbus_dev_reset); | ||
| 1797 | } | ||
| 1798 | |||
| 1799 | static void vmbus_dev_instance_init(Object *obj) | ||
| 1800 | diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c | ||
| 1801 | index XXXXXXX..XXXXXXX 100644 | ||
| 1802 | --- a/hw/i2c/aspeed_i2c.c | ||
| 1803 | +++ b/hw/i2c/aspeed_i2c.c | ||
| 1804 | @@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_class_init(ObjectClass *klass, void *data) | ||
| 1805 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1806 | |||
| 1807 | dc->vmsd = &aspeed_i2c_vmstate; | ||
| 1808 | - dc->reset = aspeed_i2c_reset; | ||
| 1809 | + device_class_set_legacy_reset(dc, aspeed_i2c_reset); | ||
| 1810 | device_class_set_props(dc, aspeed_i2c_properties); | ||
| 1811 | dc->realize = aspeed_i2c_realize; | ||
| 1812 | dc->desc = "Aspeed I2C Controller"; | ||
| 1813 | @@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_class_init(ObjectClass *klass, void *data) | ||
| 1814 | |||
| 1815 | dc->desc = "Aspeed I2C Bus"; | ||
| 1816 | dc->realize = aspeed_i2c_bus_realize; | ||
| 1817 | - dc->reset = aspeed_i2c_bus_reset; | ||
| 1818 | + device_class_set_legacy_reset(dc, aspeed_i2c_bus_reset); | ||
| 1819 | device_class_set_props(dc, aspeed_i2c_bus_properties); | ||
| 1820 | } | ||
| 1821 | |||
| 1822 | diff --git a/hw/i2c/bcm2835_i2c.c b/hw/i2c/bcm2835_i2c.c | ||
| 1823 | index XXXXXXX..XXXXXXX 100644 | ||
| 1824 | --- a/hw/i2c/bcm2835_i2c.c | ||
| 1825 | +++ b/hw/i2c/bcm2835_i2c.c | ||
| 1826 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_i2c_class_init(ObjectClass *klass, void *data) | ||
| 1827 | { | ||
| 1828 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1829 | |||
| 1830 | - dc->reset = bcm2835_i2c_reset; | ||
| 1831 | + device_class_set_legacy_reset(dc, bcm2835_i2c_reset); | ||
| 1832 | dc->realize = bcm2835_i2c_realize; | ||
| 1833 | dc->vmsd = &vmstate_bcm2835_i2c; | ||
| 1834 | } | ||
| 1835 | diff --git a/hw/i2c/exynos4210_i2c.c b/hw/i2c/exynos4210_i2c.c | ||
| 1836 | index XXXXXXX..XXXXXXX 100644 | ||
| 1837 | --- a/hw/i2c/exynos4210_i2c.c | ||
| 1838 | +++ b/hw/i2c/exynos4210_i2c.c | ||
| 1839 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_i2c_class_init(ObjectClass *klass, void *data) | ||
| 1840 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1841 | |||
| 1842 | dc->vmsd = &exynos4210_i2c_vmstate; | ||
| 1843 | - dc->reset = exynos4210_i2c_reset; | ||
| 1844 | + device_class_set_legacy_reset(dc, exynos4210_i2c_reset); | ||
| 1845 | } | ||
| 1846 | |||
| 1847 | static const TypeInfo exynos4210_i2c_type_info = { | ||
| 1848 | diff --git a/hw/i2c/imx_i2c.c b/hw/i2c/imx_i2c.c | ||
| 1849 | index XXXXXXX..XXXXXXX 100644 | ||
| 1850 | --- a/hw/i2c/imx_i2c.c | ||
| 1851 | +++ b/hw/i2c/imx_i2c.c | ||
| 1852 | @@ -XXX,XX +XXX,XX @@ static void imx_i2c_class_init(ObjectClass *klass, void *data) | ||
| 1853 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1854 | |||
| 1855 | dc->vmsd = &imx_i2c_vmstate; | ||
| 1856 | - dc->reset = imx_i2c_reset; | ||
| 1857 | + device_class_set_legacy_reset(dc, imx_i2c_reset); | ||
| 1858 | dc->realize = imx_i2c_realize; | ||
| 1859 | dc->desc = "i.MX I2C Controller"; | ||
| 1860 | } | ||
| 1861 | diff --git a/hw/i2c/microbit_i2c.c b/hw/i2c/microbit_i2c.c | ||
| 1862 | index XXXXXXX..XXXXXXX 100644 | ||
| 1863 | --- a/hw/i2c/microbit_i2c.c | ||
| 1864 | +++ b/hw/i2c/microbit_i2c.c | ||
| 1865 | @@ -XXX,XX +XXX,XX @@ static void microbit_i2c_class_init(ObjectClass *klass, void *data) | ||
| 1866 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1867 | |||
| 1868 | dc->vmsd = µbit_i2c_vmstate; | ||
| 1869 | - dc->reset = microbit_i2c_reset; | ||
| 1870 | + device_class_set_legacy_reset(dc, microbit_i2c_reset); | ||
| 1871 | dc->realize = microbit_i2c_realize; | ||
| 1872 | dc->desc = "Microbit I2C controller"; | ||
| 1873 | } | ||
| 1874 | diff --git a/hw/i2c/mpc_i2c.c b/hw/i2c/mpc_i2c.c | ||
| 1875 | index XXXXXXX..XXXXXXX 100644 | ||
| 1876 | --- a/hw/i2c/mpc_i2c.c | ||
| 1877 | +++ b/hw/i2c/mpc_i2c.c | ||
| 1878 | @@ -XXX,XX +XXX,XX @@ static void mpc_i2c_class_init(ObjectClass *klass, void *data) | ||
| 1879 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1880 | |||
| 1881 | dc->vmsd = &mpc_i2c_vmstate ; | ||
| 1882 | - dc->reset = mpc_i2c_reset; | ||
| 1883 | + device_class_set_legacy_reset(dc, mpc_i2c_reset); | ||
| 1884 | dc->realize = mpc_i2c_realize; | ||
| 1885 | dc->desc = "MPC I2C Controller"; | ||
| 1886 | } | ||
| 1887 | diff --git a/hw/i2c/omap_i2c.c b/hw/i2c/omap_i2c.c | ||
| 1888 | index XXXXXXX..XXXXXXX 100644 | ||
| 1889 | --- a/hw/i2c/omap_i2c.c | ||
| 1890 | +++ b/hw/i2c/omap_i2c.c | ||
| 1891 | @@ -XXX,XX +XXX,XX @@ static void omap_i2c_class_init(ObjectClass *klass, void *data) | ||
| 1892 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1893 | |||
| 1894 | device_class_set_props(dc, omap_i2c_properties); | ||
| 1895 | - dc->reset = omap_i2c_reset; | ||
| 1896 | + device_class_set_legacy_reset(dc, omap_i2c_reset); | ||
| 1897 | /* Reason: pointer properties "iclk", "fclk" */ | ||
| 1898 | dc->user_creatable = false; | ||
| 1899 | dc->realize = omap_i2c_realize; | ||
| 1900 | diff --git a/hw/i2c/ppc4xx_i2c.c b/hw/i2c/ppc4xx_i2c.c | ||
| 1901 | index XXXXXXX..XXXXXXX 100644 | ||
| 1902 | --- a/hw/i2c/ppc4xx_i2c.c | ||
| 1903 | +++ b/hw/i2c/ppc4xx_i2c.c | ||
| 1904 | @@ -XXX,XX +XXX,XX @@ static void ppc4xx_i2c_class_init(ObjectClass *klass, void *data) | ||
| 1905 | { | ||
| 1906 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1907 | |||
| 1908 | - dc->reset = ppc4xx_i2c_reset; | ||
| 1909 | + device_class_set_legacy_reset(dc, ppc4xx_i2c_reset); | ||
| 1910 | } | ||
| 1911 | |||
| 1912 | static const TypeInfo ppc4xx_i2c_type_info = { | ||
| 1913 | diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c | ||
| 1914 | index XXXXXXX..XXXXXXX 100644 | ||
| 1915 | --- a/hw/i2c/smbus_eeprom.c | ||
| 1916 | +++ b/hw/i2c/smbus_eeprom.c | ||
| 1917 | @@ -XXX,XX +XXX,XX @@ static void smbus_eeprom_class_initfn(ObjectClass *klass, void *data) | ||
| 1918 | SMBusDeviceClass *sc = SMBUS_DEVICE_CLASS(klass); | ||
| 1919 | |||
| 1920 | dc->realize = smbus_eeprom_realize; | ||
| 1921 | - dc->reset = smbus_eeprom_reset; | ||
| 1922 | + device_class_set_legacy_reset(dc, smbus_eeprom_reset); | ||
| 1923 | sc->receive_byte = eeprom_receive_byte; | ||
| 1924 | sc->write_data = eeprom_write_data; | ||
| 1925 | dc->vmsd = &vmstate_smbus_eeprom; | ||
| 1926 | diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c | ||
| 1927 | index XXXXXXX..XXXXXXX 100644 | ||
| 1928 | --- a/hw/i386/amd_iommu.c | ||
| 1929 | +++ b/hw/i386/amd_iommu.c | ||
| 1930 | @@ -XXX,XX +XXX,XX @@ static void amdvi_sysbus_class_init(ObjectClass *klass, void *data) | ||
| 1931 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1932 | X86IOMMUClass *dc_class = X86_IOMMU_DEVICE_CLASS(klass); | ||
| 1933 | |||
| 1934 | - dc->reset = amdvi_sysbus_reset; | ||
| 1935 | + device_class_set_legacy_reset(dc, amdvi_sysbus_reset); | ||
| 1936 | dc->vmsd = &vmstate_amdvi_sysbus; | ||
| 1937 | dc->hotpluggable = false; | ||
| 1938 | dc_class->realize = amdvi_sysbus_realize; | ||
| 1939 | diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c | ||
| 1940 | index XXXXXXX..XXXXXXX 100644 | ||
| 1941 | --- a/hw/i386/intel_iommu.c | ||
| 1942 | +++ b/hw/i386/intel_iommu.c | ||
| 1943 | @@ -XXX,XX +XXX,XX @@ static void vtd_class_init(ObjectClass *klass, void *data) | ||
| 1944 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1945 | X86IOMMUClass *x86_class = X86_IOMMU_DEVICE_CLASS(klass); | ||
| 1946 | |||
| 1947 | - dc->reset = vtd_reset; | ||
| 1948 | + device_class_set_legacy_reset(dc, vtd_reset); | ||
| 1949 | dc->vmsd = &vtd_vmstate; | ||
| 1950 | device_class_set_props(dc, vtd_properties); | ||
| 1951 | dc->hotpluggable = false; | ||
| 1952 | diff --git a/hw/i386/kvm/i8254.c b/hw/i386/kvm/i8254.c | ||
| 1953 | index XXXXXXX..XXXXXXX 100644 | ||
| 1954 | --- a/hw/i386/kvm/i8254.c | ||
| 1955 | +++ b/hw/i386/kvm/i8254.c | ||
| 1956 | @@ -XXX,XX +XXX,XX @@ static void kvm_pit_class_init(ObjectClass *klass, void *data) | ||
| 1957 | &kpc->parent_realize); | ||
| 1958 | k->set_channel_gate = kvm_pit_set_gate; | ||
| 1959 | k->get_channel_info = kvm_pit_get_channel_info; | ||
| 1960 | - dc->reset = kvm_pit_reset; | ||
| 1961 | + device_class_set_legacy_reset(dc, kvm_pit_reset); | ||
| 1962 | device_class_set_props(dc, kvm_pit_properties); | ||
| 1963 | } | ||
| 1964 | |||
| 1965 | diff --git a/hw/i386/kvm/i8259.c b/hw/i386/kvm/i8259.c | ||
| 1966 | index XXXXXXX..XXXXXXX 100644 | ||
| 1967 | --- a/hw/i386/kvm/i8259.c | ||
| 1968 | +++ b/hw/i386/kvm/i8259.c | ||
| 1969 | @@ -XXX,XX +XXX,XX @@ static void kvm_i8259_class_init(ObjectClass *klass, void *data) | ||
| 1970 | PICCommonClass *k = PIC_COMMON_CLASS(klass); | ||
| 1971 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1972 | |||
| 1973 | - dc->reset = kvm_pic_reset; | ||
| 1974 | + device_class_set_legacy_reset(dc, kvm_pic_reset); | ||
| 1975 | device_class_set_parent_realize(dc, kvm_pic_realize, &kpc->parent_realize); | ||
| 1976 | k->pre_save = kvm_pic_get; | ||
| 1977 | k->post_load = kvm_pic_put; | ||
| 1978 | diff --git a/hw/i386/kvm/ioapic.c b/hw/i386/kvm/ioapic.c | ||
| 1979 | index XXXXXXX..XXXXXXX 100644 | ||
| 1980 | --- a/hw/i386/kvm/ioapic.c | ||
| 1981 | +++ b/hw/i386/kvm/ioapic.c | ||
| 1982 | @@ -XXX,XX +XXX,XX @@ static void kvm_ioapic_class_init(ObjectClass *klass, void *data) | ||
| 1983 | k->realize = kvm_ioapic_realize; | ||
| 1984 | k->pre_save = kvm_ioapic_get; | ||
| 1985 | k->post_load = kvm_ioapic_put; | ||
| 1986 | - dc->reset = kvm_ioapic_reset; | ||
| 1987 | + device_class_set_legacy_reset(dc, kvm_ioapic_reset); | ||
| 1988 | device_class_set_props(dc, kvm_ioapic_properties); | ||
| 1989 | } | ||
| 1990 | |||
| 1991 | diff --git a/hw/i386/kvm/xen_overlay.c b/hw/i386/kvm/xen_overlay.c | ||
| 1992 | index XXXXXXX..XXXXXXX 100644 | ||
| 1993 | --- a/hw/i386/kvm/xen_overlay.c | ||
| 1994 | +++ b/hw/i386/kvm/xen_overlay.c | ||
| 1995 | @@ -XXX,XX +XXX,XX @@ static void xen_overlay_class_init(ObjectClass *klass, void *data) | ||
| 1996 | { | ||
| 1997 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 1998 | |||
| 1999 | - dc->reset = xen_overlay_reset; | ||
| 2000 | + device_class_set_legacy_reset(dc, xen_overlay_reset); | ||
| 2001 | dc->realize = xen_overlay_realize; | ||
| 2002 | dc->vmsd = &xen_overlay_vmstate; | ||
| 2003 | } | ||
| 2004 | diff --git a/hw/i386/port92.c b/hw/i386/port92.c | ||
| 2005 | index XXXXXXX..XXXXXXX 100644 | ||
| 2006 | --- a/hw/i386/port92.c | ||
| 2007 | +++ b/hw/i386/port92.c | ||
| 2008 | @@ -XXX,XX +XXX,XX @@ static void port92_class_initfn(ObjectClass *klass, void *data) | ||
| 2009 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2010 | |||
| 2011 | dc->realize = port92_realizefn; | ||
| 2012 | - dc->reset = port92_reset; | ||
| 2013 | + device_class_set_legacy_reset(dc, port92_reset); | ||
| 2014 | dc->vmsd = &vmstate_port92_isa; | ||
| 2015 | /* | ||
| 2016 | * Reason: unlike ordinary ISA devices, this one needs additional | ||
| 2017 | diff --git a/hw/i386/vapic.c b/hw/i386/vapic.c | ||
| 2018 | index XXXXXXX..XXXXXXX 100644 | ||
| 2019 | --- a/hw/i386/vapic.c | ||
| 2020 | +++ b/hw/i386/vapic.c | ||
| 2021 | @@ -XXX,XX +XXX,XX @@ static void vapic_class_init(ObjectClass *klass, void *data) | ||
| 2022 | { | ||
| 2023 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2024 | |||
| 2025 | - dc->reset = vapic_reset; | ||
| 2026 | + device_class_set_legacy_reset(dc, vapic_reset); | ||
| 2027 | dc->vmsd = &vmstate_vapic; | ||
| 2028 | dc->realize = vapic_realize; | ||
| 2029 | } | ||
| 2030 | diff --git a/hw/i386/vmmouse.c b/hw/i386/vmmouse.c | ||
| 2031 | index XXXXXXX..XXXXXXX 100644 | ||
| 2032 | --- a/hw/i386/vmmouse.c | ||
| 2033 | +++ b/hw/i386/vmmouse.c | ||
| 2034 | @@ -XXX,XX +XXX,XX @@ static void vmmouse_class_initfn(ObjectClass *klass, void *data) | ||
| 2035 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2036 | |||
| 2037 | dc->realize = vmmouse_realizefn; | ||
| 2038 | - dc->reset = vmmouse_reset; | ||
| 2039 | + device_class_set_legacy_reset(dc, vmmouse_reset); | ||
| 2040 | dc->vmsd = &vmstate_vmmouse; | ||
| 2041 | device_class_set_props(dc, vmmouse_properties); | ||
| 2042 | set_bit(DEVICE_CATEGORY_INPUT, dc->categories); | ||
| 2043 | diff --git a/hw/i386/xen/xen_platform.c b/hw/i386/xen/xen_platform.c | ||
| 2044 | index XXXXXXX..XXXXXXX 100644 | ||
| 2045 | --- a/hw/i386/xen/xen_platform.c | ||
| 2046 | +++ b/hw/i386/xen/xen_platform.c | ||
| 2047 | @@ -XXX,XX +XXX,XX @@ static void xen_platform_class_init(ObjectClass *klass, void *data) | ||
| 2048 | k->revision = 1; | ||
| 2049 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 2050 | dc->desc = "XEN platform pci device"; | ||
| 2051 | - dc->reset = platform_reset; | ||
| 2052 | + device_class_set_legacy_reset(dc, platform_reset); | ||
| 2053 | dc->vmsd = &vmstate_xen_platform; | ||
| 2054 | } | ||
| 2055 | |||
| 2056 | diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c | ||
| 2057 | index XXXXXXX..XXXXXXX 100644 | ||
| 2058 | --- a/hw/ide/ahci.c | ||
| 2059 | +++ b/hw/ide/ahci.c | ||
| 2060 | @@ -XXX,XX +XXX,XX @@ static void sysbus_ahci_class_init(ObjectClass *klass, void *data) | ||
| 2061 | dc->realize = sysbus_ahci_realize; | ||
| 2062 | dc->vmsd = &vmstate_sysbus_ahci; | ||
| 2063 | device_class_set_props(dc, sysbus_ahci_properties); | ||
| 2064 | - dc->reset = sysbus_ahci_reset; | ||
| 2065 | + device_class_set_legacy_reset(dc, sysbus_ahci_reset); | ||
| 2066 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | ||
| 2067 | } | ||
| 2068 | |||
| 2069 | diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c | ||
| 2070 | index XXXXXXX..XXXXXXX 100644 | ||
| 2071 | --- a/hw/ide/cmd646.c | ||
| 2072 | +++ b/hw/ide/cmd646.c | ||
| 2073 | @@ -XXX,XX +XXX,XX @@ static void cmd646_ide_class_init(ObjectClass *klass, void *data) | ||
| 2074 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2075 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | ||
| 2076 | |||
| 2077 | - dc->reset = cmd646_reset; | ||
| 2078 | + device_class_set_legacy_reset(dc, cmd646_reset); | ||
| 2079 | dc->vmsd = &vmstate_ide_pci; | ||
| 2080 | k->realize = pci_cmd646_ide_realize; | ||
| 2081 | k->exit = pci_cmd646_ide_exitfn; | ||
| 2082 | diff --git a/hw/ide/ich.c b/hw/ide/ich.c | ||
| 2083 | index XXXXXXX..XXXXXXX 100644 | ||
| 2084 | --- a/hw/ide/ich.c | ||
| 2085 | +++ b/hw/ide/ich.c | ||
| 2086 | @@ -XXX,XX +XXX,XX @@ static void ich_ahci_class_init(ObjectClass *klass, void *data) | ||
| 2087 | k->revision = 0x02; | ||
| 2088 | k->class_id = PCI_CLASS_STORAGE_SATA; | ||
| 2089 | dc->vmsd = &vmstate_ich9_ahci; | ||
| 2090 | - dc->reset = pci_ich9_reset; | ||
| 2091 | + device_class_set_legacy_reset(dc, pci_ich9_reset); | ||
| 2092 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | ||
| 2093 | } | ||
| 2094 | |||
| 2095 | diff --git a/hw/ide/isa.c b/hw/ide/isa.c | ||
| 2096 | index XXXXXXX..XXXXXXX 100644 | ||
| 2097 | --- a/hw/ide/isa.c | ||
| 2098 | +++ b/hw/ide/isa.c | ||
| 2099 | @@ -XXX,XX +XXX,XX @@ static void isa_ide_class_initfn(ObjectClass *klass, void *data) | ||
| 2100 | |||
| 2101 | dc->realize = isa_ide_realizefn; | ||
| 2102 | dc->fw_name = "ide"; | ||
| 2103 | - dc->reset = isa_ide_reset; | ||
| 2104 | + device_class_set_legacy_reset(dc, isa_ide_reset); | ||
| 2105 | device_class_set_props(dc, isa_ide_properties); | ||
| 2106 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | ||
| 2107 | } | ||
| 2108 | diff --git a/hw/ide/macio.c b/hw/ide/macio.c | ||
| 2109 | index XXXXXXX..XXXXXXX 100644 | ||
| 2110 | --- a/hw/ide/macio.c | ||
| 2111 | +++ b/hw/ide/macio.c | ||
| 2112 | @@ -XXX,XX +XXX,XX @@ static void macio_ide_class_init(ObjectClass *oc, void *data) | ||
| 2113 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 2114 | |||
| 2115 | dc->realize = macio_ide_realizefn; | ||
| 2116 | - dc->reset = macio_ide_reset; | ||
| 2117 | + device_class_set_legacy_reset(dc, macio_ide_reset); | ||
| 2118 | device_class_set_props(dc, macio_ide_properties); | ||
| 2119 | dc->vmsd = &vmstate_pmac; | ||
| 2120 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | ||
| 2121 | diff --git a/hw/ide/microdrive.c b/hw/ide/microdrive.c | ||
| 2122 | index XXXXXXX..XXXXXXX 100644 | ||
| 2123 | --- a/hw/ide/microdrive.c | ||
| 2124 | +++ b/hw/ide/microdrive.c | ||
| 2125 | @@ -XXX,XX +XXX,XX @@ static void microdrive_class_init(ObjectClass *oc, void *data) | ||
| 2126 | pcc->io_write = md_common_write; | ||
| 2127 | |||
| 2128 | dc->realize = microdrive_realize; | ||
| 2129 | - dc->reset = md_reset; | ||
| 2130 | + device_class_set_legacy_reset(dc, md_reset); | ||
| 2131 | dc->vmsd = &vmstate_microdrive; | ||
| 2132 | } | ||
| 2133 | |||
| 2134 | diff --git a/hw/ide/mmio.c b/hw/ide/mmio.c | ||
| 2135 | index XXXXXXX..XXXXXXX 100644 | ||
| 2136 | --- a/hw/ide/mmio.c | ||
| 2137 | +++ b/hw/ide/mmio.c | ||
| 2138 | @@ -XXX,XX +XXX,XX @@ static void mmio_ide_class_init(ObjectClass *oc, void *data) | ||
| 2139 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 2140 | |||
| 2141 | dc->realize = mmio_ide_realizefn; | ||
| 2142 | - dc->reset = mmio_ide_reset; | ||
| 2143 | + device_class_set_legacy_reset(dc, mmio_ide_reset); | ||
| 2144 | device_class_set_props(dc, mmio_ide_properties); | ||
| 2145 | dc->vmsd = &vmstate_ide_mmio; | ||
| 2146 | } | ||
| 2147 | diff --git a/hw/ide/piix.c b/hw/ide/piix.c | ||
| 2148 | index XXXXXXX..XXXXXXX 100644 | ||
| 2149 | --- a/hw/ide/piix.c | ||
| 2150 | +++ b/hw/ide/piix.c | ||
| 2151 | @@ -XXX,XX +XXX,XX @@ static void piix3_ide_class_init(ObjectClass *klass, void *data) | ||
| 2152 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2153 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | ||
| 2154 | |||
| 2155 | - dc->reset = piix_ide_reset; | ||
| 2156 | + device_class_set_legacy_reset(dc, piix_ide_reset); | ||
| 2157 | dc->vmsd = &vmstate_ide_pci; | ||
| 2158 | k->realize = pci_piix_ide_realize; | ||
| 2159 | k->exit = pci_piix_ide_exitfn; | ||
| 2160 | @@ -XXX,XX +XXX,XX @@ static void piix4_ide_class_init(ObjectClass *klass, void *data) | ||
| 2161 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2162 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | ||
| 2163 | |||
| 2164 | - dc->reset = piix_ide_reset; | ||
| 2165 | + device_class_set_legacy_reset(dc, piix_ide_reset); | ||
| 2166 | dc->vmsd = &vmstate_ide_pci; | ||
| 2167 | k->realize = pci_piix_ide_realize; | ||
| 2168 | k->exit = pci_piix_ide_exitfn; | ||
| 2169 | diff --git a/hw/ide/sii3112.c b/hw/ide/sii3112.c | ||
| 2170 | index XXXXXXX..XXXXXXX 100644 | ||
| 2171 | --- a/hw/ide/sii3112.c | ||
| 2172 | +++ b/hw/ide/sii3112.c | ||
| 2173 | @@ -XXX,XX +XXX,XX @@ static void sii3112_pci_class_init(ObjectClass *klass, void *data) | ||
| 2174 | pd->class_id = PCI_CLASS_STORAGE_RAID; | ||
| 2175 | pd->revision = 1; | ||
| 2176 | pd->realize = sii3112_pci_realize; | ||
| 2177 | - dc->reset = sii3112_reset; | ||
| 2178 | + device_class_set_legacy_reset(dc, sii3112_reset); | ||
| 2179 | dc->desc = "SiI3112A SATA controller"; | ||
| 2180 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | ||
| 2181 | } | ||
| 2182 | diff --git a/hw/ide/via.c b/hw/ide/via.c | ||
| 2183 | index XXXXXXX..XXXXXXX 100644 | ||
| 2184 | --- a/hw/ide/via.c | ||
| 2185 | +++ b/hw/ide/via.c | ||
| 2186 | @@ -XXX,XX +XXX,XX @@ static void via_ide_class_init(ObjectClass *klass, void *data) | ||
| 2187 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2188 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | ||
| 2189 | |||
| 2190 | - dc->reset = via_ide_reset; | ||
| 2191 | + device_class_set_legacy_reset(dc, via_ide_reset); | ||
| 2192 | dc->vmsd = &vmstate_ide_pci; | ||
| 2193 | /* Reason: only works as function of VIA southbridge */ | ||
| 2194 | dc->user_creatable = false; | ||
| 2195 | diff --git a/hw/input/adb-kbd.c b/hw/input/adb-kbd.c | ||
| 2196 | index XXXXXXX..XXXXXXX 100644 | ||
| 2197 | --- a/hw/input/adb-kbd.c | ||
| 2198 | +++ b/hw/input/adb-kbd.c | ||
| 2199 | @@ -XXX,XX +XXX,XX @@ static void adb_kbd_class_init(ObjectClass *oc, void *data) | ||
| 2200 | |||
| 2201 | adc->devreq = adb_kbd_request; | ||
| 2202 | adc->devhasdata = adb_kbd_has_data; | ||
| 2203 | - dc->reset = adb_kbd_reset; | ||
| 2204 | + device_class_set_legacy_reset(dc, adb_kbd_reset); | ||
| 2205 | dc->vmsd = &vmstate_adb_kbd; | ||
| 2206 | } | ||
| 2207 | |||
| 2208 | diff --git a/hw/input/adb-mouse.c b/hw/input/adb-mouse.c | ||
| 2209 | index XXXXXXX..XXXXXXX 100644 | ||
| 2210 | --- a/hw/input/adb-mouse.c | ||
| 2211 | +++ b/hw/input/adb-mouse.c | ||
| 2212 | @@ -XXX,XX +XXX,XX @@ static void adb_mouse_class_init(ObjectClass *oc, void *data) | ||
| 2213 | |||
| 2214 | adc->devreq = adb_mouse_request; | ||
| 2215 | adc->devhasdata = adb_mouse_has_data; | ||
| 2216 | - dc->reset = adb_mouse_reset; | ||
| 2217 | + device_class_set_legacy_reset(dc, adb_mouse_reset); | ||
| 2218 | dc->vmsd = &vmstate_adb_mouse; | ||
| 2219 | } | ||
| 2220 | |||
| 2221 | diff --git a/hw/input/lm832x.c b/hw/input/lm832x.c | ||
| 2222 | index XXXXXXX..XXXXXXX 100644 | ||
| 2223 | --- a/hw/input/lm832x.c | ||
| 2224 | +++ b/hw/input/lm832x.c | ||
| 2225 | @@ -XXX,XX +XXX,XX @@ static void lm8323_class_init(ObjectClass *klass, void *data) | ||
| 2226 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2227 | I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); | ||
| 2228 | |||
| 2229 | - dc->reset = lm_kbd_reset; | ||
| 2230 | + device_class_set_legacy_reset(dc, lm_kbd_reset); | ||
| 2231 | dc->realize = lm8323_realize; | ||
| 2232 | k->event = lm_i2c_event; | ||
| 2233 | k->recv = lm_i2c_rx; | ||
| 2234 | diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c | ||
| 2235 | index XXXXXXX..XXXXXXX 100644 | ||
| 2236 | --- a/hw/input/pckbd.c | ||
| 2237 | +++ b/hw/input/pckbd.c | ||
| 2238 | @@ -XXX,XX +XXX,XX @@ static void i8042_mmio_class_init(ObjectClass *klass, void *data) | ||
| 2239 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2240 | |||
| 2241 | dc->realize = i8042_mmio_realize; | ||
| 2242 | - dc->reset = i8042_mmio_reset; | ||
| 2243 | + device_class_set_legacy_reset(dc, i8042_mmio_reset); | ||
| 2244 | dc->vmsd = &vmstate_kbd_mmio; | ||
| 2245 | device_class_set_props(dc, i8042_mmio_properties); | ||
| 2246 | set_bit(DEVICE_CATEGORY_INPUT, dc->categories); | ||
| 2247 | @@ -XXX,XX +XXX,XX @@ static void i8042_class_initfn(ObjectClass *klass, void *data) | ||
| 2248 | AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); | ||
| 2249 | |||
| 2250 | device_class_set_props(dc, i8042_properties); | ||
| 2251 | - dc->reset = i8042_reset; | ||
| 2252 | + device_class_set_legacy_reset(dc, i8042_reset); | ||
| 2253 | dc->realize = i8042_realizefn; | ||
| 2254 | dc->vmsd = &vmstate_kbd_isa; | ||
| 2255 | adevc->build_dev_aml = i8042_build_aml; | ||
| 2256 | diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c | ||
| 2257 | index XXXXXXX..XXXXXXX 100644 | ||
| 2258 | --- a/hw/intc/allwinner-a10-pic.c | ||
| 2259 | +++ b/hw/intc/allwinner-a10-pic.c | ||
| 2260 | @@ -XXX,XX +XXX,XX @@ static void aw_a10_pic_class_init(ObjectClass *klass, void *data) | ||
| 2261 | { | ||
| 2262 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2263 | |||
| 2264 | - dc->reset = aw_a10_pic_reset; | ||
| 2265 | + device_class_set_legacy_reset(dc, aw_a10_pic_reset); | ||
| 2266 | dc->desc = "allwinner a10 pic"; | ||
| 2267 | dc->vmsd = &vmstate_aw_a10_pic; | ||
| 2268 | } | ||
| 2269 | diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c | ||
| 2270 | index XXXXXXX..XXXXXXX 100644 | ||
| 2271 | --- a/hw/intc/apic_common.c | ||
| 2272 | +++ b/hw/intc/apic_common.c | ||
| 2273 | @@ -XXX,XX +XXX,XX @@ static void apic_common_class_init(ObjectClass *klass, void *data) | ||
| 2274 | { | ||
| 2275 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2276 | |||
| 2277 | - dc->reset = apic_reset_common; | ||
| 2278 | + device_class_set_legacy_reset(dc, apic_reset_common); | ||
| 2279 | device_class_set_props(dc, apic_properties_common); | ||
| 2280 | dc->realize = apic_common_realize; | ||
| 2281 | dc->unrealize = apic_common_unrealize; | ||
| 2282 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
| 2283 | index XXXXXXX..XXXXXXX 100644 | ||
| 2284 | --- a/hw/intc/armv7m_nvic.c | ||
| 2285 | +++ b/hw/intc/armv7m_nvic.c | ||
| 2286 | @@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_class_init(ObjectClass *klass, void *data) | ||
| 2287 | |||
| 2288 | dc->vmsd = &vmstate_nvic; | ||
| 2289 | device_class_set_props(dc, props_nvic); | ||
| 2290 | - dc->reset = armv7m_nvic_reset; | ||
| 2291 | + device_class_set_legacy_reset(dc, armv7m_nvic_reset); | ||
| 2292 | dc->realize = armv7m_nvic_realize; | ||
| 2293 | } | ||
| 2294 | |||
| 2295 | diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c | ||
| 2296 | index XXXXXXX..XXXXXXX 100644 | ||
| 2297 | --- a/hw/intc/aspeed_intc.c | ||
| 2298 | +++ b/hw/intc/aspeed_intc.c | ||
| 2299 | @@ -XXX,XX +XXX,XX @@ static void aspeed_intc_class_init(ObjectClass *klass, void *data) | ||
| 2300 | |||
| 2301 | dc->desc = "ASPEED INTC Controller"; | ||
| 2302 | dc->realize = aspeed_intc_realize; | ||
| 2303 | - dc->reset = aspeed_intc_reset; | ||
| 2304 | + device_class_set_legacy_reset(dc, aspeed_intc_reset); | ||
| 2305 | dc->vmsd = NULL; | ||
| 2306 | } | ||
| 2307 | |||
| 2308 | diff --git a/hw/intc/aspeed_vic.c b/hw/intc/aspeed_vic.c | ||
| 2309 | index XXXXXXX..XXXXXXX 100644 | ||
| 2310 | --- a/hw/intc/aspeed_vic.c | ||
| 2311 | +++ b/hw/intc/aspeed_vic.c | ||
| 2312 | @@ -XXX,XX +XXX,XX @@ static void aspeed_vic_class_init(ObjectClass *klass, void *data) | ||
| 2313 | { | ||
| 2314 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2315 | dc->realize = aspeed_vic_realize; | ||
| 2316 | - dc->reset = aspeed_vic_reset; | ||
| 2317 | + device_class_set_legacy_reset(dc, aspeed_vic_reset); | ||
| 2318 | dc->desc = "ASPEED Interrupt Controller (New)"; | ||
| 2319 | dc->vmsd = &vmstate_aspeed_vic; | ||
| 2320 | } | ||
| 2321 | diff --git a/hw/intc/bcm2835_ic.c b/hw/intc/bcm2835_ic.c | ||
| 2322 | index XXXXXXX..XXXXXXX 100644 | ||
| 2323 | --- a/hw/intc/bcm2835_ic.c | ||
| 2324 | +++ b/hw/intc/bcm2835_ic.c | ||
| 2325 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_ic_class_init(ObjectClass *klass, void *data) | ||
| 2326 | { | ||
| 2327 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2328 | |||
| 2329 | - dc->reset = bcm2835_ic_reset; | ||
| 2330 | + device_class_set_legacy_reset(dc, bcm2835_ic_reset); | ||
| 2331 | dc->vmsd = &vmstate_bcm2835_ic; | ||
| 2332 | } | ||
| 2333 | |||
| 2334 | diff --git a/hw/intc/bcm2836_control.c b/hw/intc/bcm2836_control.c | ||
| 2335 | index XXXXXXX..XXXXXXX 100644 | ||
| 2336 | --- a/hw/intc/bcm2836_control.c | ||
| 2337 | +++ b/hw/intc/bcm2836_control.c | ||
| 2338 | @@ -XXX,XX +XXX,XX @@ static void bcm2836_control_class_init(ObjectClass *klass, void *data) | ||
| 2339 | { | ||
| 2340 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2341 | |||
| 2342 | - dc->reset = bcm2836_control_reset; | ||
| 2343 | + device_class_set_legacy_reset(dc, bcm2836_control_reset); | ||
| 2344 | dc->vmsd = &vmstate_bcm2836_control; | ||
| 2345 | } | ||
| 2346 | |||
| 2347 | diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c | ||
| 2348 | index XXXXXXX..XXXXXXX 100644 | ||
| 2349 | --- a/hw/intc/exynos4210_combiner.c | ||
| 2350 | +++ b/hw/intc/exynos4210_combiner.c | ||
| 2351 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_combiner_class_init(ObjectClass *klass, void *data) | ||
| 2352 | { | ||
| 2353 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2354 | |||
| 2355 | - dc->reset = exynos4210_combiner_reset; | ||
| 2356 | + device_class_set_legacy_reset(dc, exynos4210_combiner_reset); | ||
| 2357 | device_class_set_props(dc, exynos4210_combiner_properties); | ||
| 2358 | dc->vmsd = &vmstate_exynos4210_combiner; | ||
| 2359 | } | ||
| 2360 | diff --git a/hw/intc/goldfish_pic.c b/hw/intc/goldfish_pic.c | ||
| 2361 | index XXXXXXX..XXXXXXX 100644 | ||
| 2362 | --- a/hw/intc/goldfish_pic.c | ||
| 2363 | +++ b/hw/intc/goldfish_pic.c | ||
| 2364 | @@ -XXX,XX +XXX,XX @@ static void goldfish_pic_class_init(ObjectClass *oc, void *data) | ||
| 2365 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 2366 | InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(oc); | ||
| 2367 | |||
| 2368 | - dc->reset = goldfish_pic_reset; | ||
| 2369 | + device_class_set_legacy_reset(dc, goldfish_pic_reset); | ||
| 2370 | dc->realize = goldfish_pic_realize; | ||
| 2371 | dc->vmsd = &vmstate_goldfish_pic; | ||
| 2372 | ic->get_statistics = goldfish_pic_get_statistics; | ||
| 2373 | diff --git a/hw/intc/grlib_irqmp.c b/hw/intc/grlib_irqmp.c | ||
| 2374 | index XXXXXXX..XXXXXXX 100644 | ||
| 2375 | --- a/hw/intc/grlib_irqmp.c | ||
| 2376 | +++ b/hw/intc/grlib_irqmp.c | ||
| 2377 | @@ -XXX,XX +XXX,XX @@ static void grlib_irqmp_class_init(ObjectClass *klass, void *data) | ||
| 2378 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2379 | |||
| 2380 | dc->realize = grlib_irqmp_realize; | ||
| 2381 | - dc->reset = grlib_irqmp_reset; | ||
| 2382 | + device_class_set_legacy_reset(dc, grlib_irqmp_reset); | ||
| 2383 | device_class_set_props(dc, grlib_irqmp_properties); | ||
| 2384 | } | ||
| 2385 | |||
| 2386 | diff --git a/hw/intc/heathrow_pic.c b/hw/intc/heathrow_pic.c | ||
| 2387 | index XXXXXXX..XXXXXXX 100644 | ||
| 2388 | --- a/hw/intc/heathrow_pic.c | ||
| 2389 | +++ b/hw/intc/heathrow_pic.c | ||
| 2390 | @@ -XXX,XX +XXX,XX @@ static void heathrow_class_init(ObjectClass *oc, void *data) | ||
| 2391 | { | ||
| 2392 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 2393 | |||
| 2394 | - dc->reset = heathrow_reset; | ||
| 2395 | + device_class_set_legacy_reset(dc, heathrow_reset); | ||
| 2396 | dc->vmsd = &vmstate_heathrow; | ||
| 2397 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 2398 | } | ||
| 2399 | diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c | ||
| 2400 | index XXXXXXX..XXXXXXX 100644 | ||
| 2401 | --- a/hw/intc/i8259.c | ||
| 2402 | +++ b/hw/intc/i8259.c | ||
| 2403 | @@ -XXX,XX +XXX,XX @@ static void i8259_class_init(ObjectClass *klass, void *data) | ||
| 2404 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2405 | |||
| 2406 | device_class_set_parent_realize(dc, pic_realize, &k->parent_realize); | ||
| 2407 | - dc->reset = pic_reset; | ||
| 2408 | + device_class_set_legacy_reset(dc, pic_reset); | ||
| 2409 | } | ||
| 2410 | |||
| 2411 | static const TypeInfo i8259_info = { | ||
| 2412 | diff --git a/hw/intc/imx_avic.c b/hw/intc/imx_avic.c | ||
| 2413 | index XXXXXXX..XXXXXXX 100644 | ||
| 2414 | --- a/hw/intc/imx_avic.c | ||
| 2415 | +++ b/hw/intc/imx_avic.c | ||
| 2416 | @@ -XXX,XX +XXX,XX @@ static void imx_avic_class_init(ObjectClass *klass, void *data) | ||
| 2417 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2418 | |||
| 2419 | dc->vmsd = &vmstate_imx_avic; | ||
| 2420 | - dc->reset = imx_avic_reset; | ||
| 2421 | + device_class_set_legacy_reset(dc, imx_avic_reset); | ||
| 2422 | dc->desc = "i.MX Advanced Vector Interrupt Controller"; | ||
| 2423 | } | ||
| 2424 | |||
| 2425 | diff --git a/hw/intc/imx_gpcv2.c b/hw/intc/imx_gpcv2.c | ||
| 2426 | index XXXXXXX..XXXXXXX 100644 | ||
| 2427 | --- a/hw/intc/imx_gpcv2.c | ||
| 2428 | +++ b/hw/intc/imx_gpcv2.c | ||
| 2429 | @@ -XXX,XX +XXX,XX @@ static void imx_gpcv2_class_init(ObjectClass *klass, void *data) | ||
| 2430 | { | ||
| 2431 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2432 | |||
| 2433 | - dc->reset = imx_gpcv2_reset; | ||
| 2434 | + device_class_set_legacy_reset(dc, imx_gpcv2_reset); | ||
| 2435 | dc->vmsd = &vmstate_imx_gpcv2; | ||
| 2436 | dc->desc = "i.MX GPCv2 Module"; | ||
| 2437 | } | ||
| 2438 | diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c | ||
| 2439 | index XXXXXXX..XXXXXXX 100644 | ||
| 2440 | --- a/hw/intc/ioapic.c | ||
| 2441 | +++ b/hw/intc/ioapic.c | ||
| 2442 | @@ -XXX,XX +XXX,XX @@ static void ioapic_class_init(ObjectClass *klass, void *data) | ||
| 2443 | * migration, otherwise first 24 gsi routes will be invalid. | ||
| 2444 | */ | ||
| 2445 | k->post_load = ioapic_update_kvm_routes; | ||
| 2446 | - dc->reset = ioapic_reset_common; | ||
| 2447 | + device_class_set_legacy_reset(dc, ioapic_reset_common); | ||
| 2448 | device_class_set_props(dc, ioapic_properties); | ||
| 2449 | } | ||
| 2450 | |||
| 2451 | diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c | ||
| 2452 | index XXXXXXX..XXXXXXX 100644 | ||
| 2453 | --- a/hw/intc/loongarch_extioi.c | ||
| 2454 | +++ b/hw/intc/loongarch_extioi.c | ||
| 2455 | @@ -XXX,XX +XXX,XX @@ static void loongarch_extioi_class_init(ObjectClass *klass, void *data) | ||
| 2456 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2457 | |||
| 2458 | dc->realize = loongarch_extioi_realize; | ||
| 2459 | - dc->reset = loongarch_extioi_reset; | ||
| 2460 | + device_class_set_legacy_reset(dc, loongarch_extioi_reset); | ||
| 2461 | device_class_set_props(dc, extioi_properties); | ||
| 2462 | dc->vmsd = &vmstate_loongarch_extioi; | ||
| 2463 | } | ||
| 2464 | diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c | ||
| 2465 | index XXXXXXX..XXXXXXX 100644 | ||
| 2466 | --- a/hw/intc/loongarch_pch_pic.c | ||
| 2467 | +++ b/hw/intc/loongarch_pch_pic.c | ||
| 2468 | @@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data) | ||
| 2469 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2470 | |||
| 2471 | dc->realize = loongarch_pch_pic_realize; | ||
| 2472 | - dc->reset = loongarch_pch_pic_reset; | ||
| 2473 | + device_class_set_legacy_reset(dc, loongarch_pch_pic_reset); | ||
| 2474 | dc->vmsd = &vmstate_loongarch_pch_pic; | ||
| 2475 | device_class_set_props(dc, loongarch_pch_pic_properties); | ||
| 2476 | } | ||
| 2477 | diff --git a/hw/intc/m68k_irqc.c b/hw/intc/m68k_irqc.c | ||
| 2478 | index XXXXXXX..XXXXXXX 100644 | ||
| 2479 | --- a/hw/intc/m68k_irqc.c | ||
| 2480 | +++ b/hw/intc/m68k_irqc.c | ||
| 2481 | @@ -XXX,XX +XXX,XX @@ static void m68k_irqc_class_init(ObjectClass *oc, void *data) | ||
| 2482 | |||
| 2483 | device_class_set_props(dc, m68k_irqc_properties); | ||
| 2484 | nc->nmi_monitor_handler = m68k_nmi; | ||
| 2485 | - dc->reset = m68k_irqc_reset; | ||
| 2486 | + device_class_set_legacy_reset(dc, m68k_irqc_reset); | ||
| 2487 | dc->vmsd = &vmstate_m68k_irqc; | ||
| 2488 | ic->get_statistics = m68k_irqc_get_statistics; | ||
| 2489 | ic->print_info = m68k_irqc_print_info; | ||
| 2490 | diff --git a/hw/intc/omap_intc.c b/hw/intc/omap_intc.c | ||
| 2491 | index XXXXXXX..XXXXXXX 100644 | ||
| 2492 | --- a/hw/intc/omap_intc.c | ||
| 2493 | +++ b/hw/intc/omap_intc.c | ||
| 2494 | @@ -XXX,XX +XXX,XX @@ static void omap_intc_class_init(ObjectClass *klass, void *data) | ||
| 2495 | { | ||
| 2496 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2497 | |||
| 2498 | - dc->reset = omap_inth_reset; | ||
| 2499 | + device_class_set_legacy_reset(dc, omap_inth_reset); | ||
| 2500 | device_class_set_props(dc, omap_intc_properties); | ||
| 2501 | /* Reason: pointer property "clk" */ | ||
| 2502 | dc->user_creatable = false; | ||
| 2503 | @@ -XXX,XX +XXX,XX @@ static void omap2_intc_class_init(ObjectClass *klass, void *data) | ||
| 2504 | { | ||
| 2505 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2506 | |||
| 2507 | - dc->reset = omap_inth_reset; | ||
| 2508 | + device_class_set_legacy_reset(dc, omap_inth_reset); | ||
| 2509 | device_class_set_props(dc, omap2_intc_properties); | ||
| 2510 | /* Reason: pointer property "iclk", "fclk" */ | ||
| 2511 | dc->user_creatable = false; | ||
| 2512 | diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c | ||
| 2513 | index XXXXXXX..XXXXXXX 100644 | ||
| 2514 | --- a/hw/intc/openpic.c | ||
| 2515 | +++ b/hw/intc/openpic.c | ||
| 2516 | @@ -XXX,XX +XXX,XX @@ static void openpic_class_init(ObjectClass *oc, void *data) | ||
| 2517 | |||
| 2518 | dc->realize = openpic_realize; | ||
| 2519 | device_class_set_props(dc, openpic_properties); | ||
| 2520 | - dc->reset = openpic_reset; | ||
| 2521 | + device_class_set_legacy_reset(dc, openpic_reset); | ||
| 2522 | dc->vmsd = &vmstate_openpic; | ||
| 2523 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 2524 | } | ||
| 2525 | diff --git a/hw/intc/openpic_kvm.c b/hw/intc/openpic_kvm.c | ||
| 2526 | index XXXXXXX..XXXXXXX 100644 | ||
| 2527 | --- a/hw/intc/openpic_kvm.c | ||
| 2528 | +++ b/hw/intc/openpic_kvm.c | ||
| 2529 | @@ -XXX,XX +XXX,XX @@ static void kvm_openpic_class_init(ObjectClass *oc, void *data) | ||
| 2530 | |||
| 2531 | dc->realize = kvm_openpic_realize; | ||
| 2532 | device_class_set_props(dc, kvm_openpic_properties); | ||
| 2533 | - dc->reset = kvm_openpic_reset; | ||
| 2534 | + device_class_set_legacy_reset(dc, kvm_openpic_reset); | ||
| 2535 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 2536 | } | ||
| 2537 | |||
| 2538 | diff --git a/hw/intc/pl190.c b/hw/intc/pl190.c | ||
| 2539 | index XXXXXXX..XXXXXXX 100644 | ||
| 2540 | --- a/hw/intc/pl190.c | ||
| 2541 | +++ b/hw/intc/pl190.c | ||
| 2542 | @@ -XXX,XX +XXX,XX @@ static void pl190_class_init(ObjectClass *klass, void *data) | ||
| 2543 | { | ||
| 2544 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2545 | |||
| 2546 | - dc->reset = pl190_reset; | ||
| 2547 | + device_class_set_legacy_reset(dc, pl190_reset); | ||
| 2548 | dc->vmsd = &vmstate_pl190; | ||
| 2549 | } | ||
| 2550 | |||
| 2551 | diff --git a/hw/intc/ppc-uic.c b/hw/intc/ppc-uic.c | ||
| 2552 | index XXXXXXX..XXXXXXX 100644 | ||
| 2553 | --- a/hw/intc/ppc-uic.c | ||
| 2554 | +++ b/hw/intc/ppc-uic.c | ||
| 2555 | @@ -XXX,XX +XXX,XX @@ static void ppc_uic_class_init(ObjectClass *klass, void *data) | ||
| 2556 | { | ||
| 2557 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2558 | |||
| 2559 | - dc->reset = ppc_uic_reset; | ||
| 2560 | + device_class_set_legacy_reset(dc, ppc_uic_reset); | ||
| 2561 | dc->realize = ppc_uic_realize; | ||
| 2562 | dc->vmsd = &ppc_uic_vmstate; | ||
| 2563 | device_class_set_props(dc, ppc_uic_properties); | ||
| 2564 | diff --git a/hw/intc/s390_flic.c b/hw/intc/s390_flic.c | ||
| 2565 | index XXXXXXX..XXXXXXX 100644 | ||
| 2566 | --- a/hw/intc/s390_flic.c | ||
| 2567 | +++ b/hw/intc/s390_flic.c | ||
| 2568 | @@ -XXX,XX +XXX,XX @@ static void qemu_s390_flic_class_init(ObjectClass *oc, void *data) | ||
| 2569 | S390FLICStateClass *fsc = S390_FLIC_COMMON_CLASS(oc); | ||
| 2570 | |||
| 2571 | device_class_set_props(dc, qemu_s390_flic_properties); | ||
| 2572 | - dc->reset = qemu_s390_flic_reset; | ||
| 2573 | + device_class_set_legacy_reset(dc, qemu_s390_flic_reset); | ||
| 2574 | dc->vmsd = &qemu_s390_flic_vmstate; | ||
| 2575 | fsc->register_io_adapter = qemu_s390_register_io_adapter; | ||
| 2576 | fsc->io_adapter_map = qemu_s390_io_adapter_map; | ||
| 2577 | diff --git a/hw/intc/s390_flic_kvm.c b/hw/intc/s390_flic_kvm.c | ||
| 2578 | index XXXXXXX..XXXXXXX 100644 | ||
| 2579 | --- a/hw/intc/s390_flic_kvm.c | ||
| 2580 | +++ b/hw/intc/s390_flic_kvm.c | ||
| 2581 | @@ -XXX,XX +XXX,XX @@ static void kvm_s390_flic_class_init(ObjectClass *oc, void *data) | ||
| 2582 | device_class_set_parent_realize(dc, kvm_s390_flic_realize, | ||
| 2583 | &kfsc->parent_realize); | ||
| 2584 | dc->vmsd = &kvm_s390_flic_vmstate; | ||
| 2585 | - dc->reset = kvm_s390_flic_reset; | ||
| 2586 | + device_class_set_legacy_reset(dc, kvm_s390_flic_reset); | ||
| 2587 | fsc->register_io_adapter = kvm_s390_register_io_adapter; | ||
| 2588 | fsc->io_adapter_map = kvm_s390_io_adapter_map; | ||
| 2589 | fsc->add_adapter_routes = kvm_s390_add_adapter_routes; | ||
| 2590 | diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c | ||
| 2591 | index XXXXXXX..XXXXXXX 100644 | ||
| 2592 | --- a/hw/intc/sifive_plic.c | ||
| 2593 | +++ b/hw/intc/sifive_plic.c | ||
| 2594 | @@ -XXX,XX +XXX,XX @@ static void sifive_plic_class_init(ObjectClass *klass, void *data) | ||
| 2595 | { | ||
| 2596 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2597 | |||
| 2598 | - dc->reset = sifive_plic_reset; | ||
| 2599 | + device_class_set_legacy_reset(dc, sifive_plic_reset); | ||
| 2600 | device_class_set_props(dc, sifive_plic_properties); | ||
| 2601 | dc->realize = sifive_plic_realize; | ||
| 2602 | dc->vmsd = &vmstate_sifive_plic; | ||
| 2603 | diff --git a/hw/intc/slavio_intctl.c b/hw/intc/slavio_intctl.c | ||
| 2604 | index XXXXXXX..XXXXXXX 100644 | ||
| 2605 | --- a/hw/intc/slavio_intctl.c | ||
| 2606 | +++ b/hw/intc/slavio_intctl.c | ||
| 2607 | @@ -XXX,XX +XXX,XX @@ static void slavio_intctl_class_init(ObjectClass *klass, void *data) | ||
| 2608 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2609 | InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(klass); | ||
| 2610 | |||
| 2611 | - dc->reset = slavio_intctl_reset; | ||
| 2612 | + device_class_set_legacy_reset(dc, slavio_intctl_reset); | ||
| 2613 | dc->vmsd = &vmstate_intctl; | ||
| 2614 | #ifdef DEBUG_IRQ_COUNT | ||
| 2615 | ic->get_statistics = slavio_intctl_get_statistics; | ||
| 2616 | diff --git a/hw/intc/xlnx-pmu-iomod-intc.c b/hw/intc/xlnx-pmu-iomod-intc.c | ||
| 2617 | index XXXXXXX..XXXXXXX 100644 | ||
| 2618 | --- a/hw/intc/xlnx-pmu-iomod-intc.c | ||
| 2619 | +++ b/hw/intc/xlnx-pmu-iomod-intc.c | ||
| 2620 | @@ -XXX,XX +XXX,XX @@ static void xlnx_pmu_io_intc_class_init(ObjectClass *klass, void *data) | ||
| 2621 | { | ||
| 2622 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2623 | |||
| 2624 | - dc->reset = xlnx_pmu_io_intc_reset; | ||
| 2625 | + device_class_set_legacy_reset(dc, xlnx_pmu_io_intc_reset); | ||
| 2626 | dc->realize = xlnx_pmu_io_intc_realize; | ||
| 2627 | dc->vmsd = &vmstate_xlnx_pmu_io_intc; | ||
| 2628 | device_class_set_props(dc, xlnx_pmu_io_intc_properties); | ||
| 2629 | diff --git a/hw/intc/xlnx-zynqmp-ipi.c b/hw/intc/xlnx-zynqmp-ipi.c | ||
| 2630 | index XXXXXXX..XXXXXXX 100644 | ||
| 2631 | --- a/hw/intc/xlnx-zynqmp-ipi.c | ||
| 2632 | +++ b/hw/intc/xlnx-zynqmp-ipi.c | ||
| 2633 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_ipi_class_init(ObjectClass *klass, void *data) | ||
| 2634 | { | ||
| 2635 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2636 | |||
| 2637 | - dc->reset = xlnx_zynqmp_ipi_reset; | ||
| 2638 | + device_class_set_legacy_reset(dc, xlnx_zynqmp_ipi_reset); | ||
| 2639 | dc->realize = xlnx_zynqmp_ipi_realize; | ||
| 2640 | dc->vmsd = &vmstate_zynqmp_pmu_ipi; | ||
| 2641 | } | ||
| 2642 | diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c | ||
| 2643 | index XXXXXXX..XXXXXXX 100644 | ||
| 2644 | --- a/hw/isa/lpc_ich9.c | ||
| 2645 | +++ b/hw/isa/lpc_ich9.c | ||
| 2646 | @@ -XXX,XX +XXX,XX @@ static void ich9_lpc_class_init(ObjectClass *klass, void *data) | ||
| 2647 | AcpiDevAmlIfClass *amldevc = ACPI_DEV_AML_IF_CLASS(klass); | ||
| 2648 | |||
| 2649 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); | ||
| 2650 | - dc->reset = ich9_lpc_reset; | ||
| 2651 | + device_class_set_legacy_reset(dc, ich9_lpc_reset); | ||
| 2652 | k->realize = ich9_lpc_realize; | ||
| 2653 | dc->vmsd = &vmstate_ich9_lpc; | ||
| 2654 | device_class_set_props(dc, ich9_lpc_properties); | ||
| 2655 | diff --git a/hw/isa/pc87312.c b/hw/isa/pc87312.c | ||
| 2656 | index XXXXXXX..XXXXXXX 100644 | ||
| 2657 | --- a/hw/isa/pc87312.c | ||
| 2658 | +++ b/hw/isa/pc87312.c | ||
| 2659 | @@ -XXX,XX +XXX,XX @@ static void pc87312_class_init(ObjectClass *klass, void *data) | ||
| 2660 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2661 | ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); | ||
| 2662 | |||
| 2663 | - dc->reset = pc87312_reset; | ||
| 2664 | + device_class_set_legacy_reset(dc, pc87312_reset); | ||
| 2665 | dc->vmsd = &vmstate_pc87312; | ||
| 2666 | device_class_set_parent_realize(dc, pc87312_realize, | ||
| 2667 | &sc->parent_realize); | ||
| 2668 | diff --git a/hw/isa/piix.c b/hw/isa/piix.c | ||
| 2669 | index XXXXXXX..XXXXXXX 100644 | ||
| 2670 | --- a/hw/isa/piix.c | ||
| 2671 | +++ b/hw/isa/piix.c | ||
| 2672 | @@ -XXX,XX +XXX,XX @@ static void pci_piix_class_init(ObjectClass *klass, void *data) | ||
| 2673 | AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); | ||
| 2674 | |||
| 2675 | k->config_write = piix_write_config; | ||
| 2676 | - dc->reset = piix_reset; | ||
| 2677 | + device_class_set_legacy_reset(dc, piix_reset); | ||
| 2678 | dc->desc = "ISA bridge"; | ||
| 2679 | dc->hotpluggable = false; | ||
| 2680 | k->vendor_id = PCI_VENDOR_ID_INTEL; | ||
| 2681 | diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c | ||
| 2682 | index XXXXXXX..XXXXXXX 100644 | ||
| 2683 | --- a/hw/isa/vt82c686.c | ||
| 2684 | +++ b/hw/isa/vt82c686.c | ||
| 2685 | @@ -XXX,XX +XXX,XX @@ static void via_pm_class_init(ObjectClass *klass, void *data) | ||
| 2686 | k->device_id = info->device_id; | ||
| 2687 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | ||
| 2688 | k->revision = 0x40; | ||
| 2689 | - dc->reset = via_pm_reset; | ||
| 2690 | + device_class_set_legacy_reset(dc, via_pm_reset); | ||
| 2691 | /* Reason: part of VIA south bridge, does not exist stand alone */ | ||
| 2692 | dc->user_creatable = false; | ||
| 2693 | dc->vmsd = &vmstate_acpi; | ||
| 2694 | @@ -XXX,XX +XXX,XX @@ static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) | ||
| 2695 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2696 | ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); | ||
| 2697 | |||
| 2698 | - dc->reset = vt82c686b_superio_reset; | ||
| 2699 | + device_class_set_legacy_reset(dc, vt82c686b_superio_reset); | ||
| 2700 | sc->serial.count = 2; | ||
| 2701 | sc->parallel.count = 1; | ||
| 2702 | sc->ide.count = 0; /* emulated by via-ide */ | ||
| 2703 | @@ -XXX,XX +XXX,XX @@ static void vt8231_superio_class_init(ObjectClass *klass, void *data) | ||
| 2704 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2705 | ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); | ||
| 2706 | |||
| 2707 | - dc->reset = vt8231_superio_reset; | ||
| 2708 | + device_class_set_legacy_reset(dc, vt8231_superio_reset); | ||
| 2709 | sc->serial.count = 1; | ||
| 2710 | sc->parallel.count = 1; | ||
| 2711 | sc->ide.count = 0; /* emulated by via-ide */ | ||
| 2712 | @@ -XXX,XX +XXX,XX @@ static void vt82c686b_class_init(ObjectClass *klass, void *data) | ||
| 2713 | k->device_id = PCI_DEVICE_ID_VIA_82C686B_ISA; | ||
| 2714 | k->class_id = PCI_CLASS_BRIDGE_ISA; | ||
| 2715 | k->revision = 0x40; | ||
| 2716 | - dc->reset = vt82c686b_isa_reset; | ||
| 2717 | + device_class_set_legacy_reset(dc, vt82c686b_isa_reset); | ||
| 2718 | dc->desc = "ISA bridge"; | ||
| 2719 | dc->vmsd = &vmstate_via; | ||
| 2720 | /* Reason: part of VIA VT82C686 southbridge, needs to be wired up */ | ||
| 2721 | @@ -XXX,XX +XXX,XX @@ static void vt8231_class_init(ObjectClass *klass, void *data) | ||
| 2722 | k->device_id = PCI_DEVICE_ID_VIA_8231_ISA; | ||
| 2723 | k->class_id = PCI_CLASS_BRIDGE_ISA; | ||
| 2724 | k->revision = 0x10; | ||
| 2725 | - dc->reset = vt8231_isa_reset; | ||
| 2726 | + device_class_set_legacy_reset(dc, vt8231_isa_reset); | ||
| 2727 | dc->desc = "ISA bridge"; | ||
| 2728 | dc->vmsd = &vmstate_via; | ||
| 2729 | /* Reason: part of VIA VT8231 southbridge, needs to be wired up */ | ||
| 2730 | diff --git a/hw/m68k/mcf5206.c b/hw/m68k/mcf5206.c | ||
| 2731 | index XXXXXXX..XXXXXXX 100644 | ||
| 2732 | --- a/hw/m68k/mcf5206.c | ||
| 2733 | +++ b/hw/m68k/mcf5206.c | ||
| 2734 | @@ -XXX,XX +XXX,XX @@ static void mcf5206_mbar_class_init(ObjectClass *oc, void *data) | ||
| 2735 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 2736 | dc->desc = "MCF5206 system integration module"; | ||
| 2737 | dc->realize = mcf5206_mbar_realize; | ||
| 2738 | - dc->reset = m5206_mbar_reset; | ||
| 2739 | + device_class_set_legacy_reset(dc, m5206_mbar_reset); | ||
| 2740 | } | ||
| 2741 | |||
| 2742 | static const TypeInfo mcf5206_mbar_info = { | ||
| 2743 | diff --git a/hw/m68k/mcf_intc.c b/hw/m68k/mcf_intc.c | ||
| 2744 | index XXXXXXX..XXXXXXX 100644 | ||
| 2745 | --- a/hw/m68k/mcf_intc.c | ||
| 2746 | +++ b/hw/m68k/mcf_intc.c | ||
| 2747 | @@ -XXX,XX +XXX,XX @@ static void mcf_intc_class_init(ObjectClass *oc, void *data) | ||
| 2748 | |||
| 2749 | device_class_set_props(dc, mcf_intc_properties); | ||
| 2750 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 2751 | - dc->reset = mcf_intc_reset; | ||
| 2752 | + device_class_set_legacy_reset(dc, mcf_intc_reset); | ||
| 2753 | } | ||
| 2754 | |||
| 2755 | static const TypeInfo mcf_intc_gate_info = { | ||
| 2756 | diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c | ||
| 2757 | index XXXXXXX..XXXXXXX 100644 | ||
| 2758 | --- a/hw/m68k/next-cube.c | ||
| 2759 | +++ b/hw/m68k/next-cube.c | ||
| 2760 | @@ -XXX,XX +XXX,XX @@ static void next_pc_class_init(ObjectClass *klass, void *data) | ||
| 2761 | |||
| 2762 | dc->desc = "NeXT Peripheral Controller"; | ||
| 2763 | dc->realize = next_pc_realize; | ||
| 2764 | - dc->reset = next_pc_reset; | ||
| 2765 | + device_class_set_legacy_reset(dc, next_pc_reset); | ||
| 2766 | device_class_set_props(dc, next_pc_properties); | ||
| 2767 | dc->vmsd = &next_pc_vmstate; | ||
| 2768 | } | ||
| 2769 | diff --git a/hw/m68k/next-kbd.c b/hw/m68k/next-kbd.c | ||
| 2770 | index XXXXXXX..XXXXXXX 100644 | ||
| 2771 | --- a/hw/m68k/next-kbd.c | ||
| 2772 | +++ b/hw/m68k/next-kbd.c | ||
| 2773 | @@ -XXX,XX +XXX,XX @@ static void nextkbd_class_init(ObjectClass *oc, void *data) | ||
| 2774 | set_bit(DEVICE_CATEGORY_INPUT, dc->categories); | ||
| 2775 | dc->vmsd = &nextkbd_vmstate; | ||
| 2776 | dc->realize = nextkbd_realize; | ||
| 2777 | - dc->reset = nextkbd_reset; | ||
| 2778 | + device_class_set_legacy_reset(dc, nextkbd_reset); | ||
| 2779 | } | ||
| 2780 | |||
| 2781 | static const TypeInfo nextkbd_info = { | ||
| 2782 | diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c | ||
| 2783 | index XXXXXXX..XXXXXXX 100644 | ||
| 2784 | --- a/hw/mem/cxl_type3.c | ||
| 2785 | +++ b/hw/mem/cxl_type3.c | ||
| 2786 | @@ -XXX,XX +XXX,XX @@ static void ct3_class_init(ObjectClass *oc, void *data) | ||
| 2787 | |||
| 2788 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | ||
| 2789 | dc->desc = "CXL Memory Device (Type 3)"; | ||
| 2790 | - dc->reset = ct3d_reset; | ||
| 2791 | + device_class_set_legacy_reset(dc, ct3d_reset); | ||
| 2792 | device_class_set_props(dc, ct3_props); | ||
| 2793 | |||
| 2794 | cvc->get_lsa_size = get_lsa_size; | ||
| 2795 | diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c | ||
| 2796 | index XXXXXXX..XXXXXXX 100644 | ||
| 2797 | --- a/hw/misc/a9scu.c | ||
| 2798 | +++ b/hw/misc/a9scu.c | ||
| 2799 | @@ -XXX,XX +XXX,XX @@ static void a9_scu_class_init(ObjectClass *klass, void *data) | ||
| 2800 | |||
| 2801 | device_class_set_props(dc, a9_scu_properties); | ||
| 2802 | dc->vmsd = &vmstate_a9_scu; | ||
| 2803 | - dc->reset = a9_scu_reset; | ||
| 2804 | + device_class_set_legacy_reset(dc, a9_scu_reset); | ||
| 2805 | dc->realize = a9_scu_realize; | ||
| 2806 | } | ||
| 2807 | |||
| 2808 | diff --git a/hw/misc/allwinner-cpucfg.c b/hw/misc/allwinner-cpucfg.c | ||
| 2809 | index XXXXXXX..XXXXXXX 100644 | ||
| 2810 | --- a/hw/misc/allwinner-cpucfg.c | ||
| 2811 | +++ b/hw/misc/allwinner-cpucfg.c | ||
| 2812 | @@ -XXX,XX +XXX,XX @@ static void allwinner_cpucfg_class_init(ObjectClass *klass, void *data) | ||
| 2813 | { | ||
| 2814 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2815 | |||
| 2816 | - dc->reset = allwinner_cpucfg_reset; | ||
| 2817 | + device_class_set_legacy_reset(dc, allwinner_cpucfg_reset); | ||
| 2818 | dc->vmsd = &allwinner_cpucfg_vmstate; | ||
| 2819 | } | ||
| 2820 | |||
| 2821 | diff --git a/hw/misc/allwinner-h3-ccu.c b/hw/misc/allwinner-h3-ccu.c | ||
| 2822 | index XXXXXXX..XXXXXXX 100644 | ||
| 2823 | --- a/hw/misc/allwinner-h3-ccu.c | ||
| 2824 | +++ b/hw/misc/allwinner-h3-ccu.c | ||
| 2825 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_ccu_class_init(ObjectClass *klass, void *data) | ||
| 2826 | { | ||
| 2827 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2828 | |||
| 2829 | - dc->reset = allwinner_h3_ccu_reset; | ||
| 2830 | + device_class_set_legacy_reset(dc, allwinner_h3_ccu_reset); | ||
| 2831 | dc->vmsd = &allwinner_h3_ccu_vmstate; | ||
| 2832 | } | ||
| 2833 | |||
| 2834 | diff --git a/hw/misc/allwinner-h3-dramc.c b/hw/misc/allwinner-h3-dramc.c | ||
| 2835 | index XXXXXXX..XXXXXXX 100644 | ||
| 2836 | --- a/hw/misc/allwinner-h3-dramc.c | ||
| 2837 | +++ b/hw/misc/allwinner-h3-dramc.c | ||
| 2838 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_dramc_class_init(ObjectClass *klass, void *data) | ||
| 2839 | { | ||
| 2840 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2841 | |||
| 2842 | - dc->reset = allwinner_h3_dramc_reset; | ||
| 2843 | + device_class_set_legacy_reset(dc, allwinner_h3_dramc_reset); | ||
| 2844 | dc->vmsd = &allwinner_h3_dramc_vmstate; | ||
| 2845 | dc->realize = allwinner_h3_dramc_realize; | ||
| 2846 | device_class_set_props(dc, allwinner_h3_dramc_properties); | ||
| 2847 | diff --git a/hw/misc/allwinner-h3-sysctrl.c b/hw/misc/allwinner-h3-sysctrl.c | ||
| 2848 | index XXXXXXX..XXXXXXX 100644 | ||
| 2849 | --- a/hw/misc/allwinner-h3-sysctrl.c | ||
| 2850 | +++ b/hw/misc/allwinner-h3-sysctrl.c | ||
| 2851 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_sysctrl_class_init(ObjectClass *klass, void *data) | ||
| 2852 | { | ||
| 2853 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2854 | |||
| 2855 | - dc->reset = allwinner_h3_sysctrl_reset; | ||
| 2856 | + device_class_set_legacy_reset(dc, allwinner_h3_sysctrl_reset); | ||
| 2857 | dc->vmsd = &allwinner_h3_sysctrl_vmstate; | ||
| 2858 | } | ||
| 2859 | |||
| 2860 | diff --git a/hw/misc/allwinner-r40-ccu.c b/hw/misc/allwinner-r40-ccu.c | ||
| 2861 | index XXXXXXX..XXXXXXX 100644 | ||
| 2862 | --- a/hw/misc/allwinner-r40-ccu.c | ||
| 2863 | +++ b/hw/misc/allwinner-r40-ccu.c | ||
| 2864 | @@ -XXX,XX +XXX,XX @@ static void allwinner_r40_ccu_class_init(ObjectClass *klass, void *data) | ||
| 2865 | { | ||
| 2866 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2867 | |||
| 2868 | - dc->reset = allwinner_r40_ccu_reset; | ||
| 2869 | + device_class_set_legacy_reset(dc, allwinner_r40_ccu_reset); | ||
| 2870 | dc->vmsd = &allwinner_r40_ccu_vmstate; | ||
| 2871 | } | ||
| 2872 | |||
| 2873 | diff --git a/hw/misc/allwinner-r40-dramc.c b/hw/misc/allwinner-r40-dramc.c | ||
| 2874 | index XXXXXXX..XXXXXXX 100644 | ||
| 2875 | --- a/hw/misc/allwinner-r40-dramc.c | ||
| 2876 | +++ b/hw/misc/allwinner-r40-dramc.c | ||
| 2877 | @@ -XXX,XX +XXX,XX @@ static void allwinner_r40_dramc_class_init(ObjectClass *klass, void *data) | ||
| 2878 | { | ||
| 2879 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2880 | |||
| 2881 | - dc->reset = allwinner_r40_dramc_reset; | ||
| 2882 | + device_class_set_legacy_reset(dc, allwinner_r40_dramc_reset); | ||
| 2883 | dc->vmsd = &allwinner_r40_dramc_vmstate; | ||
| 2884 | dc->realize = allwinner_r40_dramc_realize; | ||
| 2885 | device_class_set_props(dc, allwinner_r40_dramc_properties); | ||
| 2886 | diff --git a/hw/misc/allwinner-sid.c b/hw/misc/allwinner-sid.c | ||
| 2887 | index XXXXXXX..XXXXXXX 100644 | ||
| 2888 | --- a/hw/misc/allwinner-sid.c | ||
| 2889 | +++ b/hw/misc/allwinner-sid.c | ||
| 2890 | @@ -XXX,XX +XXX,XX @@ static void allwinner_sid_class_init(ObjectClass *klass, void *data) | ||
| 2891 | { | ||
| 2892 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2893 | |||
| 2894 | - dc->reset = allwinner_sid_reset; | ||
| 2895 | + device_class_set_legacy_reset(dc, allwinner_sid_reset); | ||
| 2896 | dc->vmsd = &allwinner_sid_vmstate; | ||
| 2897 | device_class_set_props(dc, allwinner_sid_properties); | ||
| 2898 | } | ||
| 2899 | diff --git a/hw/misc/allwinner-sramc.c b/hw/misc/allwinner-sramc.c | ||
| 2900 | index XXXXXXX..XXXXXXX 100644 | ||
| 2901 | --- a/hw/misc/allwinner-sramc.c | ||
| 2902 | +++ b/hw/misc/allwinner-sramc.c | ||
| 2903 | @@ -XXX,XX +XXX,XX @@ static void allwinner_sramc_class_init(ObjectClass *klass, void *data) | ||
| 2904 | { | ||
| 2905 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2906 | |||
| 2907 | - dc->reset = allwinner_sramc_reset; | ||
| 2908 | + device_class_set_legacy_reset(dc, allwinner_sramc_reset); | ||
| 2909 | dc->vmsd = &allwinner_sramc_vmstate; | ||
| 2910 | } | ||
| 2911 | |||
| 2912 | diff --git a/hw/misc/applesmc.c b/hw/misc/applesmc.c | ||
| 2913 | index XXXXXXX..XXXXXXX 100644 | ||
| 2914 | --- a/hw/misc/applesmc.c | ||
| 2915 | +++ b/hw/misc/applesmc.c | ||
| 2916 | @@ -XXX,XX +XXX,XX @@ static void qdev_applesmc_class_init(ObjectClass *klass, void *data) | ||
| 2917 | |||
| 2918 | dc->realize = applesmc_isa_realize; | ||
| 2919 | dc->unrealize = applesmc_unrealize; | ||
| 2920 | - dc->reset = qdev_applesmc_isa_reset; | ||
| 2921 | + device_class_set_legacy_reset(dc, qdev_applesmc_isa_reset); | ||
| 2922 | device_class_set_props(dc, applesmc_isa_properties); | ||
| 2923 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 2924 | adevc->build_dev_aml = build_applesmc_aml; | ||
| 2925 | diff --git a/hw/misc/arm_l2x0.c b/hw/misc/arm_l2x0.c | ||
| 2926 | index XXXXXXX..XXXXXXX 100644 | ||
| 2927 | --- a/hw/misc/arm_l2x0.c | ||
| 2928 | +++ b/hw/misc/arm_l2x0.c | ||
| 2929 | @@ -XXX,XX +XXX,XX @@ static void l2x0_class_init(ObjectClass *klass, void *data) | ||
| 2930 | |||
| 2931 | dc->vmsd = &vmstate_l2x0; | ||
| 2932 | device_class_set_props(dc, l2x0_properties); | ||
| 2933 | - dc->reset = l2x0_priv_reset; | ||
| 2934 | + device_class_set_legacy_reset(dc, l2x0_priv_reset); | ||
| 2935 | } | ||
| 2936 | |||
| 2937 | static const TypeInfo l2x0_info = { | ||
| 2938 | diff --git a/hw/misc/arm_sysctl.c b/hw/misc/arm_sysctl.c | ||
| 2939 | index XXXXXXX..XXXXXXX 100644 | ||
| 2940 | --- a/hw/misc/arm_sysctl.c | ||
| 2941 | +++ b/hw/misc/arm_sysctl.c | ||
| 2942 | @@ -XXX,XX +XXX,XX @@ static void arm_sysctl_class_init(ObjectClass *klass, void *data) | ||
| 2943 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2944 | |||
| 2945 | dc->realize = arm_sysctl_realize; | ||
| 2946 | - dc->reset = arm_sysctl_reset; | ||
| 2947 | + device_class_set_legacy_reset(dc, arm_sysctl_reset); | ||
| 2948 | dc->vmsd = &vmstate_arm_sysctl; | ||
| 2949 | device_class_set_props(dc, arm_sysctl_properties); | ||
| 2950 | } | ||
| 2951 | diff --git a/hw/misc/armsse-cpu-pwrctrl.c b/hw/misc/armsse-cpu-pwrctrl.c | ||
| 2952 | index XXXXXXX..XXXXXXX 100644 | ||
| 2953 | --- a/hw/misc/armsse-cpu-pwrctrl.c | ||
| 2954 | +++ b/hw/misc/armsse-cpu-pwrctrl.c | ||
| 2955 | @@ -XXX,XX +XXX,XX @@ static void pwrctrl_class_init(ObjectClass *klass, void *data) | ||
| 2956 | { | ||
| 2957 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2958 | |||
| 2959 | - dc->reset = pwrctrl_reset; | ||
| 2960 | + device_class_set_legacy_reset(dc, pwrctrl_reset); | ||
| 2961 | dc->vmsd = &pwrctrl_vmstate; | ||
| 2962 | } | ||
| 2963 | |||
| 2964 | diff --git a/hw/misc/armsse-mhu.c b/hw/misc/armsse-mhu.c | ||
| 2965 | index XXXXXXX..XXXXXXX 100644 | ||
| 2966 | --- a/hw/misc/armsse-mhu.c | ||
| 2967 | +++ b/hw/misc/armsse-mhu.c | ||
| 2968 | @@ -XXX,XX +XXX,XX @@ static void armsse_mhu_class_init(ObjectClass *klass, void *data) | ||
| 2969 | { | ||
| 2970 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2971 | |||
| 2972 | - dc->reset = armsse_mhu_reset; | ||
| 2973 | + device_class_set_legacy_reset(dc, armsse_mhu_reset); | ||
| 2974 | dc->vmsd = &armsse_mhu_vmstate; | ||
| 2975 | } | ||
| 2976 | |||
| 2977 | diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c | ||
| 2978 | index XXXXXXX..XXXXXXX 100644 | ||
| 2979 | --- a/hw/misc/aspeed_hace.c | ||
| 2980 | +++ b/hw/misc/aspeed_hace.c | ||
| 2981 | @@ -XXX,XX +XXX,XX @@ static void aspeed_hace_class_init(ObjectClass *klass, void *data) | ||
| 2982 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 2983 | |||
| 2984 | dc->realize = aspeed_hace_realize; | ||
| 2985 | - dc->reset = aspeed_hace_reset; | ||
| 2986 | + device_class_set_legacy_reset(dc, aspeed_hace_reset); | ||
| 2987 | device_class_set_props(dc, aspeed_hace_properties); | ||
| 2988 | dc->vmsd = &vmstate_aspeed_hace; | ||
| 2989 | } | ||
| 2990 | diff --git a/hw/misc/aspeed_i3c.c b/hw/misc/aspeed_i3c.c | ||
| 2991 | index XXXXXXX..XXXXXXX 100644 | ||
| 2992 | --- a/hw/misc/aspeed_i3c.c | ||
| 2993 | +++ b/hw/misc/aspeed_i3c.c | ||
| 2994 | @@ -XXX,XX +XXX,XX @@ static void aspeed_i3c_device_class_init(ObjectClass *klass, void *data) | ||
| 2995 | |||
| 2996 | dc->desc = "Aspeed I3C Device"; | ||
| 2997 | dc->realize = aspeed_i3c_device_realize; | ||
| 2998 | - dc->reset = aspeed_i3c_device_reset; | ||
| 2999 | + device_class_set_legacy_reset(dc, aspeed_i3c_device_reset); | ||
| 3000 | device_class_set_props(dc, aspeed_i3c_device_properties); | ||
| 3001 | } | ||
| 3002 | |||
| 3003 | @@ -XXX,XX +XXX,XX @@ static void aspeed_i3c_class_init(ObjectClass *klass, void *data) | ||
| 3004 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3005 | |||
| 3006 | dc->realize = aspeed_i3c_realize; | ||
| 3007 | - dc->reset = aspeed_i3c_reset; | ||
| 3008 | + device_class_set_legacy_reset(dc, aspeed_i3c_reset); | ||
| 3009 | dc->desc = "Aspeed I3C Controller"; | ||
| 3010 | dc->vmsd = &vmstate_aspeed_i3c; | ||
| 3011 | } | ||
| 3012 | diff --git a/hw/misc/aspeed_lpc.c b/hw/misc/aspeed_lpc.c | ||
| 3013 | index XXXXXXX..XXXXXXX 100644 | ||
| 3014 | --- a/hw/misc/aspeed_lpc.c | ||
| 3015 | +++ b/hw/misc/aspeed_lpc.c | ||
| 3016 | @@ -XXX,XX +XXX,XX @@ static void aspeed_lpc_class_init(ObjectClass *klass, void *data) | ||
| 3017 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3018 | |||
| 3019 | dc->realize = aspeed_lpc_realize; | ||
| 3020 | - dc->reset = aspeed_lpc_reset; | ||
| 3021 | + device_class_set_legacy_reset(dc, aspeed_lpc_reset); | ||
| 3022 | dc->desc = "Aspeed LPC Controller", | ||
| 3023 | dc->vmsd = &vmstate_aspeed_lpc; | ||
| 3024 | device_class_set_props(dc, aspeed_lpc_properties); | ||
| 3025 | diff --git a/hw/misc/aspeed_peci.c b/hw/misc/aspeed_peci.c | ||
| 3026 | index XXXXXXX..XXXXXXX 100644 | ||
| 3027 | --- a/hw/misc/aspeed_peci.c | ||
| 3028 | +++ b/hw/misc/aspeed_peci.c | ||
| 3029 | @@ -XXX,XX +XXX,XX @@ static void aspeed_peci_class_init(ObjectClass *klass, void *data) | ||
| 3030 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3031 | |||
| 3032 | dc->realize = aspeed_peci_realize; | ||
| 3033 | - dc->reset = aspeed_peci_reset; | ||
| 3034 | + device_class_set_legacy_reset(dc, aspeed_peci_reset); | ||
| 3035 | dc->desc = "Aspeed PECI Controller"; | ||
| 3036 | } | ||
| 3037 | |||
| 3038 | diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c | ||
| 3039 | index XXXXXXX..XXXXXXX 100644 | ||
| 3040 | --- a/hw/misc/aspeed_sbc.c | ||
| 3041 | +++ b/hw/misc/aspeed_sbc.c | ||
| 3042 | @@ -XXX,XX +XXX,XX @@ static void aspeed_sbc_class_init(ObjectClass *klass, void *data) | ||
| 3043 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3044 | |||
| 3045 | dc->realize = aspeed_sbc_realize; | ||
| 3046 | - dc->reset = aspeed_sbc_reset; | ||
| 3047 | + device_class_set_legacy_reset(dc, aspeed_sbc_reset); | ||
| 3048 | dc->vmsd = &vmstate_aspeed_sbc; | ||
| 3049 | device_class_set_props(dc, aspeed_sbc_properties); | ||
| 3050 | } | ||
| 3051 | diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c | ||
| 3052 | index XXXXXXX..XXXXXXX 100644 | ||
| 3053 | --- a/hw/misc/aspeed_scu.c | ||
| 3054 | +++ b/hw/misc/aspeed_scu.c | ||
| 3055 | @@ -XXX,XX +XXX,XX @@ static void aspeed_scu_class_init(ObjectClass *klass, void *data) | ||
| 3056 | { | ||
| 3057 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3058 | dc->realize = aspeed_scu_realize; | ||
| 3059 | - dc->reset = aspeed_scu_reset; | ||
| 3060 | + device_class_set_legacy_reset(dc, aspeed_scu_reset); | ||
| 3061 | dc->desc = "ASPEED System Control Unit"; | ||
| 3062 | dc->vmsd = &vmstate_aspeed_scu; | ||
| 3063 | device_class_set_props(dc, aspeed_scu_properties); | ||
| 3064 | @@ -XXX,XX +XXX,XX @@ static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data) | ||
| 3065 | AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); | ||
| 3066 | |||
| 3067 | dc->desc = "ASPEED 2600 System Control Unit"; | ||
| 3068 | - dc->reset = aspeed_ast2600_scu_reset; | ||
| 3069 | + device_class_set_legacy_reset(dc, aspeed_ast2600_scu_reset); | ||
| 3070 | asc->resets = ast2600_a3_resets; | ||
| 3071 | asc->calc_hpll = aspeed_2600_scu_calc_hpll; | ||
| 3072 | asc->get_apb = aspeed_2600_scu_get_apb_freq; | ||
| 3073 | @@ -XXX,XX +XXX,XX @@ static void aspeed_2700_scu_class_init(ObjectClass *klass, void *data) | ||
| 3074 | AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); | ||
| 3075 | |||
| 3076 | dc->desc = "ASPEED 2700 System Control Unit"; | ||
| 3077 | - dc->reset = aspeed_ast2700_scu_reset; | ||
| 3078 | + device_class_set_legacy_reset(dc, aspeed_ast2700_scu_reset); | ||
| 3079 | asc->resets = ast2700_a0_resets; | ||
| 3080 | asc->calc_hpll = aspeed_2600_scu_calc_hpll; | ||
| 3081 | asc->get_apb = aspeed_2700_scu_get_apb_freq; | ||
| 3082 | @@ -XXX,XX +XXX,XX @@ static void aspeed_2700_scuio_class_init(ObjectClass *klass, void *data) | ||
| 3083 | AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); | ||
| 3084 | |||
| 3085 | dc->desc = "ASPEED 2700 System Control Unit I/O"; | ||
| 3086 | - dc->reset = aspeed_ast2700_scu_reset; | ||
| 3087 | + device_class_set_legacy_reset(dc, aspeed_ast2700_scu_reset); | ||
| 3088 | asc->resets = ast2700_a0_resets_io; | ||
| 3089 | asc->calc_hpll = aspeed_2600_scu_calc_hpll; | ||
| 3090 | asc->get_apb = aspeed_2700_scuio_get_apb_freq; | ||
| 3091 | @@ -XXX,XX +XXX,XX @@ static void aspeed_1030_scu_class_init(ObjectClass *klass, void *data) | ||
| 3092 | AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); | ||
| 3093 | |||
| 3094 | dc->desc = "ASPEED 1030 System Control Unit"; | ||
| 3095 | - dc->reset = aspeed_ast1030_scu_reset; | ||
| 3096 | + device_class_set_legacy_reset(dc, aspeed_ast1030_scu_reset); | ||
| 3097 | asc->resets = ast1030_a1_resets; | ||
| 3098 | asc->calc_hpll = aspeed_2600_scu_calc_hpll; | ||
| 3099 | asc->get_apb = aspeed_1030_scu_get_apb_freq; | ||
| 3100 | diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c | ||
| 3101 | index XXXXXXX..XXXXXXX 100644 | ||
| 3102 | --- a/hw/misc/aspeed_sdmc.c | ||
| 3103 | +++ b/hw/misc/aspeed_sdmc.c | ||
| 3104 | @@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_class_init(ObjectClass *klass, void *data) | ||
| 3105 | { | ||
| 3106 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3107 | dc->realize = aspeed_sdmc_realize; | ||
| 3108 | - dc->reset = aspeed_sdmc_reset; | ||
| 3109 | + device_class_set_legacy_reset(dc, aspeed_sdmc_reset); | ||
| 3110 | dc->desc = "ASPEED SDRAM Memory Controller"; | ||
| 3111 | dc->vmsd = &vmstate_aspeed_sdmc; | ||
| 3112 | device_class_set_props(dc, aspeed_sdmc_properties); | ||
| 3113 | @@ -XXX,XX +XXX,XX @@ static void aspeed_2700_sdmc_class_init(ObjectClass *klass, void *data) | ||
| 3114 | AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); | ||
| 3115 | |||
| 3116 | dc->desc = "ASPEED 2700 SDRAM Memory Controller"; | ||
| 3117 | - dc->reset = aspeed_2700_sdmc_reset; | ||
| 3118 | + device_class_set_legacy_reset(dc, aspeed_2700_sdmc_reset); | ||
| 3119 | |||
| 3120 | asc->is_bus64bit = true; | ||
| 3121 | asc->max_ram_size = 8 * GiB; | ||
| 3122 | diff --git a/hw/misc/aspeed_xdma.c b/hw/misc/aspeed_xdma.c | ||
| 3123 | index XXXXXXX..XXXXXXX 100644 | ||
| 3124 | --- a/hw/misc/aspeed_xdma.c | ||
| 3125 | +++ b/hw/misc/aspeed_xdma.c | ||
| 3126 | @@ -XXX,XX +XXX,XX @@ static void aspeed_xdma_class_init(ObjectClass *classp, void *data) | ||
| 3127 | DeviceClass *dc = DEVICE_CLASS(classp); | ||
| 3128 | |||
| 3129 | dc->realize = aspeed_xdma_realize; | ||
| 3130 | - dc->reset = aspeed_xdma_reset; | ||
| 3131 | + device_class_set_legacy_reset(dc, aspeed_xdma_reset); | ||
| 3132 | dc->vmsd = &aspeed_xdma_vmstate; | ||
| 3133 | } | ||
| 3134 | |||
| 3135 | diff --git a/hw/misc/avr_power.c b/hw/misc/avr_power.c | ||
| 3136 | index XXXXXXX..XXXXXXX 100644 | ||
| 3137 | --- a/hw/misc/avr_power.c | ||
| 3138 | +++ b/hw/misc/avr_power.c | ||
| 3139 | @@ -XXX,XX +XXX,XX @@ static void avr_mask_class_init(ObjectClass *klass, void *data) | ||
| 3140 | { | ||
| 3141 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3142 | |||
| 3143 | - dc->reset = avr_mask_reset; | ||
| 3144 | + device_class_set_legacy_reset(dc, avr_mask_reset); | ||
| 3145 | } | ||
| 3146 | |||
| 3147 | static const TypeInfo avr_mask_info = { | ||
| 3148 | diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c | ||
| 3149 | index XXXXXXX..XXXXXXX 100644 | ||
| 3150 | --- a/hw/misc/bcm2835_cprman.c | ||
| 3151 | +++ b/hw/misc/bcm2835_cprman.c | ||
| 3152 | @@ -XXX,XX +XXX,XX @@ static void pll_class_init(ObjectClass *klass, void *data) | ||
| 3153 | { | ||
| 3154 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3155 | |||
| 3156 | - dc->reset = pll_reset; | ||
| 3157 | + device_class_set_legacy_reset(dc, pll_reset); | ||
| 3158 | dc->vmsd = &pll_vmstate; | ||
| 3159 | } | ||
| 3160 | |||
| 3161 | @@ -XXX,XX +XXX,XX @@ static void pll_channel_class_init(ObjectClass *klass, void *data) | ||
| 3162 | { | ||
| 3163 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3164 | |||
| 3165 | - dc->reset = pll_channel_reset; | ||
| 3166 | + device_class_set_legacy_reset(dc, pll_channel_reset); | ||
| 3167 | dc->vmsd = &pll_channel_vmstate; | ||
| 3168 | } | ||
| 3169 | |||
| 3170 | @@ -XXX,XX +XXX,XX @@ static void clock_mux_class_init(ObjectClass *klass, void *data) | ||
| 3171 | { | ||
| 3172 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3173 | |||
| 3174 | - dc->reset = clock_mux_reset; | ||
| 3175 | + device_class_set_legacy_reset(dc, clock_mux_reset); | ||
| 3176 | dc->vmsd = &clock_mux_vmstate; | ||
| 3177 | } | ||
| 3178 | |||
| 3179 | @@ -XXX,XX +XXX,XX @@ static void cprman_class_init(ObjectClass *klass, void *data) | ||
| 3180 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3181 | |||
| 3182 | dc->realize = cprman_realize; | ||
| 3183 | - dc->reset = cprman_reset; | ||
| 3184 | + device_class_set_legacy_reset(dc, cprman_reset); | ||
| 3185 | dc->vmsd = &cprman_vmstate; | ||
| 3186 | device_class_set_props(dc, cprman_properties); | ||
| 3187 | } | ||
| 3188 | diff --git a/hw/misc/bcm2835_mbox.c b/hw/misc/bcm2835_mbox.c | ||
| 3189 | index XXXXXXX..XXXXXXX 100644 | ||
| 3190 | --- a/hw/misc/bcm2835_mbox.c | ||
| 3191 | +++ b/hw/misc/bcm2835_mbox.c | ||
| 3192 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_mbox_class_init(ObjectClass *klass, void *data) | ||
| 3193 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3194 | |||
| 3195 | dc->realize = bcm2835_mbox_realize; | ||
| 3196 | - dc->reset = bcm2835_mbox_reset; | ||
| 3197 | + device_class_set_legacy_reset(dc, bcm2835_mbox_reset); | ||
| 3198 | dc->vmsd = &vmstate_bcm2835_mbox; | ||
| 3199 | } | ||
| 3200 | |||
| 3201 | diff --git a/hw/misc/bcm2835_mphi.c b/hw/misc/bcm2835_mphi.c | ||
| 3202 | index XXXXXXX..XXXXXXX 100644 | ||
| 3203 | --- a/hw/misc/bcm2835_mphi.c | ||
| 3204 | +++ b/hw/misc/bcm2835_mphi.c | ||
| 3205 | @@ -XXX,XX +XXX,XX @@ static void mphi_class_init(ObjectClass *klass, void *data) | ||
| 3206 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3207 | |||
| 3208 | dc->realize = mphi_realize; | ||
| 3209 | - dc->reset = mphi_reset; | ||
| 3210 | + device_class_set_legacy_reset(dc, mphi_reset); | ||
| 3211 | dc->vmsd = &vmstate_mphi_state; | ||
| 3212 | } | ||
| 3213 | |||
| 3214 | diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c | ||
| 3215 | index XXXXXXX..XXXXXXX 100644 | ||
| 3216 | --- a/hw/misc/bcm2835_powermgt.c | ||
| 3217 | +++ b/hw/misc/bcm2835_powermgt.c | ||
| 3218 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data) | ||
| 3219 | { | ||
| 3220 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3221 | |||
| 3222 | - dc->reset = bcm2835_powermgt_reset; | ||
| 3223 | + device_class_set_legacy_reset(dc, bcm2835_powermgt_reset); | ||
| 3224 | dc->vmsd = &vmstate_bcm2835_powermgt; | ||
| 3225 | } | ||
| 3226 | |||
| 3227 | diff --git a/hw/misc/bcm2835_rng.c b/hw/misc/bcm2835_rng.c | ||
| 3228 | index XXXXXXX..XXXXXXX 100644 | ||
| 3229 | --- a/hw/misc/bcm2835_rng.c | ||
| 3230 | +++ b/hw/misc/bcm2835_rng.c | ||
| 3231 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_rng_class_init(ObjectClass *klass, void *data) | ||
| 3232 | { | ||
| 3233 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3234 | |||
| 3235 | - dc->reset = bcm2835_rng_reset; | ||
| 3236 | + device_class_set_legacy_reset(dc, bcm2835_rng_reset); | ||
| 3237 | dc->vmsd = &vmstate_bcm2835_rng; | ||
| 3238 | } | ||
| 3239 | |||
| 3240 | diff --git a/hw/misc/bcm2835_thermal.c b/hw/misc/bcm2835_thermal.c | ||
| 3241 | index XXXXXXX..XXXXXXX 100644 | ||
| 3242 | --- a/hw/misc/bcm2835_thermal.c | ||
| 3243 | +++ b/hw/misc/bcm2835_thermal.c | ||
| 3244 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_thermal_class_init(ObjectClass *klass, void *data) | ||
| 3245 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3246 | |||
| 3247 | dc->realize = bcm2835_thermal_realize; | ||
| 3248 | - dc->reset = bcm2835_thermal_reset; | ||
| 3249 | + device_class_set_legacy_reset(dc, bcm2835_thermal_reset); | ||
| 3250 | dc->vmsd = &bcm2835_thermal_vmstate; | ||
| 3251 | } | ||
| 3252 | |||
| 3253 | diff --git a/hw/misc/eccmemctl.c b/hw/misc/eccmemctl.c | ||
| 3254 | index XXXXXXX..XXXXXXX 100644 | ||
| 3255 | --- a/hw/misc/eccmemctl.c | ||
| 3256 | +++ b/hw/misc/eccmemctl.c | ||
| 3257 | @@ -XXX,XX +XXX,XX @@ static void ecc_class_init(ObjectClass *klass, void *data) | ||
| 3258 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3259 | |||
| 3260 | dc->realize = ecc_realize; | ||
| 3261 | - dc->reset = ecc_reset; | ||
| 3262 | + device_class_set_legacy_reset(dc, ecc_reset); | ||
| 3263 | dc->vmsd = &vmstate_ecc; | ||
| 3264 | device_class_set_props(dc, ecc_properties); | ||
| 3265 | } | ||
| 3266 | diff --git a/hw/misc/exynos4210_clk.c b/hw/misc/exynos4210_clk.c | ||
| 3267 | index XXXXXXX..XXXXXXX 100644 | ||
| 3268 | --- a/hw/misc/exynos4210_clk.c | ||
| 3269 | +++ b/hw/misc/exynos4210_clk.c | ||
| 3270 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_clk_class_init(ObjectClass *klass, void *data) | ||
| 3271 | { | ||
| 3272 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3273 | |||
| 3274 | - dc->reset = exynos4210_clk_reset; | ||
| 3275 | + device_class_set_legacy_reset(dc, exynos4210_clk_reset); | ||
| 3276 | dc->vmsd = &exynos4210_clk_vmstate; | ||
| 3277 | } | ||
| 3278 | |||
| 3279 | diff --git a/hw/misc/exynos4210_pmu.c b/hw/misc/exynos4210_pmu.c | ||
| 3280 | index XXXXXXX..XXXXXXX 100644 | ||
| 3281 | --- a/hw/misc/exynos4210_pmu.c | ||
| 3282 | +++ b/hw/misc/exynos4210_pmu.c | ||
| 3283 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pmu_class_init(ObjectClass *klass, void *data) | ||
| 3284 | { | ||
| 3285 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3286 | |||
| 3287 | - dc->reset = exynos4210_pmu_reset; | ||
| 3288 | + device_class_set_legacy_reset(dc, exynos4210_pmu_reset); | ||
| 3289 | dc->vmsd = &exynos4210_pmu_vmstate; | ||
| 3290 | } | ||
| 3291 | |||
| 3292 | diff --git a/hw/misc/exynos4210_rng.c b/hw/misc/exynos4210_rng.c | ||
| 3293 | index XXXXXXX..XXXXXXX 100644 | ||
| 3294 | --- a/hw/misc/exynos4210_rng.c | ||
| 3295 | +++ b/hw/misc/exynos4210_rng.c | ||
| 3296 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_rng_class_init(ObjectClass *klass, void *data) | ||
| 3297 | { | ||
| 3298 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3299 | |||
| 3300 | - dc->reset = exynos4210_rng_reset; | ||
| 3301 | + device_class_set_legacy_reset(dc, exynos4210_rng_reset); | ||
| 3302 | dc->vmsd = &exynos4210_rng_vmstate; | ||
| 3303 | } | ||
| 3304 | |||
| 3305 | diff --git a/hw/misc/imx25_ccm.c b/hw/misc/imx25_ccm.c | ||
| 3306 | index XXXXXXX..XXXXXXX 100644 | ||
| 3307 | --- a/hw/misc/imx25_ccm.c | ||
| 3308 | +++ b/hw/misc/imx25_ccm.c | ||
| 3309 | @@ -XXX,XX +XXX,XX @@ static void imx25_ccm_class_init(ObjectClass *klass, void *data) | ||
| 3310 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3311 | IMXCCMClass *ccm = IMX_CCM_CLASS(klass); | ||
| 3312 | |||
| 3313 | - dc->reset = imx25_ccm_reset; | ||
| 3314 | + device_class_set_legacy_reset(dc, imx25_ccm_reset); | ||
| 3315 | dc->vmsd = &vmstate_imx25_ccm; | ||
| 3316 | dc->desc = "i.MX25 Clock Control Module"; | ||
| 3317 | |||
| 3318 | diff --git a/hw/misc/imx31_ccm.c b/hw/misc/imx31_ccm.c | ||
| 3319 | index XXXXXXX..XXXXXXX 100644 | ||
| 3320 | --- a/hw/misc/imx31_ccm.c | ||
| 3321 | +++ b/hw/misc/imx31_ccm.c | ||
| 3322 | @@ -XXX,XX +XXX,XX @@ static void imx31_ccm_class_init(ObjectClass *klass, void *data) | ||
| 3323 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3324 | IMXCCMClass *ccm = IMX_CCM_CLASS(klass); | ||
| 3325 | |||
| 3326 | - dc->reset = imx31_ccm_reset; | ||
| 3327 | + device_class_set_legacy_reset(dc, imx31_ccm_reset); | ||
| 3328 | dc->vmsd = &vmstate_imx31_ccm; | ||
| 3329 | dc->desc = "i.MX31 Clock Control Module"; | ||
| 3330 | |||
| 3331 | diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c | ||
| 3332 | index XXXXXXX..XXXXXXX 100644 | ||
| 3333 | --- a/hw/misc/imx6_ccm.c | ||
| 3334 | +++ b/hw/misc/imx6_ccm.c | ||
| 3335 | @@ -XXX,XX +XXX,XX @@ static void imx6_ccm_class_init(ObjectClass *klass, void *data) | ||
| 3336 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3337 | IMXCCMClass *ccm = IMX_CCM_CLASS(klass); | ||
| 3338 | |||
| 3339 | - dc->reset = imx6_ccm_reset; | ||
| 3340 | + device_class_set_legacy_reset(dc, imx6_ccm_reset); | ||
| 3341 | dc->vmsd = &vmstate_imx6_ccm; | ||
| 3342 | dc->desc = "i.MX6 Clock Control Module"; | ||
| 3343 | |||
| 3344 | diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c | ||
| 3345 | index XXXXXXX..XXXXXXX 100644 | ||
| 3346 | --- a/hw/misc/imx6_src.c | ||
| 3347 | +++ b/hw/misc/imx6_src.c | ||
| 3348 | @@ -XXX,XX +XXX,XX @@ static void imx6_src_class_init(ObjectClass *klass, void *data) | ||
| 3349 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3350 | |||
| 3351 | dc->realize = imx6_src_realize; | ||
| 3352 | - dc->reset = imx6_src_reset; | ||
| 3353 | + device_class_set_legacy_reset(dc, imx6_src_reset); | ||
| 3354 | dc->vmsd = &vmstate_imx6_src; | ||
| 3355 | dc->desc = "i.MX6 System Reset Controller"; | ||
| 3356 | } | ||
| 3357 | diff --git a/hw/misc/imx6ul_ccm.c b/hw/misc/imx6ul_ccm.c | ||
| 3358 | index XXXXXXX..XXXXXXX 100644 | ||
| 3359 | --- a/hw/misc/imx6ul_ccm.c | ||
| 3360 | +++ b/hw/misc/imx6ul_ccm.c | ||
| 3361 | @@ -XXX,XX +XXX,XX @@ static void imx6ul_ccm_class_init(ObjectClass *klass, void *data) | ||
| 3362 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3363 | IMXCCMClass *ccm = IMX_CCM_CLASS(klass); | ||
| 3364 | |||
| 3365 | - dc->reset = imx6ul_ccm_reset; | ||
| 3366 | + device_class_set_legacy_reset(dc, imx6ul_ccm_reset); | ||
| 3367 | dc->vmsd = &vmstate_imx6ul_ccm; | ||
| 3368 | dc->desc = "i.MX6UL Clock Control Module"; | ||
| 3369 | |||
| 3370 | diff --git a/hw/misc/imx7_ccm.c b/hw/misc/imx7_ccm.c | ||
| 3371 | index XXXXXXX..XXXXXXX 100644 | ||
| 3372 | --- a/hw/misc/imx7_ccm.c | ||
| 3373 | +++ b/hw/misc/imx7_ccm.c | ||
| 3374 | @@ -XXX,XX +XXX,XX @@ static void imx7_ccm_class_init(ObjectClass *klass, void *data) | ||
| 3375 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3376 | IMXCCMClass *ccm = IMX_CCM_CLASS(klass); | ||
| 3377 | |||
| 3378 | - dc->reset = imx7_ccm_reset; | ||
| 3379 | + device_class_set_legacy_reset(dc, imx7_ccm_reset); | ||
| 3380 | dc->vmsd = &vmstate_imx7_ccm; | ||
| 3381 | dc->desc = "i.MX7 Clock Control Module"; | ||
| 3382 | |||
| 3383 | @@ -XXX,XX +XXX,XX @@ static void imx7_analog_class_init(ObjectClass *klass, void *data) | ||
| 3384 | { | ||
| 3385 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3386 | |||
| 3387 | - dc->reset = imx7_analog_reset; | ||
| 3388 | + device_class_set_legacy_reset(dc, imx7_analog_reset); | ||
| 3389 | dc->vmsd = &vmstate_imx7_analog; | ||
| 3390 | dc->desc = "i.MX7 Analog Module"; | ||
| 3391 | } | ||
| 3392 | diff --git a/hw/misc/imx7_snvs.c b/hw/misc/imx7_snvs.c | ||
| 3393 | index XXXXXXX..XXXXXXX 100644 | ||
| 3394 | --- a/hw/misc/imx7_snvs.c | ||
| 3395 | +++ b/hw/misc/imx7_snvs.c | ||
| 3396 | @@ -XXX,XX +XXX,XX @@ static void imx7_snvs_class_init(ObjectClass *klass, void *data) | ||
| 3397 | { | ||
| 3398 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3399 | |||
| 3400 | - dc->reset = imx7_snvs_reset; | ||
| 3401 | + device_class_set_legacy_reset(dc, imx7_snvs_reset); | ||
| 3402 | dc->vmsd = &vmstate_imx7_snvs; | ||
| 3403 | dc->desc = "i.MX7 Secure Non-Volatile Storage Module"; | ||
| 3404 | } | ||
| 3405 | diff --git a/hw/misc/imx7_src.c b/hw/misc/imx7_src.c | ||
| 3406 | index XXXXXXX..XXXXXXX 100644 | ||
| 3407 | --- a/hw/misc/imx7_src.c | ||
| 3408 | +++ b/hw/misc/imx7_src.c | ||
| 3409 | @@ -XXX,XX +XXX,XX @@ static void imx7_src_class_init(ObjectClass *klass, void *data) | ||
| 3410 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3411 | |||
| 3412 | dc->realize = imx7_src_realize; | ||
| 3413 | - dc->reset = imx7_src_reset; | ||
| 3414 | + device_class_set_legacy_reset(dc, imx7_src_reset); | ||
| 3415 | dc->vmsd = &vmstate_imx7_src; | ||
| 3416 | dc->desc = "i.MX6 System Reset Controller"; | ||
| 3417 | } | ||
| 3418 | diff --git a/hw/misc/imx_rngc.c b/hw/misc/imx_rngc.c | ||
| 3419 | index XXXXXXX..XXXXXXX 100644 | ||
| 3420 | --- a/hw/misc/imx_rngc.c | ||
| 3421 | +++ b/hw/misc/imx_rngc.c | ||
| 3422 | @@ -XXX,XX +XXX,XX @@ static void imx_rngc_class_init(ObjectClass *klass, void *data) | ||
| 3423 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3424 | |||
| 3425 | dc->realize = imx_rngc_realize; | ||
| 3426 | - dc->reset = imx_rngc_reset; | ||
| 3427 | + device_class_set_legacy_reset(dc, imx_rngc_reset); | ||
| 3428 | dc->desc = RNGC_NAME, | ||
| 3429 | dc->vmsd = &vmstate_imx_rngc; | ||
| 3430 | } | ||
| 3431 | diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c | ||
| 3432 | index XXXXXXX..XXXXXXX 100644 | ||
| 3433 | --- a/hw/misc/iotkit-secctl.c | ||
| 3434 | +++ b/hw/misc/iotkit-secctl.c | ||
| 3435 | @@ -XXX,XX +XXX,XX @@ static void iotkit_secctl_class_init(ObjectClass *klass, void *data) | ||
| 3436 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3437 | |||
| 3438 | dc->vmsd = &iotkit_secctl_vmstate; | ||
| 3439 | - dc->reset = iotkit_secctl_reset; | ||
| 3440 | + device_class_set_legacy_reset(dc, iotkit_secctl_reset); | ||
| 3441 | dc->realize = iotkit_secctl_realize; | ||
| 3442 | device_class_set_props(dc, iotkit_secctl_props); | ||
| 3443 | } | ||
| 3444 | diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c | ||
| 3445 | index XXXXXXX..XXXXXXX 100644 | ||
| 3446 | --- a/hw/misc/iotkit-sysctl.c | ||
| 3447 | +++ b/hw/misc/iotkit-sysctl.c | ||
| 3448 | @@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_class_init(ObjectClass *klass, void *data) | ||
| 3449 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3450 | |||
| 3451 | dc->vmsd = &iotkit_sysctl_vmstate; | ||
| 3452 | - dc->reset = iotkit_sysctl_reset; | ||
| 3453 | + device_class_set_legacy_reset(dc, iotkit_sysctl_reset); | ||
| 3454 | device_class_set_props(dc, iotkit_sysctl_props); | ||
| 3455 | dc->realize = iotkit_sysctl_realize; | ||
| 3456 | } | ||
| 3457 | diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c | ||
| 3458 | index XXXXXXX..XXXXXXX 100644 | ||
| 3459 | --- a/hw/misc/ivshmem.c | ||
| 3460 | +++ b/hw/misc/ivshmem.c | ||
| 3461 | @@ -XXX,XX +XXX,XX @@ static void ivshmem_common_class_init(ObjectClass *klass, void *data) | ||
| 3462 | k->device_id = PCI_DEVICE_ID_IVSHMEM; | ||
| 3463 | k->class_id = PCI_CLASS_MEMORY_RAM; | ||
| 3464 | k->revision = 1; | ||
| 3465 | - dc->reset = ivshmem_reset; | ||
| 3466 | + device_class_set_legacy_reset(dc, ivshmem_reset); | ||
| 3467 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 3468 | dc->desc = "Inter-VM shared memory"; | ||
| 3469 | } | ||
| 3470 | diff --git a/hw/misc/lasi.c b/hw/misc/lasi.c | ||
| 3471 | index XXXXXXX..XXXXXXX 100644 | ||
| 3472 | --- a/hw/misc/lasi.c | ||
| 3473 | +++ b/hw/misc/lasi.c | ||
| 3474 | @@ -XXX,XX +XXX,XX @@ static void lasi_class_init(ObjectClass *klass, void *data) | ||
| 3475 | { | ||
| 3476 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3477 | |||
| 3478 | - dc->reset = lasi_reset; | ||
| 3479 | + device_class_set_legacy_reset(dc, lasi_reset); | ||
| 3480 | dc->vmsd = &vmstate_lasi; | ||
| 3481 | } | ||
| 3482 | |||
| 3483 | diff --git a/hw/misc/led.c b/hw/misc/led.c | ||
| 3484 | index XXXXXXX..XXXXXXX 100644 | ||
| 3485 | --- a/hw/misc/led.c | ||
| 3486 | +++ b/hw/misc/led.c | ||
| 3487 | @@ -XXX,XX +XXX,XX @@ static void led_class_init(ObjectClass *klass, void *data) | ||
| 3488 | |||
| 3489 | dc->desc = "LED"; | ||
| 3490 | dc->vmsd = &vmstate_led; | ||
| 3491 | - dc->reset = led_reset; | ||
| 3492 | + device_class_set_legacy_reset(dc, led_reset); | ||
| 3493 | dc->realize = led_realize; | ||
| 3494 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); | ||
| 3495 | device_class_set_props(dc, led_properties); | ||
| 3496 | diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c | ||
| 3497 | index XXXXXXX..XXXXXXX 100644 | ||
| 3498 | --- a/hw/misc/macio/cuda.c | ||
| 3499 | +++ b/hw/misc/macio/cuda.c | ||
| 3500 | @@ -XXX,XX +XXX,XX @@ static void cuda_class_init(ObjectClass *oc, void *data) | ||
| 3501 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 3502 | |||
| 3503 | dc->realize = cuda_realize; | ||
| 3504 | - dc->reset = cuda_reset; | ||
| 3505 | + device_class_set_legacy_reset(dc, cuda_reset); | ||
| 3506 | dc->vmsd = &vmstate_cuda; | ||
| 3507 | device_class_set_props(dc, cuda_properties); | ||
| 3508 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); | ||
| 3509 | diff --git a/hw/misc/macio/gpio.c b/hw/misc/macio/gpio.c | ||
| 3510 | index XXXXXXX..XXXXXXX 100644 | ||
| 3511 | --- a/hw/misc/macio/gpio.c | ||
| 3512 | +++ b/hw/misc/macio/gpio.c | ||
| 3513 | @@ -XXX,XX +XXX,XX @@ static void macio_gpio_class_init(ObjectClass *oc, void *data) | ||
| 3514 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 3515 | NMIClass *nc = NMI_CLASS(oc); | ||
| 3516 | |||
| 3517 | - dc->reset = macio_gpio_reset; | ||
| 3518 | + device_class_set_legacy_reset(dc, macio_gpio_reset); | ||
| 3519 | dc->vmsd = &vmstate_macio_gpio; | ||
| 3520 | nc->nmi_monitor_handler = macio_gpio_nmi; | ||
| 3521 | } | ||
| 3522 | diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c | ||
| 3523 | index XXXXXXX..XXXXXXX 100644 | ||
| 3524 | --- a/hw/misc/macio/mac_dbdma.c | ||
| 3525 | +++ b/hw/misc/macio/mac_dbdma.c | ||
| 3526 | @@ -XXX,XX +XXX,XX @@ static void mac_dbdma_class_init(ObjectClass *oc, void *data) | ||
| 3527 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 3528 | |||
| 3529 | dc->realize = mac_dbdma_realize; | ||
| 3530 | - dc->reset = mac_dbdma_reset; | ||
| 3531 | + device_class_set_legacy_reset(dc, mac_dbdma_reset); | ||
| 3532 | dc->vmsd = &vmstate_dbdma; | ||
| 3533 | } | ||
| 3534 | |||
| 3535 | diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c | ||
| 3536 | index XXXXXXX..XXXXXXX 100644 | ||
| 3537 | --- a/hw/misc/macio/pmu.c | ||
| 3538 | +++ b/hw/misc/macio/pmu.c | ||
| 3539 | @@ -XXX,XX +XXX,XX @@ static void pmu_class_init(ObjectClass *oc, void *data) | ||
| 3540 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 3541 | |||
| 3542 | dc->realize = pmu_realize; | ||
| 3543 | - dc->reset = pmu_reset; | ||
| 3544 | + device_class_set_legacy_reset(dc, pmu_reset); | ||
| 3545 | dc->vmsd = &vmstate_pmu; | ||
| 3546 | device_class_set_props(dc, pmu_properties); | ||
| 3547 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); | ||
| 3548 | diff --git a/hw/misc/mips_cmgcr.c b/hw/misc/mips_cmgcr.c | ||
| 3549 | index XXXXXXX..XXXXXXX 100644 | ||
| 3550 | --- a/hw/misc/mips_cmgcr.c | ||
| 3551 | +++ b/hw/misc/mips_cmgcr.c | ||
| 3552 | @@ -XXX,XX +XXX,XX @@ static void mips_gcr_class_init(ObjectClass *klass, void *data) | ||
| 3553 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3554 | device_class_set_props(dc, mips_gcr_properties); | ||
| 3555 | dc->vmsd = &vmstate_mips_gcr; | ||
| 3556 | - dc->reset = mips_gcr_reset; | ||
| 3557 | + device_class_set_legacy_reset(dc, mips_gcr_reset); | ||
| 3558 | dc->realize = mips_gcr_realize; | ||
| 3559 | } | ||
| 3560 | |||
| 3561 | diff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c | ||
| 3562 | index XXXXXXX..XXXXXXX 100644 | ||
| 3563 | --- a/hw/misc/mips_cpc.c | ||
| 3564 | +++ b/hw/misc/mips_cpc.c | ||
| 3565 | @@ -XXX,XX +XXX,XX @@ static void mips_cpc_class_init(ObjectClass *klass, void *data) | ||
| 3566 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3567 | |||
| 3568 | dc->realize = mips_cpc_realize; | ||
| 3569 | - dc->reset = mips_cpc_reset; | ||
| 3570 | + device_class_set_legacy_reset(dc, mips_cpc_reset); | ||
| 3571 | dc->vmsd = &vmstate_mips_cpc; | ||
| 3572 | device_class_set_props(dc, mips_cpc_properties); | ||
| 3573 | } | ||
| 3574 | diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c | ||
| 3575 | index XXXXXXX..XXXXXXX 100644 | ||
| 3576 | --- a/hw/misc/mips_itu.c | ||
| 3577 | +++ b/hw/misc/mips_itu.c | ||
| 3578 | @@ -XXX,XX +XXX,XX @@ static void mips_itu_class_init(ObjectClass *klass, void *data) | ||
| 3579 | |||
| 3580 | device_class_set_props(dc, mips_itu_properties); | ||
| 3581 | dc->realize = mips_itu_realize; | ||
| 3582 | - dc->reset = mips_itu_reset; | ||
| 3583 | + device_class_set_legacy_reset(dc, mips_itu_reset); | ||
| 3584 | } | ||
| 3585 | |||
| 3586 | static const TypeInfo mips_itu_info = { | ||
| 3587 | diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c | ||
| 3588 | index XXXXXXX..XXXXXXX 100644 | ||
| 3589 | --- a/hw/misc/mps2-fpgaio.c | ||
| 3590 | +++ b/hw/misc/mps2-fpgaio.c | ||
| 3591 | @@ -XXX,XX +XXX,XX @@ static void mps2_fpgaio_class_init(ObjectClass *klass, void *data) | ||
| 3592 | |||
| 3593 | dc->vmsd = &mps2_fpgaio_vmstate; | ||
| 3594 | dc->realize = mps2_fpgaio_realize; | ||
| 3595 | - dc->reset = mps2_fpgaio_reset; | ||
| 3596 | + device_class_set_legacy_reset(dc, mps2_fpgaio_reset); | ||
| 3597 | device_class_set_props(dc, mps2_fpgaio_properties); | ||
| 3598 | } | ||
| 3599 | |||
| 3600 | diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c | ||
| 3601 | index XXXXXXX..XXXXXXX 100644 | ||
| 3602 | --- a/hw/misc/mps2-scc.c | ||
| 3603 | +++ b/hw/misc/mps2-scc.c | ||
| 3604 | @@ -XXX,XX +XXX,XX @@ static void mps2_scc_class_init(ObjectClass *klass, void *data) | ||
| 3605 | |||
| 3606 | dc->realize = mps2_scc_realize; | ||
| 3607 | dc->vmsd = &mps2_scc_vmstate; | ||
| 3608 | - dc->reset = mps2_scc_reset; | ||
| 3609 | + device_class_set_legacy_reset(dc, mps2_scc_reset); | ||
| 3610 | device_class_set_props(dc, mps2_scc_properties); | ||
| 3611 | } | ||
| 3612 | |||
| 3613 | diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c | ||
| 3614 | index XXXXXXX..XXXXXXX 100644 | ||
| 3615 | --- a/hw/misc/msf2-sysreg.c | ||
| 3616 | +++ b/hw/misc/msf2-sysreg.c | ||
| 3617 | @@ -XXX,XX +XXX,XX @@ static void msf2_sysreg_class_init(ObjectClass *klass, void *data) | ||
| 3618 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3619 | |||
| 3620 | dc->vmsd = &vmstate_msf2_sysreg; | ||
| 3621 | - dc->reset = msf2_sysreg_reset; | ||
| 3622 | + device_class_set_legacy_reset(dc, msf2_sysreg_reset); | ||
| 3623 | device_class_set_props(dc, msf2_sysreg_properties); | ||
| 3624 | dc->realize = msf2_sysreg_realize; | ||
| 3625 | } | ||
| 3626 | diff --git a/hw/misc/nrf51_rng.c b/hw/misc/nrf51_rng.c | ||
| 3627 | index XXXXXXX..XXXXXXX 100644 | ||
| 3628 | --- a/hw/misc/nrf51_rng.c | ||
| 3629 | +++ b/hw/misc/nrf51_rng.c | ||
| 3630 | @@ -XXX,XX +XXX,XX @@ static void nrf51_rng_class_init(ObjectClass *klass, void *data) | ||
| 3631 | |||
| 3632 | device_class_set_props(dc, nrf51_rng_properties); | ||
| 3633 | dc->vmsd = &vmstate_rng; | ||
| 3634 | - dc->reset = nrf51_rng_reset; | ||
| 3635 | + device_class_set_legacy_reset(dc, nrf51_rng_reset); | ||
| 3636 | } | ||
| 3637 | |||
| 3638 | static const TypeInfo nrf51_rng_info = { | ||
| 3639 | diff --git a/hw/misc/pci-testdev.c b/hw/misc/pci-testdev.c | ||
| 3640 | index XXXXXXX..XXXXXXX 100644 | ||
| 3641 | --- a/hw/misc/pci-testdev.c | ||
| 3642 | +++ b/hw/misc/pci-testdev.c | ||
| 3643 | @@ -XXX,XX +XXX,XX @@ static void pci_testdev_class_init(ObjectClass *klass, void *data) | ||
| 3644 | k->class_id = PCI_CLASS_OTHERS; | ||
| 3645 | dc->desc = "PCI Test Device"; | ||
| 3646 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 3647 | - dc->reset = qdev_pci_testdev_reset; | ||
| 3648 | + device_class_set_legacy_reset(dc, qdev_pci_testdev_reset); | ||
| 3649 | device_class_set_props(dc, pci_testdev_properties); | ||
| 3650 | } | ||
| 3651 | |||
| 3652 | diff --git a/hw/misc/sifive_e_aon.c b/hw/misc/sifive_e_aon.c | ||
| 3653 | index XXXXXXX..XXXXXXX 100644 | ||
| 3654 | --- a/hw/misc/sifive_e_aon.c | ||
| 3655 | +++ b/hw/misc/sifive_e_aon.c | ||
| 3656 | @@ -XXX,XX +XXX,XX @@ static void sifive_e_aon_class_init(ObjectClass *oc, void *data) | ||
| 3657 | { | ||
| 3658 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 3659 | |||
| 3660 | - dc->reset = sifive_e_aon_reset; | ||
| 3661 | + device_class_set_legacy_reset(dc, sifive_e_aon_reset); | ||
| 3662 | device_class_set_props(dc, sifive_e_aon_properties); | ||
| 3663 | } | ||
| 3664 | |||
| 3665 | diff --git a/hw/misc/sifive_u_prci.c b/hw/misc/sifive_u_prci.c | ||
| 3666 | index XXXXXXX..XXXXXXX 100644 | ||
| 3667 | --- a/hw/misc/sifive_u_prci.c | ||
| 3668 | +++ b/hw/misc/sifive_u_prci.c | ||
| 3669 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_prci_class_init(ObjectClass *klass, void *data) | ||
| 3670 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3671 | |||
| 3672 | dc->realize = sifive_u_prci_realize; | ||
| 3673 | - dc->reset = sifive_u_prci_reset; | ||
| 3674 | + device_class_set_legacy_reset(dc, sifive_u_prci_reset); | ||
| 3675 | } | ||
| 3676 | |||
| 3677 | static const TypeInfo sifive_u_prci_info = { | ||
| 3678 | diff --git a/hw/misc/slavio_misc.c b/hw/misc/slavio_misc.c | ||
| 3679 | index XXXXXXX..XXXXXXX 100644 | ||
| 3680 | --- a/hw/misc/slavio_misc.c | ||
| 3681 | +++ b/hw/misc/slavio_misc.c | ||
| 3682 | @@ -XXX,XX +XXX,XX @@ static void slavio_misc_class_init(ObjectClass *klass, void *data) | ||
| 3683 | { | ||
| 3684 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3685 | |||
| 3686 | - dc->reset = slavio_misc_reset; | ||
| 3687 | + device_class_set_legacy_reset(dc, slavio_misc_reset); | ||
| 3688 | dc->vmsd = &vmstate_misc; | ||
| 3689 | } | ||
| 3690 | |||
| 3691 | diff --git a/hw/misc/stm32f2xx_syscfg.c b/hw/misc/stm32f2xx_syscfg.c | ||
| 3692 | index XXXXXXX..XXXXXXX 100644 | ||
| 3693 | --- a/hw/misc/stm32f2xx_syscfg.c | ||
| 3694 | +++ b/hw/misc/stm32f2xx_syscfg.c | ||
| 3695 | @@ -XXX,XX +XXX,XX @@ static void stm32f2xx_syscfg_class_init(ObjectClass *klass, void *data) | ||
| 3696 | { | ||
| 3697 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3698 | |||
| 3699 | - dc->reset = stm32f2xx_syscfg_reset; | ||
| 3700 | + device_class_set_legacy_reset(dc, stm32f2xx_syscfg_reset); | ||
| 3701 | } | ||
| 3702 | |||
| 3703 | static const TypeInfo stm32f2xx_syscfg_info = { | ||
| 3704 | diff --git a/hw/misc/stm32f4xx_exti.c b/hw/misc/stm32f4xx_exti.c | ||
| 3705 | index XXXXXXX..XXXXXXX 100644 | ||
| 3706 | --- a/hw/misc/stm32f4xx_exti.c | ||
| 3707 | +++ b/hw/misc/stm32f4xx_exti.c | ||
| 3708 | @@ -XXX,XX +XXX,XX @@ static void stm32f4xx_exti_class_init(ObjectClass *klass, void *data) | ||
| 3709 | { | ||
| 3710 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3711 | |||
| 3712 | - dc->reset = stm32f4xx_exti_reset; | ||
| 3713 | + device_class_set_legacy_reset(dc, stm32f4xx_exti_reset); | ||
| 3714 | dc->vmsd = &vmstate_stm32f4xx_exti; | ||
| 3715 | } | ||
| 3716 | |||
| 3717 | diff --git a/hw/misc/stm32f4xx_syscfg.c b/hw/misc/stm32f4xx_syscfg.c | ||
| 3718 | index XXXXXXX..XXXXXXX 100644 | ||
| 3719 | --- a/hw/misc/stm32f4xx_syscfg.c | ||
| 3720 | +++ b/hw/misc/stm32f4xx_syscfg.c | ||
| 3721 | @@ -XXX,XX +XXX,XX @@ static void stm32f4xx_syscfg_class_init(ObjectClass *klass, void *data) | ||
| 3722 | { | ||
| 3723 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3724 | |||
| 3725 | - dc->reset = stm32f4xx_syscfg_reset; | ||
| 3726 | + device_class_set_legacy_reset(dc, stm32f4xx_syscfg_reset); | ||
| 3727 | dc->vmsd = &vmstate_stm32f4xx_syscfg; | ||
| 3728 | } | ||
| 3729 | |||
| 3730 | diff --git a/hw/misc/tz-mpc.c b/hw/misc/tz-mpc.c | ||
| 3731 | index XXXXXXX..XXXXXXX 100644 | ||
| 3732 | --- a/hw/misc/tz-mpc.c | ||
| 3733 | +++ b/hw/misc/tz-mpc.c | ||
| 3734 | @@ -XXX,XX +XXX,XX @@ static void tz_mpc_class_init(ObjectClass *klass, void *data) | ||
| 3735 | |||
| 3736 | dc->realize = tz_mpc_realize; | ||
| 3737 | dc->vmsd = &tz_mpc_vmstate; | ||
| 3738 | - dc->reset = tz_mpc_reset; | ||
| 3739 | + device_class_set_legacy_reset(dc, tz_mpc_reset); | ||
| 3740 | device_class_set_props(dc, tz_mpc_properties); | ||
| 3741 | } | ||
| 3742 | |||
| 3743 | diff --git a/hw/misc/tz-msc.c b/hw/misc/tz-msc.c | ||
| 3744 | index XXXXXXX..XXXXXXX 100644 | ||
| 3745 | --- a/hw/misc/tz-msc.c | ||
| 3746 | +++ b/hw/misc/tz-msc.c | ||
| 3747 | @@ -XXX,XX +XXX,XX @@ static void tz_msc_class_init(ObjectClass *klass, void *data) | ||
| 3748 | |||
| 3749 | dc->realize = tz_msc_realize; | ||
| 3750 | dc->vmsd = &tz_msc_vmstate; | ||
| 3751 | - dc->reset = tz_msc_reset; | ||
| 3752 | + device_class_set_legacy_reset(dc, tz_msc_reset); | ||
| 3753 | device_class_set_props(dc, tz_msc_properties); | ||
| 3754 | } | ||
| 3755 | |||
| 3756 | diff --git a/hw/misc/tz-ppc.c b/hw/misc/tz-ppc.c | ||
| 3757 | index XXXXXXX..XXXXXXX 100644 | ||
| 3758 | --- a/hw/misc/tz-ppc.c | ||
| 3759 | +++ b/hw/misc/tz-ppc.c | ||
| 3760 | @@ -XXX,XX +XXX,XX @@ static void tz_ppc_class_init(ObjectClass *klass, void *data) | ||
| 3761 | |||
| 3762 | dc->realize = tz_ppc_realize; | ||
| 3763 | dc->vmsd = &tz_ppc_vmstate; | ||
| 3764 | - dc->reset = tz_ppc_reset; | ||
| 3765 | + device_class_set_legacy_reset(dc, tz_ppc_reset); | ||
| 3766 | device_class_set_props(dc, tz_ppc_properties); | ||
| 3767 | } | ||
| 3768 | |||
| 3769 | diff --git a/hw/misc/virt_ctrl.c b/hw/misc/virt_ctrl.c | ||
| 3770 | index XXXXXXX..XXXXXXX 100644 | ||
| 3771 | --- a/hw/misc/virt_ctrl.c | ||
| 3772 | +++ b/hw/misc/virt_ctrl.c | ||
| 3773 | @@ -XXX,XX +XXX,XX @@ static void virt_ctrl_class_init(ObjectClass *oc, void *data) | ||
| 3774 | { | ||
| 3775 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 3776 | |||
| 3777 | - dc->reset = virt_ctrl_reset; | ||
| 3778 | + device_class_set_legacy_reset(dc, virt_ctrl_reset); | ||
| 3779 | dc->realize = virt_ctrl_realize; | ||
| 3780 | dc->vmsd = &vmstate_virt_ctrl; | ||
| 3781 | } | ||
| 3782 | diff --git a/hw/misc/xlnx-versal-cfu.c b/hw/misc/xlnx-versal-cfu.c | ||
| 3783 | index XXXXXXX..XXXXXXX 100644 | ||
| 3784 | --- a/hw/misc/xlnx-versal-cfu.c | ||
| 3785 | +++ b/hw/misc/xlnx-versal-cfu.c | ||
| 3786 | @@ -XXX,XX +XXX,XX @@ static void cfu_apb_class_init(ObjectClass *klass, void *data) | ||
| 3787 | { | ||
| 3788 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3789 | |||
| 3790 | - dc->reset = cfu_apb_reset; | ||
| 3791 | + device_class_set_legacy_reset(dc, cfu_apb_reset); | ||
| 3792 | dc->vmsd = &vmstate_cfu_apb; | ||
| 3793 | device_class_set_props(dc, cfu_props); | ||
| 3794 | } | ||
| 3795 | diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c | ||
| 3796 | index XXXXXXX..XXXXXXX 100644 | ||
| 3797 | --- a/hw/net/allwinner-sun8i-emac.c | ||
| 3798 | +++ b/hw/net/allwinner-sun8i-emac.c | ||
| 3799 | @@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_class_init(ObjectClass *klass, void *data) | ||
| 3800 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3801 | |||
| 3802 | dc->realize = allwinner_sun8i_emac_realize; | ||
| 3803 | - dc->reset = allwinner_sun8i_emac_reset; | ||
| 3804 | + device_class_set_legacy_reset(dc, allwinner_sun8i_emac_reset); | ||
| 3805 | dc->vmsd = &vmstate_aw_emac; | ||
| 3806 | device_class_set_props(dc, allwinner_sun8i_emac_properties); | ||
| 3807 | } | ||
| 3808 | diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c | ||
| 3809 | index XXXXXXX..XXXXXXX 100644 | ||
| 3810 | --- a/hw/net/allwinner_emac.c | ||
| 3811 | +++ b/hw/net/allwinner_emac.c | ||
| 3812 | @@ -XXX,XX +XXX,XX @@ static void aw_emac_class_init(ObjectClass *klass, void *data) | ||
| 3813 | |||
| 3814 | dc->realize = aw_emac_realize; | ||
| 3815 | device_class_set_props(dc, aw_emac_properties); | ||
| 3816 | - dc->reset = aw_emac_reset; | ||
| 3817 | + device_class_set_legacy_reset(dc, aw_emac_reset); | ||
| 3818 | dc->vmsd = &vmstate_aw_emac; | ||
| 3819 | } | ||
| 3820 | |||
| 3821 | diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c | ||
| 3822 | index XXXXXXX..XXXXXXX 100644 | ||
| 3823 | --- a/hw/net/cadence_gem.c | ||
| 3824 | +++ b/hw/net/cadence_gem.c | ||
| 3825 | @@ -XXX,XX +XXX,XX @@ static void gem_class_init(ObjectClass *klass, void *data) | ||
| 3826 | dc->realize = gem_realize; | ||
| 3827 | device_class_set_props(dc, gem_properties); | ||
| 3828 | dc->vmsd = &vmstate_cadence_gem; | ||
| 3829 | - dc->reset = gem_reset; | ||
| 3830 | + device_class_set_legacy_reset(dc, gem_reset); | ||
| 3831 | } | ||
| 3832 | |||
| 3833 | static const TypeInfo gem_info = { | ||
| 3834 | diff --git a/hw/net/can/can_kvaser_pci.c b/hw/net/can/can_kvaser_pci.c | ||
| 3835 | index XXXXXXX..XXXXXXX 100644 | ||
| 3836 | --- a/hw/net/can/can_kvaser_pci.c | ||
| 3837 | +++ b/hw/net/can/can_kvaser_pci.c | ||
| 3838 | @@ -XXX,XX +XXX,XX @@ static void kvaser_pci_class_init(ObjectClass *klass, void *data) | ||
| 3839 | k->class_id = 0x00ff00; | ||
| 3840 | dc->desc = "Kvaser PCICANx"; | ||
| 3841 | dc->vmsd = &vmstate_kvaser_pci; | ||
| 3842 | - dc->reset = kvaser_pci_reset; | ||
| 3843 | + device_class_set_legacy_reset(dc, kvaser_pci_reset); | ||
| 3844 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 3845 | } | ||
| 3846 | |||
| 3847 | diff --git a/hw/net/can/can_mioe3680_pci.c b/hw/net/can/can_mioe3680_pci.c | ||
| 3848 | index XXXXXXX..XXXXXXX 100644 | ||
| 3849 | --- a/hw/net/can/can_mioe3680_pci.c | ||
| 3850 | +++ b/hw/net/can/can_mioe3680_pci.c | ||
| 3851 | @@ -XXX,XX +XXX,XX @@ static void mioe3680_pci_class_init(ObjectClass *klass, void *data) | ||
| 3852 | dc->desc = "Mioe3680 PCICANx"; | ||
| 3853 | dc->vmsd = &vmstate_mioe3680_pci; | ||
| 3854 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 3855 | - dc->reset = mioe3680_pci_reset; | ||
| 3856 | + device_class_set_legacy_reset(dc, mioe3680_pci_reset); | ||
| 3857 | } | ||
| 3858 | |||
| 3859 | static const TypeInfo mioe3680_pci_info = { | ||
| 3860 | diff --git a/hw/net/can/can_pcm3680_pci.c b/hw/net/can/can_pcm3680_pci.c | ||
| 3861 | index XXXXXXX..XXXXXXX 100644 | ||
| 3862 | --- a/hw/net/can/can_pcm3680_pci.c | ||
| 3863 | +++ b/hw/net/can/can_pcm3680_pci.c | ||
| 3864 | @@ -XXX,XX +XXX,XX @@ static void pcm3680i_pci_class_init(ObjectClass *klass, void *data) | ||
| 3865 | dc->desc = "Pcm3680i PCICANx"; | ||
| 3866 | dc->vmsd = &vmstate_pcm3680i_pci; | ||
| 3867 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 3868 | - dc->reset = pcm3680i_pci_reset; | ||
| 3869 | + device_class_set_legacy_reset(dc, pcm3680i_pci_reset); | ||
| 3870 | } | ||
| 3871 | |||
| 3872 | static const TypeInfo pcm3680i_pci_info = { | ||
| 3873 | diff --git a/hw/net/can/ctucan_pci.c b/hw/net/can/ctucan_pci.c | ||
| 3874 | index XXXXXXX..XXXXXXX 100644 | ||
| 3875 | --- a/hw/net/can/ctucan_pci.c | ||
| 3876 | +++ b/hw/net/can/ctucan_pci.c | ||
| 3877 | @@ -XXX,XX +XXX,XX @@ static void ctucan_pci_class_init(ObjectClass *klass, void *data) | ||
| 3878 | dc->desc = "CTU CAN PCI"; | ||
| 3879 | dc->vmsd = &vmstate_ctucan_pci; | ||
| 3880 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 3881 | - dc->reset = ctucan_pci_reset; | ||
| 3882 | + device_class_set_legacy_reset(dc, ctucan_pci_reset); | ||
| 3883 | } | ||
| 3884 | |||
| 3885 | static const TypeInfo ctucan_pci_info = { | ||
| 3886 | diff --git a/hw/net/can/xlnx-versal-canfd.c b/hw/net/can/xlnx-versal-canfd.c | ||
| 3887 | index XXXXXXX..XXXXXXX 100644 | ||
| 3888 | --- a/hw/net/can/xlnx-versal-canfd.c | ||
| 3889 | +++ b/hw/net/can/xlnx-versal-canfd.c | ||
| 3890 | @@ -XXX,XX +XXX,XX @@ static void canfd_class_init(ObjectClass *klass, void *data) | ||
| 3891 | { | ||
| 3892 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3893 | |||
| 3894 | - dc->reset = canfd_reset; | ||
| 3895 | + device_class_set_legacy_reset(dc, canfd_reset); | ||
| 3896 | dc->realize = canfd_realize; | ||
| 3897 | device_class_set_props(dc, canfd_core_properties); | ||
| 3898 | dc->vmsd = &vmstate_canfd; | ||
| 3899 | diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c | ||
| 3900 | index XXXXXXX..XXXXXXX 100644 | ||
| 3901 | --- a/hw/net/dp8393x.c | ||
| 3902 | +++ b/hw/net/dp8393x.c | ||
| 3903 | @@ -XXX,XX +XXX,XX @@ static void dp8393x_class_init(ObjectClass *klass, void *data) | ||
| 3904 | |||
| 3905 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); | ||
| 3906 | dc->realize = dp8393x_realize; | ||
| 3907 | - dc->reset = dp8393x_reset; | ||
| 3908 | + device_class_set_legacy_reset(dc, dp8393x_reset); | ||
| 3909 | dc->vmsd = &vmstate_dp8393x; | ||
| 3910 | device_class_set_props(dc, dp8393x_properties); | ||
| 3911 | } | ||
| 3912 | diff --git a/hw/net/etraxfs_eth.c b/hw/net/etraxfs_eth.c | ||
| 3913 | index XXXXXXX..XXXXXXX 100644 | ||
| 3914 | --- a/hw/net/etraxfs_eth.c | ||
| 3915 | +++ b/hw/net/etraxfs_eth.c | ||
| 3916 | @@ -XXX,XX +XXX,XX @@ static void etraxfs_eth_class_init(ObjectClass *klass, void *data) | ||
| 3917 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3918 | |||
| 3919 | dc->realize = etraxfs_eth_realize; | ||
| 3920 | - dc->reset = etraxfs_eth_reset; | ||
| 3921 | + device_class_set_legacy_reset(dc, etraxfs_eth_reset); | ||
| 3922 | device_class_set_props(dc, etraxfs_eth_properties); | ||
| 3923 | /* Reason: dma_out, dma_in are not user settable */ | ||
| 3924 | dc->user_creatable = false; | ||
| 3925 | diff --git a/hw/net/fsl_etsec/etsec.c b/hw/net/fsl_etsec/etsec.c | ||
| 3926 | index XXXXXXX..XXXXXXX 100644 | ||
| 3927 | --- a/hw/net/fsl_etsec/etsec.c | ||
| 3928 | +++ b/hw/net/fsl_etsec/etsec.c | ||
| 3929 | @@ -XXX,XX +XXX,XX @@ static void etsec_class_init(ObjectClass *klass, void *data) | ||
| 3930 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3931 | |||
| 3932 | dc->realize = etsec_realize; | ||
| 3933 | - dc->reset = etsec_reset; | ||
| 3934 | + device_class_set_legacy_reset(dc, etsec_reset); | ||
| 3935 | device_class_set_props(dc, etsec_properties); | ||
| 3936 | /* Supported by ppce500 machine */ | ||
| 3937 | dc->user_creatable = true; | ||
| 3938 | diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c | ||
| 3939 | index XXXXXXX..XXXXXXX 100644 | ||
| 3940 | --- a/hw/net/ftgmac100.c | ||
| 3941 | +++ b/hw/net/ftgmac100.c | ||
| 3942 | @@ -XXX,XX +XXX,XX @@ static void ftgmac100_class_init(ObjectClass *klass, void *data) | ||
| 3943 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3944 | |||
| 3945 | dc->vmsd = &vmstate_ftgmac100; | ||
| 3946 | - dc->reset = ftgmac100_reset; | ||
| 3947 | + device_class_set_legacy_reset(dc, ftgmac100_reset); | ||
| 3948 | device_class_set_props(dc, ftgmac100_properties); | ||
| 3949 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); | ||
| 3950 | dc->realize = ftgmac100_realize; | ||
| 3951 | @@ -XXX,XX +XXX,XX @@ static void aspeed_mii_class_init(ObjectClass *klass, void *data) | ||
| 3952 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 3953 | |||
| 3954 | dc->vmsd = &vmstate_aspeed_mii; | ||
| 3955 | - dc->reset = aspeed_mii_reset; | ||
| 3956 | + device_class_set_legacy_reset(dc, aspeed_mii_reset); | ||
| 3957 | dc->realize = aspeed_mii_realize; | ||
| 3958 | dc->desc = "Aspeed MII controller"; | ||
| 3959 | device_class_set_props(dc, aspeed_mii_properties); | ||
| 3960 | diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c | 54 | diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c |
| 3961 | index XXXXXXX..XXXXXXX 100644 | 55 | index XXXXXXX..XXXXXXX 100644 |
| 3962 | --- a/hw/net/imx_fec.c | 56 | --- a/hw/net/imx_fec.c |
| 3963 | +++ b/hw/net/imx_fec.c | 57 | +++ b/hw/net/imx_fec.c |
| 3964 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_class_init(ObjectClass *klass, void *data) | 58 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth_txdescs = { |
| 3965 | DeviceClass *dc = DEVICE_CLASS(klass); | 59 | |
| 3966 | 60 | static const VMStateDescription vmstate_imx_eth = { | |
| 3967 | dc->vmsd = &vmstate_imx_eth; | 61 | .name = TYPE_IMX_FEC, |
| 3968 | - dc->reset = imx_eth_reset; | 62 | - .version_id = 2, |
| 3969 | + device_class_set_legacy_reset(dc, imx_eth_reset); | 63 | - .minimum_version_id = 2, |
| 3970 | device_class_set_props(dc, imx_eth_properties); | 64 | + .version_id = 3, |
| 3971 | dc->realize = imx_eth_realize; | 65 | + .minimum_version_id = 3, |
| 3972 | dc->desc = "i.MX FEC/ENET Ethernet Controller"; | 66 | .fields = (const VMStateField[]) { |
| 3973 | diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c | 67 | VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX), |
| 68 | VMSTATE_UINT32(rx_descriptor, IMXFECState), | ||
| 69 | VMSTATE_UINT32(tx_descriptor[0], IMXFECState), | ||
| 70 | - VMSTATE_UINT32(phy_status, IMXFECState), | ||
| 71 | - VMSTATE_UINT32(phy_control, IMXFECState), | ||
| 72 | - VMSTATE_UINT32(phy_advertise, IMXFECState), | ||
| 73 | - VMSTATE_UINT32(phy_int, IMXFECState), | ||
| 74 | - VMSTATE_UINT32(phy_int_mask, IMXFECState), | ||
| 75 | VMSTATE_END_OF_LIST() | ||
| 76 | }, | ||
| 77 | .subsections = (const VMStateDescription * const []) { | ||
| 78 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth = { | ||
| 79 | }, | ||
| 80 | }; | ||
| 81 | |||
| 82 | -#define PHY_INT_ENERGYON (1 << 7) | ||
| 83 | -#define PHY_INT_AUTONEG_COMPLETE (1 << 6) | ||
| 84 | -#define PHY_INT_FAULT (1 << 5) | ||
| 85 | -#define PHY_INT_DOWN (1 << 4) | ||
| 86 | -#define PHY_INT_AUTONEG_LP (1 << 3) | ||
| 87 | -#define PHY_INT_PARFAULT (1 << 2) | ||
| 88 | -#define PHY_INT_AUTONEG_PAGE (1 << 1) | ||
| 89 | - | ||
| 90 | static void imx_eth_update(IMXFECState *s); | ||
| 91 | |||
| 92 | /* | ||
| 93 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_update(IMXFECState *s); | ||
| 94 | * For now we don't handle any GPIO/interrupt line, so the OS will | ||
| 95 | * have to poll for the PHY status. | ||
| 96 | */ | ||
| 97 | -static void imx_phy_update_irq(IMXFECState *s) | ||
| 98 | +static void imx_phy_update_irq(void *opaque, int n, int level) | ||
| 99 | { | ||
| 100 | - imx_eth_update(s); | ||
| 101 | -} | ||
| 102 | - | ||
| 103 | -static void imx_phy_update_link(IMXFECState *s) | ||
| 104 | -{ | ||
| 105 | - /* Autonegotiation status mirrors link status. */ | ||
| 106 | - if (qemu_get_queue(s->nic)->link_down) { | ||
| 107 | - trace_imx_phy_update_link("down"); | ||
| 108 | - s->phy_status &= ~0x0024; | ||
| 109 | - s->phy_int |= PHY_INT_DOWN; | ||
| 110 | - } else { | ||
| 111 | - trace_imx_phy_update_link("up"); | ||
| 112 | - s->phy_status |= 0x0024; | ||
| 113 | - s->phy_int |= PHY_INT_ENERGYON; | ||
| 114 | - s->phy_int |= PHY_INT_AUTONEG_COMPLETE; | ||
| 115 | - } | ||
| 116 | - imx_phy_update_irq(s); | ||
| 117 | + imx_eth_update(opaque); | ||
| 118 | } | ||
| 119 | |||
| 120 | static void imx_eth_set_link(NetClientState *nc) | ||
| 121 | { | ||
| 122 | - imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc))); | ||
| 123 | -} | ||
| 124 | - | ||
| 125 | -static void imx_phy_reset(IMXFECState *s) | ||
| 126 | -{ | ||
| 127 | - trace_imx_phy_reset(); | ||
| 128 | - | ||
| 129 | - s->phy_status = 0x7809; | ||
| 130 | - s->phy_control = 0x3000; | ||
| 131 | - s->phy_advertise = 0x01e1; | ||
| 132 | - s->phy_int_mask = 0; | ||
| 133 | - s->phy_int = 0; | ||
| 134 | - imx_phy_update_link(s); | ||
| 135 | + lan9118_phy_update_link(&IMX_FEC(qemu_get_nic_opaque(nc))->mii, | ||
| 136 | + nc->link_down); | ||
| 137 | } | ||
| 138 | |||
| 139 | static uint32_t imx_phy_read(IMXFECState *s, int reg) | ||
| 140 | { | ||
| 141 | - uint32_t val; | ||
| 142 | uint32_t phy = reg / 32; | ||
| 143 | |||
| 144 | if (!s->phy_connected) { | ||
| 145 | @@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg) | ||
| 146 | |||
| 147 | reg %= 32; | ||
| 148 | |||
| 149 | - switch (reg) { | ||
| 150 | - case 0: /* Basic Control */ | ||
| 151 | - val = s->phy_control; | ||
| 152 | - break; | ||
| 153 | - case 1: /* Basic Status */ | ||
| 154 | - val = s->phy_status; | ||
| 155 | - break; | ||
| 156 | - case 2: /* ID1 */ | ||
| 157 | - val = 0x0007; | ||
| 158 | - break; | ||
| 159 | - case 3: /* ID2 */ | ||
| 160 | - val = 0xc0d1; | ||
| 161 | - break; | ||
| 162 | - case 4: /* Auto-neg advertisement */ | ||
| 163 | - val = s->phy_advertise; | ||
| 164 | - break; | ||
| 165 | - case 5: /* Auto-neg Link Partner Ability */ | ||
| 166 | - val = 0x0f71; | ||
| 167 | - break; | ||
| 168 | - case 6: /* Auto-neg Expansion */ | ||
| 169 | - val = 1; | ||
| 170 | - break; | ||
| 171 | - case 29: /* Interrupt source. */ | ||
| 172 | - val = s->phy_int; | ||
| 173 | - s->phy_int = 0; | ||
| 174 | - imx_phy_update_irq(s); | ||
| 175 | - break; | ||
| 176 | - case 30: /* Interrupt mask */ | ||
| 177 | - val = s->phy_int_mask; | ||
| 178 | - break; | ||
| 179 | - case 17: | ||
| 180 | - case 18: | ||
| 181 | - case 27: | ||
| 182 | - case 31: | ||
| 183 | - qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n", | ||
| 184 | - TYPE_IMX_FEC, __func__, reg); | ||
| 185 | - val = 0; | ||
| 186 | - break; | ||
| 187 | - default: | ||
| 188 | - qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n", | ||
| 189 | - TYPE_IMX_FEC, __func__, reg); | ||
| 190 | - val = 0; | ||
| 191 | - break; | ||
| 192 | - } | ||
| 193 | - | ||
| 194 | - trace_imx_phy_read(val, phy, reg); | ||
| 195 | - | ||
| 196 | - return val; | ||
| 197 | + return lan9118_phy_read(&s->mii, reg); | ||
| 198 | } | ||
| 199 | |||
| 200 | static void imx_phy_write(IMXFECState *s, int reg, uint32_t val) | ||
| 201 | @@ -XXX,XX +XXX,XX @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val) | ||
| 202 | |||
| 203 | reg %= 32; | ||
| 204 | |||
| 205 | - trace_imx_phy_write(val, phy, reg); | ||
| 206 | - | ||
| 207 | - switch (reg) { | ||
| 208 | - case 0: /* Basic Control */ | ||
| 209 | - if (val & 0x8000) { | ||
| 210 | - imx_phy_reset(s); | ||
| 211 | - } else { | ||
| 212 | - s->phy_control = val & 0x7980; | ||
| 213 | - /* Complete autonegotiation immediately. */ | ||
| 214 | - if (val & 0x1000) { | ||
| 215 | - s->phy_status |= 0x0020; | ||
| 216 | - } | ||
| 217 | - } | ||
| 218 | - break; | ||
| 219 | - case 4: /* Auto-neg advertisement */ | ||
| 220 | - s->phy_advertise = (val & 0x2d7f) | 0x80; | ||
| 221 | - break; | ||
| 222 | - case 30: /* Interrupt mask */ | ||
| 223 | - s->phy_int_mask = val & 0xff; | ||
| 224 | - imx_phy_update_irq(s); | ||
| 225 | - break; | ||
| 226 | - case 17: | ||
| 227 | - case 18: | ||
| 228 | - case 27: | ||
| 229 | - case 31: | ||
| 230 | - qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n", | ||
| 231 | - TYPE_IMX_FEC, __func__, reg); | ||
| 232 | - break; | ||
| 233 | - default: | ||
| 234 | - qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n", | ||
| 235 | - TYPE_IMX_FEC, __func__, reg); | ||
| 236 | - break; | ||
| 237 | - } | ||
| 238 | + lan9118_phy_write(&s->mii, reg, val); | ||
| 239 | } | ||
| 240 | |||
| 241 | static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr) | ||
| 242 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_reset(DeviceState *d) | ||
| 243 | |||
| 244 | s->rx_descriptor = 0; | ||
| 245 | memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor)); | ||
| 246 | - | ||
| 247 | - /* We also reset the PHY */ | ||
| 248 | - imx_phy_reset(s); | ||
| 249 | } | ||
| 250 | |||
| 251 | static uint32_t imx_default_read(IMXFECState *s, uint32_t index) | ||
| 252 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp) | ||
| 253 | sysbus_init_irq(sbd, &s->irq[0]); | ||
| 254 | sysbus_init_irq(sbd, &s->irq[1]); | ||
| 255 | |||
| 256 | + qemu_init_irq(&s->mii_irq, imx_phy_update_irq, s, 0); | ||
| 257 | + object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY); | ||
| 258 | + if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) { | ||
| 259 | + return; | ||
| 260 | + } | ||
| 261 | + qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq); | ||
| 262 | + | ||
| 263 | qemu_macaddr_default_if_unset(&s->conf.macaddr); | ||
| 264 | |||
| 265 | s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf, | ||
| 266 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c | ||
| 3974 | index XXXXXXX..XXXXXXX 100644 | 267 | index XXXXXXX..XXXXXXX 100644 |
| 3975 | --- a/hw/net/lan9118.c | 268 | --- a/hw/net/lan9118_phy.c |
| 3976 | +++ b/hw/net/lan9118.c | 269 | +++ b/hw/net/lan9118_phy.c |
| 3977 | @@ -XXX,XX +XXX,XX @@ static void lan9118_class_init(ObjectClass *klass, void *data) | 270 | @@ -XXX,XX +XXX,XX @@ |
| 271 | * Copyright (c) 2009 CodeSourcery, LLC. | ||
| 272 | * Written by Paul Brook | ||
| 273 | * | ||
| 274 | + * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net> | ||
| 275 | + * | ||
| 276 | * This code is licensed under the GNU GPL v2 | ||
| 277 | * | ||
| 278 | * Contributions after 2012-01-13 are licensed under the terms of the | ||
| 279 | @@ -XXX,XX +XXX,XX @@ | ||
| 280 | #include "hw/resettable.h" | ||
| 281 | #include "migration/vmstate.h" | ||
| 282 | #include "qemu/log.h" | ||
| 283 | +#include "trace.h" | ||
| 284 | |||
| 285 | #define PHY_INT_ENERGYON (1 << 7) | ||
| 286 | #define PHY_INT_AUTONEG_COMPLETE (1 << 6) | ||
| 287 | @@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) | ||
| 288 | |||
| 289 | switch (reg) { | ||
| 290 | case 0: /* Basic Control */ | ||
| 291 | - return s->control; | ||
| 292 | + val = s->control; | ||
| 293 | + break; | ||
| 294 | case 1: /* Basic Status */ | ||
| 295 | - return s->status; | ||
| 296 | + val = s->status; | ||
| 297 | + break; | ||
| 298 | case 2: /* ID1 */ | ||
| 299 | - return 0x0007; | ||
| 300 | + val = 0x0007; | ||
| 301 | + break; | ||
| 302 | case 3: /* ID2 */ | ||
| 303 | - return 0xc0d1; | ||
| 304 | + val = 0xc0d1; | ||
| 305 | + break; | ||
| 306 | case 4: /* Auto-neg advertisement */ | ||
| 307 | - return s->advertise; | ||
| 308 | + val = s->advertise; | ||
| 309 | + break; | ||
| 310 | case 5: /* Auto-neg Link Partner Ability */ | ||
| 311 | - return 0x0f71; | ||
| 312 | + val = 0x0f71; | ||
| 313 | + break; | ||
| 314 | case 6: /* Auto-neg Expansion */ | ||
| 315 | - return 1; | ||
| 316 | - /* TODO 17, 18, 27, 29, 30, 31 */ | ||
| 317 | + val = 1; | ||
| 318 | + break; | ||
| 319 | case 29: /* Interrupt source. */ | ||
| 320 | val = s->ints; | ||
| 321 | s->ints = 0; | ||
| 322 | lan9118_phy_update_irq(s); | ||
| 323 | - return val; | ||
| 324 | + break; | ||
| 325 | case 30: /* Interrupt mask */ | ||
| 326 | - return s->int_mask; | ||
| 327 | + val = s->int_mask; | ||
| 328 | + break; | ||
| 329 | + case 17: | ||
| 330 | + case 18: | ||
| 331 | + case 27: | ||
| 332 | + case 31: | ||
| 333 | + qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n", | ||
| 334 | + __func__, reg); | ||
| 335 | + val = 0; | ||
| 336 | + break; | ||
| 337 | default: | ||
| 338 | - qemu_log_mask(LOG_GUEST_ERROR, | ||
| 339 | - "lan9118_phy_read: PHY read reg %d\n", reg); | ||
| 340 | - return 0; | ||
| 341 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n", | ||
| 342 | + __func__, reg); | ||
| 343 | + val = 0; | ||
| 344 | + break; | ||
| 345 | } | ||
| 346 | + | ||
| 347 | + trace_lan9118_phy_read(val, reg); | ||
| 348 | + | ||
| 349 | + return val; | ||
| 350 | } | ||
| 351 | |||
| 352 | void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) | ||
| 3978 | { | 353 | { |
| 3979 | DeviceClass *dc = DEVICE_CLASS(klass); | 354 | + trace_lan9118_phy_write(val, reg); |
| 3980 | 355 | + | |
| 3981 | - dc->reset = lan9118_reset; | 356 | switch (reg) { |
| 3982 | + device_class_set_legacy_reset(dc, lan9118_reset); | 357 | case 0: /* Basic Control */ |
| 3983 | device_class_set_props(dc, lan9118_properties); | 358 | if (val & 0x8000) { |
| 3984 | dc->vmsd = &vmstate_lan9118; | 359 | lan9118_phy_reset(s); |
| 3985 | dc->realize = lan9118_realize; | 360 | - break; |
| 3986 | diff --git a/hw/net/lance.c b/hw/net/lance.c | 361 | - } |
| 362 | - s->control = val & 0x7980; | ||
| 363 | - /* Complete autonegotiation immediately. */ | ||
| 364 | - if (val & 0x1000) { | ||
| 365 | - s->status |= 0x0020; | ||
| 366 | + } else { | ||
| 367 | + s->control = val & 0x7980; | ||
| 368 | + /* Complete autonegotiation immediately. */ | ||
| 369 | + if (val & 0x1000) { | ||
| 370 | + s->status |= 0x0020; | ||
| 371 | + } | ||
| 372 | } | ||
| 373 | break; | ||
| 374 | case 4: /* Auto-neg advertisement */ | ||
| 375 | s->advertise = (val & 0x2d7f) | 0x80; | ||
| 376 | break; | ||
| 377 | - /* TODO 17, 18, 27, 31 */ | ||
| 378 | case 30: /* Interrupt mask */ | ||
| 379 | s->int_mask = val & 0xff; | ||
| 380 | lan9118_phy_update_irq(s); | ||
| 381 | break; | ||
| 382 | + case 17: | ||
| 383 | + case 18: | ||
| 384 | + case 27: | ||
| 385 | + case 31: | ||
| 386 | + qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n", | ||
| 387 | + __func__, reg); | ||
| 388 | + break; | ||
| 389 | default: | ||
| 390 | - qemu_log_mask(LOG_GUEST_ERROR, | ||
| 391 | - "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val); | ||
| 392 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n", | ||
| 393 | + __func__, reg); | ||
| 394 | + break; | ||
| 395 | } | ||
| 396 | } | ||
| 397 | |||
| 398 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) | ||
| 399 | |||
| 400 | /* Autonegotiation status mirrors link status. */ | ||
| 401 | if (link_down) { | ||
| 402 | + trace_lan9118_phy_update_link("down"); | ||
| 403 | s->status &= ~0x0024; | ||
| 404 | s->ints |= PHY_INT_DOWN; | ||
| 405 | } else { | ||
| 406 | + trace_lan9118_phy_update_link("up"); | ||
| 407 | s->status |= 0x0024; | ||
| 408 | s->ints |= PHY_INT_ENERGYON; | ||
| 409 | s->ints |= PHY_INT_AUTONEG_COMPLETE; | ||
| 410 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) | ||
| 411 | |||
| 412 | void lan9118_phy_reset(Lan9118PhyState *s) | ||
| 413 | { | ||
| 414 | + trace_lan9118_phy_reset(); | ||
| 415 | + | ||
| 416 | s->control = 0x3000; | ||
| 417 | s->status = 0x7809; | ||
| 418 | s->advertise = 0x01e1; | ||
| 419 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118_phy = { | ||
| 420 | .version_id = 1, | ||
| 421 | .minimum_version_id = 1, | ||
| 422 | .fields = (const VMStateField[]) { | ||
| 423 | - VMSTATE_UINT16(control, Lan9118PhyState), | ||
| 424 | VMSTATE_UINT16(status, Lan9118PhyState), | ||
| 425 | + VMSTATE_UINT16(control, Lan9118PhyState), | ||
| 426 | VMSTATE_UINT16(advertise, Lan9118PhyState), | ||
| 427 | VMSTATE_UINT16(ints, Lan9118PhyState), | ||
| 428 | VMSTATE_UINT16(int_mask, Lan9118PhyState), | ||
| 429 | diff --git a/hw/net/Kconfig b/hw/net/Kconfig | ||
| 3987 | index XXXXXXX..XXXXXXX 100644 | 430 | index XXXXXXX..XXXXXXX 100644 |
| 3988 | --- a/hw/net/lance.c | 431 | --- a/hw/net/Kconfig |
| 3989 | +++ b/hw/net/lance.c | 432 | +++ b/hw/net/Kconfig |
| 3990 | @@ -XXX,XX +XXX,XX @@ static void lance_class_init(ObjectClass *klass, void *data) | 433 | @@ -XXX,XX +XXX,XX @@ config ALLWINNER_SUN8I_EMAC |
| 3991 | dc->realize = lance_realize; | 434 | |
| 3992 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); | 435 | config IMX_FEC |
| 3993 | dc->fw_name = "ethernet"; | 436 | bool |
| 3994 | - dc->reset = lance_reset; | 437 | + select LAN9118_PHY |
| 3995 | + device_class_set_legacy_reset(dc, lance_reset); | 438 | |
| 3996 | dc->vmsd = &vmstate_lance; | 439 | config CADENCE |
| 3997 | device_class_set_props(dc, lance_properties); | 440 | bool |
| 3998 | } | 441 | diff --git a/hw/net/trace-events b/hw/net/trace-events |
| 3999 | diff --git a/hw/net/lasi_i82596.c b/hw/net/lasi_i82596.c | ||
| 4000 | index XXXXXXX..XXXXXXX 100644 | 442 | index XXXXXXX..XXXXXXX 100644 |
| 4001 | --- a/hw/net/lasi_i82596.c | 443 | --- a/hw/net/trace-events |
| 4002 | +++ b/hw/net/lasi_i82596.c | 444 | +++ b/hw/net/trace-events |
| 4003 | @@ -XXX,XX +XXX,XX @@ static void lasi_82596_class_init(ObjectClass *klass, void *data) | 445 | @@ -XXX,XX +XXX,XX @@ allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u" |
| 4004 | dc->realize = lasi_82596_realize; | 446 | allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64 |
| 4005 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); | 447 | allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64 |
| 4006 | dc->fw_name = "ethernet"; | 448 | |
| 4007 | - dc->reset = lasi_82596_reset; | 449 | +# lan9118_phy.c |
| 4008 | + device_class_set_legacy_reset(dc, lasi_82596_reset); | 450 | +lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16 |
| 4009 | dc->vmsd = &vmstate_lasi_82596; | 451 | +lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16 |
| 4010 | dc->user_creatable = false; | 452 | +lan9118_phy_update_link(const char *s) "%s" |
| 4011 | device_class_set_props(dc, lasi_82596_properties); | 453 | +lan9118_phy_reset(void) "" |
| 4012 | diff --git a/hw/net/mcf_fec.c b/hw/net/mcf_fec.c | 454 | + |
| 4013 | index XXXXXXX..XXXXXXX 100644 | 455 | # lance.c |
| 4014 | --- a/hw/net/mcf_fec.c | 456 | lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x" |
| 4015 | +++ b/hw/net/mcf_fec.c | 457 | lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x" |
| 4016 | @@ -XXX,XX +XXX,XX @@ static void mcf_fec_class_init(ObjectClass *oc, void *data) | 458 | @@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries" |
| 4017 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); | 459 | i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION" |
| 4018 | dc->realize = mcf_fec_realize; | 460 | |
| 4019 | dc->desc = "MCF Fast Ethernet Controller network device"; | 461 | # imx_fec.c |
| 4020 | - dc->reset = mcf_fec_reset; | 462 | -imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]" |
| 4021 | + device_class_set_legacy_reset(dc, mcf_fec_reset); | 463 | imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)" |
| 4022 | device_class_set_props(dc, mcf_fec_properties); | 464 | -imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]" |
| 4023 | } | 465 | imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)" |
| 4024 | 466 | -imx_phy_update_link(const char *s) "%s" | |
| 4025 | diff --git a/hw/net/mipsnet.c b/hw/net/mipsnet.c | 467 | -imx_phy_reset(void) "" |
| 4026 | index XXXXXXX..XXXXXXX 100644 | 468 | imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x" |
| 4027 | --- a/hw/net/mipsnet.c | 469 | imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x" |
| 4028 | +++ b/hw/net/mipsnet.c | 470 | imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit" |
| 4029 | @@ -XXX,XX +XXX,XX @@ static void mipsnet_class_init(ObjectClass *klass, void *data) | ||
| 4030 | dc->realize = mipsnet_realize; | ||
| 4031 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); | ||
| 4032 | dc->desc = "MIPS Simulator network device"; | ||
| 4033 | - dc->reset = mipsnet_sysbus_reset; | ||
| 4034 | + device_class_set_legacy_reset(dc, mipsnet_sysbus_reset); | ||
| 4035 | dc->vmsd = &vmstate_mipsnet; | ||
| 4036 | device_class_set_props(dc, mipsnet_properties); | ||
| 4037 | } | ||
| 4038 | diff --git a/hw/net/msf2-emac.c b/hw/net/msf2-emac.c | ||
| 4039 | index XXXXXXX..XXXXXXX 100644 | ||
| 4040 | --- a/hw/net/msf2-emac.c | ||
| 4041 | +++ b/hw/net/msf2-emac.c | ||
| 4042 | @@ -XXX,XX +XXX,XX @@ static void msf2_emac_class_init(ObjectClass *klass, void *data) | ||
| 4043 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 4044 | |||
| 4045 | dc->realize = msf2_emac_realize; | ||
| 4046 | - dc->reset = msf2_emac_reset; | ||
| 4047 | + device_class_set_legacy_reset(dc, msf2_emac_reset); | ||
| 4048 | dc->vmsd = &vmstate_msf2_emac; | ||
| 4049 | device_class_set_props(dc, msf2_emac_properties); | ||
| 4050 | } | ||
| 4051 | diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c | ||
| 4052 | index XXXXXXX..XXXXXXX 100644 | ||
| 4053 | --- a/hw/net/npcm7xx_emc.c | ||
| 4054 | +++ b/hw/net/npcm7xx_emc.c | ||
| 4055 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_emc_class_init(ObjectClass *klass, void *data) | ||
| 4056 | dc->desc = "NPCM7xx EMC Controller"; | ||
| 4057 | dc->realize = npcm7xx_emc_realize; | ||
| 4058 | dc->unrealize = npcm7xx_emc_unrealize; | ||
| 4059 | - dc->reset = npcm7xx_emc_reset; | ||
| 4060 | + device_class_set_legacy_reset(dc, npcm7xx_emc_reset); | ||
| 4061 | dc->vmsd = &vmstate_npcm7xx_emc; | ||
| 4062 | device_class_set_props(dc, npcm7xx_emc_properties); | ||
| 4063 | } | ||
| 4064 | diff --git a/hw/net/npcm_gmac.c b/hw/net/npcm_gmac.c | ||
| 4065 | index XXXXXXX..XXXXXXX 100644 | ||
| 4066 | --- a/hw/net/npcm_gmac.c | ||
| 4067 | +++ b/hw/net/npcm_gmac.c | ||
| 4068 | @@ -XXX,XX +XXX,XX @@ static void npcm_gmac_class_init(ObjectClass *klass, void *data) | ||
| 4069 | dc->desc = "NPCM GMAC Controller"; | ||
| 4070 | dc->realize = npcm_gmac_realize; | ||
| 4071 | dc->unrealize = npcm_gmac_unrealize; | ||
| 4072 | - dc->reset = npcm_gmac_reset; | ||
| 4073 | + device_class_set_legacy_reset(dc, npcm_gmac_reset); | ||
| 4074 | dc->vmsd = &vmstate_npcm_gmac; | ||
| 4075 | device_class_set_props(dc, npcm_gmac_properties); | ||
| 4076 | } | ||
| 4077 | diff --git a/hw/net/opencores_eth.c b/hw/net/opencores_eth.c | ||
| 4078 | index XXXXXXX..XXXXXXX 100644 | ||
| 4079 | --- a/hw/net/opencores_eth.c | ||
| 4080 | +++ b/hw/net/opencores_eth.c | ||
| 4081 | @@ -XXX,XX +XXX,XX @@ static void open_eth_class_init(ObjectClass *klass, void *data) | ||
| 4082 | dc->realize = sysbus_open_eth_realize; | ||
| 4083 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); | ||
| 4084 | dc->desc = "Opencores 10/100 Mbit Ethernet"; | ||
| 4085 | - dc->reset = qdev_open_eth_reset; | ||
| 4086 | + device_class_set_legacy_reset(dc, qdev_open_eth_reset); | ||
| 4087 | device_class_set_props(dc, open_eth_properties); | ||
| 4088 | } | ||
| 4089 | |||
| 4090 | diff --git a/hw/net/pcnet-pci.c b/hw/net/pcnet-pci.c | ||
| 4091 | index XXXXXXX..XXXXXXX 100644 | ||
| 4092 | --- a/hw/net/pcnet-pci.c | ||
| 4093 | +++ b/hw/net/pcnet-pci.c | ||
| 4094 | @@ -XXX,XX +XXX,XX @@ static void pcnet_class_init(ObjectClass *klass, void *data) | ||
| 4095 | k->device_id = PCI_DEVICE_ID_AMD_LANCE; | ||
| 4096 | k->revision = 0x10; | ||
| 4097 | k->class_id = PCI_CLASS_NETWORK_ETHERNET; | ||
| 4098 | - dc->reset = pci_reset; | ||
| 4099 | + device_class_set_legacy_reset(dc, pci_reset); | ||
| 4100 | dc->vmsd = &vmstate_pci_pcnet; | ||
| 4101 | device_class_set_props(dc, pcnet_properties); | ||
| 4102 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); | ||
| 4103 | diff --git a/hw/net/rocker/rocker.c b/hw/net/rocker/rocker.c | ||
| 4104 | index XXXXXXX..XXXXXXX 100644 | ||
| 4105 | --- a/hw/net/rocker/rocker.c | ||
| 4106 | +++ b/hw/net/rocker/rocker.c | ||
| 4107 | @@ -XXX,XX +XXX,XX @@ static void rocker_class_init(ObjectClass *klass, void *data) | ||
| 4108 | k->class_id = PCI_CLASS_NETWORK_OTHER; | ||
| 4109 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); | ||
| 4110 | dc->desc = "Rocker Switch"; | ||
| 4111 | - dc->reset = rocker_reset; | ||
| 4112 | + device_class_set_legacy_reset(dc, rocker_reset); | ||
| 4113 | device_class_set_props(dc, rocker_properties); | ||
| 4114 | dc->vmsd = &rocker_vmsd; | ||
| 4115 | } | ||
| 4116 | diff --git a/hw/net/rtl8139.c b/hw/net/rtl8139.c | ||
| 4117 | index XXXXXXX..XXXXXXX 100644 | ||
| 4118 | --- a/hw/net/rtl8139.c | ||
| 4119 | +++ b/hw/net/rtl8139.c | ||
| 4120 | @@ -XXX,XX +XXX,XX @@ static void rtl8139_class_init(ObjectClass *klass, void *data) | ||
| 4121 | k->device_id = PCI_DEVICE_ID_REALTEK_8139; | ||
| 4122 | k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */ | ||
| 4123 | k->class_id = PCI_CLASS_NETWORK_ETHERNET; | ||
| 4124 | - dc->reset = rtl8139_reset; | ||
| 4125 | + device_class_set_legacy_reset(dc, rtl8139_reset); | ||
| 4126 | dc->vmsd = &vmstate_rtl8139; | ||
| 4127 | device_class_set_props(dc, rtl8139_properties); | ||
| 4128 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); | ||
| 4129 | diff --git a/hw/net/smc91c111.c b/hw/net/smc91c111.c | ||
| 4130 | index XXXXXXX..XXXXXXX 100644 | ||
| 4131 | --- a/hw/net/smc91c111.c | ||
| 4132 | +++ b/hw/net/smc91c111.c | ||
| 4133 | @@ -XXX,XX +XXX,XX @@ static void smc91c111_class_init(ObjectClass *klass, void *data) | ||
| 4134 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 4135 | |||
| 4136 | dc->realize = smc91c111_realize; | ||
| 4137 | - dc->reset = smc91c111_reset; | ||
| 4138 | + device_class_set_legacy_reset(dc, smc91c111_reset); | ||
| 4139 | dc->vmsd = &vmstate_smc91c111; | ||
| 4140 | device_class_set_props(dc, smc91c111_properties); | ||
| 4141 | } | ||
| 4142 | diff --git a/hw/net/stellaris_enet.c b/hw/net/stellaris_enet.c | ||
| 4143 | index XXXXXXX..XXXXXXX 100644 | ||
| 4144 | --- a/hw/net/stellaris_enet.c | ||
| 4145 | +++ b/hw/net/stellaris_enet.c | ||
| 4146 | @@ -XXX,XX +XXX,XX @@ static void stellaris_enet_class_init(ObjectClass *klass, void *data) | ||
| 4147 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 4148 | |||
| 4149 | dc->realize = stellaris_enet_realize; | ||
| 4150 | - dc->reset = stellaris_enet_reset; | ||
| 4151 | + device_class_set_legacy_reset(dc, stellaris_enet_reset); | ||
| 4152 | device_class_set_props(dc, stellaris_enet_properties); | ||
| 4153 | dc->vmsd = &vmstate_stellaris_enet; | ||
| 4154 | } | ||
| 4155 | diff --git a/hw/net/sungem.c b/hw/net/sungem.c | ||
| 4156 | index XXXXXXX..XXXXXXX 100644 | ||
| 4157 | --- a/hw/net/sungem.c | ||
| 4158 | +++ b/hw/net/sungem.c | ||
| 4159 | @@ -XXX,XX +XXX,XX @@ static void sungem_class_init(ObjectClass *klass, void *data) | ||
| 4160 | k->revision = 0x01; | ||
| 4161 | k->class_id = PCI_CLASS_NETWORK_ETHERNET; | ||
| 4162 | dc->vmsd = &vmstate_sungem; | ||
| 4163 | - dc->reset = sungem_reset; | ||
| 4164 | + device_class_set_legacy_reset(dc, sungem_reset); | ||
| 4165 | device_class_set_props(dc, sungem_properties); | ||
| 4166 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); | ||
| 4167 | } | ||
| 4168 | diff --git a/hw/net/sunhme.c b/hw/net/sunhme.c | ||
| 4169 | index XXXXXXX..XXXXXXX 100644 | ||
| 4170 | --- a/hw/net/sunhme.c | ||
| 4171 | +++ b/hw/net/sunhme.c | ||
| 4172 | @@ -XXX,XX +XXX,XX @@ static void sunhme_class_init(ObjectClass *klass, void *data) | ||
| 4173 | k->device_id = PCI_DEVICE_ID_SUN_HME; | ||
| 4174 | k->class_id = PCI_CLASS_NETWORK_ETHERNET; | ||
| 4175 | dc->vmsd = &vmstate_hme; | ||
| 4176 | - dc->reset = sunhme_reset; | ||
| 4177 | + device_class_set_legacy_reset(dc, sunhme_reset); | ||
| 4178 | device_class_set_props(dc, sunhme_properties); | ||
| 4179 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); | ||
| 4180 | } | ||
| 4181 | diff --git a/hw/net/tulip.c b/hw/net/tulip.c | ||
| 4182 | index XXXXXXX..XXXXXXX 100644 | ||
| 4183 | --- a/hw/net/tulip.c | ||
| 4184 | +++ b/hw/net/tulip.c | ||
| 4185 | @@ -XXX,XX +XXX,XX @@ static void tulip_class_init(ObjectClass *klass, void *data) | ||
| 4186 | k->class_id = PCI_CLASS_NETWORK_ETHERNET; | ||
| 4187 | dc->vmsd = &vmstate_pci_tulip; | ||
| 4188 | device_class_set_props(dc, tulip_properties); | ||
| 4189 | - dc->reset = tulip_qdev_reset; | ||
| 4190 | + device_class_set_legacy_reset(dc, tulip_qdev_reset); | ||
| 4191 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); | ||
| 4192 | } | ||
| 4193 | |||
| 4194 | diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c | ||
| 4195 | index XXXXXXX..XXXXXXX 100644 | ||
| 4196 | --- a/hw/net/vmxnet3.c | ||
| 4197 | +++ b/hw/net/vmxnet3.c | ||
| 4198 | @@ -XXX,XX +XXX,XX @@ static void vmxnet3_class_init(ObjectClass *class, void *data) | ||
| 4199 | device_class_set_parent_realize(dc, vmxnet3_realize, | ||
| 4200 | &vc->parent_dc_realize); | ||
| 4201 | dc->desc = "VMWare Paravirtualized Ethernet v3"; | ||
| 4202 | - dc->reset = vmxnet3_qdev_reset; | ||
| 4203 | + device_class_set_legacy_reset(dc, vmxnet3_qdev_reset); | ||
| 4204 | dc->vmsd = &vmstate_vmxnet3; | ||
| 4205 | device_class_set_props(dc, vmxnet3_properties); | ||
| 4206 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); | ||
| 4207 | diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c | ||
| 4208 | index XXXXXXX..XXXXXXX 100644 | ||
| 4209 | --- a/hw/net/xilinx_axienet.c | ||
| 4210 | +++ b/hw/net/xilinx_axienet.c | ||
| 4211 | @@ -XXX,XX +XXX,XX @@ static void xilinx_enet_class_init(ObjectClass *klass, void *data) | ||
| 4212 | |||
| 4213 | dc->realize = xilinx_enet_realize; | ||
| 4214 | device_class_set_props(dc, xilinx_enet_properties); | ||
| 4215 | - dc->reset = xilinx_axienet_reset; | ||
| 4216 | + device_class_set_legacy_reset(dc, xilinx_axienet_reset); | ||
| 4217 | } | ||
| 4218 | |||
| 4219 | static void xilinx_enet_control_stream_class_init(ObjectClass *klass, | ||
| 4220 | diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c | ||
| 4221 | index XXXXXXX..XXXXXXX 100644 | ||
| 4222 | --- a/hw/net/xilinx_ethlite.c | ||
| 4223 | +++ b/hw/net/xilinx_ethlite.c | ||
| 4224 | @@ -XXX,XX +XXX,XX @@ static void xilinx_ethlite_class_init(ObjectClass *klass, void *data) | ||
| 4225 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 4226 | |||
| 4227 | dc->realize = xilinx_ethlite_realize; | ||
| 4228 | - dc->reset = xilinx_ethlite_reset; | ||
| 4229 | + device_class_set_legacy_reset(dc, xilinx_ethlite_reset); | ||
| 4230 | device_class_set_props(dc, xilinx_ethlite_properties); | ||
| 4231 | } | ||
| 4232 | |||
| 4233 | diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c | ||
| 4234 | index XXXXXXX..XXXXXXX 100644 | ||
| 4235 | --- a/hw/nvme/ctrl.c | ||
| 4236 | +++ b/hw/nvme/ctrl.c | ||
| 4237 | @@ -XXX,XX +XXX,XX @@ static void nvme_class_init(ObjectClass *oc, void *data) | ||
| 4238 | dc->desc = "Non-Volatile Memory Express"; | ||
| 4239 | device_class_set_props(dc, nvme_props); | ||
| 4240 | dc->vmsd = &nvme_vmstate; | ||
| 4241 | - dc->reset = nvme_pci_reset; | ||
| 4242 | + device_class_set_legacy_reset(dc, nvme_pci_reset); | ||
| 4243 | } | ||
| 4244 | |||
| 4245 | static void nvme_instance_init(Object *obj) | ||
| 4246 | diff --git a/hw/nvram/eeprom_at24c.c b/hw/nvram/eeprom_at24c.c | ||
| 4247 | index XXXXXXX..XXXXXXX 100644 | ||
| 4248 | --- a/hw/nvram/eeprom_at24c.c | ||
| 4249 | +++ b/hw/nvram/eeprom_at24c.c | ||
| 4250 | @@ -XXX,XX +XXX,XX @@ void at24c_eeprom_class_init(ObjectClass *klass, void *data) | ||
| 4251 | k->send = &at24c_eeprom_send; | ||
| 4252 | |||
| 4253 | device_class_set_props(dc, at24c_eeprom_props); | ||
| 4254 | - dc->reset = at24c_eeprom_reset; | ||
| 4255 | + device_class_set_legacy_reset(dc, at24c_eeprom_reset); | ||
| 4256 | } | ||
| 4257 | |||
| 4258 | static | ||
| 4259 | diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c | ||
| 4260 | index XXXXXXX..XXXXXXX 100644 | ||
| 4261 | --- a/hw/nvram/fw_cfg.c | ||
| 4262 | +++ b/hw/nvram/fw_cfg.c | ||
| 4263 | @@ -XXX,XX +XXX,XX @@ static void fw_cfg_class_init(ObjectClass *klass, void *data) | ||
| 4264 | { | ||
| 4265 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 4266 | |||
| 4267 | - dc->reset = fw_cfg_reset; | ||
| 4268 | + device_class_set_legacy_reset(dc, fw_cfg_reset); | ||
| 4269 | dc->vmsd = &vmstate_fw_cfg; | ||
| 4270 | |||
| 4271 | device_class_set_props(dc, fw_cfg_properties); | ||
| 4272 | diff --git a/hw/nvram/mac_nvram.c b/hw/nvram/mac_nvram.c | ||
| 4273 | index XXXXXXX..XXXXXXX 100644 | ||
| 4274 | --- a/hw/nvram/mac_nvram.c | ||
| 4275 | +++ b/hw/nvram/mac_nvram.c | ||
| 4276 | @@ -XXX,XX +XXX,XX @@ static void macio_nvram_class_init(ObjectClass *oc, void *data) | ||
| 4277 | |||
| 4278 | dc->realize = macio_nvram_realizefn; | ||
| 4279 | dc->unrealize = macio_nvram_unrealizefn; | ||
| 4280 | - dc->reset = macio_nvram_reset; | ||
| 4281 | + device_class_set_legacy_reset(dc, macio_nvram_reset); | ||
| 4282 | dc->vmsd = &vmstate_macio_nvram; | ||
| 4283 | device_class_set_props(dc, macio_nvram_properties); | ||
| 4284 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 4285 | diff --git a/hw/nvram/nrf51_nvm.c b/hw/nvram/nrf51_nvm.c | ||
| 4286 | index XXXXXXX..XXXXXXX 100644 | ||
| 4287 | --- a/hw/nvram/nrf51_nvm.c | ||
| 4288 | +++ b/hw/nvram/nrf51_nvm.c | ||
| 4289 | @@ -XXX,XX +XXX,XX @@ static void nrf51_nvm_class_init(ObjectClass *klass, void *data) | ||
| 4290 | device_class_set_props(dc, nrf51_nvm_properties); | ||
| 4291 | dc->vmsd = &vmstate_nvm; | ||
| 4292 | dc->realize = nrf51_nvm_realize; | ||
| 4293 | - dc->reset = nrf51_nvm_reset; | ||
| 4294 | + device_class_set_legacy_reset(dc, nrf51_nvm_reset); | ||
| 4295 | } | ||
| 4296 | |||
| 4297 | static const TypeInfo nrf51_nvm_info = { | ||
| 4298 | diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c | ||
| 4299 | index XXXXXXX..XXXXXXX 100644 | ||
| 4300 | --- a/hw/pci-bridge/cxl_downstream.c | ||
| 4301 | +++ b/hw/pci-bridge/cxl_downstream.c | ||
| 4302 | @@ -XXX,XX +XXX,XX @@ static void cxl_dsp_class_init(ObjectClass *oc, void *data) | ||
| 4303 | k->revision = 0; | ||
| 4304 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); | ||
| 4305 | dc->desc = "CXL Switch Downstream Port"; | ||
| 4306 | - dc->reset = cxl_dsp_reset; | ||
| 4307 | + device_class_set_legacy_reset(dc, cxl_dsp_reset); | ||
| 4308 | } | ||
| 4309 | |||
| 4310 | static const TypeInfo cxl_dsp_info = { | ||
| 4311 | diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c | ||
| 4312 | index XXXXXXX..XXXXXXX 100644 | ||
| 4313 | --- a/hw/pci-bridge/cxl_upstream.c | ||
| 4314 | +++ b/hw/pci-bridge/cxl_upstream.c | ||
| 4315 | @@ -XXX,XX +XXX,XX @@ static void cxl_upstream_class_init(ObjectClass *oc, void *data) | ||
| 4316 | k->revision = 0; | ||
| 4317 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); | ||
| 4318 | dc->desc = "CXL Switch Upstream Port"; | ||
| 4319 | - dc->reset = cxl_usp_reset; | ||
| 4320 | + device_class_set_legacy_reset(dc, cxl_usp_reset); | ||
| 4321 | device_class_set_props(dc, cxl_upstream_props); | ||
| 4322 | } | ||
| 4323 | |||
| 4324 | diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c | ||
| 4325 | index XXXXXXX..XXXXXXX 100644 | ||
| 4326 | --- a/hw/pci-bridge/i82801b11.c | ||
| 4327 | +++ b/hw/pci-bridge/i82801b11.c | ||
| 4328 | @@ -XXX,XX +XXX,XX @@ static void i82801b11_bridge_class_init(ObjectClass *klass, void *data) | ||
| 4329 | k->realize = i82801b11_bridge_realize; | ||
| 4330 | k->config_write = pci_bridge_write_config; | ||
| 4331 | dc->vmsd = &i82801b11_bridge_dev_vmstate; | ||
| 4332 | - dc->reset = pci_bridge_reset; | ||
| 4333 | + device_class_set_legacy_reset(dc, pci_bridge_reset); | ||
| 4334 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); | ||
| 4335 | } | ||
| 4336 | |||
| 4337 | diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c | ||
| 4338 | index XXXXXXX..XXXXXXX 100644 | ||
| 4339 | --- a/hw/pci-bridge/pci_bridge_dev.c | ||
| 4340 | +++ b/hw/pci-bridge/pci_bridge_dev.c | ||
| 4341 | @@ -XXX,XX +XXX,XX @@ static void pci_bridge_dev_class_init(ObjectClass *klass, void *data) | ||
| 4342 | k->device_id = PCI_DEVICE_ID_REDHAT_BRIDGE; | ||
| 4343 | k->class_id = PCI_CLASS_BRIDGE_PCI; | ||
| 4344 | dc->desc = "Standard PCI Bridge"; | ||
| 4345 | - dc->reset = qdev_pci_bridge_dev_reset; | ||
| 4346 | + device_class_set_legacy_reset(dc, qdev_pci_bridge_dev_reset); | ||
| 4347 | device_class_set_props(dc, pci_bridge_dev_properties); | ||
| 4348 | dc->vmsd = &pci_bridge_dev_vmstate; | ||
| 4349 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); | ||
| 4350 | diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c | ||
| 4351 | index XXXXXXX..XXXXXXX 100644 | ||
| 4352 | --- a/hw/pci-bridge/pci_expander_bridge.c | ||
| 4353 | +++ b/hw/pci-bridge/pci_expander_bridge.c | ||
| 4354 | @@ -XXX,XX +XXX,XX @@ static void pxb_cxl_dev_class_init(ObjectClass *klass, void *data) | ||
| 4355 | |||
| 4356 | /* Host bridges aren't hotpluggable. FIXME: spec reference */ | ||
| 4357 | dc->hotpluggable = false; | ||
| 4358 | - dc->reset = pxb_cxl_dev_reset; | ||
| 4359 | + device_class_set_legacy_reset(dc, pxb_cxl_dev_reset); | ||
| 4360 | } | ||
| 4361 | |||
| 4362 | static const TypeInfo pxb_cxl_dev_info = { | ||
| 4363 | diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridge.c | ||
| 4364 | index XXXXXXX..XXXXXXX 100644 | ||
| 4365 | --- a/hw/pci-bridge/pcie_pci_bridge.c | ||
| 4366 | +++ b/hw/pci-bridge/pcie_pci_bridge.c | ||
| 4367 | @@ -XXX,XX +XXX,XX @@ static void pcie_pci_bridge_class_init(ObjectClass *klass, void *data) | ||
| 4368 | k->config_write = pcie_pci_bridge_write_config; | ||
| 4369 | dc->vmsd = &pcie_pci_bridge_dev_vmstate; | ||
| 4370 | device_class_set_props(dc, pcie_pci_bridge_dev_properties); | ||
| 4371 | - dc->reset = &pcie_pci_bridge_reset; | ||
| 4372 | + device_class_set_legacy_reset(dc, pcie_pci_bridge_reset); | ||
| 4373 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); | ||
| 4374 | hc->plug = pci_bridge_dev_plug_cb; | ||
| 4375 | hc->unplug = pci_bridge_dev_unplug_cb; | ||
| 4376 | diff --git a/hw/pci-bridge/simba.c b/hw/pci-bridge/simba.c | ||
| 4377 | index XXXXXXX..XXXXXXX 100644 | ||
| 4378 | --- a/hw/pci-bridge/simba.c | ||
| 4379 | +++ b/hw/pci-bridge/simba.c | ||
| 4380 | @@ -XXX,XX +XXX,XX @@ static void simba_pci_bridge_class_init(ObjectClass *klass, void *data) | ||
| 4381 | k->revision = 0x11; | ||
| 4382 | k->config_write = pci_bridge_write_config; | ||
| 4383 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); | ||
| 4384 | - dc->reset = pci_bridge_reset; | ||
| 4385 | + device_class_set_legacy_reset(dc, pci_bridge_reset); | ||
| 4386 | dc->vmsd = &vmstate_pci_device; | ||
| 4387 | } | ||
| 4388 | |||
| 4389 | diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c | ||
| 4390 | index XXXXXXX..XXXXXXX 100644 | ||
| 4391 | --- a/hw/pci-bridge/xio3130_downstream.c | ||
| 4392 | +++ b/hw/pci-bridge/xio3130_downstream.c | ||
| 4393 | @@ -XXX,XX +XXX,XX @@ static void xio3130_downstream_class_init(ObjectClass *klass, void *data) | ||
| 4394 | k->revision = XIO3130_REVISION; | ||
| 4395 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); | ||
| 4396 | dc->desc = "TI X3130 Downstream Port of PCI Express Switch"; | ||
| 4397 | - dc->reset = xio3130_downstream_reset; | ||
| 4398 | + device_class_set_legacy_reset(dc, xio3130_downstream_reset); | ||
| 4399 | dc->vmsd = &vmstate_xio3130_downstream; | ||
| 4400 | device_class_set_props(dc, xio3130_downstream_props); | ||
| 4401 | } | ||
| 4402 | diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c | ||
| 4403 | index XXXXXXX..XXXXXXX 100644 | ||
| 4404 | --- a/hw/pci-bridge/xio3130_upstream.c | ||
| 4405 | +++ b/hw/pci-bridge/xio3130_upstream.c | ||
| 4406 | @@ -XXX,XX +XXX,XX @@ static void xio3130_upstream_class_init(ObjectClass *klass, void *data) | ||
| 4407 | k->revision = XIO3130_REVISION; | ||
| 4408 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); | ||
| 4409 | dc->desc = "TI X3130 Upstream Port of PCI Express Switch"; | ||
| 4410 | - dc->reset = xio3130_upstream_reset; | ||
| 4411 | + device_class_set_legacy_reset(dc, xio3130_upstream_reset); | ||
| 4412 | dc->vmsd = &vmstate_xio3130_upstream; | ||
| 4413 | } | ||
| 4414 | |||
| 4415 | diff --git a/hw/pci-host/astro.c b/hw/pci-host/astro.c | ||
| 4416 | index XXXXXXX..XXXXXXX 100644 | ||
| 4417 | --- a/hw/pci-host/astro.c | ||
| 4418 | +++ b/hw/pci-host/astro.c | ||
| 4419 | @@ -XXX,XX +XXX,XX @@ static void elroy_pcihost_class_init(ObjectClass *klass, void *data) | ||
| 4420 | { | ||
| 4421 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 4422 | |||
| 4423 | - dc->reset = elroy_reset; | ||
| 4424 | + device_class_set_legacy_reset(dc, elroy_reset); | ||
| 4425 | device_class_set_props(dc, elroy_pcihost_properties); | ||
| 4426 | dc->vmsd = &vmstate_elroy; | ||
| 4427 | dc->user_creatable = false; | ||
| 4428 | @@ -XXX,XX +XXX,XX @@ static void astro_class_init(ObjectClass *klass, void *data) | ||
| 4429 | { | ||
| 4430 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 4431 | |||
| 4432 | - dc->reset = astro_reset; | ||
| 4433 | + device_class_set_legacy_reset(dc, astro_reset); | ||
| 4434 | dc->vmsd = &vmstate_astro; | ||
| 4435 | dc->realize = astro_realize; | ||
| 4436 | /* | ||
| 4437 | diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c | ||
| 4438 | index XXXXXXX..XXXXXXX 100644 | ||
| 4439 | --- a/hw/pci-host/designware.c | ||
| 4440 | +++ b/hw/pci-host/designware.c | ||
| 4441 | @@ -XXX,XX +XXX,XX @@ static void designware_pcie_root_class_init(ObjectClass *klass, void *data) | ||
| 4442 | k->config_read = designware_pcie_root_config_read; | ||
| 4443 | k->config_write = designware_pcie_root_config_write; | ||
| 4444 | |||
| 4445 | - dc->reset = pci_bridge_reset; | ||
| 4446 | + device_class_set_legacy_reset(dc, pci_bridge_reset); | ||
| 4447 | /* | ||
| 4448 | * PCI-facing part of the host bridge, not usable without the | ||
| 4449 | * host-facing part, which can't be device_add'ed, yet. | ||
| 4450 | diff --git a/hw/pci-host/dino.c b/hw/pci-host/dino.c | ||
| 4451 | index XXXXXXX..XXXXXXX 100644 | ||
| 4452 | --- a/hw/pci-host/dino.c | ||
| 4453 | +++ b/hw/pci-host/dino.c | ||
| 4454 | @@ -XXX,XX +XXX,XX @@ static void dino_pcihost_class_init(ObjectClass *klass, void *data) | ||
| 4455 | { | ||
| 4456 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 4457 | |||
| 4458 | - dc->reset = dino_pcihost_reset; | ||
| 4459 | + device_class_set_legacy_reset(dc, dino_pcihost_reset); | ||
| 4460 | dc->realize = dino_pcihost_realize; | ||
| 4461 | dc->unrealize = dino_pcihost_unrealize; | ||
| 4462 | device_class_set_props(dc, dino_pcihost_properties); | ||
| 4463 | diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c | ||
| 4464 | index XXXXXXX..XXXXXXX 100644 | ||
| 4465 | --- a/hw/pci-host/gt64120.c | ||
| 4466 | +++ b/hw/pci-host/gt64120.c | ||
| 4467 | @@ -XXX,XX +XXX,XX @@ static void gt64120_class_init(ObjectClass *klass, void *data) | ||
| 4468 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); | ||
| 4469 | device_class_set_props(dc, gt64120_properties); | ||
| 4470 | dc->realize = gt64120_realize; | ||
| 4471 | - dc->reset = gt64120_reset; | ||
| 4472 | + device_class_set_legacy_reset(dc, gt64120_reset); | ||
| 4473 | dc->vmsd = &vmstate_gt64120; | ||
| 4474 | } | ||
| 4475 | |||
| 4476 | diff --git a/hw/pci-host/mv64361.c b/hw/pci-host/mv64361.c | ||
| 4477 | index XXXXXXX..XXXXXXX 100644 | ||
| 4478 | --- a/hw/pci-host/mv64361.c | ||
| 4479 | +++ b/hw/pci-host/mv64361.c | ||
| 4480 | @@ -XXX,XX +XXX,XX @@ static void mv64361_class_init(ObjectClass *klass, void *data) | ||
| 4481 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 4482 | |||
| 4483 | dc->realize = mv64361_realize; | ||
| 4484 | - dc->reset = mv64361_reset; | ||
| 4485 | + device_class_set_legacy_reset(dc, mv64361_reset); | ||
| 4486 | } | ||
| 4487 | |||
| 4488 | static const TypeInfo mv64361_type_info = { | ||
| 4489 | diff --git a/hw/pci-host/ppc440_pcix.c b/hw/pci-host/ppc440_pcix.c | ||
| 4490 | index XXXXXXX..XXXXXXX 100644 | ||
| 4491 | --- a/hw/pci-host/ppc440_pcix.c | ||
| 4492 | +++ b/hw/pci-host/ppc440_pcix.c | ||
| 4493 | @@ -XXX,XX +XXX,XX @@ static void ppc440_pcix_class_init(ObjectClass *klass, void *data) | ||
| 4494 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 4495 | |||
| 4496 | dc->realize = ppc440_pcix_realize; | ||
| 4497 | - dc->reset = ppc440_pcix_reset; | ||
| 4498 | + device_class_set_legacy_reset(dc, ppc440_pcix_reset); | ||
| 4499 | } | ||
| 4500 | |||
| 4501 | static const TypeInfo ppc440_pcix_info = { | ||
| 4502 | diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c | ||
| 4503 | index XXXXXXX..XXXXXXX 100644 | ||
| 4504 | --- a/hw/pci-host/q35.c | ||
| 4505 | +++ b/hw/pci-host/q35.c | ||
| 4506 | @@ -XXX,XX +XXX,XX @@ static void mch_class_init(ObjectClass *klass, void *data) | ||
| 4507 | |||
| 4508 | k->realize = mch_realize; | ||
| 4509 | k->config_write = mch_write_config; | ||
| 4510 | - dc->reset = mch_reset; | ||
| 4511 | + device_class_set_legacy_reset(dc, mch_reset); | ||
| 4512 | device_class_set_props(dc, mch_props); | ||
| 4513 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); | ||
| 4514 | dc->desc = "Host bridge"; | ||
| 4515 | diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c | ||
| 4516 | index XXXXXXX..XXXXXXX 100644 | ||
| 4517 | --- a/hw/pci-host/sabre.c | ||
| 4518 | +++ b/hw/pci-host/sabre.c | ||
| 4519 | @@ -XXX,XX +XXX,XX @@ static void sabre_class_init(ObjectClass *klass, void *data) | ||
| 4520 | SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); | ||
| 4521 | |||
| 4522 | dc->realize = sabre_realize; | ||
| 4523 | - dc->reset = sabre_reset; | ||
| 4524 | + device_class_set_legacy_reset(dc, sabre_reset); | ||
| 4525 | device_class_set_props(dc, sabre_properties); | ||
| 4526 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); | ||
| 4527 | dc->fw_name = "pci"; | ||
| 4528 | diff --git a/hw/pci-host/versatile.c b/hw/pci-host/versatile.c | ||
| 4529 | index XXXXXXX..XXXXXXX 100644 | ||
| 4530 | --- a/hw/pci-host/versatile.c | ||
| 4531 | +++ b/hw/pci-host/versatile.c | ||
| 4532 | @@ -XXX,XX +XXX,XX @@ static void pci_vpb_class_init(ObjectClass *klass, void *data) | ||
| 4533 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 4534 | |||
| 4535 | dc->realize = pci_vpb_realize; | ||
| 4536 | - dc->reset = pci_vpb_reset; | ||
| 4537 | + device_class_set_legacy_reset(dc, pci_vpb_reset); | ||
| 4538 | dc->vmsd = &pci_vpb_vmstate; | ||
| 4539 | device_class_set_props(dc, pci_vpb_properties); | ||
| 4540 | } | ||
| 4541 | diff --git a/hw/pci-host/xilinx-pcie.c b/hw/pci-host/xilinx-pcie.c | ||
| 4542 | index XXXXXXX..XXXXXXX 100644 | ||
| 4543 | --- a/hw/pci-host/xilinx-pcie.c | ||
| 4544 | +++ b/hw/pci-host/xilinx-pcie.c | ||
| 4545 | @@ -XXX,XX +XXX,XX @@ static void xilinx_pcie_root_class_init(ObjectClass *klass, void *data) | ||
| 4546 | k->class_id = PCI_CLASS_BRIDGE_HOST; | ||
| 4547 | k->realize = xilinx_pcie_root_realize; | ||
| 4548 | k->exit = pci_bridge_exitfn; | ||
| 4549 | - dc->reset = pci_bridge_reset; | ||
| 4550 | + device_class_set_legacy_reset(dc, pci_bridge_reset); | ||
| 4551 | k->config_read = xilinx_pcie_root_config_read; | ||
| 4552 | k->config_write = xilinx_pcie_root_config_write; | ||
| 4553 | /* | ||
| 4554 | diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c | ||
| 4555 | index XXXXXXX..XXXXXXX 100644 | ||
| 4556 | --- a/hw/ppc/pnv_psi.c | ||
| 4557 | +++ b/hw/ppc/pnv_psi.c | ||
| 4558 | @@ -XXX,XX +XXX,XX @@ static void pnv_psi_power9_class_init(ObjectClass *klass, void *data) | ||
| 4559 | |||
| 4560 | dc->desc = "PowerNV PSI Controller POWER9"; | ||
| 4561 | dc->realize = pnv_psi_power9_realize; | ||
| 4562 | - dc->reset = pnv_psi_power9_reset; | ||
| 4563 | + device_class_set_legacy_reset(dc, pnv_psi_power9_reset); | ||
| 4564 | |||
| 4565 | ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE; | ||
| 4566 | ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE; | ||
| 4567 | @@ -XXX,XX +XXX,XX @@ static void pnv_psi_class_init(ObjectClass *klass, void *data) | ||
| 4568 | |||
| 4569 | dc->desc = "PowerNV PSI Controller"; | ||
| 4570 | device_class_set_props(dc, pnv_psi_properties); | ||
| 4571 | - dc->reset = pnv_psi_reset; | ||
| 4572 | + device_class_set_legacy_reset(dc, pnv_psi_reset); | ||
| 4573 | dc->user_creatable = false; | ||
| 4574 | } | ||
| 4575 | |||
| 4576 | diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c | ||
| 4577 | index XXXXXXX..XXXXXXX 100644 | ||
| 4578 | --- a/hw/ppc/ppc405_boards.c | ||
| 4579 | +++ b/hw/ppc/ppc405_boards.c | ||
| 4580 | @@ -XXX,XX +XXX,XX @@ static void ref405ep_fpga_class_init(ObjectClass *oc, void *data) | ||
| 4581 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 4582 | |||
| 4583 | dc->realize = ref405ep_fpga_realize; | ||
| 4584 | - dc->reset = ref405ep_fpga_reset; | ||
| 4585 | + device_class_set_legacy_reset(dc, ref405ep_fpga_reset); | ||
| 4586 | /* Reason: only works as part of a ppc405 board */ | ||
| 4587 | dc->user_creatable = false; | ||
| 4588 | } | ||
| 4589 | diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c | ||
| 4590 | index XXXXXXX..XXXXXXX 100644 | ||
| 4591 | --- a/hw/ppc/ppc405_uc.c | ||
| 4592 | +++ b/hw/ppc/ppc405_uc.c | ||
| 4593 | @@ -XXX,XX +XXX,XX @@ static void ppc405_pob_class_init(ObjectClass *oc, void *data) | ||
| 4594 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 4595 | |||
| 4596 | dc->realize = ppc405_pob_realize; | ||
| 4597 | - dc->reset = ppc405_pob_reset; | ||
| 4598 | + device_class_set_legacy_reset(dc, ppc405_pob_reset); | ||
| 4599 | /* Reason: only works as function of a ppc4xx SoC */ | ||
| 4600 | dc->user_creatable = false; | ||
| 4601 | } | ||
| 4602 | @@ -XXX,XX +XXX,XX @@ static void ppc405_opba_class_init(ObjectClass *oc, void *data) | ||
| 4603 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 4604 | |||
| 4605 | dc->realize = ppc405_opba_realize; | ||
| 4606 | - dc->reset = ppc405_opba_reset; | ||
| 4607 | + device_class_set_legacy_reset(dc, ppc405_opba_reset); | ||
| 4608 | /* Reason: only works as function of a ppc4xx SoC */ | ||
| 4609 | dc->user_creatable = false; | ||
| 4610 | } | ||
| 4611 | @@ -XXX,XX +XXX,XX @@ static void ppc405_dma_class_init(ObjectClass *oc, void *data) | ||
| 4612 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 4613 | |||
| 4614 | dc->realize = ppc405_dma_realize; | ||
| 4615 | - dc->reset = ppc405_dma_reset; | ||
| 4616 | + device_class_set_legacy_reset(dc, ppc405_dma_reset); | ||
| 4617 | /* Reason: only works as function of a ppc4xx SoC */ | ||
| 4618 | dc->user_creatable = false; | ||
| 4619 | } | ||
| 4620 | @@ -XXX,XX +XXX,XX @@ static void ppc405_ocm_class_init(ObjectClass *oc, void *data) | ||
| 4621 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 4622 | |||
| 4623 | dc->realize = ppc405_ocm_realize; | ||
| 4624 | - dc->reset = ppc405_ocm_reset; | ||
| 4625 | + device_class_set_legacy_reset(dc, ppc405_ocm_reset); | ||
| 4626 | /* Reason: only works as function of a ppc4xx SoC */ | ||
| 4627 | dc->user_creatable = false; | ||
| 4628 | } | ||
| 4629 | @@ -XXX,XX +XXX,XX @@ static void ppc405_gpt_class_init(ObjectClass *oc, void *data) | ||
| 4630 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 4631 | |||
| 4632 | dc->realize = ppc405_gpt_realize; | ||
| 4633 | - dc->reset = ppc405_gpt_reset; | ||
| 4634 | + device_class_set_legacy_reset(dc, ppc405_gpt_reset); | ||
| 4635 | /* Reason: only works as function of a ppc4xx SoC */ | ||
| 4636 | dc->user_creatable = false; | ||
| 4637 | } | ||
| 4638 | @@ -XXX,XX +XXX,XX @@ static void ppc405_cpc_class_init(ObjectClass *oc, void *data) | ||
| 4639 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 4640 | |||
| 4641 | dc->realize = ppc405_cpc_realize; | ||
| 4642 | - dc->reset = ppc405_cpc_reset; | ||
| 4643 | + device_class_set_legacy_reset(dc, ppc405_cpc_reset); | ||
| 4644 | /* Reason: only works as function of a ppc4xx SoC */ | ||
| 4645 | dc->user_creatable = false; | ||
| 4646 | device_class_set_props(dc, ppc405_cpc_properties); | ||
| 4647 | diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c | ||
| 4648 | index XXXXXXX..XXXXXXX 100644 | ||
| 4649 | --- a/hw/ppc/ppc4xx_devs.c | ||
| 4650 | +++ b/hw/ppc/ppc4xx_devs.c | ||
| 4651 | @@ -XXX,XX +XXX,XX @@ static void ppc4xx_mal_class_init(ObjectClass *oc, void *data) | ||
| 4652 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 4653 | |||
| 4654 | dc->realize = ppc4xx_mal_realize; | ||
| 4655 | - dc->reset = ppc4xx_mal_reset; | ||
| 4656 | + device_class_set_legacy_reset(dc, ppc4xx_mal_reset); | ||
| 4657 | /* Reason: only works as function of a ppc4xx SoC */ | ||
| 4658 | dc->user_creatable = false; | ||
| 4659 | device_class_set_props(dc, ppc4xx_mal_properties); | ||
| 4660 | @@ -XXX,XX +XXX,XX @@ static void ppc405_plb_class_init(ObjectClass *oc, void *data) | ||
| 4661 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 4662 | |||
| 4663 | dc->realize = ppc405_plb_realize; | ||
| 4664 | - dc->reset = ppc405_plb_reset; | ||
| 4665 | + device_class_set_legacy_reset(dc, ppc405_plb_reset); | ||
| 4666 | /* Reason: only works as function of a ppc4xx SoC */ | ||
| 4667 | dc->user_creatable = false; | ||
| 4668 | } | ||
| 4669 | @@ -XXX,XX +XXX,XX @@ static void ppc405_ebc_class_init(ObjectClass *oc, void *data) | ||
| 4670 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 4671 | |||
| 4672 | dc->realize = ppc405_ebc_realize; | ||
| 4673 | - dc->reset = ppc405_ebc_reset; | ||
| 4674 | + device_class_set_legacy_reset(dc, ppc405_ebc_reset); | ||
| 4675 | /* Reason: only works as function of a ppc4xx SoC */ | ||
| 4676 | dc->user_creatable = false; | ||
| 4677 | } | ||
| 4678 | diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c | ||
| 4679 | index XXXXXXX..XXXXXXX 100644 | ||
| 4680 | --- a/hw/ppc/ppc4xx_sdram.c | ||
| 4681 | +++ b/hw/ppc/ppc4xx_sdram.c | ||
| 4682 | @@ -XXX,XX +XXX,XX @@ static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc, void *data) | ||
| 4683 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 4684 | |||
| 4685 | dc->realize = ppc4xx_sdram_ddr_realize; | ||
| 4686 | - dc->reset = ppc4xx_sdram_ddr_reset; | ||
| 4687 | + device_class_set_legacy_reset(dc, ppc4xx_sdram_ddr_reset); | ||
| 4688 | /* Reason: only works as function of a ppc4xx SoC */ | ||
| 4689 | dc->user_creatable = false; | ||
| 4690 | device_class_set_props(dc, ppc4xx_sdram_ddr_props); | ||
| 4691 | @@ -XXX,XX +XXX,XX @@ static void ppc4xx_sdram_ddr2_class_init(ObjectClass *oc, void *data) | ||
| 4692 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 4693 | |||
| 4694 | dc->realize = ppc4xx_sdram_ddr2_realize; | ||
| 4695 | - dc->reset = ppc4xx_sdram_ddr2_reset; | ||
| 4696 | + device_class_set_legacy_reset(dc, ppc4xx_sdram_ddr2_reset); | ||
| 4697 | /* Reason: only works as function of a ppc4xx SoC */ | ||
| 4698 | dc->user_creatable = false; | ||
| 4699 | device_class_set_props(dc, ppc4xx_sdram_ddr2_props); | ||
| 4700 | diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c | ||
| 4701 | index XXXXXXX..XXXXXXX 100644 | ||
| 4702 | --- a/hw/ppc/ppce500_spin.c | ||
| 4703 | +++ b/hw/ppc/ppce500_spin.c | ||
| 4704 | @@ -XXX,XX +XXX,XX @@ static void ppce500_spin_class_init(ObjectClass *klass, void *data) | ||
| 4705 | { | ||
| 4706 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 4707 | |||
| 4708 | - dc->reset = spin_reset; | ||
| 4709 | + device_class_set_legacy_reset(dc, spin_reset); | ||
| 4710 | } | ||
| 4711 | |||
| 4712 | static const TypeInfo ppce500_spin_info = { | ||
| 4713 | diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c | ||
| 4714 | index XXXXXXX..XXXXXXX 100644 | ||
| 4715 | --- a/hw/ppc/spapr_cpu_core.c | ||
| 4716 | +++ b/hw/ppc/spapr_cpu_core.c | ||
| 4717 | @@ -XXX,XX +XXX,XX @@ static void spapr_cpu_core_class_init(ObjectClass *oc, void *data) | ||
| 4718 | |||
| 4719 | dc->realize = spapr_cpu_core_realize; | ||
| 4720 | dc->unrealize = spapr_cpu_core_unrealize; | ||
| 4721 | - dc->reset = spapr_cpu_core_reset; | ||
| 4722 | + device_class_set_legacy_reset(dc, spapr_cpu_core_reset); | ||
| 4723 | device_class_set_props(dc, spapr_cpu_core_properties); | ||
| 4724 | scc->cpu_type = data; | ||
| 4725 | } | ||
| 4726 | diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c | ||
| 4727 | index XXXXXXX..XXXXXXX 100644 | ||
| 4728 | --- a/hw/ppc/spapr_iommu.c | ||
| 4729 | +++ b/hw/ppc/spapr_iommu.c | ||
| 4730 | @@ -XXX,XX +XXX,XX @@ static void spapr_tce_table_class_init(ObjectClass *klass, void *data) | ||
| 4731 | { | ||
| 4732 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 4733 | dc->realize = spapr_tce_table_realize; | ||
| 4734 | - dc->reset = spapr_tce_reset; | ||
| 4735 | + device_class_set_legacy_reset(dc, spapr_tce_reset); | ||
| 4736 | dc->unrealize = spapr_tce_table_unrealize; | ||
| 4737 | /* Reason: This is just an internal device for handling the hypercalls */ | ||
| 4738 | dc->user_creatable = false; | ||
| 4739 | diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c | ||
| 4740 | index XXXXXXX..XXXXXXX 100644 | ||
| 4741 | --- a/hw/ppc/spapr_pci.c | ||
| 4742 | +++ b/hw/ppc/spapr_pci.c | ||
| 4743 | @@ -XXX,XX +XXX,XX @@ static void spapr_phb_class_init(ObjectClass *klass, void *data) | ||
| 4744 | dc->realize = spapr_phb_realize; | ||
| 4745 | dc->unrealize = spapr_phb_unrealize; | ||
| 4746 | device_class_set_props(dc, spapr_phb_properties); | ||
| 4747 | - dc->reset = spapr_phb_reset; | ||
| 4748 | + device_class_set_legacy_reset(dc, spapr_phb_reset); | ||
| 4749 | dc->vmsd = &vmstate_spapr_pci; | ||
| 4750 | /* Supported by TYPE_SPAPR_MACHINE */ | ||
| 4751 | dc->user_creatable = true; | ||
| 4752 | diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c | ||
| 4753 | index XXXXXXX..XXXXXXX 100644 | ||
| 4754 | --- a/hw/ppc/spapr_vio.c | ||
| 4755 | +++ b/hw/ppc/spapr_vio.c | ||
| 4756 | @@ -XXX,XX +XXX,XX @@ static void vio_spapr_device_class_init(ObjectClass *klass, void *data) | ||
| 4757 | { | ||
| 4758 | DeviceClass *k = DEVICE_CLASS(klass); | ||
| 4759 | k->realize = spapr_vio_busdev_realize; | ||
| 4760 | - k->reset = spapr_vio_busdev_reset; | ||
| 4761 | + device_class_set_legacy_reset(k, spapr_vio_busdev_reset); | ||
| 4762 | k->bus_type = TYPE_SPAPR_VIO_BUS; | ||
| 4763 | } | ||
| 4764 | |||
| 4765 | diff --git a/hw/remote/proxy.c b/hw/remote/proxy.c | ||
| 4766 | index XXXXXXX..XXXXXXX 100644 | ||
| 4767 | --- a/hw/remote/proxy.c | ||
| 4768 | +++ b/hw/remote/proxy.c | ||
| 4769 | @@ -XXX,XX +XXX,XX @@ static void pci_proxy_dev_class_init(ObjectClass *klass, void *data) | ||
| 4770 | k->config_read = pci_proxy_read_config; | ||
| 4771 | k->config_write = pci_proxy_write_config; | ||
| 4772 | |||
| 4773 | - dc->reset = proxy_device_reset; | ||
| 4774 | + device_class_set_legacy_reset(dc, proxy_device_reset); | ||
| 4775 | |||
| 4776 | device_class_set_props(dc, proxy_properties); | ||
| 4777 | } | ||
| 4778 | diff --git a/hw/rtc/allwinner-rtc.c b/hw/rtc/allwinner-rtc.c | ||
| 4779 | index XXXXXXX..XXXXXXX 100644 | ||
| 4780 | --- a/hw/rtc/allwinner-rtc.c | ||
| 4781 | +++ b/hw/rtc/allwinner-rtc.c | ||
| 4782 | @@ -XXX,XX +XXX,XX @@ static void allwinner_rtc_class_init(ObjectClass *klass, void *data) | ||
| 4783 | { | ||
| 4784 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 4785 | |||
| 4786 | - dc->reset = allwinner_rtc_reset; | ||
| 4787 | + device_class_set_legacy_reset(dc, allwinner_rtc_reset); | ||
| 4788 | dc->vmsd = &allwinner_rtc_vmstate; | ||
| 4789 | device_class_set_props(dc, allwinner_rtc_properties); | ||
| 4790 | } | ||
| 4791 | diff --git a/hw/rtc/aspeed_rtc.c b/hw/rtc/aspeed_rtc.c | ||
| 4792 | index XXXXXXX..XXXXXXX 100644 | ||
| 4793 | --- a/hw/rtc/aspeed_rtc.c | ||
| 4794 | +++ b/hw/rtc/aspeed_rtc.c | ||
| 4795 | @@ -XXX,XX +XXX,XX @@ static void aspeed_rtc_class_init(ObjectClass *klass, void *data) | ||
| 4796 | |||
| 4797 | dc->realize = aspeed_rtc_realize; | ||
| 4798 | dc->vmsd = &vmstate_aspeed_rtc; | ||
| 4799 | - dc->reset = aspeed_rtc_reset; | ||
| 4800 | + device_class_set_legacy_reset(dc, aspeed_rtc_reset); | ||
| 4801 | } | ||
| 4802 | |||
| 4803 | static const TypeInfo aspeed_rtc_info = { | ||
| 4804 | diff --git a/hw/rtc/ds1338.c b/hw/rtc/ds1338.c | ||
| 4805 | index XXXXXXX..XXXXXXX 100644 | ||
| 4806 | --- a/hw/rtc/ds1338.c | ||
| 4807 | +++ b/hw/rtc/ds1338.c | ||
| 4808 | @@ -XXX,XX +XXX,XX @@ static void ds1338_class_init(ObjectClass *klass, void *data) | ||
| 4809 | k->event = ds1338_event; | ||
| 4810 | k->recv = ds1338_recv; | ||
| 4811 | k->send = ds1338_send; | ||
| 4812 | - dc->reset = ds1338_reset; | ||
| 4813 | + device_class_set_legacy_reset(dc, ds1338_reset); | ||
| 4814 | dc->vmsd = &vmstate_ds1338; | ||
| 4815 | } | ||
| 4816 | |||
| 4817 | diff --git a/hw/rtc/exynos4210_rtc.c b/hw/rtc/exynos4210_rtc.c | ||
| 4818 | index XXXXXXX..XXXXXXX 100644 | ||
| 4819 | --- a/hw/rtc/exynos4210_rtc.c | ||
| 4820 | +++ b/hw/rtc/exynos4210_rtc.c | ||
| 4821 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_rtc_class_init(ObjectClass *klass, void *data) | ||
| 4822 | { | ||
| 4823 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 4824 | |||
| 4825 | - dc->reset = exynos4210_rtc_reset; | ||
| 4826 | + device_class_set_legacy_reset(dc, exynos4210_rtc_reset); | ||
| 4827 | dc->vmsd = &vmstate_exynos4210_rtc_state; | ||
| 4828 | } | ||
| 4829 | |||
| 4830 | diff --git a/hw/rtc/goldfish_rtc.c b/hw/rtc/goldfish_rtc.c | ||
| 4831 | index XXXXXXX..XXXXXXX 100644 | ||
| 4832 | --- a/hw/rtc/goldfish_rtc.c | ||
| 4833 | +++ b/hw/rtc/goldfish_rtc.c | ||
| 4834 | @@ -XXX,XX +XXX,XX @@ static void goldfish_rtc_class_init(ObjectClass *klass, void *data) | ||
| 4835 | |||
| 4836 | device_class_set_props(dc, goldfish_rtc_properties); | ||
| 4837 | dc->realize = goldfish_rtc_realize; | ||
| 4838 | - dc->reset = goldfish_rtc_reset; | ||
| 4839 | + device_class_set_legacy_reset(dc, goldfish_rtc_reset); | ||
| 4840 | dc->vmsd = &goldfish_rtc_vmstate; | ||
| 4841 | } | ||
| 4842 | |||
| 4843 | diff --git a/hw/rtc/ls7a_rtc.c b/hw/rtc/ls7a_rtc.c | ||
| 4844 | index XXXXXXX..XXXXXXX 100644 | ||
| 4845 | --- a/hw/rtc/ls7a_rtc.c | ||
| 4846 | +++ b/hw/rtc/ls7a_rtc.c | ||
| 4847 | @@ -XXX,XX +XXX,XX @@ static void ls7a_rtc_class_init(ObjectClass *klass, void *data) | ||
| 4848 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 4849 | dc->vmsd = &vmstate_ls7a_rtc; | ||
| 4850 | dc->realize = ls7a_rtc_realize; | ||
| 4851 | - dc->reset = ls7a_rtc_reset; | ||
| 4852 | + device_class_set_legacy_reset(dc, ls7a_rtc_reset); | ||
| 4853 | dc->desc = "ls7a rtc"; | ||
| 4854 | } | ||
| 4855 | |||
| 4856 | diff --git a/hw/rtc/m48t59-isa.c b/hw/rtc/m48t59-isa.c | ||
| 4857 | index XXXXXXX..XXXXXXX 100644 | ||
| 4858 | --- a/hw/rtc/m48t59-isa.c | ||
| 4859 | +++ b/hw/rtc/m48t59-isa.c | ||
| 4860 | @@ -XXX,XX +XXX,XX @@ static void m48txx_isa_class_init(ObjectClass *klass, void *data) | ||
| 4861 | NvramClass *nc = NVRAM_CLASS(klass); | ||
| 4862 | |||
| 4863 | dc->realize = m48t59_isa_realize; | ||
| 4864 | - dc->reset = m48t59_reset_isa; | ||
| 4865 | + device_class_set_legacy_reset(dc, m48t59_reset_isa); | ||
| 4866 | device_class_set_props(dc, m48t59_isa_properties); | ||
| 4867 | nc->read = m48txx_isa_read; | ||
| 4868 | nc->write = m48txx_isa_write; | ||
| 4869 | diff --git a/hw/rtc/m48t59.c b/hw/rtc/m48t59.c | ||
| 4870 | index XXXXXXX..XXXXXXX 100644 | ||
| 4871 | --- a/hw/rtc/m48t59.c | ||
| 4872 | +++ b/hw/rtc/m48t59.c | ||
| 4873 | @@ -XXX,XX +XXX,XX @@ static void m48txx_sysbus_class_init(ObjectClass *klass, void *data) | ||
| 4874 | NvramClass *nc = NVRAM_CLASS(klass); | ||
| 4875 | |||
| 4876 | dc->realize = m48t59_realize; | ||
| 4877 | - dc->reset = m48t59_reset_sysbus; | ||
| 4878 | + device_class_set_legacy_reset(dc, m48t59_reset_sysbus); | ||
| 4879 | device_class_set_props(dc, m48t59_sysbus_properties); | ||
| 4880 | dc->vmsd = &vmstate_m48t59; | ||
| 4881 | nc->read = m48txx_sysbus_read; | ||
| 4882 | diff --git a/hw/rtc/xlnx-zynqmp-rtc.c b/hw/rtc/xlnx-zynqmp-rtc.c | ||
| 4883 | index XXXXXXX..XXXXXXX 100644 | ||
| 4884 | --- a/hw/rtc/xlnx-zynqmp-rtc.c | ||
| 4885 | +++ b/hw/rtc/xlnx-zynqmp-rtc.c | ||
| 4886 | @@ -XXX,XX +XXX,XX @@ static void rtc_class_init(ObjectClass *klass, void *data) | ||
| 4887 | { | ||
| 4888 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 4889 | |||
| 4890 | - dc->reset = rtc_reset; | ||
| 4891 | + device_class_set_legacy_reset(dc, rtc_reset); | ||
| 4892 | dc->vmsd = &vmstate_rtc; | ||
| 4893 | } | ||
| 4894 | |||
| 4895 | diff --git a/hw/s390x/event-facility.c b/hw/s390x/event-facility.c | ||
| 4896 | index XXXXXXX..XXXXXXX 100644 | ||
| 4897 | --- a/hw/s390x/event-facility.c | ||
| 4898 | +++ b/hw/s390x/event-facility.c | ||
| 4899 | @@ -XXX,XX +XXX,XX @@ static void init_event_facility_class(ObjectClass *klass, void *data) | ||
| 4900 | SCLPEventFacilityClass *k = EVENT_FACILITY_CLASS(dc); | ||
| 4901 | |||
| 4902 | dc->realize = realize_event_facility; | ||
| 4903 | - dc->reset = reset_event_facility; | ||
| 4904 | + device_class_set_legacy_reset(dc, reset_event_facility); | ||
| 4905 | dc->vmsd = &vmstate_event_facility; | ||
| 4906 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 4907 | k->command_handler = command_handler; | ||
| 4908 | diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c | ||
| 4909 | index XXXXXXX..XXXXXXX 100644 | ||
| 4910 | --- a/hw/s390x/ipl.c | ||
| 4911 | +++ b/hw/s390x/ipl.c | ||
| 4912 | @@ -XXX,XX +XXX,XX @@ static void s390_ipl_class_init(ObjectClass *klass, void *data) | ||
| 4913 | |||
| 4914 | dc->realize = s390_ipl_realize; | ||
| 4915 | device_class_set_props(dc, s390_ipl_properties); | ||
| 4916 | - dc->reset = s390_ipl_reset; | ||
| 4917 | + device_class_set_legacy_reset(dc, s390_ipl_reset); | ||
| 4918 | dc->vmsd = &vmstate_ipl; | ||
| 4919 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 4920 | /* Reason: Loads the ROMs and thus can only be used one time - internally */ | ||
| 4921 | diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c | ||
| 4922 | index XXXXXXX..XXXXXXX 100644 | ||
| 4923 | --- a/hw/s390x/s390-pci-bus.c | ||
| 4924 | +++ b/hw/s390x/s390-pci-bus.c | ||
| 4925 | @@ -XXX,XX +XXX,XX @@ static void s390_pcihost_class_init(ObjectClass *klass, void *data) | ||
| 4926 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 4927 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); | ||
| 4928 | |||
| 4929 | - dc->reset = s390_pcihost_reset; | ||
| 4930 | + device_class_set_legacy_reset(dc, s390_pcihost_reset); | ||
| 4931 | dc->realize = s390_pcihost_realize; | ||
| 4932 | dc->unrealize = s390_pcihost_unrealize; | ||
| 4933 | hc->pre_plug = s390_pcihost_pre_plug; | ||
| 4934 | @@ -XXX,XX +XXX,XX @@ static void s390_pci_device_class_init(ObjectClass *klass, void *data) | ||
| 4935 | |||
| 4936 | dc->desc = "zpci device"; | ||
| 4937 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 4938 | - dc->reset = s390_pci_device_reset; | ||
| 4939 | + device_class_set_legacy_reset(dc, s390_pci_device_reset); | ||
| 4940 | dc->bus_type = TYPE_S390_PCI_BUS; | ||
| 4941 | dc->realize = s390_pci_device_realize; | ||
| 4942 | device_class_set_props(dc, s390_pci_device_properties); | ||
| 4943 | diff --git a/hw/s390x/sclpquiesce.c b/hw/s390x/sclpquiesce.c | ||
| 4944 | index XXXXXXX..XXXXXXX 100644 | ||
| 4945 | --- a/hw/s390x/sclpquiesce.c | ||
| 4946 | +++ b/hw/s390x/sclpquiesce.c | ||
| 4947 | @@ -XXX,XX +XXX,XX @@ static void quiesce_class_init(ObjectClass *klass, void *data) | ||
| 4948 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 4949 | SCLPEventClass *k = SCLP_EVENT_CLASS(klass); | ||
| 4950 | |||
| 4951 | - dc->reset = quiesce_reset; | ||
| 4952 | + device_class_set_legacy_reset(dc, quiesce_reset); | ||
| 4953 | dc->vmsd = &vmstate_sclpquiesce; | ||
| 4954 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 4955 | /* | ||
| 4956 | diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c | ||
| 4957 | index XXXXXXX..XXXXXXX 100644 | ||
| 4958 | --- a/hw/scsi/esp-pci.c | ||
| 4959 | +++ b/hw/scsi/esp-pci.c | ||
| 4960 | @@ -XXX,XX +XXX,XX @@ static void esp_pci_class_init(ObjectClass *klass, void *data) | ||
| 4961 | k->class_id = PCI_CLASS_STORAGE_SCSI; | ||
| 4962 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | ||
| 4963 | dc->desc = "AMD Am53c974 PCscsi-PCI SCSI adapter"; | ||
| 4964 | - dc->reset = esp_pci_hard_reset; | ||
| 4965 | + device_class_set_legacy_reset(dc, esp_pci_hard_reset); | ||
| 4966 | dc->vmsd = &vmstate_esp_pci_scsi; | ||
| 4967 | } | ||
| 4968 | |||
| 4969 | diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c | ||
| 4970 | index XXXXXXX..XXXXXXX 100644 | ||
| 4971 | --- a/hw/scsi/esp.c | ||
| 4972 | +++ b/hw/scsi/esp.c | ||
| 4973 | @@ -XXX,XX +XXX,XX @@ static void sysbus_esp_class_init(ObjectClass *klass, void *data) | ||
| 4974 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 4975 | |||
| 4976 | dc->realize = sysbus_esp_realize; | ||
| 4977 | - dc->reset = sysbus_esp_hard_reset; | ||
| 4978 | + device_class_set_legacy_reset(dc, sysbus_esp_hard_reset); | ||
| 4979 | dc->vmsd = &vmstate_sysbus_esp_scsi; | ||
| 4980 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | ||
| 4981 | } | ||
| 4982 | diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c | ||
| 4983 | index XXXXXXX..XXXXXXX 100644 | ||
| 4984 | --- a/hw/scsi/lsi53c895a.c | ||
| 4985 | +++ b/hw/scsi/lsi53c895a.c | ||
| 4986 | @@ -XXX,XX +XXX,XX @@ static void lsi_class_init(ObjectClass *klass, void *data) | ||
| 4987 | k->device_id = PCI_DEVICE_ID_LSI_53C895A; | ||
| 4988 | k->class_id = PCI_CLASS_STORAGE_SCSI; | ||
| 4989 | k->subsystem_id = 0x1000; | ||
| 4990 | - dc->reset = lsi_scsi_reset; | ||
| 4991 | + device_class_set_legacy_reset(dc, lsi_scsi_reset); | ||
| 4992 | dc->vmsd = &vmstate_lsi_scsi; | ||
| 4993 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | ||
| 4994 | } | ||
| 4995 | diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c | ||
| 4996 | index XXXXXXX..XXXXXXX 100644 | ||
| 4997 | --- a/hw/scsi/megasas.c | ||
| 4998 | +++ b/hw/scsi/megasas.c | ||
| 4999 | @@ -XXX,XX +XXX,XX @@ static void megasas_class_init(ObjectClass *oc, void *data) | ||
| 5000 | e->product_name = info->product_name; | ||
| 5001 | e->product_version = info->product_version; | ||
| 5002 | device_class_set_props(dc, info->props); | ||
| 5003 | - dc->reset = megasas_scsi_reset; | ||
| 5004 | + device_class_set_legacy_reset(dc, megasas_scsi_reset); | ||
| 5005 | dc->vmsd = info->vmsd; | ||
| 5006 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | ||
| 5007 | dc->desc = info->desc; | ||
| 5008 | diff --git a/hw/scsi/mptsas.c b/hw/scsi/mptsas.c | ||
| 5009 | index XXXXXXX..XXXXXXX 100644 | ||
| 5010 | --- a/hw/scsi/mptsas.c | ||
| 5011 | +++ b/hw/scsi/mptsas.c | ||
| 5012 | @@ -XXX,XX +XXX,XX @@ static void mptsas1068_class_init(ObjectClass *oc, void *data) | ||
| 5013 | pc->subsystem_id = 0x8000; | ||
| 5014 | pc->class_id = PCI_CLASS_STORAGE_SCSI; | ||
| 5015 | device_class_set_props(dc, mptsas_properties); | ||
| 5016 | - dc->reset = mptsas_reset; | ||
| 5017 | + device_class_set_legacy_reset(dc, mptsas_reset); | ||
| 5018 | dc->vmsd = &vmstate_mptsas; | ||
| 5019 | dc->desc = "LSI SAS 1068"; | ||
| 5020 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | ||
| 5021 | diff --git a/hw/scsi/scsi-disk.c b/hw/scsi/scsi-disk.c | ||
| 5022 | index XXXXXXX..XXXXXXX 100644 | ||
| 5023 | --- a/hw/scsi/scsi-disk.c | ||
| 5024 | +++ b/hw/scsi/scsi-disk.c | ||
| 5025 | @@ -XXX,XX +XXX,XX @@ static void scsi_disk_base_class_initfn(ObjectClass *klass, void *data) | ||
| 5026 | SCSIDiskClass *sdc = SCSI_DISK_BASE_CLASS(klass); | ||
| 5027 | |||
| 5028 | dc->fw_name = "disk"; | ||
| 5029 | - dc->reset = scsi_disk_reset; | ||
| 5030 | + device_class_set_legacy_reset(dc, scsi_disk_reset); | ||
| 5031 | sdc->dma_readv = scsi_dma_readv; | ||
| 5032 | sdc->dma_writev = scsi_dma_writev; | ||
| 5033 | sdc->need_fua_emulation = scsi_is_cmd_fua; | ||
| 5034 | diff --git a/hw/scsi/scsi-generic.c b/hw/scsi/scsi-generic.c | ||
| 5035 | index XXXXXXX..XXXXXXX 100644 | ||
| 5036 | --- a/hw/scsi/scsi-generic.c | ||
| 5037 | +++ b/hw/scsi/scsi-generic.c | ||
| 5038 | @@ -XXX,XX +XXX,XX @@ static void scsi_generic_class_initfn(ObjectClass *klass, void *data) | ||
| 5039 | sc->parse_cdb = scsi_generic_parse_cdb; | ||
| 5040 | dc->fw_name = "disk"; | ||
| 5041 | dc->desc = "pass through generic scsi device (/dev/sg*)"; | ||
| 5042 | - dc->reset = scsi_generic_reset; | ||
| 5043 | + device_class_set_legacy_reset(dc, scsi_generic_reset); | ||
| 5044 | device_class_set_props(dc, scsi_generic_properties); | ||
| 5045 | dc->vmsd = &vmstate_scsi_device; | ||
| 5046 | } | ||
| 5047 | diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c | ||
| 5048 | index XXXXXXX..XXXXXXX 100644 | ||
| 5049 | --- a/hw/scsi/vmw_pvscsi.c | ||
| 5050 | +++ b/hw/scsi/vmw_pvscsi.c | ||
| 5051 | @@ -XXX,XX +XXX,XX @@ static void pvscsi_class_init(ObjectClass *klass, void *data) | ||
| 5052 | k->subsystem_id = 0x1000; | ||
| 5053 | device_class_set_parent_realize(dc, pvscsi_realize, | ||
| 5054 | &pvs_k->parent_dc_realize); | ||
| 5055 | - dc->reset = pvscsi_reset; | ||
| 5056 | + device_class_set_legacy_reset(dc, pvscsi_reset); | ||
| 5057 | dc->vmsd = &vmstate_pvscsi; | ||
| 5058 | device_class_set_props(dc, pvscsi_properties); | ||
| 5059 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | ||
| 5060 | diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c | ||
| 5061 | index XXXXXXX..XXXXXXX 100644 | ||
| 5062 | --- a/hw/sd/allwinner-sdhost.c | ||
| 5063 | +++ b/hw/sd/allwinner-sdhost.c | ||
| 5064 | @@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_class_init(ObjectClass *klass, void *data) | ||
| 5065 | { | ||
| 5066 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5067 | |||
| 5068 | - dc->reset = allwinner_sdhost_reset; | ||
| 5069 | + device_class_set_legacy_reset(dc, allwinner_sdhost_reset); | ||
| 5070 | dc->vmsd = &vmstate_allwinner_sdhost; | ||
| 5071 | dc->realize = allwinner_sdhost_realize; | ||
| 5072 | device_class_set_props(dc, allwinner_sdhost_properties); | ||
| 5073 | diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c | ||
| 5074 | index XXXXXXX..XXXXXXX 100644 | ||
| 5075 | --- a/hw/sd/aspeed_sdhci.c | ||
| 5076 | +++ b/hw/sd/aspeed_sdhci.c | ||
| 5077 | @@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) | ||
| 5078 | DeviceClass *dc = DEVICE_CLASS(classp); | ||
| 5079 | |||
| 5080 | dc->realize = aspeed_sdhci_realize; | ||
| 5081 | - dc->reset = aspeed_sdhci_reset; | ||
| 5082 | + device_class_set_legacy_reset(dc, aspeed_sdhci_reset); | ||
| 5083 | dc->vmsd = &vmstate_aspeed_sdhci; | ||
| 5084 | device_class_set_props(dc, aspeed_sdhci_properties); | ||
| 5085 | } | ||
| 5086 | diff --git a/hw/sd/bcm2835_sdhost.c b/hw/sd/bcm2835_sdhost.c | ||
| 5087 | index XXXXXXX..XXXXXXX 100644 | ||
| 5088 | --- a/hw/sd/bcm2835_sdhost.c | ||
| 5089 | +++ b/hw/sd/bcm2835_sdhost.c | ||
| 5090 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_class_init(ObjectClass *klass, void *data) | ||
| 5091 | { | ||
| 5092 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5093 | |||
| 5094 | - dc->reset = bcm2835_sdhost_reset; | ||
| 5095 | + device_class_set_legacy_reset(dc, bcm2835_sdhost_reset); | ||
| 5096 | dc->vmsd = &vmstate_bcm2835_sdhost; | ||
| 5097 | } | ||
| 5098 | |||
| 5099 | diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c | ||
| 5100 | index XXXXXXX..XXXXXXX 100644 | ||
| 5101 | --- a/hw/sd/cadence_sdhci.c | ||
| 5102 | +++ b/hw/sd/cadence_sdhci.c | ||
| 5103 | @@ -XXX,XX +XXX,XX @@ static void cadence_sdhci_class_init(ObjectClass *classp, void *data) | ||
| 5104 | |||
| 5105 | dc->desc = "Cadence SD/SDIO/eMMC Host Controller (SD4HC)"; | ||
| 5106 | dc->realize = cadence_sdhci_realize; | ||
| 5107 | - dc->reset = cadence_sdhci_reset; | ||
| 5108 | + device_class_set_legacy_reset(dc, cadence_sdhci_reset); | ||
| 5109 | dc->vmsd = &vmstate_cadence_sdhci; | ||
| 5110 | } | ||
| 5111 | |||
| 5112 | diff --git a/hw/sd/npcm7xx_sdhci.c b/hw/sd/npcm7xx_sdhci.c | ||
| 5113 | index XXXXXXX..XXXXXXX 100644 | ||
| 5114 | --- a/hw/sd/npcm7xx_sdhci.c | ||
| 5115 | +++ b/hw/sd/npcm7xx_sdhci.c | ||
| 5116 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_sdhci_class_init(ObjectClass *classp, void *data) | ||
| 5117 | |||
| 5118 | dc->desc = "NPCM7xx SD/eMMC Host Controller"; | ||
| 5119 | dc->realize = npcm7xx_sdhci_realize; | ||
| 5120 | - dc->reset = npcm7xx_sdhci_reset; | ||
| 5121 | + device_class_set_legacy_reset(dc, npcm7xx_sdhci_reset); | ||
| 5122 | dc->vmsd = &vmstate_npcm7xx_sdhci; | ||
| 5123 | } | ||
| 5124 | |||
| 5125 | diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c | ||
| 5126 | index XXXXXXX..XXXXXXX 100644 | ||
| 5127 | --- a/hw/sd/pl181.c | ||
| 5128 | +++ b/hw/sd/pl181.c | ||
| 5129 | @@ -XXX,XX +XXX,XX @@ static void pl181_class_init(ObjectClass *klass, void *data) | ||
| 5130 | DeviceClass *k = DEVICE_CLASS(klass); | ||
| 5131 | |||
| 5132 | k->vmsd = &vmstate_pl181; | ||
| 5133 | - k->reset = pl181_reset; | ||
| 5134 | + device_class_set_legacy_reset(k, pl181_reset); | ||
| 5135 | /* Reason: output IRQs should be wired up */ | ||
| 5136 | k->user_creatable = false; | ||
| 5137 | } | ||
| 5138 | diff --git a/hw/sd/pxa2xx_mmci.c b/hw/sd/pxa2xx_mmci.c | ||
| 5139 | index XXXXXXX..XXXXXXX 100644 | ||
| 5140 | --- a/hw/sd/pxa2xx_mmci.c | ||
| 5141 | +++ b/hw/sd/pxa2xx_mmci.c | ||
| 5142 | @@ -XXX,XX +XXX,XX @@ static void pxa2xx_mmci_class_init(ObjectClass *klass, void *data) | ||
| 5143 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5144 | |||
| 5145 | dc->vmsd = &vmstate_pxa2xx_mmci; | ||
| 5146 | - dc->reset = pxa2xx_mmci_reset; | ||
| 5147 | + device_class_set_legacy_reset(dc, pxa2xx_mmci_reset); | ||
| 5148 | } | ||
| 5149 | |||
| 5150 | static void pxa2xx_mmci_bus_class_init(ObjectClass *klass, void *data) | ||
| 5151 | diff --git a/hw/sd/sd.c b/hw/sd/sd.c | ||
| 5152 | index XXXXXXX..XXXXXXX 100644 | ||
| 5153 | --- a/hw/sd/sd.c | ||
| 5154 | +++ b/hw/sd/sd.c | ||
| 5155 | @@ -XXX,XX +XXX,XX @@ static void sdmmc_common_class_init(ObjectClass *klass, void *data) | ||
| 5156 | |||
| 5157 | device_class_set_props(dc, sdmmc_common_properties); | ||
| 5158 | dc->vmsd = &sd_vmstate; | ||
| 5159 | - dc->reset = sd_reset; | ||
| 5160 | + device_class_set_legacy_reset(dc, sd_reset); | ||
| 5161 | dc->bus_type = TYPE_SD_BUS; | ||
| 5162 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | ||
| 5163 | |||
| 5164 | diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c | ||
| 5165 | index XXXXXXX..XXXXXXX 100644 | ||
| 5166 | --- a/hw/sd/sdhci.c | ||
| 5167 | +++ b/hw/sd/sdhci.c | ||
| 5168 | @@ -XXX,XX +XXX,XX @@ void sdhci_common_class_init(ObjectClass *klass, void *data) | ||
| 5169 | |||
| 5170 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | ||
| 5171 | dc->vmsd = &sdhci_vmstate; | ||
| 5172 | - dc->reset = sdhci_poweron_reset; | ||
| 5173 | + device_class_set_legacy_reset(dc, sdhci_poweron_reset); | ||
| 5174 | } | ||
| 5175 | |||
| 5176 | /* --- qdev SysBus --- */ | ||
| 5177 | diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c | ||
| 5178 | index XXXXXXX..XXXXXXX 100644 | ||
| 5179 | --- a/hw/sd/ssi-sd.c | ||
| 5180 | +++ b/hw/sd/ssi-sd.c | ||
| 5181 | @@ -XXX,XX +XXX,XX @@ static void ssi_sd_class_init(ObjectClass *klass, void *data) | ||
| 5182 | k->transfer = ssi_sd_transfer; | ||
| 5183 | k->cs_polarity = SSI_CS_LOW; | ||
| 5184 | dc->vmsd = &vmstate_ssi_sd; | ||
| 5185 | - dc->reset = ssi_sd_reset; | ||
| 5186 | + device_class_set_legacy_reset(dc, ssi_sd_reset); | ||
| 5187 | /* Reason: GPIO chip-select line should be wired up */ | ||
| 5188 | dc->user_creatable = false; | ||
| 5189 | } | ||
| 5190 | diff --git a/hw/sensor/dps310.c b/hw/sensor/dps310.c | ||
| 5191 | index XXXXXXX..XXXXXXX 100644 | ||
| 5192 | --- a/hw/sensor/dps310.c | ||
| 5193 | +++ b/hw/sensor/dps310.c | ||
| 5194 | @@ -XXX,XX +XXX,XX @@ static void dps310_class_init(ObjectClass *klass, void *data) | ||
| 5195 | k->event = dps310_event; | ||
| 5196 | k->recv = dps310_rx; | ||
| 5197 | k->send = dps310_tx; | ||
| 5198 | - dc->reset = dps310_reset; | ||
| 5199 | + device_class_set_legacy_reset(dc, dps310_reset); | ||
| 5200 | dc->vmsd = &vmstate_dps310; | ||
| 5201 | } | ||
| 5202 | |||
| 5203 | diff --git a/hw/sensor/emc141x.c b/hw/sensor/emc141x.c | ||
| 5204 | index XXXXXXX..XXXXXXX 100644 | ||
| 5205 | --- a/hw/sensor/emc141x.c | ||
| 5206 | +++ b/hw/sensor/emc141x.c | ||
| 5207 | @@ -XXX,XX +XXX,XX @@ static void emc141x_class_init(ObjectClass *klass, void *data) | ||
| 5208 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5209 | I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); | ||
| 5210 | |||
| 5211 | - dc->reset = emc141x_reset; | ||
| 5212 | + device_class_set_legacy_reset(dc, emc141x_reset); | ||
| 5213 | k->event = emc141x_event; | ||
| 5214 | k->recv = emc141x_rx; | ||
| 5215 | k->send = emc141x_tx; | ||
| 5216 | diff --git a/hw/sensor/lsm303dlhc_mag.c b/hw/sensor/lsm303dlhc_mag.c | ||
| 5217 | index XXXXXXX..XXXXXXX 100644 | ||
| 5218 | --- a/hw/sensor/lsm303dlhc_mag.c | ||
| 5219 | +++ b/hw/sensor/lsm303dlhc_mag.c | ||
| 5220 | @@ -XXX,XX +XXX,XX @@ static void lsm303dlhc_mag_class_init(ObjectClass *klass, void *data) | ||
| 5221 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5222 | I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); | ||
| 5223 | |||
| 5224 | - dc->reset = lsm303dlhc_mag_reset; | ||
| 5225 | + device_class_set_legacy_reset(dc, lsm303dlhc_mag_reset); | ||
| 5226 | dc->vmsd = &vmstate_lsm303dlhc_mag; | ||
| 5227 | k->event = lsm303dlhc_mag_event; | ||
| 5228 | k->recv = lsm303dlhc_mag_recv; | ||
| 5229 | diff --git a/hw/sparc/sun4m_iommu.c b/hw/sparc/sun4m_iommu.c | ||
| 5230 | index XXXXXXX..XXXXXXX 100644 | ||
| 5231 | --- a/hw/sparc/sun4m_iommu.c | ||
| 5232 | +++ b/hw/sparc/sun4m_iommu.c | ||
| 5233 | @@ -XXX,XX +XXX,XX @@ static void iommu_class_init(ObjectClass *klass, void *data) | ||
| 5234 | { | ||
| 5235 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5236 | |||
| 5237 | - dc->reset = iommu_reset; | ||
| 5238 | + device_class_set_legacy_reset(dc, iommu_reset); | ||
| 5239 | dc->vmsd = &vmstate_iommu; | ||
| 5240 | device_class_set_props(dc, iommu_properties); | ||
| 5241 | } | ||
| 5242 | diff --git a/hw/sparc64/sun4u_iommu.c b/hw/sparc64/sun4u_iommu.c | ||
| 5243 | index XXXXXXX..XXXXXXX 100644 | ||
| 5244 | --- a/hw/sparc64/sun4u_iommu.c | ||
| 5245 | +++ b/hw/sparc64/sun4u_iommu.c | ||
| 5246 | @@ -XXX,XX +XXX,XX @@ static void iommu_class_init(ObjectClass *klass, void *data) | ||
| 5247 | { | ||
| 5248 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5249 | |||
| 5250 | - dc->reset = iommu_reset; | ||
| 5251 | + device_class_set_legacy_reset(dc, iommu_reset); | ||
| 5252 | } | ||
| 5253 | |||
| 5254 | static const TypeInfo iommu_info = { | ||
| 5255 | diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c | ||
| 5256 | index XXXXXXX..XXXXXXX 100644 | ||
| 5257 | --- a/hw/ssi/aspeed_smc.c | ||
| 5258 | +++ b/hw/ssi/aspeed_smc.c | ||
| 5259 | @@ -XXX,XX +XXX,XX @@ static void aspeed_smc_class_init(ObjectClass *klass, void *data) | ||
| 5260 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5261 | |||
| 5262 | dc->realize = aspeed_smc_realize; | ||
| 5263 | - dc->reset = aspeed_smc_reset; | ||
| 5264 | + device_class_set_legacy_reset(dc, aspeed_smc_reset); | ||
| 5265 | device_class_set_props(dc, aspeed_smc_properties); | ||
| 5266 | dc->vmsd = &vmstate_aspeed_smc; | ||
| 5267 | } | ||
| 5268 | diff --git a/hw/ssi/bcm2835_spi.c b/hw/ssi/bcm2835_spi.c | ||
| 5269 | index XXXXXXX..XXXXXXX 100644 | ||
| 5270 | --- a/hw/ssi/bcm2835_spi.c | ||
| 5271 | +++ b/hw/ssi/bcm2835_spi.c | ||
| 5272 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_spi_class_init(ObjectClass *klass, void *data) | ||
| 5273 | { | ||
| 5274 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5275 | |||
| 5276 | - dc->reset = bcm2835_spi_reset; | ||
| 5277 | + device_class_set_legacy_reset(dc, bcm2835_spi_reset); | ||
| 5278 | dc->realize = bcm2835_spi_realize; | ||
| 5279 | dc->vmsd = &vmstate_bcm2835_spi; | ||
| 5280 | } | ||
| 5281 | diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c | ||
| 5282 | index XXXXXXX..XXXXXXX 100644 | ||
| 5283 | --- a/hw/ssi/ibex_spi_host.c | ||
| 5284 | +++ b/hw/ssi/ibex_spi_host.c | ||
| 5285 | @@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_class_init(ObjectClass *klass, void *data) | ||
| 5286 | { | ||
| 5287 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5288 | dc->realize = ibex_spi_host_realize; | ||
| 5289 | - dc->reset = ibex_spi_host_reset; | ||
| 5290 | + device_class_set_legacy_reset(dc, ibex_spi_host_reset); | ||
| 5291 | dc->vmsd = &vmstate_ibex; | ||
| 5292 | device_class_set_props(dc, ibex_spi_properties); | ||
| 5293 | } | ||
| 5294 | diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c | ||
| 5295 | index XXXXXXX..XXXXXXX 100644 | ||
| 5296 | --- a/hw/ssi/imx_spi.c | ||
| 5297 | +++ b/hw/ssi/imx_spi.c | ||
| 5298 | @@ -XXX,XX +XXX,XX @@ static void imx_spi_class_init(ObjectClass *klass, void *data) | ||
| 5299 | |||
| 5300 | dc->realize = imx_spi_realize; | ||
| 5301 | dc->vmsd = &vmstate_imx_spi; | ||
| 5302 | - dc->reset = imx_spi_reset; | ||
| 5303 | + device_class_set_legacy_reset(dc, imx_spi_reset); | ||
| 5304 | dc->desc = "i.MX SPI Controller"; | ||
| 5305 | } | ||
| 5306 | |||
| 5307 | diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c | ||
| 5308 | index XXXXXXX..XXXXXXX 100644 | ||
| 5309 | --- a/hw/ssi/mss-spi.c | ||
| 5310 | +++ b/hw/ssi/mss-spi.c | ||
| 5311 | @@ -XXX,XX +XXX,XX @@ static void mss_spi_class_init(ObjectClass *klass, void *data) | ||
| 5312 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5313 | |||
| 5314 | dc->realize = mss_spi_realize; | ||
| 5315 | - dc->reset = mss_spi_reset; | ||
| 5316 | + device_class_set_legacy_reset(dc, mss_spi_reset); | ||
| 5317 | dc->vmsd = &vmstate_mss_spi; | ||
| 5318 | } | ||
| 5319 | |||
| 5320 | diff --git a/hw/ssi/pl022.c b/hw/ssi/pl022.c | ||
| 5321 | index XXXXXXX..XXXXXXX 100644 | ||
| 5322 | --- a/hw/ssi/pl022.c | ||
| 5323 | +++ b/hw/ssi/pl022.c | ||
| 5324 | @@ -XXX,XX +XXX,XX @@ static void pl022_class_init(ObjectClass *klass, void *data) | ||
| 5325 | { | ||
| 5326 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5327 | |||
| 5328 | - dc->reset = pl022_reset; | ||
| 5329 | + device_class_set_legacy_reset(dc, pl022_reset); | ||
| 5330 | dc->vmsd = &vmstate_pl022; | ||
| 5331 | dc->realize = pl022_realize; | ||
| 5332 | } | ||
| 5333 | diff --git a/hw/ssi/pnv_spi.c b/hw/ssi/pnv_spi.c | ||
| 5334 | index XXXXXXX..XXXXXXX 100644 | ||
| 5335 | --- a/hw/ssi/pnv_spi.c | ||
| 5336 | +++ b/hw/ssi/pnv_spi.c | ||
| 5337 | @@ -XXX,XX +XXX,XX @@ static void pnv_spi_class_init(ObjectClass *klass, void *data) | ||
| 5338 | |||
| 5339 | dc->desc = "PowerNV SPI"; | ||
| 5340 | dc->realize = pnv_spi_realize; | ||
| 5341 | - dc->reset = do_reset; | ||
| 5342 | + device_class_set_legacy_reset(dc, do_reset); | ||
| 5343 | device_class_set_props(dc, pnv_spi_properties); | ||
| 5344 | } | ||
| 5345 | |||
| 5346 | diff --git a/hw/ssi/sifive_spi.c b/hw/ssi/sifive_spi.c | ||
| 5347 | index XXXXXXX..XXXXXXX 100644 | ||
| 5348 | --- a/hw/ssi/sifive_spi.c | ||
| 5349 | +++ b/hw/ssi/sifive_spi.c | ||
| 5350 | @@ -XXX,XX +XXX,XX @@ static void sifive_spi_class_init(ObjectClass *klass, void *data) | ||
| 5351 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5352 | |||
| 5353 | device_class_set_props(dc, sifive_spi_properties); | ||
| 5354 | - dc->reset = sifive_spi_reset; | ||
| 5355 | + device_class_set_legacy_reset(dc, sifive_spi_reset); | ||
| 5356 | dc->realize = sifive_spi_realize; | ||
| 5357 | } | ||
| 5358 | |||
| 5359 | diff --git a/hw/ssi/stm32f2xx_spi.c b/hw/ssi/stm32f2xx_spi.c | ||
| 5360 | index XXXXXXX..XXXXXXX 100644 | ||
| 5361 | --- a/hw/ssi/stm32f2xx_spi.c | ||
| 5362 | +++ b/hw/ssi/stm32f2xx_spi.c | ||
| 5363 | @@ -XXX,XX +XXX,XX @@ static void stm32f2xx_spi_class_init(ObjectClass *klass, void *data) | ||
| 5364 | { | ||
| 5365 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5366 | |||
| 5367 | - dc->reset = stm32f2xx_spi_reset; | ||
| 5368 | + device_class_set_legacy_reset(dc, stm32f2xx_spi_reset); | ||
| 5369 | dc->vmsd = &vmstate_stm32f2xx_spi; | ||
| 5370 | } | ||
| 5371 | |||
| 5372 | diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c | ||
| 5373 | index XXXXXXX..XXXXXXX 100644 | ||
| 5374 | --- a/hw/ssi/xilinx_spi.c | ||
| 5375 | +++ b/hw/ssi/xilinx_spi.c | ||
| 5376 | @@ -XXX,XX +XXX,XX @@ static void xilinx_spi_class_init(ObjectClass *klass, void *data) | ||
| 5377 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5378 | |||
| 5379 | dc->realize = xilinx_spi_realize; | ||
| 5380 | - dc->reset = xlx_spi_reset; | ||
| 5381 | + device_class_set_legacy_reset(dc, xlx_spi_reset); | ||
| 5382 | device_class_set_props(dc, xilinx_spi_properties); | ||
| 5383 | dc->vmsd = &vmstate_xilinx_spi; | ||
| 5384 | } | ||
| 5385 | diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c | ||
| 5386 | index XXXXXXX..XXXXXXX 100644 | ||
| 5387 | --- a/hw/ssi/xilinx_spips.c | ||
| 5388 | +++ b/hw/ssi/xilinx_spips.c | ||
| 5389 | @@ -XXX,XX +XXX,XX @@ static void xilinx_spips_class_init(ObjectClass *klass, void *data) | ||
| 5390 | XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); | ||
| 5391 | |||
| 5392 | dc->realize = xilinx_spips_realize; | ||
| 5393 | - dc->reset = xilinx_spips_reset; | ||
| 5394 | + device_class_set_legacy_reset(dc, xilinx_spips_reset); | ||
| 5395 | device_class_set_props(dc, xilinx_spips_properties); | ||
| 5396 | dc->vmsd = &vmstate_xilinx_spips; | ||
| 5397 | |||
| 5398 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_qspips_class_init(ObjectClass *klass, void * data) | ||
| 5399 | XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); | ||
| 5400 | |||
| 5401 | dc->realize = xlnx_zynqmp_qspips_realize; | ||
| 5402 | - dc->reset = xlnx_zynqmp_qspips_reset; | ||
| 5403 | + device_class_set_legacy_reset(dc, xlnx_zynqmp_qspips_reset); | ||
| 5404 | dc->vmsd = &vmstate_xlnx_zynqmp_qspips; | ||
| 5405 | device_class_set_props(dc, xilinx_zynqmp_qspips_properties); | ||
| 5406 | xsc->reg_ops = &xlnx_zynqmp_qspips_ops; | ||
| 5407 | diff --git a/hw/ssi/xlnx-versal-ospi.c b/hw/ssi/xlnx-versal-ospi.c | ||
| 5408 | index XXXXXXX..XXXXXXX 100644 | ||
| 5409 | --- a/hw/ssi/xlnx-versal-ospi.c | ||
| 5410 | +++ b/hw/ssi/xlnx-versal-ospi.c | ||
| 5411 | @@ -XXX,XX +XXX,XX @@ static void xlnx_versal_ospi_class_init(ObjectClass *klass, void *data) | ||
| 5412 | { | ||
| 5413 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5414 | |||
| 5415 | - dc->reset = xlnx_versal_ospi_reset; | ||
| 5416 | + device_class_set_legacy_reset(dc, xlnx_versal_ospi_reset); | ||
| 5417 | dc->realize = xlnx_versal_ospi_realize; | ||
| 5418 | dc->vmsd = &vmstate_xlnx_versal_ospi; | ||
| 5419 | device_class_set_props(dc, xlnx_versal_ospi_properties); | ||
| 5420 | diff --git a/hw/timer/a9gtimer.c b/hw/timer/a9gtimer.c | ||
| 5421 | index XXXXXXX..XXXXXXX 100644 | ||
| 5422 | --- a/hw/timer/a9gtimer.c | ||
| 5423 | +++ b/hw/timer/a9gtimer.c | ||
| 5424 | @@ -XXX,XX +XXX,XX @@ static void a9_gtimer_class_init(ObjectClass *klass, void *data) | ||
| 5425 | |||
| 5426 | dc->realize = a9_gtimer_realize; | ||
| 5427 | dc->vmsd = &vmstate_a9_gtimer; | ||
| 5428 | - dc->reset = a9_gtimer_reset; | ||
| 5429 | + device_class_set_legacy_reset(dc, a9_gtimer_reset); | ||
| 5430 | device_class_set_props(dc, a9_gtimer_properties); | ||
| 5431 | } | ||
| 5432 | |||
| 5433 | diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c | ||
| 5434 | index XXXXXXX..XXXXXXX 100644 | ||
| 5435 | --- a/hw/timer/allwinner-a10-pit.c | ||
| 5436 | +++ b/hw/timer/allwinner-a10-pit.c | ||
| 5437 | @@ -XXX,XX +XXX,XX @@ static void a10_pit_class_init(ObjectClass *klass, void *data) | ||
| 5438 | { | ||
| 5439 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5440 | |||
| 5441 | - dc->reset = a10_pit_reset; | ||
| 5442 | + device_class_set_legacy_reset(dc, a10_pit_reset); | ||
| 5443 | device_class_set_props(dc, a10_pit_properties); | ||
| 5444 | dc->desc = "allwinner a10 timer"; | ||
| 5445 | dc->vmsd = &vmstate_a10_pit; | ||
| 5446 | diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c | ||
| 5447 | index XXXXXXX..XXXXXXX 100644 | ||
| 5448 | --- a/hw/timer/arm_mptimer.c | ||
| 5449 | +++ b/hw/timer/arm_mptimer.c | ||
| 5450 | @@ -XXX,XX +XXX,XX @@ static void arm_mptimer_class_init(ObjectClass *klass, void *data) | ||
| 5451 | |||
| 5452 | dc->realize = arm_mptimer_realize; | ||
| 5453 | dc->vmsd = &vmstate_arm_mptimer; | ||
| 5454 | - dc->reset = arm_mptimer_reset; | ||
| 5455 | + device_class_set_legacy_reset(dc, arm_mptimer_reset); | ||
| 5456 | device_class_set_props(dc, arm_mptimer_properties); | ||
| 5457 | } | ||
| 5458 | |||
| 5459 | diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c | ||
| 5460 | index XXXXXXX..XXXXXXX 100644 | ||
| 5461 | --- a/hw/timer/armv7m_systick.c | ||
| 5462 | +++ b/hw/timer/armv7m_systick.c | ||
| 5463 | @@ -XXX,XX +XXX,XX @@ static void systick_class_init(ObjectClass *klass, void *data) | ||
| 5464 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5465 | |||
| 5466 | dc->vmsd = &vmstate_systick; | ||
| 5467 | - dc->reset = systick_reset; | ||
| 5468 | + device_class_set_legacy_reset(dc, systick_reset); | ||
| 5469 | dc->realize = systick_realize; | ||
| 5470 | } | ||
| 5471 | |||
| 5472 | diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c | ||
| 5473 | index XXXXXXX..XXXXXXX 100644 | ||
| 5474 | --- a/hw/timer/aspeed_timer.c | ||
| 5475 | +++ b/hw/timer/aspeed_timer.c | ||
| 5476 | @@ -XXX,XX +XXX,XX @@ static void timer_class_init(ObjectClass *klass, void *data) | ||
| 5477 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5478 | |||
| 5479 | dc->realize = aspeed_timer_realize; | ||
| 5480 | - dc->reset = aspeed_timer_reset; | ||
| 5481 | + device_class_set_legacy_reset(dc, aspeed_timer_reset); | ||
| 5482 | dc->desc = "ASPEED Timer"; | ||
| 5483 | dc->vmsd = &vmstate_aspeed_timer_state; | ||
| 5484 | device_class_set_props(dc, aspeed_timer_properties); | ||
| 5485 | diff --git a/hw/timer/avr_timer16.c b/hw/timer/avr_timer16.c | ||
| 5486 | index XXXXXXX..XXXXXXX 100644 | ||
| 5487 | --- a/hw/timer/avr_timer16.c | ||
| 5488 | +++ b/hw/timer/avr_timer16.c | ||
| 5489 | @@ -XXX,XX +XXX,XX @@ static void avr_timer16_class_init(ObjectClass *klass, void *data) | ||
| 5490 | { | ||
| 5491 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5492 | |||
| 5493 | - dc->reset = avr_timer16_reset; | ||
| 5494 | + device_class_set_legacy_reset(dc, avr_timer16_reset); | ||
| 5495 | dc->realize = avr_timer16_realize; | ||
| 5496 | device_class_set_props(dc, avr_timer16_properties); | ||
| 5497 | } | ||
| 5498 | diff --git a/hw/timer/bcm2835_systmr.c b/hw/timer/bcm2835_systmr.c | ||
| 5499 | index XXXXXXX..XXXXXXX 100644 | ||
| 5500 | --- a/hw/timer/bcm2835_systmr.c | ||
| 5501 | +++ b/hw/timer/bcm2835_systmr.c | ||
| 5502 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_systmr_class_init(ObjectClass *klass, void *data) | ||
| 5503 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5504 | |||
| 5505 | dc->realize = bcm2835_systmr_realize; | ||
| 5506 | - dc->reset = bcm2835_systmr_reset; | ||
| 5507 | + device_class_set_legacy_reset(dc, bcm2835_systmr_reset); | ||
| 5508 | dc->vmsd = &bcm2835_systmr_vmstate; | ||
| 5509 | } | ||
| 5510 | |||
| 5511 | diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c | ||
| 5512 | index XXXXXXX..XXXXXXX 100644 | ||
| 5513 | --- a/hw/timer/cmsdk-apb-dualtimer.c | ||
| 5514 | +++ b/hw/timer/cmsdk-apb-dualtimer.c | ||
| 5515 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_class_init(ObjectClass *klass, void *data) | ||
| 5516 | |||
| 5517 | dc->realize = cmsdk_apb_dualtimer_realize; | ||
| 5518 | dc->vmsd = &cmsdk_apb_dualtimer_vmstate; | ||
| 5519 | - dc->reset = cmsdk_apb_dualtimer_reset; | ||
| 5520 | + device_class_set_legacy_reset(dc, cmsdk_apb_dualtimer_reset); | ||
| 5521 | } | ||
| 5522 | |||
| 5523 | static const TypeInfo cmsdk_apb_dualtimer_info = { | ||
| 5524 | diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c | ||
| 5525 | index XXXXXXX..XXXXXXX 100644 | ||
| 5526 | --- a/hw/timer/cmsdk-apb-timer.c | ||
| 5527 | +++ b/hw/timer/cmsdk-apb-timer.c | ||
| 5528 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data) | ||
| 5529 | |||
| 5530 | dc->realize = cmsdk_apb_timer_realize; | ||
| 5531 | dc->vmsd = &cmsdk_apb_timer_vmstate; | ||
| 5532 | - dc->reset = cmsdk_apb_timer_reset; | ||
| 5533 | + device_class_set_legacy_reset(dc, cmsdk_apb_timer_reset); | ||
| 5534 | } | ||
| 5535 | |||
| 5536 | static const TypeInfo cmsdk_apb_timer_info = { | ||
| 5537 | diff --git a/hw/timer/digic-timer.c b/hw/timer/digic-timer.c | ||
| 5538 | index XXXXXXX..XXXXXXX 100644 | ||
| 5539 | --- a/hw/timer/digic-timer.c | ||
| 5540 | +++ b/hw/timer/digic-timer.c | ||
| 5541 | @@ -XXX,XX +XXX,XX @@ static void digic_timer_class_init(ObjectClass *klass, void *class_data) | ||
| 5542 | { | ||
| 5543 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5544 | |||
| 5545 | - dc->reset = digic_timer_reset; | ||
| 5546 | + device_class_set_legacy_reset(dc, digic_timer_reset); | ||
| 5547 | dc->vmsd = &vmstate_digic_timer; | ||
| 5548 | } | ||
| 5549 | |||
| 5550 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c | ||
| 5551 | index XXXXXXX..XXXXXXX 100644 | ||
| 5552 | --- a/hw/timer/exynos4210_mct.c | ||
| 5553 | +++ b/hw/timer/exynos4210_mct.c | ||
| 5554 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_class_init(ObjectClass *klass, void *data) | ||
| 5555 | { | ||
| 5556 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5557 | |||
| 5558 | - dc->reset = exynos4210_mct_reset; | ||
| 5559 | + device_class_set_legacy_reset(dc, exynos4210_mct_reset); | ||
| 5560 | dc->vmsd = &vmstate_exynos4210_mct_state; | ||
| 5561 | } | ||
| 5562 | |||
| 5563 | diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c | ||
| 5564 | index XXXXXXX..XXXXXXX 100644 | ||
| 5565 | --- a/hw/timer/exynos4210_pwm.c | ||
| 5566 | +++ b/hw/timer/exynos4210_pwm.c | ||
| 5567 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_class_init(ObjectClass *klass, void *data) | ||
| 5568 | { | ||
| 5569 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5570 | |||
| 5571 | - dc->reset = exynos4210_pwm_reset; | ||
| 5572 | + device_class_set_legacy_reset(dc, exynos4210_pwm_reset); | ||
| 5573 | dc->vmsd = &vmstate_exynos4210_pwm_state; | ||
| 5574 | } | ||
| 5575 | |||
| 5576 | diff --git a/hw/timer/grlib_gptimer.c b/hw/timer/grlib_gptimer.c | ||
| 5577 | index XXXXXXX..XXXXXXX 100644 | ||
| 5578 | --- a/hw/timer/grlib_gptimer.c | ||
| 5579 | +++ b/hw/timer/grlib_gptimer.c | ||
| 5580 | @@ -XXX,XX +XXX,XX @@ static void grlib_gptimer_class_init(ObjectClass *klass, void *data) | ||
| 5581 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5582 | |||
| 5583 | dc->realize = grlib_gptimer_realize; | ||
| 5584 | - dc->reset = grlib_gptimer_reset; | ||
| 5585 | + device_class_set_legacy_reset(dc, grlib_gptimer_reset); | ||
| 5586 | device_class_set_props(dc, grlib_gptimer_properties); | ||
| 5587 | } | ||
| 5588 | |||
| 5589 | diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c | ||
| 5590 | index XXXXXXX..XXXXXXX 100644 | ||
| 5591 | --- a/hw/timer/hpet.c | ||
| 5592 | +++ b/hw/timer/hpet.c | ||
| 5593 | @@ -XXX,XX +XXX,XX @@ static void hpet_device_class_init(ObjectClass *klass, void *data) | ||
| 5594 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5595 | |||
| 5596 | dc->realize = hpet_realize; | ||
| 5597 | - dc->reset = hpet_reset; | ||
| 5598 | + device_class_set_legacy_reset(dc, hpet_reset); | ||
| 5599 | dc->vmsd = &vmstate_hpet; | ||
| 5600 | device_class_set_props(dc, hpet_device_properties); | ||
| 5601 | } | ||
| 5602 | diff --git a/hw/timer/i8254.c b/hw/timer/i8254.c | ||
| 5603 | index XXXXXXX..XXXXXXX 100644 | ||
| 5604 | --- a/hw/timer/i8254.c | ||
| 5605 | +++ b/hw/timer/i8254.c | ||
| 5606 | @@ -XXX,XX +XXX,XX @@ static void pit_class_initfn(ObjectClass *klass, void *data) | ||
| 5607 | k->set_channel_gate = pit_set_channel_gate; | ||
| 5608 | k->get_channel_info = pit_get_channel_info_common; | ||
| 5609 | k->post_load = pit_post_load; | ||
| 5610 | - dc->reset = pit_reset; | ||
| 5611 | + device_class_set_legacy_reset(dc, pit_reset); | ||
| 5612 | } | ||
| 5613 | |||
| 5614 | static const TypeInfo pit_info = { | ||
| 5615 | diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c | ||
| 5616 | index XXXXXXX..XXXXXXX 100644 | ||
| 5617 | --- a/hw/timer/ibex_timer.c | ||
| 5618 | +++ b/hw/timer/ibex_timer.c | ||
| 5619 | @@ -XXX,XX +XXX,XX @@ static void ibex_timer_class_init(ObjectClass *klass, void *data) | ||
| 5620 | { | ||
| 5621 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5622 | |||
| 5623 | - dc->reset = ibex_timer_reset; | ||
| 5624 | + device_class_set_legacy_reset(dc, ibex_timer_reset); | ||
| 5625 | dc->vmsd = &vmstate_ibex_timer; | ||
| 5626 | dc->realize = ibex_timer_realize; | ||
| 5627 | device_class_set_props(dc, ibex_timer_properties); | ||
| 5628 | diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c | ||
| 5629 | index XXXXXXX..XXXXXXX 100644 | ||
| 5630 | --- a/hw/timer/imx_epit.c | ||
| 5631 | +++ b/hw/timer/imx_epit.c | ||
| 5632 | @@ -XXX,XX +XXX,XX @@ static void imx_epit_class_init(ObjectClass *klass, void *data) | ||
| 5633 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5634 | |||
| 5635 | dc->realize = imx_epit_realize; | ||
| 5636 | - dc->reset = imx_epit_dev_reset; | ||
| 5637 | + device_class_set_legacy_reset(dc, imx_epit_dev_reset); | ||
| 5638 | dc->vmsd = &vmstate_imx_timer_epit; | ||
| 5639 | dc->desc = "i.MX periodic timer"; | ||
| 5640 | } | ||
| 5641 | diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c | ||
| 5642 | index XXXXXXX..XXXXXXX 100644 | ||
| 5643 | --- a/hw/timer/imx_gpt.c | ||
| 5644 | +++ b/hw/timer/imx_gpt.c | ||
| 5645 | @@ -XXX,XX +XXX,XX @@ static void imx_gpt_class_init(ObjectClass *klass, void *data) | ||
| 5646 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5647 | |||
| 5648 | dc->realize = imx_gpt_realize; | ||
| 5649 | - dc->reset = imx_gpt_reset; | ||
| 5650 | + device_class_set_legacy_reset(dc, imx_gpt_reset); | ||
| 5651 | dc->vmsd = &vmstate_imx_timer_gpt; | ||
| 5652 | dc->desc = "i.MX general timer"; | ||
| 5653 | } | ||
| 5654 | diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c | ||
| 5655 | index XXXXXXX..XXXXXXX 100644 | ||
| 5656 | --- a/hw/timer/nrf51_timer.c | ||
| 5657 | +++ b/hw/timer/nrf51_timer.c | ||
| 5658 | @@ -XXX,XX +XXX,XX @@ static void nrf51_timer_class_init(ObjectClass *klass, void *data) | ||
| 5659 | { | ||
| 5660 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5661 | |||
| 5662 | - dc->reset = nrf51_timer_reset; | ||
| 5663 | + device_class_set_legacy_reset(dc, nrf51_timer_reset); | ||
| 5664 | dc->vmsd = &vmstate_nrf51_timer; | ||
| 5665 | device_class_set_props(dc, nrf51_timer_properties); | ||
| 5666 | } | ||
| 5667 | diff --git a/hw/timer/renesas_cmt.c b/hw/timer/renesas_cmt.c | ||
| 5668 | index XXXXXXX..XXXXXXX 100644 | ||
| 5669 | --- a/hw/timer/renesas_cmt.c | ||
| 5670 | +++ b/hw/timer/renesas_cmt.c | ||
| 5671 | @@ -XXX,XX +XXX,XX @@ static void rcmt_class_init(ObjectClass *klass, void *data) | ||
| 5672 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5673 | |||
| 5674 | dc->vmsd = &vmstate_rcmt; | ||
| 5675 | - dc->reset = rcmt_reset; | ||
| 5676 | + device_class_set_legacy_reset(dc, rcmt_reset); | ||
| 5677 | device_class_set_props(dc, rcmt_properties); | ||
| 5678 | } | ||
| 5679 | |||
| 5680 | diff --git a/hw/timer/renesas_tmr.c b/hw/timer/renesas_tmr.c | ||
| 5681 | index XXXXXXX..XXXXXXX 100644 | ||
| 5682 | --- a/hw/timer/renesas_tmr.c | ||
| 5683 | +++ b/hw/timer/renesas_tmr.c | ||
| 5684 | @@ -XXX,XX +XXX,XX @@ static void rtmr_class_init(ObjectClass *klass, void *data) | ||
| 5685 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5686 | |||
| 5687 | dc->vmsd = &vmstate_rtmr; | ||
| 5688 | - dc->reset = rtmr_reset; | ||
| 5689 | + device_class_set_legacy_reset(dc, rtmr_reset); | ||
| 5690 | device_class_set_props(dc, rtmr_properties); | ||
| 5691 | } | ||
| 5692 | |||
| 5693 | diff --git a/hw/timer/sifive_pwm.c b/hw/timer/sifive_pwm.c | ||
| 5694 | index XXXXXXX..XXXXXXX 100644 | ||
| 5695 | --- a/hw/timer/sifive_pwm.c | ||
| 5696 | +++ b/hw/timer/sifive_pwm.c | ||
| 5697 | @@ -XXX,XX +XXX,XX @@ static void sifive_pwm_class_init(ObjectClass *klass, void *data) | ||
| 5698 | { | ||
| 5699 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5700 | |||
| 5701 | - dc->reset = sifive_pwm_reset; | ||
| 5702 | + device_class_set_legacy_reset(dc, sifive_pwm_reset); | ||
| 5703 | device_class_set_props(dc, sifive_pwm_properties); | ||
| 5704 | dc->vmsd = &vmstate_sifive_pwm; | ||
| 5705 | dc->realize = sifive_pwm_realize; | ||
| 5706 | diff --git a/hw/timer/slavio_timer.c b/hw/timer/slavio_timer.c | ||
| 5707 | index XXXXXXX..XXXXXXX 100644 | ||
| 5708 | --- a/hw/timer/slavio_timer.c | ||
| 5709 | +++ b/hw/timer/slavio_timer.c | ||
| 5710 | @@ -XXX,XX +XXX,XX @@ static void slavio_timer_class_init(ObjectClass *klass, void *data) | ||
| 5711 | { | ||
| 5712 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5713 | |||
| 5714 | - dc->reset = slavio_timer_reset; | ||
| 5715 | + device_class_set_legacy_reset(dc, slavio_timer_reset); | ||
| 5716 | dc->vmsd = &vmstate_slavio_timer; | ||
| 5717 | device_class_set_props(dc, slavio_timer_properties); | ||
| 5718 | } | ||
| 5719 | diff --git a/hw/timer/sse-counter.c b/hw/timer/sse-counter.c | ||
| 5720 | index XXXXXXX..XXXXXXX 100644 | ||
| 5721 | --- a/hw/timer/sse-counter.c | ||
| 5722 | +++ b/hw/timer/sse-counter.c | ||
| 5723 | @@ -XXX,XX +XXX,XX @@ static void sse_counter_class_init(ObjectClass *klass, void *data) | ||
| 5724 | |||
| 5725 | dc->realize = sse_counter_realize; | ||
| 5726 | dc->vmsd = &sse_counter_vmstate; | ||
| 5727 | - dc->reset = sse_counter_reset; | ||
| 5728 | + device_class_set_legacy_reset(dc, sse_counter_reset); | ||
| 5729 | } | ||
| 5730 | |||
| 5731 | static const TypeInfo sse_counter_info = { | ||
| 5732 | diff --git a/hw/timer/sse-timer.c b/hw/timer/sse-timer.c | ||
| 5733 | index XXXXXXX..XXXXXXX 100644 | ||
| 5734 | --- a/hw/timer/sse-timer.c | ||
| 5735 | +++ b/hw/timer/sse-timer.c | ||
| 5736 | @@ -XXX,XX +XXX,XX @@ static void sse_timer_class_init(ObjectClass *klass, void *data) | ||
| 5737 | |||
| 5738 | dc->realize = sse_timer_realize; | ||
| 5739 | dc->vmsd = &sse_timer_vmstate; | ||
| 5740 | - dc->reset = sse_timer_reset; | ||
| 5741 | + device_class_set_legacy_reset(dc, sse_timer_reset); | ||
| 5742 | device_class_set_props(dc, sse_timer_properties); | ||
| 5743 | } | ||
| 5744 | |||
| 5745 | diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c | ||
| 5746 | index XXXXXXX..XXXXXXX 100644 | ||
| 5747 | --- a/hw/timer/stm32f2xx_timer.c | ||
| 5748 | +++ b/hw/timer/stm32f2xx_timer.c | ||
| 5749 | @@ -XXX,XX +XXX,XX @@ static void stm32f2xx_timer_class_init(ObjectClass *klass, void *data) | ||
| 5750 | { | ||
| 5751 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5752 | |||
| 5753 | - dc->reset = stm32f2xx_timer_reset; | ||
| 5754 | + device_class_set_legacy_reset(dc, stm32f2xx_timer_reset); | ||
| 5755 | device_class_set_props(dc, stm32f2xx_timer_properties); | ||
| 5756 | dc->vmsd = &vmstate_stm32f2xx_timer; | ||
| 5757 | dc->realize = stm32f2xx_timer_realize; | ||
| 5758 | diff --git a/hw/tpm/tpm_tis_i2c.c b/hw/tpm/tpm_tis_i2c.c | ||
| 5759 | index XXXXXXX..XXXXXXX 100644 | ||
| 5760 | --- a/hw/tpm/tpm_tis_i2c.c | ||
| 5761 | +++ b/hw/tpm/tpm_tis_i2c.c | ||
| 5762 | @@ -XXX,XX +XXX,XX @@ static void tpm_tis_i2c_class_init(ObjectClass *klass, void *data) | ||
| 5763 | TPMIfClass *tc = TPM_IF_CLASS(klass); | ||
| 5764 | |||
| 5765 | dc->realize = tpm_tis_i2c_realizefn; | ||
| 5766 | - dc->reset = tpm_tis_i2c_reset; | ||
| 5767 | + device_class_set_legacy_reset(dc, tpm_tis_i2c_reset); | ||
| 5768 | dc->vmsd = &vmstate_tpm_tis_i2c; | ||
| 5769 | device_class_set_props(dc, tpm_tis_i2c_properties); | ||
| 5770 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 5771 | diff --git a/hw/tpm/tpm_tis_isa.c b/hw/tpm/tpm_tis_isa.c | ||
| 5772 | index XXXXXXX..XXXXXXX 100644 | ||
| 5773 | --- a/hw/tpm/tpm_tis_isa.c | ||
| 5774 | +++ b/hw/tpm/tpm_tis_isa.c | ||
| 5775 | @@ -XXX,XX +XXX,XX @@ static void tpm_tis_isa_class_init(ObjectClass *klass, void *data) | ||
| 5776 | dc->vmsd = &vmstate_tpm_tis_isa; | ||
| 5777 | tc->model = TPM_MODEL_TPM_TIS; | ||
| 5778 | dc->realize = tpm_tis_isa_realizefn; | ||
| 5779 | - dc->reset = tpm_tis_isa_reset; | ||
| 5780 | + device_class_set_legacy_reset(dc, tpm_tis_isa_reset); | ||
| 5781 | tc->request_completed = tpm_tis_isa_request_completed; | ||
| 5782 | tc->get_version = tpm_tis_isa_get_tpm_version; | ||
| 5783 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 5784 | diff --git a/hw/tpm/tpm_tis_sysbus.c b/hw/tpm/tpm_tis_sysbus.c | ||
| 5785 | index XXXXXXX..XXXXXXX 100644 | ||
| 5786 | --- a/hw/tpm/tpm_tis_sysbus.c | ||
| 5787 | +++ b/hw/tpm/tpm_tis_sysbus.c | ||
| 5788 | @@ -XXX,XX +XXX,XX @@ static void tpm_tis_sysbus_class_init(ObjectClass *klass, void *data) | ||
| 5789 | tc->model = TPM_MODEL_TPM_TIS; | ||
| 5790 | dc->realize = tpm_tis_sysbus_realizefn; | ||
| 5791 | dc->user_creatable = true; | ||
| 5792 | - dc->reset = tpm_tis_sysbus_reset; | ||
| 5793 | + device_class_set_legacy_reset(dc, tpm_tis_sysbus_reset); | ||
| 5794 | tc->request_completed = tpm_tis_sysbus_request_completed; | ||
| 5795 | tc->get_version = tpm_tis_sysbus_get_tpm_version; | ||
| 5796 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 5797 | diff --git a/hw/tricore/tricore_testdevice.c b/hw/tricore/tricore_testdevice.c | ||
| 5798 | index XXXXXXX..XXXXXXX 100644 | ||
| 5799 | --- a/hw/tricore/tricore_testdevice.c | ||
| 5800 | +++ b/hw/tricore/tricore_testdevice.c | ||
| 5801 | @@ -XXX,XX +XXX,XX @@ static void tricore_testdevice_class_init(ObjectClass *klass, void *data) | ||
| 5802 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5803 | |||
| 5804 | device_class_set_props(dc, tricore_testdevice_properties); | ||
| 5805 | - dc->reset = tricore_testdevice_reset; | ||
| 5806 | + device_class_set_legacy_reset(dc, tricore_testdevice_reset); | ||
| 5807 | } | ||
| 5808 | |||
| 5809 | static const TypeInfo tricore_testdevice_info = { | ||
| 5810 | diff --git a/hw/usb/hcd-dwc3.c b/hw/usb/hcd-dwc3.c | ||
| 5811 | index XXXXXXX..XXXXXXX 100644 | ||
| 5812 | --- a/hw/usb/hcd-dwc3.c | ||
| 5813 | +++ b/hw/usb/hcd-dwc3.c | ||
| 5814 | @@ -XXX,XX +XXX,XX @@ static void usb_dwc3_class_init(ObjectClass *klass, void *data) | ||
| 5815 | { | ||
| 5816 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5817 | |||
| 5818 | - dc->reset = usb_dwc3_reset; | ||
| 5819 | + device_class_set_legacy_reset(dc, usb_dwc3_reset); | ||
| 5820 | dc->realize = usb_dwc3_realize; | ||
| 5821 | dc->vmsd = &vmstate_usb_dwc3; | ||
| 5822 | device_class_set_props(dc, usb_dwc3_properties); | ||
| 5823 | diff --git a/hw/usb/hcd-ehci-pci.c b/hw/usb/hcd-ehci-pci.c | ||
| 5824 | index XXXXXXX..XXXXXXX 100644 | ||
| 5825 | --- a/hw/usb/hcd-ehci-pci.c | ||
| 5826 | +++ b/hw/usb/hcd-ehci-pci.c | ||
| 5827 | @@ -XXX,XX +XXX,XX @@ static void ehci_class_init(ObjectClass *klass, void *data) | ||
| 5828 | k->config_write = usb_ehci_pci_write_config; | ||
| 5829 | dc->vmsd = &vmstate_ehci_pci; | ||
| 5830 | device_class_set_props(dc, ehci_pci_properties); | ||
| 5831 | - dc->reset = usb_ehci_pci_reset; | ||
| 5832 | + device_class_set_legacy_reset(dc, usb_ehci_pci_reset); | ||
| 5833 | } | ||
| 5834 | |||
| 5835 | static const TypeInfo ehci_pci_type_info = { | ||
| 5836 | diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c | ||
| 5837 | index XXXXXXX..XXXXXXX 100644 | ||
| 5838 | --- a/hw/usb/hcd-ehci-sysbus.c | ||
| 5839 | +++ b/hw/usb/hcd-ehci-sysbus.c | ||
| 5840 | @@ -XXX,XX +XXX,XX @@ static void ehci_sysbus_class_init(ObjectClass *klass, void *data) | ||
| 5841 | dc->realize = usb_ehci_sysbus_realize; | ||
| 5842 | dc->vmsd = &vmstate_ehci_sysbus; | ||
| 5843 | device_class_set_props(dc, ehci_sysbus_properties); | ||
| 5844 | - dc->reset = usb_ehci_sysbus_reset; | ||
| 5845 | + device_class_set_legacy_reset(dc, usb_ehci_sysbus_reset); | ||
| 5846 | set_bit(DEVICE_CATEGORY_USB, dc->categories); | ||
| 5847 | } | ||
| 5848 | |||
| 5849 | diff --git a/hw/usb/hcd-ohci-pci.c b/hw/usb/hcd-ohci-pci.c | ||
| 5850 | index XXXXXXX..XXXXXXX 100644 | ||
| 5851 | --- a/hw/usb/hcd-ohci-pci.c | ||
| 5852 | +++ b/hw/usb/hcd-ohci-pci.c | ||
| 5853 | @@ -XXX,XX +XXX,XX @@ static void ohci_pci_class_init(ObjectClass *klass, void *data) | ||
| 5854 | device_class_set_props(dc, ohci_pci_properties); | ||
| 5855 | dc->hotpluggable = false; | ||
| 5856 | dc->vmsd = &vmstate_ohci; | ||
| 5857 | - dc->reset = usb_ohci_reset_pci; | ||
| 5858 | + device_class_set_legacy_reset(dc, usb_ohci_reset_pci); | ||
| 5859 | } | ||
| 5860 | |||
| 5861 | static const TypeInfo ohci_pci_info = { | ||
| 5862 | diff --git a/hw/usb/hcd-ohci-sysbus.c b/hw/usb/hcd-ohci-sysbus.c | ||
| 5863 | index XXXXXXX..XXXXXXX 100644 | ||
| 5864 | --- a/hw/usb/hcd-ohci-sysbus.c | ||
| 5865 | +++ b/hw/usb/hcd-ohci-sysbus.c | ||
| 5866 | @@ -XXX,XX +XXX,XX @@ static void ohci_sysbus_class_init(ObjectClass *klass, void *data) | ||
| 5867 | set_bit(DEVICE_CATEGORY_USB, dc->categories); | ||
| 5868 | dc->desc = "OHCI USB Controller"; | ||
| 5869 | device_class_set_props(dc, ohci_sysbus_properties); | ||
| 5870 | - dc->reset = ohci_sysbus_reset; | ||
| 5871 | + device_class_set_legacy_reset(dc, ohci_sysbus_reset); | ||
| 5872 | } | ||
| 5873 | |||
| 5874 | static const TypeInfo ohci_sysbus_types[] = { | ||
| 5875 | diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c | ||
| 5876 | index XXXXXXX..XXXXXXX 100644 | ||
| 5877 | --- a/hw/usb/hcd-uhci.c | ||
| 5878 | +++ b/hw/usb/hcd-uhci.c | ||
| 5879 | @@ -XXX,XX +XXX,XX @@ static void uhci_class_init(ObjectClass *klass, void *data) | ||
| 5880 | |||
| 5881 | k->class_id = PCI_CLASS_SERIAL_USB; | ||
| 5882 | dc->vmsd = &vmstate_uhci; | ||
| 5883 | - dc->reset = uhci_reset; | ||
| 5884 | + device_class_set_legacy_reset(dc, uhci_reset); | ||
| 5885 | set_bit(DEVICE_CATEGORY_USB, dc->categories); | ||
| 5886 | } | ||
| 5887 | |||
| 5888 | diff --git a/hw/usb/hcd-xhci-pci.c b/hw/usb/hcd-xhci-pci.c | ||
| 5889 | index XXXXXXX..XXXXXXX 100644 | ||
| 5890 | --- a/hw/usb/hcd-xhci-pci.c | ||
| 5891 | +++ b/hw/usb/hcd-xhci-pci.c | ||
| 5892 | @@ -XXX,XX +XXX,XX @@ static void xhci_class_init(ObjectClass *klass, void *data) | ||
| 5893 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | ||
| 5894 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5895 | |||
| 5896 | - dc->reset = xhci_pci_reset; | ||
| 5897 | + device_class_set_legacy_reset(dc, xhci_pci_reset); | ||
| 5898 | dc->vmsd = &vmstate_xhci_pci; | ||
| 5899 | set_bit(DEVICE_CATEGORY_USB, dc->categories); | ||
| 5900 | k->realize = usb_xhci_pci_realize; | ||
| 5901 | diff --git a/hw/usb/hcd-xhci-sysbus.c b/hw/usb/hcd-xhci-sysbus.c | ||
| 5902 | index XXXXXXX..XXXXXXX 100644 | ||
| 5903 | --- a/hw/usb/hcd-xhci-sysbus.c | ||
| 5904 | +++ b/hw/usb/hcd-xhci-sysbus.c | ||
| 5905 | @@ -XXX,XX +XXX,XX @@ static void xhci_sysbus_class_init(ObjectClass *klass, void *data) | ||
| 5906 | { | ||
| 5907 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5908 | |||
| 5909 | - dc->reset = xhci_sysbus_reset; | ||
| 5910 | + device_class_set_legacy_reset(dc, xhci_sysbus_reset); | ||
| 5911 | dc->realize = xhci_sysbus_realize; | ||
| 5912 | dc->vmsd = &vmstate_xhci_sysbus; | ||
| 5913 | device_class_set_props(dc, xhci_sysbus_props); | ||
| 5914 | diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c | ||
| 5915 | index XXXXXXX..XXXXXXX 100644 | ||
| 5916 | --- a/hw/usb/hcd-xhci.c | ||
| 5917 | +++ b/hw/usb/hcd-xhci.c | ||
| 5918 | @@ -XXX,XX +XXX,XX @@ static void xhci_class_init(ObjectClass *klass, void *data) | ||
| 5919 | |||
| 5920 | dc->realize = usb_xhci_realize; | ||
| 5921 | dc->unrealize = usb_xhci_unrealize; | ||
| 5922 | - dc->reset = xhci_reset; | ||
| 5923 | + device_class_set_legacy_reset(dc, xhci_reset); | ||
| 5924 | device_class_set_props(dc, xhci_properties); | ||
| 5925 | dc->user_creatable = false; | ||
| 5926 | } | ||
| 5927 | diff --git a/hw/usb/imx-usb-phy.c b/hw/usb/imx-usb-phy.c | ||
| 5928 | index XXXXXXX..XXXXXXX 100644 | ||
| 5929 | --- a/hw/usb/imx-usb-phy.c | ||
| 5930 | +++ b/hw/usb/imx-usb-phy.c | ||
| 5931 | @@ -XXX,XX +XXX,XX @@ static void imx_usbphy_class_init(ObjectClass *klass, void *data) | ||
| 5932 | { | ||
| 5933 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5934 | |||
| 5935 | - dc->reset = imx_usbphy_reset; | ||
| 5936 | + device_class_set_legacy_reset(dc, imx_usbphy_reset); | ||
| 5937 | dc->vmsd = &vmstate_imx_usbphy; | ||
| 5938 | dc->desc = "i.MX USB PHY Module"; | ||
| 5939 | dc->realize = imx_usbphy_realize; | ||
| 5940 | diff --git a/hw/usb/tusb6010.c b/hw/usb/tusb6010.c | ||
| 5941 | index XXXXXXX..XXXXXXX 100644 | ||
| 5942 | --- a/hw/usb/tusb6010.c | ||
| 5943 | +++ b/hw/usb/tusb6010.c | ||
| 5944 | @@ -XXX,XX +XXX,XX @@ static void tusb6010_class_init(ObjectClass *klass, void *data) | ||
| 5945 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5946 | |||
| 5947 | dc->realize = tusb6010_realize; | ||
| 5948 | - dc->reset = tusb6010_reset; | ||
| 5949 | + device_class_set_legacy_reset(dc, tusb6010_reset); | ||
| 5950 | } | ||
| 5951 | |||
| 5952 | static const TypeInfo tusb6010_info = { | ||
| 5953 | diff --git a/hw/vfio/ap.c b/hw/vfio/ap.c | ||
| 5954 | index XXXXXXX..XXXXXXX 100644 | ||
| 5955 | --- a/hw/vfio/ap.c | ||
| 5956 | +++ b/hw/vfio/ap.c | ||
| 5957 | @@ -XXX,XX +XXX,XX @@ static void vfio_ap_class_init(ObjectClass *klass, void *data) | ||
| 5958 | dc->realize = vfio_ap_realize; | ||
| 5959 | dc->unrealize = vfio_ap_unrealize; | ||
| 5960 | dc->hotpluggable = true; | ||
| 5961 | - dc->reset = vfio_ap_reset; | ||
| 5962 | + device_class_set_legacy_reset(dc, vfio_ap_reset); | ||
| 5963 | dc->bus_type = TYPE_AP_BUS; | ||
| 5964 | } | ||
| 5965 | |||
| 5966 | diff --git a/hw/vfio/ccw.c b/hw/vfio/ccw.c | ||
| 5967 | index XXXXXXX..XXXXXXX 100644 | ||
| 5968 | --- a/hw/vfio/ccw.c | ||
| 5969 | +++ b/hw/vfio/ccw.c | ||
| 5970 | @@ -XXX,XX +XXX,XX @@ static void vfio_ccw_class_init(ObjectClass *klass, void *data) | ||
| 5971 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 5972 | dc->realize = vfio_ccw_realize; | ||
| 5973 | dc->unrealize = vfio_ccw_unrealize; | ||
| 5974 | - dc->reset = vfio_ccw_reset; | ||
| 5975 | + device_class_set_legacy_reset(dc, vfio_ccw_reset); | ||
| 5976 | |||
| 5977 | cdc->handle_request = vfio_ccw_handle_request; | ||
| 5978 | cdc->handle_halt = vfio_ccw_handle_halt; | ||
| 5979 | diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c | ||
| 5980 | index XXXXXXX..XXXXXXX 100644 | ||
| 5981 | --- a/hw/vfio/pci.c | ||
| 5982 | +++ b/hw/vfio/pci.c | ||
| 5983 | @@ -XXX,XX +XXX,XX @@ static void vfio_pci_dev_class_init(ObjectClass *klass, void *data) | ||
| 5984 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5985 | PCIDeviceClass *pdc = PCI_DEVICE_CLASS(klass); | ||
| 5986 | |||
| 5987 | - dc->reset = vfio_pci_reset; | ||
| 5988 | + device_class_set_legacy_reset(dc, vfio_pci_reset); | ||
| 5989 | device_class_set_props(dc, vfio_pci_dev_properties); | ||
| 5990 | #ifdef CONFIG_IOMMUFD | ||
| 5991 | object_class_property_add_str(klass, "fd", NULL, vfio_pci_set_fd); | ||
| 5992 | diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c | ||
| 5993 | index XXXXXXX..XXXXXXX 100644 | ||
| 5994 | --- a/hw/virtio/virtio-mmio.c | ||
| 5995 | +++ b/hw/virtio/virtio-mmio.c | ||
| 5996 | @@ -XXX,XX +XXX,XX @@ static void virtio_mmio_class_init(ObjectClass *klass, void *data) | ||
| 5997 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 5998 | |||
| 5999 | dc->realize = virtio_mmio_realizefn; | ||
| 6000 | - dc->reset = virtio_mmio_reset; | ||
| 6001 | + device_class_set_legacy_reset(dc, virtio_mmio_reset); | ||
| 6002 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
| 6003 | device_class_set_props(dc, virtio_mmio_properties); | ||
| 6004 | } | ||
| 6005 | diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c | ||
| 6006 | index XXXXXXX..XXXXXXX 100644 | ||
| 6007 | --- a/hw/watchdog/cmsdk-apb-watchdog.c | ||
| 6008 | +++ b/hw/watchdog/cmsdk-apb-watchdog.c | ||
| 6009 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data) | ||
| 6010 | |||
| 6011 | dc->realize = cmsdk_apb_watchdog_realize; | ||
| 6012 | dc->vmsd = &cmsdk_apb_watchdog_vmstate; | ||
| 6013 | - dc->reset = cmsdk_apb_watchdog_reset; | ||
| 6014 | + device_class_set_legacy_reset(dc, cmsdk_apb_watchdog_reset); | ||
| 6015 | } | ||
| 6016 | |||
| 6017 | static const TypeInfo cmsdk_apb_watchdog_info = { | ||
| 6018 | diff --git a/hw/watchdog/sbsa_gwdt.c b/hw/watchdog/sbsa_gwdt.c | ||
| 6019 | index XXXXXXX..XXXXXXX 100644 | ||
| 6020 | --- a/hw/watchdog/sbsa_gwdt.c | ||
| 6021 | +++ b/hw/watchdog/sbsa_gwdt.c | ||
| 6022 | @@ -XXX,XX +XXX,XX @@ static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data) | ||
| 6023 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 6024 | |||
| 6025 | dc->realize = wdt_sbsa_gwdt_realize; | ||
| 6026 | - dc->reset = wdt_sbsa_gwdt_reset; | ||
| 6027 | + device_class_set_legacy_reset(dc, wdt_sbsa_gwdt_reset); | ||
| 6028 | dc->hotpluggable = false; | ||
| 6029 | set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories); | ||
| 6030 | dc->vmsd = &vmstate_sbsa_gwdt; | ||
| 6031 | diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c | ||
| 6032 | index XXXXXXX..XXXXXXX 100644 | ||
| 6033 | --- a/hw/watchdog/wdt_aspeed.c | ||
| 6034 | +++ b/hw/watchdog/wdt_aspeed.c | ||
| 6035 | @@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_class_init(ObjectClass *klass, void *data) | ||
| 6036 | |||
| 6037 | dc->desc = "ASPEED Watchdog Controller"; | ||
| 6038 | dc->realize = aspeed_wdt_realize; | ||
| 6039 | - dc->reset = aspeed_wdt_reset; | ||
| 6040 | + device_class_set_legacy_reset(dc, aspeed_wdt_reset); | ||
| 6041 | set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories); | ||
| 6042 | dc->vmsd = &vmstate_aspeed_wdt; | ||
| 6043 | device_class_set_props(dc, aspeed_wdt_properties); | ||
| 6044 | diff --git a/hw/watchdog/wdt_diag288.c b/hw/watchdog/wdt_diag288.c | ||
| 6045 | index XXXXXXX..XXXXXXX 100644 | ||
| 6046 | --- a/hw/watchdog/wdt_diag288.c | ||
| 6047 | +++ b/hw/watchdog/wdt_diag288.c | ||
| 6048 | @@ -XXX,XX +XXX,XX @@ static void wdt_diag288_class_init(ObjectClass *klass, void *data) | ||
| 6049 | |||
| 6050 | dc->realize = wdt_diag288_realize; | ||
| 6051 | dc->unrealize = wdt_diag288_unrealize; | ||
| 6052 | - dc->reset = wdt_diag288_reset; | ||
| 6053 | + device_class_set_legacy_reset(dc, wdt_diag288_reset); | ||
| 6054 | dc->hotpluggable = false; | ||
| 6055 | set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories); | ||
| 6056 | dc->vmsd = &vmstate_diag288; | ||
| 6057 | diff --git a/hw/watchdog/wdt_i6300esb.c b/hw/watchdog/wdt_i6300esb.c | ||
| 6058 | index XXXXXXX..XXXXXXX 100644 | ||
| 6059 | --- a/hw/watchdog/wdt_i6300esb.c | ||
| 6060 | +++ b/hw/watchdog/wdt_i6300esb.c | ||
| 6061 | @@ -XXX,XX +XXX,XX @@ static void i6300esb_class_init(ObjectClass *klass, void *data) | ||
| 6062 | k->vendor_id = PCI_VENDOR_ID_INTEL; | ||
| 6063 | k->device_id = PCI_DEVICE_ID_INTEL_ESB_9; | ||
| 6064 | k->class_id = PCI_CLASS_SYSTEM_OTHER; | ||
| 6065 | - dc->reset = i6300esb_reset; | ||
| 6066 | + device_class_set_legacy_reset(dc, i6300esb_reset); | ||
| 6067 | dc->vmsd = &vmstate_i6300esb; | ||
| 6068 | set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories); | ||
| 6069 | dc->desc = "Intel 6300ESB"; | ||
| 6070 | diff --git a/hw/watchdog/wdt_ib700.c b/hw/watchdog/wdt_ib700.c | ||
| 6071 | index XXXXXXX..XXXXXXX 100644 | ||
| 6072 | --- a/hw/watchdog/wdt_ib700.c | ||
| 6073 | +++ b/hw/watchdog/wdt_ib700.c | ||
| 6074 | @@ -XXX,XX +XXX,XX @@ static void wdt_ib700_class_init(ObjectClass *klass, void *data) | ||
| 6075 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 6076 | |||
| 6077 | dc->realize = wdt_ib700_realize; | ||
| 6078 | - dc->reset = wdt_ib700_reset; | ||
| 6079 | + device_class_set_legacy_reset(dc, wdt_ib700_reset); | ||
| 6080 | dc->vmsd = &vmstate_ib700; | ||
| 6081 | set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories); | ||
| 6082 | dc->desc = "iBASE 700"; | ||
| 6083 | diff --git a/hw/watchdog/wdt_imx2.c b/hw/watchdog/wdt_imx2.c | ||
| 6084 | index XXXXXXX..XXXXXXX 100644 | ||
| 6085 | --- a/hw/watchdog/wdt_imx2.c | ||
| 6086 | +++ b/hw/watchdog/wdt_imx2.c | ||
| 6087 | @@ -XXX,XX +XXX,XX @@ static void imx2_wdt_class_init(ObjectClass *klass, void *data) | ||
| 6088 | |||
| 6089 | device_class_set_props(dc, imx2_wdt_properties); | ||
| 6090 | dc->realize = imx2_wdt_realize; | ||
| 6091 | - dc->reset = imx2_wdt_reset; | ||
| 6092 | + device_class_set_legacy_reset(dc, imx2_wdt_reset); | ||
| 6093 | dc->vmsd = &vmstate_imx2_wdt; | ||
| 6094 | dc->desc = "i.MX2 watchdog timer"; | ||
| 6095 | set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories); | ||
| 6096 | -- | 471 | -- |
| 6097 | 2.34.1 | 472 | 2.34.1 | diff view generated by jsdifflib |
| 1 | From: Doug Brown <doug@schmorgal.com> | 1 | From: Bernhard Beschow <shentey@gmail.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | When checking the QEMU_CAN_FRMF_TYPE_FD flag, we need to ignore other | 3 | Turns 0x70 into 0xe0 (== 0x70 << 1) which adds the missing MII_ANLPAR_TX and |
| 4 | potentially set flags. Before this change, received CAN FD frames from | 4 | fixes the MSB of selector field to be zero, as specified in the datasheet. |
| 5 | SocketCAN weren't being recognized as CAN FD. | ||
| 6 | 5 | ||
| 7 | Signed-off-by: Doug Brown <doug@schmorgal.com> | 6 | Fixes: 2a424990170b "LAN9118 emulation" |
| 8 | Reviewed-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | 7 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> |
| 9 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | 8 | Tested-by: Guenter Roeck <linux@roeck-us.net> |
| 10 | Message-id: 20240827034927.66659-3-doug@schmorgal.com | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | Message-id: 20241102125724.532843-4-shentey@gmail.com | ||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 12 | --- | 12 | --- |
| 13 | hw/net/can/xlnx-versal-canfd.c | 2 +- | 13 | hw/net/lan9118_phy.c | 2 +- |
| 14 | 1 file changed, 1 insertion(+), 1 deletion(-) | 14 | 1 file changed, 1 insertion(+), 1 deletion(-) |
| 15 | 15 | ||
| 16 | diff --git a/hw/net/can/xlnx-versal-canfd.c b/hw/net/can/xlnx-versal-canfd.c | 16 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c |
| 17 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/hw/net/can/xlnx-versal-canfd.c | 18 | --- a/hw/net/lan9118_phy.c |
| 19 | +++ b/hw/net/can/xlnx-versal-canfd.c | 19 | +++ b/hw/net/lan9118_phy.c |
| 20 | @@ -XXX,XX +XXX,XX @@ static void store_rx_sequential(XlnxVersalCANFDState *s, | 20 | @@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) |
| 21 | 21 | val = s->advertise; | |
| 22 | dlc = frame->can_dlc; | 22 | break; |
| 23 | 23 | case 5: /* Auto-neg Link Partner Ability */ | |
| 24 | - if (frame->flags == QEMU_CAN_FRMF_TYPE_FD) { | 24 | - val = 0x0f71; |
| 25 | + if (frame->flags & QEMU_CAN_FRMF_TYPE_FD) { | 25 | + val = 0x0fe1; |
| 26 | is_canfd_frame = true; | 26 | break; |
| 27 | 27 | case 6: /* Auto-neg Expansion */ | |
| 28 | /* Store dlc value in Xilinx specific format. */ | 28 | val = 1; |
| 29 | -- | 29 | -- |
| 30 | 2.34.1 | 30 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Bernhard Beschow <shentey@gmail.com> | ||
| 1 | 2 | ||
| 3 | Prefer named constants over magic values for better readability. | ||
| 4 | |||
| 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> | ||
| 7 | Tested-by: Guenter Roeck <linux@roeck-us.net> | ||
| 8 | Message-id: 20241102125724.532843-5-shentey@gmail.com | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | include/hw/net/mii.h | 6 +++++ | ||
| 12 | hw/net/lan9118_phy.c | 63 ++++++++++++++++++++++++++++---------------- | ||
| 13 | 2 files changed, 46 insertions(+), 23 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/include/hw/net/mii.h | ||
| 18 | +++ b/include/hw/net/mii.h | ||
| 19 | @@ -XXX,XX +XXX,XX @@ | ||
| 20 | #define MII_BMSR_JABBER (1 << 1) /* Jabber detected */ | ||
| 21 | #define MII_BMSR_EXTCAP (1 << 0) /* Ext-reg capability */ | ||
| 22 | |||
| 23 | +#define MII_ANAR_RFAULT (1 << 13) /* Say we can detect faults */ | ||
| 24 | #define MII_ANAR_PAUSE_ASYM (1 << 11) /* Try for asymmetric pause */ | ||
| 25 | #define MII_ANAR_PAUSE (1 << 10) /* Try for pause */ | ||
| 26 | #define MII_ANAR_TXFD (1 << 8) | ||
| 27 | @@ -XXX,XX +XXX,XX @@ | ||
| 28 | #define MII_ANAR_10FD (1 << 6) | ||
| 29 | #define MII_ANAR_10 (1 << 5) | ||
| 30 | #define MII_ANAR_CSMACD (1 << 0) | ||
| 31 | +#define MII_ANAR_SELECT (0x001f) /* Selector bits */ | ||
| 32 | |||
| 33 | #define MII_ANLPAR_ACK (1 << 14) | ||
| 34 | #define MII_ANLPAR_PAUSEASY (1 << 11) /* can pause asymmetrically */ | ||
| 35 | @@ -XXX,XX +XXX,XX @@ | ||
| 36 | #define RTL8201CP_PHYID1 0x0000 | ||
| 37 | #define RTL8201CP_PHYID2 0x8201 | ||
| 38 | |||
| 39 | +/* SMSC LAN9118 */ | ||
| 40 | +#define SMSCLAN9118_PHYID1 0x0007 | ||
| 41 | +#define SMSCLAN9118_PHYID2 0xc0d1 | ||
| 42 | + | ||
| 43 | /* RealTek 8211E */ | ||
| 44 | #define RTL8211E_PHYID1 0x001c | ||
| 45 | #define RTL8211E_PHYID2 0xc915 | ||
| 46 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c | ||
| 47 | index XXXXXXX..XXXXXXX 100644 | ||
| 48 | --- a/hw/net/lan9118_phy.c | ||
| 49 | +++ b/hw/net/lan9118_phy.c | ||
| 50 | @@ -XXX,XX +XXX,XX @@ | ||
| 51 | |||
| 52 | #include "qemu/osdep.h" | ||
| 53 | #include "hw/net/lan9118_phy.h" | ||
| 54 | +#include "hw/net/mii.h" | ||
| 55 | #include "hw/irq.h" | ||
| 56 | #include "hw/resettable.h" | ||
| 57 | #include "migration/vmstate.h" | ||
| 58 | @@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) | ||
| 59 | uint16_t val; | ||
| 60 | |||
| 61 | switch (reg) { | ||
| 62 | - case 0: /* Basic Control */ | ||
| 63 | + case MII_BMCR: | ||
| 64 | val = s->control; | ||
| 65 | break; | ||
| 66 | - case 1: /* Basic Status */ | ||
| 67 | + case MII_BMSR: | ||
| 68 | val = s->status; | ||
| 69 | break; | ||
| 70 | - case 2: /* ID1 */ | ||
| 71 | - val = 0x0007; | ||
| 72 | + case MII_PHYID1: | ||
| 73 | + val = SMSCLAN9118_PHYID1; | ||
| 74 | break; | ||
| 75 | - case 3: /* ID2 */ | ||
| 76 | - val = 0xc0d1; | ||
| 77 | + case MII_PHYID2: | ||
| 78 | + val = SMSCLAN9118_PHYID2; | ||
| 79 | break; | ||
| 80 | - case 4: /* Auto-neg advertisement */ | ||
| 81 | + case MII_ANAR: | ||
| 82 | val = s->advertise; | ||
| 83 | break; | ||
| 84 | - case 5: /* Auto-neg Link Partner Ability */ | ||
| 85 | - val = 0x0fe1; | ||
| 86 | + case MII_ANLPAR: | ||
| 87 | + val = MII_ANLPAR_PAUSEASY | MII_ANLPAR_PAUSE | MII_ANLPAR_T4 | | ||
| 88 | + MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD | | ||
| 89 | + MII_ANLPAR_10 | MII_ANLPAR_CSMACD; | ||
| 90 | break; | ||
| 91 | - case 6: /* Auto-neg Expansion */ | ||
| 92 | - val = 1; | ||
| 93 | + case MII_ANER: | ||
| 94 | + val = MII_ANER_NWAY; | ||
| 95 | break; | ||
| 96 | case 29: /* Interrupt source. */ | ||
| 97 | val = s->ints; | ||
| 98 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) | ||
| 99 | trace_lan9118_phy_write(val, reg); | ||
| 100 | |||
| 101 | switch (reg) { | ||
| 102 | - case 0: /* Basic Control */ | ||
| 103 | - if (val & 0x8000) { | ||
| 104 | + case MII_BMCR: | ||
| 105 | + if (val & MII_BMCR_RESET) { | ||
| 106 | lan9118_phy_reset(s); | ||
| 107 | } else { | ||
| 108 | - s->control = val & 0x7980; | ||
| 109 | + s->control = val & (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 | | ||
| 110 | + MII_BMCR_AUTOEN | MII_BMCR_PDOWN | MII_BMCR_FD | | ||
| 111 | + MII_BMCR_CTST); | ||
| 112 | /* Complete autonegotiation immediately. */ | ||
| 113 | - if (val & 0x1000) { | ||
| 114 | - s->status |= 0x0020; | ||
| 115 | + if (val & MII_BMCR_AUTOEN) { | ||
| 116 | + s->status |= MII_BMSR_AN_COMP; | ||
| 117 | } | ||
| 118 | } | ||
| 119 | break; | ||
| 120 | - case 4: /* Auto-neg advertisement */ | ||
| 121 | - s->advertise = (val & 0x2d7f) | 0x80; | ||
| 122 | + case MII_ANAR: | ||
| 123 | + s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM | | ||
| 124 | + MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 | | ||
| 125 | + MII_ANAR_SELECT)) | ||
| 126 | + | MII_ANAR_TX; | ||
| 127 | break; | ||
| 128 | case 30: /* Interrupt mask */ | ||
| 129 | s->int_mask = val & 0xff; | ||
| 130 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) | ||
| 131 | /* Autonegotiation status mirrors link status. */ | ||
| 132 | if (link_down) { | ||
| 133 | trace_lan9118_phy_update_link("down"); | ||
| 134 | - s->status &= ~0x0024; | ||
| 135 | + s->status &= ~(MII_BMSR_AN_COMP | MII_BMSR_LINK_ST); | ||
| 136 | s->ints |= PHY_INT_DOWN; | ||
| 137 | } else { | ||
| 138 | trace_lan9118_phy_update_link("up"); | ||
| 139 | - s->status |= 0x0024; | ||
| 140 | + s->status |= MII_BMSR_AN_COMP | MII_BMSR_LINK_ST; | ||
| 141 | s->ints |= PHY_INT_ENERGYON; | ||
| 142 | s->ints |= PHY_INT_AUTONEG_COMPLETE; | ||
| 143 | } | ||
| 144 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_reset(Lan9118PhyState *s) | ||
| 145 | { | ||
| 146 | trace_lan9118_phy_reset(); | ||
| 147 | |||
| 148 | - s->control = 0x3000; | ||
| 149 | - s->status = 0x7809; | ||
| 150 | - s->advertise = 0x01e1; | ||
| 151 | + s->control = MII_BMCR_AUTOEN | MII_BMCR_SPEED100; | ||
| 152 | + s->status = MII_BMSR_100TX_FD | ||
| 153 | + | MII_BMSR_100TX_HD | ||
| 154 | + | MII_BMSR_10T_FD | ||
| 155 | + | MII_BMSR_10T_HD | ||
| 156 | + | MII_BMSR_AUTONEG | ||
| 157 | + | MII_BMSR_EXTCAP; | ||
| 158 | + s->advertise = MII_ANAR_TXFD | ||
| 159 | + | MII_ANAR_TX | ||
| 160 | + | MII_ANAR_10FD | ||
| 161 | + | MII_ANAR_10 | ||
| 162 | + | MII_ANAR_CSMACD; | ||
| 163 | s->int_mask = 0; | ||
| 164 | s->ints = 0; | ||
| 165 | lan9118_phy_update_link(s, s->link_down); | ||
| 166 | -- | ||
| 167 | 2.34.1 | diff view generated by jsdifflib |
| 1 | From: Doug Brown <doug@schmorgal.com> | 1 | From: Bernhard Beschow <shentey@gmail.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The interrupt level should be 0 or 1. The existing code was using the | 3 | The real device advertises this mode and the device model already advertises |
| 4 | interrupt flags to determine the level. In the only machine currently | 4 | 100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to |
| 5 | supported (xlnx-versal-virt), the GICv3 was masking off all bits except | 5 | make the model more realistic. |
| 6 | bit 0 when applying it, resulting in the IRQ never being delivered. | ||
| 7 | 6 | ||
| 8 | Signed-off-by: Doug Brown <doug@schmorgal.com> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 9 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | 8 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> |
| 10 | Reviewed-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | 9 | Tested-by: Guenter Roeck <linux@roeck-us.net> |
| 11 | Message-id: 20240827034927.66659-2-doug@schmorgal.com | 10 | Message-id: 20241102125724.532843-6-shentey@gmail.com |
| 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 13 | --- | 12 | --- |
| 14 | hw/net/can/xlnx-versal-canfd.c | 4 ++-- | 13 | hw/net/lan9118_phy.c | 4 ++-- |
| 15 | 1 file changed, 2 insertions(+), 2 deletions(-) | 14 | 1 file changed, 2 insertions(+), 2 deletions(-) |
| 16 | 15 | ||
| 17 | diff --git a/hw/net/can/xlnx-versal-canfd.c b/hw/net/can/xlnx-versal-canfd.c | 16 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c |
| 18 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 19 | --- a/hw/net/can/xlnx-versal-canfd.c | 18 | --- a/hw/net/lan9118_phy.c |
| 20 | +++ b/hw/net/can/xlnx-versal-canfd.c | 19 | +++ b/hw/net/lan9118_phy.c |
| 21 | @@ -XXX,XX +XXX,XX @@ static uint8_t canfd_dlc_array[8] = {8, 12, 16, 20, 24, 32, 48, 64}; | 20 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) |
| 22 | 21 | break; | |
| 23 | static void canfd_update_irq(XlnxVersalCANFDState *s) | 22 | case MII_ANAR: |
| 24 | { | 23 | s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM | |
| 25 | - unsigned int irq = s->regs[R_INTERRUPT_STATUS_REGISTER] & | 24 | - MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 | |
| 26 | - s->regs[R_INTERRUPT_ENABLE_REGISTER]; | 25 | - MII_ANAR_SELECT)) |
| 27 | + const bool irq = (s->regs[R_INTERRUPT_STATUS_REGISTER] & | 26 | + MII_ANAR_PAUSE | MII_ANAR_TXFD | MII_ANAR_10FD | |
| 28 | + s->regs[R_INTERRUPT_ENABLE_REGISTER]) != 0; | 27 | + MII_ANAR_10 | MII_ANAR_SELECT)) |
| 29 | g_autofree char *path = object_get_canonical_path(OBJECT(s)); | 28 | | MII_ANAR_TX; |
| 30 | 29 | break; | |
| 31 | /* RX watermark interrupts. */ | 30 | case 30: /* Interrupt mask */ |
| 32 | -- | 31 | -- |
| 33 | 2.34.1 | 32 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | For IEEE fused multiply-add, the (0 * inf) + NaN case should raise | ||
| 2 | Invalid for the multiplication of 0 by infinity. Currently we handle | ||
| 3 | this in the per-architecture ifdef ladder in pickNaNMulAdd(). | ||
| 4 | However, since this isn't really architecture specific we can hoist | ||
| 5 | it up to the generic code. | ||
| 1 | 6 | ||
| 7 | For the cases where the infzero test in pickNaNMulAdd was | ||
| 8 | returning 2, we can delete the check entirely and allow the | ||
| 9 | code to fall into the normal pick-a-NaN handling, because this | ||
| 10 | will return 2 anyway (input 'c' being the only NaN in this case). | ||
| 11 | For the cases where infzero was returning 3 to indicate "return | ||
| 12 | the default NaN", we must retain that "return 3". | ||
| 13 | |||
| 14 | For Arm, this looks like it might be a behaviour change because we | ||
| 15 | used to set float_flag_invalid | float_flag_invalid_imz only if C is | ||
| 16 | a quiet NaN. However, it is not, because Arm target code never looks | ||
| 17 | at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we | ||
| 18 | already raised float_flag_invalid via the "abc_mask & | ||
| 19 | float_cmask_snan" check in pick_nan_muladd. | ||
| 20 | |||
| 21 | For any target architecture using the "default implementation" at the | ||
| 22 | bottom of the ifdef, this is a behaviour change but will be fixing a | ||
| 23 | bug (where we failed to raise the Invalid exception for (0 * inf + | ||
| 24 | QNaN). The architectures using the default case are: | ||
| 25 | * hppa | ||
| 26 | * i386 | ||
| 27 | * sh4 | ||
| 28 | * tricore | ||
| 29 | |||
| 30 | The x86, Tricore and SH4 CPU architecture manuals are clear that this | ||
| 31 | should have raised Invalid; HPPA is a bit vaguer but still seems | ||
| 32 | clear enough. | ||
| 33 | |||
| 34 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 35 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 36 | Message-id: 20241202131347.498124-2-peter.maydell@linaro.org | ||
| 37 | --- | ||
| 38 | fpu/softfloat-parts.c.inc | 13 +++++++------ | ||
| 39 | fpu/softfloat-specialize.c.inc | 29 +---------------------------- | ||
| 40 | 2 files changed, 8 insertions(+), 34 deletions(-) | ||
| 41 | |||
| 42 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc | ||
| 43 | index XXXXXXX..XXXXXXX 100644 | ||
| 44 | --- a/fpu/softfloat-parts.c.inc | ||
| 45 | +++ b/fpu/softfloat-parts.c.inc | ||
| 46 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
| 47 | int ab_mask, int abc_mask) | ||
| 48 | { | ||
| 49 | int which; | ||
| 50 | + bool infzero = (ab_mask == float_cmask_infzero); | ||
| 51 | |||
| 52 | if (unlikely(abc_mask & float_cmask_snan)) { | ||
| 53 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); | ||
| 54 | } | ||
| 55 | |||
| 56 | - which = pickNaNMulAdd(a->cls, b->cls, c->cls, | ||
| 57 | - ab_mask == float_cmask_infzero, s); | ||
| 58 | + if (infzero) { | ||
| 59 | + /* This is (0 * inf) + NaN or (inf * 0) + NaN */ | ||
| 60 | + float_raise(float_flag_invalid | float_flag_invalid_imz, s); | ||
| 61 | + } | ||
| 62 | + | ||
| 63 | + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); | ||
| 64 | |||
| 65 | if (s->default_nan_mode || which == 3) { | ||
| 66 | - /* | ||
| 67 | - * Note that this check is after pickNaNMulAdd so that function | ||
| 68 | - * has an opportunity to set the Invalid flag for infzero. | ||
| 69 | - */ | ||
| 70 | parts_default_nan(a, s); | ||
| 71 | return a; | ||
| 72 | } | ||
| 73 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 74 | index XXXXXXX..XXXXXXX 100644 | ||
| 75 | --- a/fpu/softfloat-specialize.c.inc | ||
| 76 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 77 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 78 | * the default NaN | ||
| 79 | */ | ||
| 80 | if (infzero && is_qnan(c_cls)) { | ||
| 81 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
| 82 | return 3; | ||
| 83 | } | ||
| 84 | |||
| 85 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 86 | * case sets InvalidOp and returns the default NaN | ||
| 87 | */ | ||
| 88 | if (infzero) { | ||
| 89 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
| 90 | return 3; | ||
| 91 | } | ||
| 92 | /* Prefer sNaN over qNaN, in the a, b, c order. */ | ||
| 93 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 94 | * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
| 95 | * case sets InvalidOp and returns the input value 'c' | ||
| 96 | */ | ||
| 97 | - if (infzero) { | ||
| 98 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
| 99 | - return 2; | ||
| 100 | - } | ||
| 101 | /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
| 102 | if (is_snan(c_cls)) { | ||
| 103 | return 2; | ||
| 104 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 105 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
| 106 | * case sets InvalidOp and returns the input value 'c' | ||
| 107 | */ | ||
| 108 | - if (infzero) { | ||
| 109 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
| 110 | - return 2; | ||
| 111 | - } | ||
| 112 | + | ||
| 113 | /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
| 114 | if (is_snan(c_cls)) { | ||
| 115 | return 2; | ||
| 116 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 117 | * to return an input NaN if we have one (ie c) rather than generating | ||
| 118 | * a default NaN | ||
| 119 | */ | ||
| 120 | - if (infzero) { | ||
| 121 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
| 122 | - return 2; | ||
| 123 | - } | ||
| 124 | |||
| 125 | /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
| 126 | * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
| 127 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 128 | return 1; | ||
| 129 | } | ||
| 130 | #elif defined(TARGET_RISCV) | ||
| 131 | - /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */ | ||
| 132 | - if (infzero) { | ||
| 133 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
| 134 | - } | ||
| 135 | return 3; /* default NaN */ | ||
| 136 | #elif defined(TARGET_S390X) | ||
| 137 | if (infzero) { | ||
| 138 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
| 139 | return 3; | ||
| 140 | } | ||
| 141 | |||
| 142 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 143 | return 2; | ||
| 144 | } | ||
| 145 | #elif defined(TARGET_SPARC) | ||
| 146 | - /* For (inf,0,nan) return c. */ | ||
| 147 | - if (infzero) { | ||
| 148 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
| 149 | - return 2; | ||
| 150 | - } | ||
| 151 | /* Prefer SNaN over QNaN, order C, B, A. */ | ||
| 152 | if (is_snan(c_cls)) { | ||
| 153 | return 2; | ||
| 154 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 155 | * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns | ||
| 156 | * an input NaN if we have one (ie c). | ||
| 157 | */ | ||
| 158 | - if (infzero) { | ||
| 159 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
| 160 | - return 2; | ||
| 161 | - } | ||
| 162 | if (status->use_first_nan) { | ||
| 163 | if (is_nan(a_cls)) { | ||
| 164 | return 0; | ||
| 165 | -- | ||
| 166 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | If the target sets default_nan_mode then we're always going to return | ||
| 2 | the default NaN, and pickNaNMulAdd() no longer has any side effects. | ||
| 3 | For consistency with pickNaN(), check for default_nan_mode before | ||
| 4 | calling pickNaNMulAdd(). | ||
| 1 | 5 | ||
| 6 | When we convert pickNaNMulAdd() to allow runtime selection of the NaN | ||
| 7 | propagation rule, this means we won't have to make the targets which | ||
| 8 | use default_nan_mode also set a propagation rule. | ||
| 9 | |||
| 10 | Since RiscV always uses default_nan_mode, this allows us to remove | ||
| 11 | its ifdef case from pickNaNMulAdd(). | ||
| 12 | |||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 15 | Message-id: 20241202131347.498124-3-peter.maydell@linaro.org | ||
| 16 | --- | ||
| 17 | fpu/softfloat-parts.c.inc | 8 ++++++-- | ||
| 18 | fpu/softfloat-specialize.c.inc | 9 +++++++-- | ||
| 19 | 2 files changed, 13 insertions(+), 4 deletions(-) | ||
| 20 | |||
| 21 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc | ||
| 22 | index XXXXXXX..XXXXXXX 100644 | ||
| 23 | --- a/fpu/softfloat-parts.c.inc | ||
| 24 | +++ b/fpu/softfloat-parts.c.inc | ||
| 25 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
| 26 | float_raise(float_flag_invalid | float_flag_invalid_imz, s); | ||
| 27 | } | ||
| 28 | |||
| 29 | - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); | ||
| 30 | + if (s->default_nan_mode) { | ||
| 31 | + which = 3; | ||
| 32 | + } else { | ||
| 33 | + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); | ||
| 34 | + } | ||
| 35 | |||
| 36 | - if (s->default_nan_mode || which == 3) { | ||
| 37 | + if (which == 3) { | ||
| 38 | parts_default_nan(a, s); | ||
| 39 | return a; | ||
| 40 | } | ||
| 41 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 42 | index XXXXXXX..XXXXXXX 100644 | ||
| 43 | --- a/fpu/softfloat-specialize.c.inc | ||
| 44 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 45 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
| 46 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 47 | bool infzero, float_status *status) | ||
| 48 | { | ||
| 49 | + /* | ||
| 50 | + * We guarantee not to require the target to tell us how to | ||
| 51 | + * pick a NaN if we're always returning the default NaN. | ||
| 52 | + * But if we're not in default-NaN mode then the target must | ||
| 53 | + * specify. | ||
| 54 | + */ | ||
| 55 | + assert(!status->default_nan_mode); | ||
| 56 | #if defined(TARGET_ARM) | ||
| 57 | /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns | ||
| 58 | * the default NaN | ||
| 59 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 60 | } else { | ||
| 61 | return 1; | ||
| 62 | } | ||
| 63 | -#elif defined(TARGET_RISCV) | ||
| 64 | - return 3; /* default NaN */ | ||
| 65 | #elif defined(TARGET_S390X) | ||
| 66 | if (infzero) { | ||
| 67 | return 3; | ||
| 68 | -- | ||
| 69 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | 1 | IEEE 758 does not define a fixed rule for what NaN to return in | |
| 2 | the case of a fused multiply-add of inf * 0 + NaN. Different | ||
| 3 | architectures thus do different things: | ||
| 4 | * some return the default NaN | ||
| 5 | * some return the input NaN | ||
| 6 | * Arm returns the default NaN if the input NaN is quiet, | ||
| 7 | and the input NaN if it is signalling | ||
| 8 | |||
| 9 | We want to make this logic be runtime selected rather than | ||
| 10 | hardcoded into the binary, because: | ||
| 11 | * this will let us have multiple targets in one QEMU binary | ||
| 12 | * the Arm FEAT_AFP architectural feature includes letting | ||
| 13 | the guest select a NaN propagation rule at runtime | ||
| 14 | |||
| 15 | In this commit we add an enum for the propagation rule, the field in | ||
| 16 | float_status, and the corresponding getters and setters. We change | ||
| 17 | pickNaNMulAdd to honour this, but because all targets still leave | ||
| 18 | this field at its default 0 value, the fallback logic will pick the | ||
| 19 | rule type with the old ifdef ladder. | ||
| 20 | |||
| 21 | Note that four architectures both use the muladd softfloat functions | ||
| 22 | and did not have a branch of the ifdef ladder to specify their | ||
| 23 | behaviour (and so were ending up with the "default" case, probably | ||
| 24 | wrongly): i386, HPPA, SH4 and Tricore. SH4 and Tricore both set | ||
| 25 | default_nan_mode, and so will never get into pickNaNMulAdd(). For | ||
| 26 | HPPA and i386 we retain the same behaviour as the old default-case, | ||
| 27 | which is to not ever return the default NaN. This might not be | ||
| 28 | correct but it is not a behaviour change. | ||
| 29 | |||
| 30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 31 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 32 | Message-id: 20241202131347.498124-4-peter.maydell@linaro.org | ||
| 33 | --- | ||
| 34 | include/fpu/softfloat-helpers.h | 11 ++++ | ||
| 35 | include/fpu/softfloat-types.h | 23 +++++++++ | ||
| 36 | fpu/softfloat-specialize.c.inc | 91 ++++++++++++++++++++++----------- | ||
| 37 | 3 files changed, 95 insertions(+), 30 deletions(-) | ||
| 38 | |||
| 39 | diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h | ||
| 40 | index XXXXXXX..XXXXXXX 100644 | ||
| 41 | --- a/include/fpu/softfloat-helpers.h | ||
| 42 | +++ b/include/fpu/softfloat-helpers.h | ||
| 43 | @@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule, | ||
| 44 | status->float_2nan_prop_rule = rule; | ||
| 45 | } | ||
| 46 | |||
| 47 | +static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, | ||
| 48 | + float_status *status) | ||
| 49 | +{ | ||
| 50 | + status->float_infzeronan_rule = rule; | ||
| 51 | +} | ||
| 52 | + | ||
| 53 | static inline void set_flush_to_zero(bool val, float_status *status) | ||
| 54 | { | ||
| 55 | status->flush_to_zero = val; | ||
| 56 | @@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status) | ||
| 57 | return status->float_2nan_prop_rule; | ||
| 58 | } | ||
| 59 | |||
| 60 | +static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status) | ||
| 61 | +{ | ||
| 62 | + return status->float_infzeronan_rule; | ||
| 63 | +} | ||
| 64 | + | ||
| 65 | static inline bool get_flush_to_zero(float_status *status) | ||
| 66 | { | ||
| 67 | return status->flush_to_zero; | ||
| 68 | diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h | ||
| 69 | index XXXXXXX..XXXXXXX 100644 | ||
| 70 | --- a/include/fpu/softfloat-types.h | ||
| 71 | +++ b/include/fpu/softfloat-types.h | ||
| 72 | @@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) { | ||
| 73 | float_2nan_prop_x87, | ||
| 74 | } Float2NaNPropRule; | ||
| 75 | |||
| 76 | +/* | ||
| 77 | + * Rule for result of fused multiply-add 0 * Inf + NaN. | ||
| 78 | + * This must be a NaN, but implementations differ on whether this | ||
| 79 | + * is the input NaN or the default NaN. | ||
| 80 | + * | ||
| 81 | + * You don't need to set this if default_nan_mode is enabled. | ||
| 82 | + * When not in default-NaN mode, it is an error for the target | ||
| 83 | + * not to set the rule in float_status if it uses muladd, and we | ||
| 84 | + * will assert if we need to handle an input NaN and no rule was | ||
| 85 | + * selected. | ||
| 86 | + */ | ||
| 87 | +typedef enum __attribute__((__packed__)) { | ||
| 88 | + /* No propagation rule specified */ | ||
| 89 | + float_infzeronan_none = 0, | ||
| 90 | + /* Result is never the default NaN (so always the input NaN) */ | ||
| 91 | + float_infzeronan_dnan_never, | ||
| 92 | + /* Result is always the default NaN */ | ||
| 93 | + float_infzeronan_dnan_always, | ||
| 94 | + /* Result is the default NaN if the input NaN is quiet */ | ||
| 95 | + float_infzeronan_dnan_if_qnan, | ||
| 96 | +} FloatInfZeroNaNRule; | ||
| 97 | + | ||
| 98 | /* | ||
| 99 | * Floating Point Status. Individual architectures may maintain | ||
| 100 | * several versions of float_status for different functions. The | ||
| 101 | @@ -XXX,XX +XXX,XX @@ typedef struct float_status { | ||
| 102 | FloatRoundMode float_rounding_mode; | ||
| 103 | FloatX80RoundPrec floatx80_rounding_precision; | ||
| 104 | Float2NaNPropRule float_2nan_prop_rule; | ||
| 105 | + FloatInfZeroNaNRule float_infzeronan_rule; | ||
| 106 | bool tininess_before_rounding; | ||
| 107 | /* should denormalised results go to zero and set the inexact flag? */ | ||
| 108 | bool flush_to_zero; | ||
| 109 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 110 | index XXXXXXX..XXXXXXX 100644 | ||
| 111 | --- a/fpu/softfloat-specialize.c.inc | ||
| 112 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 113 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
| 114 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 115 | bool infzero, float_status *status) | ||
| 116 | { | ||
| 117 | + FloatInfZeroNaNRule rule = status->float_infzeronan_rule; | ||
| 118 | + | ||
| 119 | /* | ||
| 120 | * We guarantee not to require the target to tell us how to | ||
| 121 | * pick a NaN if we're always returning the default NaN. | ||
| 122 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 123 | * specify. | ||
| 124 | */ | ||
| 125 | assert(!status->default_nan_mode); | ||
| 126 | + | ||
| 127 | + if (rule == float_infzeronan_none) { | ||
| 128 | + /* | ||
| 129 | + * Temporarily fall back to ifdef ladder | ||
| 130 | + */ | ||
| 131 | #if defined(TARGET_ARM) | ||
| 132 | - /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns | ||
| 133 | - * the default NaN | ||
| 134 | - */ | ||
| 135 | - if (infzero && is_qnan(c_cls)) { | ||
| 136 | - return 3; | ||
| 137 | + /* | ||
| 138 | + * For ARM, the (inf,zero,qnan) case returns the default NaN, | ||
| 139 | + * but (inf,zero,snan) returns the input NaN. | ||
| 140 | + */ | ||
| 141 | + rule = float_infzeronan_dnan_if_qnan; | ||
| 142 | +#elif defined(TARGET_MIPS) | ||
| 143 | + if (snan_bit_is_one(status)) { | ||
| 144 | + /* | ||
| 145 | + * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) | ||
| 146 | + * case sets InvalidOp and returns the default NaN | ||
| 147 | + */ | ||
| 148 | + rule = float_infzeronan_dnan_always; | ||
| 149 | + } else { | ||
| 150 | + /* | ||
| 151 | + * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
| 152 | + * case sets InvalidOp and returns the input value 'c' | ||
| 153 | + */ | ||
| 154 | + rule = float_infzeronan_dnan_never; | ||
| 155 | + } | ||
| 156 | +#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \ | ||
| 157 | + defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
| 158 | + defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
| 159 | + /* | ||
| 160 | + * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
| 161 | + * case sets InvalidOp and returns the input value 'c' | ||
| 162 | + */ | ||
| 163 | + /* | ||
| 164 | + * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
| 165 | + * to return an input NaN if we have one (ie c) rather than generating | ||
| 166 | + * a default NaN | ||
| 167 | + */ | ||
| 168 | + rule = float_infzeronan_dnan_never; | ||
| 169 | +#elif defined(TARGET_S390X) | ||
| 170 | + rule = float_infzeronan_dnan_always; | ||
| 171 | +#endif | ||
| 172 | } | ||
| 173 | |||
| 174 | + if (infzero) { | ||
| 175 | + /* | ||
| 176 | + * Inf * 0 + NaN -- some implementations return the default NaN here, | ||
| 177 | + * and some return the input NaN. | ||
| 178 | + */ | ||
| 179 | + switch (rule) { | ||
| 180 | + case float_infzeronan_dnan_never: | ||
| 181 | + return 2; | ||
| 182 | + case float_infzeronan_dnan_always: | ||
| 183 | + return 3; | ||
| 184 | + case float_infzeronan_dnan_if_qnan: | ||
| 185 | + return is_qnan(c_cls) ? 3 : 2; | ||
| 186 | + default: | ||
| 187 | + g_assert_not_reached(); | ||
| 188 | + } | ||
| 189 | + } | ||
| 190 | + | ||
| 191 | +#if defined(TARGET_ARM) | ||
| 192 | + | ||
| 193 | /* This looks different from the ARM ARM pseudocode, because the ARM ARM | ||
| 194 | * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. | ||
| 195 | */ | ||
| 196 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 197 | } | ||
| 198 | #elif defined(TARGET_MIPS) | ||
| 199 | if (snan_bit_is_one(status)) { | ||
| 200 | - /* | ||
| 201 | - * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) | ||
| 202 | - * case sets InvalidOp and returns the default NaN | ||
| 203 | - */ | ||
| 204 | - if (infzero) { | ||
| 205 | - return 3; | ||
| 206 | - } | ||
| 207 | /* Prefer sNaN over qNaN, in the a, b, c order. */ | ||
| 208 | if (is_snan(a_cls)) { | ||
| 209 | return 0; | ||
| 210 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 211 | return 2; | ||
| 212 | } | ||
| 213 | } else { | ||
| 214 | - /* | ||
| 215 | - * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
| 216 | - * case sets InvalidOp and returns the input value 'c' | ||
| 217 | - */ | ||
| 218 | /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
| 219 | if (is_snan(c_cls)) { | ||
| 220 | return 2; | ||
| 221 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 222 | } | ||
| 223 | } | ||
| 224 | #elif defined(TARGET_LOONGARCH64) | ||
| 225 | - /* | ||
| 226 | - * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
| 227 | - * case sets InvalidOp and returns the input value 'c' | ||
| 228 | - */ | ||
| 229 | - | ||
| 230 | /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
| 231 | if (is_snan(c_cls)) { | ||
| 232 | return 2; | ||
| 233 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 234 | return 1; | ||
| 235 | } | ||
| 236 | #elif defined(TARGET_PPC) | ||
| 237 | - /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
| 238 | - * to return an input NaN if we have one (ie c) rather than generating | ||
| 239 | - * a default NaN | ||
| 240 | - */ | ||
| 241 | - | ||
| 242 | /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
| 243 | * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
| 244 | */ | ||
| 245 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 246 | return 1; | ||
| 247 | } | ||
| 248 | #elif defined(TARGET_S390X) | ||
| 249 | - if (infzero) { | ||
| 250 | - return 3; | ||
| 251 | - } | ||
| 252 | - | ||
| 253 | if (is_snan(a_cls)) { | ||
| 254 | return 0; | ||
| 255 | } else if (is_snan(b_cls)) { | ||
| 256 | -- | ||
| 257 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Explicitly set a rule in the softfloat tests for the inf-zero-nan | ||
| 2 | muladd special case. In meson.build we put -DTARGET_ARM in fpcflags, | ||
| 3 | and so we should select here the Arm rule of | ||
| 4 | float_infzeronan_dnan_if_qnan. | ||
| 1 | 5 | ||
| 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Message-id: 20241202131347.498124-5-peter.maydell@linaro.org | ||
| 9 | --- | ||
| 10 | tests/fp/fp-bench.c | 5 +++++ | ||
| 11 | tests/fp/fp-test.c | 5 +++++ | ||
| 12 | 2 files changed, 10 insertions(+) | ||
| 13 | |||
| 14 | diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/tests/fp/fp-bench.c | ||
| 17 | +++ b/tests/fp/fp-bench.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static void run_bench(void) | ||
| 19 | { | ||
| 20 | bench_func_t f; | ||
| 21 | |||
| 22 | + /* | ||
| 23 | + * These implementation-defined choices for various things IEEE | ||
| 24 | + * doesn't specify match those used by the Arm architecture. | ||
| 25 | + */ | ||
| 26 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); | ||
| 27 | + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); | ||
| 28 | |||
| 29 | f = bench_funcs[operation][precision]; | ||
| 30 | g_assert(f); | ||
| 31 | diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c | ||
| 32 | index XXXXXXX..XXXXXXX 100644 | ||
| 33 | --- a/tests/fp/fp-test.c | ||
| 34 | +++ b/tests/fp/fp-test.c | ||
| 35 | @@ -XXX,XX +XXX,XX @@ void run_test(void) | ||
| 36 | { | ||
| 37 | unsigned int i; | ||
| 38 | |||
| 39 | + /* | ||
| 40 | + * These implementation-defined choices for various things IEEE | ||
| 41 | + * doesn't specify match those used by the Arm architecture. | ||
| 42 | + */ | ||
| 43 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); | ||
| 44 | + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); | ||
| 45 | |||
| 46 | genCases_setLevel(test_level); | ||
| 47 | verCases_maxErrorCount = n_max_errors; | ||
| 48 | -- | ||
| 49 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the FloatInfZeroNaNRule explicitly for the Arm target, | ||
| 2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
| 1 | 3 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-6-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/arm/cpu.c | 3 +++ | ||
| 9 | fpu/softfloat-specialize.c.inc | 8 +------- | ||
| 10 | 2 files changed, 4 insertions(+), 7 deletions(-) | ||
| 11 | |||
| 12 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/arm/cpu.c | ||
| 15 | +++ b/target/arm/cpu.c | ||
| 16 | @@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, | ||
| 17 | * * tininess-before-rounding | ||
| 18 | * * 2-input NaN propagation prefers SNaN over QNaN, and then | ||
| 19 | * operand A over operand B (see FPProcessNaNs() pseudocode) | ||
| 20 | + * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, | ||
| 21 | + * and the input NaN if it is signalling | ||
| 22 | */ | ||
| 23 | static void arm_set_default_fp_behaviours(float_status *s) | ||
| 24 | { | ||
| 25 | set_float_detect_tininess(float_tininess_before_rounding, s); | ||
| 26 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); | ||
| 27 | + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); | ||
| 28 | } | ||
| 29 | |||
| 30 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) | ||
| 31 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 32 | index XXXXXXX..XXXXXXX 100644 | ||
| 33 | --- a/fpu/softfloat-specialize.c.inc | ||
| 34 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 35 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 36 | /* | ||
| 37 | * Temporarily fall back to ifdef ladder | ||
| 38 | */ | ||
| 39 | -#if defined(TARGET_ARM) | ||
| 40 | - /* | ||
| 41 | - * For ARM, the (inf,zero,qnan) case returns the default NaN, | ||
| 42 | - * but (inf,zero,snan) returns the input NaN. | ||
| 43 | - */ | ||
| 44 | - rule = float_infzeronan_dnan_if_qnan; | ||
| 45 | -#elif defined(TARGET_MIPS) | ||
| 46 | +#if defined(TARGET_MIPS) | ||
| 47 | if (snan_bit_is_one(status)) { | ||
| 48 | /* | ||
| 49 | * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) | ||
| 50 | -- | ||
| 51 | 2.34.1 | diff view generated by jsdifflib |
| 1 | Convert the s390 CPU to the Resettable interface. This is slightly | 1 | Set the FloatInfZeroNaNRule explicitly for s390, so we |
|---|---|---|---|
| 2 | more involved than the other CPU types were (see commits | 2 | can remove the ifdef from pickNaNMulAdd(). |
| 3 | 9130cade5fc22..d66e64dd006df) because S390 has its own set of | ||
| 4 | different kinds of reset with different behaviours that it needs to | ||
| 5 | trigger. | ||
| 6 | |||
| 7 | We handle this by adding these reset types to the Resettable | ||
| 8 | ResetType enum. Now instead of having an underlying implementation | ||
| 9 | of reset that is s390-specific and which might be called either | ||
| 10 | directly or via the DeviceClass::reset method, we can implement only | ||
| 11 | the Resettable hold phase method, and have the places that need to | ||
| 12 | trigger an s390-specific reset type do so by calling | ||
| 13 | resettable_reset(). | ||
| 14 | |||
| 15 | The other option would have been to smuggle in the s390 reset | ||
| 16 | type via, for instance, a field in the CPU state that we set | ||
| 17 | in s390_do_cpu_initial_reset() etc and then examined in the | ||
| 18 | reset method, but doing it this way seems cleaner. | ||
| 19 | |||
| 20 | The motivation for this change is that this is the last caller | ||
| 21 | of the legacy device_class_set_parent_reset() function, and | ||
| 22 | removing that will let us clean up some glue code that we added | ||
| 23 | for the transition to three-phase reset. | ||
| 24 | 3 | ||
| 25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 26 | Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> | ||
| 27 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 28 | Acked-by: Thomas Huth <thuth@redhat.com> | 6 | Message-id: 20241202131347.498124-7-peter.maydell@linaro.org |
| 29 | Message-id: 20240830145812.1967042-4-peter.maydell@linaro.org | ||
| 30 | --- | 7 | --- |
| 31 | docs/devel/reset.rst | 10 ++++++++++ | 8 | target/s390x/cpu.c | 2 ++ |
| 32 | include/hw/resettable.h | 2 ++ | 9 | fpu/softfloat-specialize.c.inc | 2 -- |
| 33 | target/s390x/cpu.h | 21 ++++----------------- | 10 | 2 files changed, 2 insertions(+), 2 deletions(-) |
| 34 | target/s390x/cpu.c | 38 +++++++++++++++++--------------------- | ||
| 35 | target/s390x/sigp.c | 8 ++------ | ||
| 36 | 5 files changed, 35 insertions(+), 44 deletions(-) | ||
| 37 | 11 | ||
| 38 | diff --git a/docs/devel/reset.rst b/docs/devel/reset.rst | ||
| 39 | index XXXXXXX..XXXXXXX 100644 | ||
| 40 | --- a/docs/devel/reset.rst | ||
| 41 | +++ b/docs/devel/reset.rst | ||
| 42 | @@ -XXX,XX +XXX,XX @@ The Resettable interface handles reset types with an enum ``ResetType``: | ||
| 43 | value on each cold reset, such as RNG seed information, and which they | ||
| 44 | must not reinitialize on a snapshot-load reset. | ||
| 45 | |||
| 46 | +``RESET_TYPE_S390_CPU_NORMAL`` | ||
| 47 | + This is only used for S390 CPU objects; it clears interrupts, stops | ||
| 48 | + processing, and clears the TLB, but does not touch register contents. | ||
| 49 | + | ||
| 50 | +``RESET_TYPE_S390_CPU_INITIAL`` | ||
| 51 | + This is only used for S390 CPU objects; it does everything | ||
| 52 | + ``RESET_TYPE_S390_CPU_NORMAL`` does and also clears the PSW, prefix, | ||
| 53 | + FPC, timer and control registers. It does not touch gprs, fprs or acrs. | ||
| 54 | + | ||
| 55 | + | ||
| 56 | Devices which implement reset methods must treat any unknown ``ResetType`` | ||
| 57 | as equivalent to ``RESET_TYPE_COLD``; this will reduce the amount of | ||
| 58 | existing code we need to change if we add more types in future. | ||
| 59 | diff --git a/include/hw/resettable.h b/include/hw/resettable.h | ||
| 60 | index XXXXXXX..XXXXXXX 100644 | ||
| 61 | --- a/include/hw/resettable.h | ||
| 62 | +++ b/include/hw/resettable.h | ||
| 63 | @@ -XXX,XX +XXX,XX @@ typedef struct ResettableState ResettableState; | ||
| 64 | typedef enum ResetType { | ||
| 65 | RESET_TYPE_COLD, | ||
| 66 | RESET_TYPE_SNAPSHOT_LOAD, | ||
| 67 | + RESET_TYPE_S390_CPU_INITIAL, | ||
| 68 | + RESET_TYPE_S390_CPU_NORMAL, | ||
| 69 | } ResetType; | ||
| 70 | |||
| 71 | /* | ||
| 72 | diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h | ||
| 73 | index XXXXXXX..XXXXXXX 100644 | ||
| 74 | --- a/target/s390x/cpu.h | ||
| 75 | +++ b/target/s390x/cpu.h | ||
| 76 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { | ||
| 77 | uint32_t irqstate_saved_size; | ||
| 78 | }; | ||
| 79 | |||
| 80 | -typedef enum cpu_reset_type { | ||
| 81 | - S390_CPU_RESET_NORMAL, | ||
| 82 | - S390_CPU_RESET_INITIAL, | ||
| 83 | - S390_CPU_RESET_CLEAR, | ||
| 84 | -} cpu_reset_type; | ||
| 85 | - | ||
| 86 | /** | ||
| 87 | * S390CPUClass: | ||
| 88 | * @parent_realize: The parent class' realize handler. | ||
| 89 | - * @parent_reset: The parent class' reset handler. | ||
| 90 | + * @parent_phases: The parent class' reset phase handlers. | ||
| 91 | * @load_normal: Performs a load normal. | ||
| 92 | - * @cpu_reset: Performs a CPU reset. | ||
| 93 | - * @initial_cpu_reset: Performs an initial CPU reset. | ||
| 94 | * | ||
| 95 | * An S/390 CPU model. | ||
| 96 | */ | ||
| 97 | @@ -XXX,XX +XXX,XX @@ struct S390CPUClass { | ||
| 98 | const char *desc; | ||
| 99 | |||
| 100 | DeviceRealize parent_realize; | ||
| 101 | - DeviceReset parent_reset; | ||
| 102 | + ResettablePhases parent_phases; | ||
| 103 | void (*load_normal)(CPUState *cpu); | ||
| 104 | - void (*reset)(CPUState *cpu, cpu_reset_type type); | ||
| 105 | }; | ||
| 106 | |||
| 107 | #ifndef CONFIG_USER_ONLY | ||
| 108 | @@ -XXX,XX +XXX,XX @@ static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg) | ||
| 109 | |||
| 110 | static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg) | ||
| 111 | { | ||
| 112 | - S390CPUClass *scc = S390_CPU_GET_CLASS(cs); | ||
| 113 | - | ||
| 114 | - scc->reset(cs, S390_CPU_RESET_NORMAL); | ||
| 115 | + resettable_reset(OBJECT(cs), RESET_TYPE_S390_CPU_NORMAL); | ||
| 116 | } | ||
| 117 | |||
| 118 | static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg) | ||
| 119 | { | ||
| 120 | - S390CPUClass *scc = S390_CPU_GET_CLASS(cs); | ||
| 121 | - | ||
| 122 | - scc->reset(cs, S390_CPU_RESET_INITIAL); | ||
| 123 | + resettable_reset(OBJECT(cs), RESET_TYPE_S390_CPU_INITIAL); | ||
| 124 | } | ||
| 125 | |||
| 126 | static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg) | ||
| 127 | diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c | 12 | diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c |
| 128 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
| 129 | --- a/target/s390x/cpu.c | 14 | --- a/target/s390x/cpu.c |
| 130 | +++ b/target/s390x/cpu.c | 15 | +++ b/target/s390x/cpu.c |
| 131 | @@ -XXX,XX +XXX,XX @@ | 16 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) |
| 132 | #include "sysemu/hw_accel.h" | ||
| 133 | #include "hw/qdev-properties.h" | ||
| 134 | #include "hw/qdev-properties-system.h" | ||
| 135 | +#include "hw/resettable.h" | ||
| 136 | #include "fpu/softfloat-helpers.h" | ||
| 137 | #include "disas/capstone.h" | ||
| 138 | #include "sysemu/tcg.h" | ||
| 139 | @@ -XXX,XX +XXX,XX @@ static void s390_query_cpu_fast(CPUState *cpu, CpuInfoFast *value) | ||
| 140 | #endif | ||
| 141 | } | ||
| 142 | |||
| 143 | -/* S390CPUClass::reset() */ | ||
| 144 | -static void s390_cpu_reset(CPUState *s, cpu_reset_type type) | ||
| 145 | +/* S390CPUClass Resettable reset_hold phase method */ | ||
| 146 | +static void s390_cpu_reset_hold(Object *obj, ResetType type) | ||
| 147 | { | ||
| 148 | - S390CPU *cpu = S390_CPU(s); | ||
| 149 | + S390CPU *cpu = S390_CPU(obj); | ||
| 150 | S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); | ||
| 151 | CPUS390XState *env = &cpu->env; | ||
| 152 | - DeviceState *dev = DEVICE(s); | ||
| 153 | |||
| 154 | - scc->parent_reset(dev); | ||
| 155 | + if (scc->parent_phases.hold) { | ||
| 156 | + scc->parent_phases.hold(obj, type); | ||
| 157 | + } | ||
| 158 | cpu->env.sigp_order = 0; | ||
| 159 | s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu); | ||
| 160 | |||
| 161 | switch (type) { | ||
| 162 | - case S390_CPU_RESET_CLEAR: | ||
| 163 | + default: | ||
| 164 | + /* RESET_TYPE_COLD: power on or "clear" reset */ | ||
| 165 | memset(env, 0, offsetof(CPUS390XState, start_initial_reset_fields)); | ||
| 166 | /* fall through */ | ||
| 167 | - case S390_CPU_RESET_INITIAL: | ||
| 168 | + case RESET_TYPE_S390_CPU_INITIAL: | ||
| 169 | /* initial reset does not clear everything! */ | ||
| 170 | memset(&env->start_initial_reset_fields, 0, | ||
| 171 | offsetof(CPUS390XState, start_normal_reset_fields) - | ||
| 172 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type) | ||
| 173 | set_float_detect_tininess(float_tininess_before_rounding, | 17 | set_float_detect_tininess(float_tininess_before_rounding, |
| 174 | &env->fpu_status); | 18 | &env->fpu_status); |
| 19 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status); | ||
| 20 | + set_float_infzeronan_rule(float_infzeronan_dnan_always, | ||
| 21 | + &env->fpu_status); | ||
| 175 | /* fall through */ | 22 | /* fall through */ |
| 176 | - case S390_CPU_RESET_NORMAL: | 23 | case RESET_TYPE_S390_CPU_NORMAL: |
| 177 | + case RESET_TYPE_S390_CPU_NORMAL: | ||
| 178 | env->psw.mask &= ~PSW_MASK_RI; | 24 | env->psw.mask &= ~PSW_MASK_RI; |
| 179 | memset(&env->start_normal_reset_fields, 0, | 25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
| 180 | offsetof(CPUS390XState, end_reset_fields) - | 26 | index XXXXXXX..XXXXXXX 100644 |
| 181 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type) | 27 | --- a/fpu/softfloat-specialize.c.inc |
| 182 | env->pfault_token = -1UL; | 28 | +++ b/fpu/softfloat-specialize.c.inc |
| 183 | env->bpbc = false; | 29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 184 | break; | 30 | * a default NaN |
| 185 | - default: | 31 | */ |
| 186 | - g_assert_not_reached(); | 32 | rule = float_infzeronan_dnan_never; |
| 33 | -#elif defined(TARGET_S390X) | ||
| 34 | - rule = float_infzeronan_dnan_always; | ||
| 35 | #endif | ||
| 187 | } | 36 | } |
| 188 | 37 | ||
| 189 | /* Reset state inside the kernel that we cannot access yet from QEMU. */ | ||
| 190 | if (kvm_enabled()) { | ||
| 191 | switch (type) { | ||
| 192 | - case S390_CPU_RESET_CLEAR: | ||
| 193 | + default: | ||
| 194 | kvm_s390_reset_vcpu_clear(cpu); | ||
| 195 | break; | ||
| 196 | - case S390_CPU_RESET_INITIAL: | ||
| 197 | + case RESET_TYPE_S390_CPU_INITIAL: | ||
| 198 | kvm_s390_reset_vcpu_initial(cpu); | ||
| 199 | break; | ||
| 200 | - case S390_CPU_RESET_NORMAL: | ||
| 201 | + case RESET_TYPE_S390_CPU_NORMAL: | ||
| 202 | kvm_s390_reset_vcpu_normal(cpu); | ||
| 203 | break; | ||
| 204 | } | ||
| 205 | @@ -XXX,XX +XXX,XX @@ static Property s390x_cpu_properties[] = { | ||
| 206 | DEFINE_PROP_END_OF_LIST() | ||
| 207 | }; | ||
| 208 | |||
| 209 | -static void s390_cpu_reset_full(DeviceState *dev) | ||
| 210 | -{ | ||
| 211 | - CPUState *s = CPU(dev); | ||
| 212 | - return s390_cpu_reset(s, S390_CPU_RESET_CLEAR); | ||
| 213 | -} | ||
| 214 | - | ||
| 215 | #ifdef CONFIG_TCG | ||
| 216 | #include "hw/core/tcg-cpu-ops.h" | ||
| 217 | |||
| 218 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) | ||
| 219 | S390CPUClass *scc = S390_CPU_CLASS(oc); | ||
| 220 | CPUClass *cc = CPU_CLASS(scc); | ||
| 221 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
| 222 | + ResettableClass *rc = RESETTABLE_CLASS(oc); | ||
| 223 | |||
| 224 | device_class_set_parent_realize(dc, s390_cpu_realizefn, | ||
| 225 | &scc->parent_realize); | ||
| 226 | device_class_set_props(dc, s390x_cpu_properties); | ||
| 227 | dc->user_creatable = true; | ||
| 228 | |||
| 229 | - device_class_set_parent_reset(dc, s390_cpu_reset_full, &scc->parent_reset); | ||
| 230 | + resettable_class_set_parent_phases(rc, NULL, s390_cpu_reset_hold, NULL, | ||
| 231 | + &scc->parent_phases); | ||
| 232 | |||
| 233 | - scc->reset = s390_cpu_reset; | ||
| 234 | cc->class_by_name = s390_cpu_class_by_name, | ||
| 235 | cc->has_work = s390_cpu_has_work; | ||
| 236 | cc->mmu_index = s390x_cpu_mmu_index; | ||
| 237 | diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c | ||
| 238 | index XXXXXXX..XXXXXXX 100644 | ||
| 239 | --- a/target/s390x/sigp.c | ||
| 240 | +++ b/target/s390x/sigp.c | ||
| 241 | @@ -XXX,XX +XXX,XX @@ static void sigp_restart(CPUState *cs, run_on_cpu_data arg) | ||
| 242 | |||
| 243 | static void sigp_initial_cpu_reset(CPUState *cs, run_on_cpu_data arg) | ||
| 244 | { | ||
| 245 | - S390CPU *cpu = S390_CPU(cs); | ||
| 246 | - S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); | ||
| 247 | SigpInfo *si = arg.host_ptr; | ||
| 248 | |||
| 249 | cpu_synchronize_state(cs); | ||
| 250 | - scc->reset(cs, S390_CPU_RESET_INITIAL); | ||
| 251 | + resettable_reset(OBJECT(cs), RESET_TYPE_S390_CPU_INITIAL); | ||
| 252 | cpu_synchronize_post_reset(cs); | ||
| 253 | si->cc = SIGP_CC_ORDER_CODE_ACCEPTED; | ||
| 254 | } | ||
| 255 | |||
| 256 | static void sigp_cpu_reset(CPUState *cs, run_on_cpu_data arg) | ||
| 257 | { | ||
| 258 | - S390CPU *cpu = S390_CPU(cs); | ||
| 259 | - S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); | ||
| 260 | SigpInfo *si = arg.host_ptr; | ||
| 261 | |||
| 262 | cpu_synchronize_state(cs); | ||
| 263 | - scc->reset(cs, S390_CPU_RESET_NORMAL); | ||
| 264 | + resettable_reset(OBJECT(cs), RESET_TYPE_S390_CPU_NORMAL); | ||
| 265 | cpu_synchronize_post_reset(cs); | ||
| 266 | si->cc = SIGP_CC_ORDER_CODE_ACCEPTED; | ||
| 267 | } | ||
| 268 | -- | 38 | -- |
| 269 | 2.34.1 | 39 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the FloatInfZeroNaNRule explicitly for the PPC target, | ||
| 2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
| 1 | 3 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-8-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/ppc/cpu_init.c | 7 +++++++ | ||
| 9 | fpu/softfloat-specialize.c.inc | 7 +------ | ||
| 10 | 2 files changed, 8 insertions(+), 6 deletions(-) | ||
| 11 | |||
| 12 | diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/ppc/cpu_init.c | ||
| 15 | +++ b/target/ppc/cpu_init.c | ||
| 16 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) | ||
| 17 | */ | ||
| 18 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); | ||
| 19 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); | ||
| 20 | + /* | ||
| 21 | + * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
| 22 | + * to return an input NaN if we have one (ie c) rather than generating | ||
| 23 | + * a default NaN | ||
| 24 | + */ | ||
| 25 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
| 26 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); | ||
| 27 | |||
| 28 | for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { | ||
| 29 | ppc_spr_t *spr = &env->spr_cb[i]; | ||
| 30 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 31 | index XXXXXXX..XXXXXXX 100644 | ||
| 32 | --- a/fpu/softfloat-specialize.c.inc | ||
| 33 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 34 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 35 | */ | ||
| 36 | rule = float_infzeronan_dnan_never; | ||
| 37 | } | ||
| 38 | -#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \ | ||
| 39 | +#elif defined(TARGET_SPARC) || \ | ||
| 40 | defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
| 41 | defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
| 42 | /* | ||
| 43 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
| 44 | * case sets InvalidOp and returns the input value 'c' | ||
| 45 | */ | ||
| 46 | - /* | ||
| 47 | - * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
| 48 | - * to return an input NaN if we have one (ie c) rather than generating | ||
| 49 | - * a default NaN | ||
| 50 | - */ | ||
| 51 | rule = float_infzeronan_dnan_never; | ||
| 52 | #endif | ||
| 53 | } | ||
| 54 | -- | ||
| 55 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the FloatInfZeroNaNRule explicitly for the MIPS target, | ||
| 2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
| 1 | 3 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-9-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/mips/fpu_helper.h | 9 +++++++++ | ||
| 9 | target/mips/msa.c | 4 ++++ | ||
| 10 | fpu/softfloat-specialize.c.inc | 16 +--------------- | ||
| 11 | 3 files changed, 14 insertions(+), 15 deletions(-) | ||
| 12 | |||
| 13 | diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/target/mips/fpu_helper.h | ||
| 16 | +++ b/target/mips/fpu_helper.h | ||
| 17 | @@ -XXX,XX +XXX,XX @@ static inline void restore_flush_mode(CPUMIPSState *env) | ||
| 18 | static inline void restore_snan_bit_mode(CPUMIPSState *env) | ||
| 19 | { | ||
| 20 | bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); | ||
| 21 | + FloatInfZeroNaNRule izn_rule; | ||
| 22 | |||
| 23 | /* | ||
| 24 | * With nan2008, SNaNs are silenced in the usual way. | ||
| 25 | @@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) | ||
| 26 | */ | ||
| 27 | set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status); | ||
| 28 | set_default_nan_mode(!nan2008, &env->active_fpu.fp_status); | ||
| 29 | + /* | ||
| 30 | + * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) | ||
| 31 | + * case sets InvalidOp and returns the default NaN. | ||
| 32 | + * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
| 33 | + * case sets InvalidOp and returns the input value 'c'. | ||
| 34 | + */ | ||
| 35 | + izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always; | ||
| 36 | + set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); | ||
| 37 | } | ||
| 38 | |||
| 39 | static inline void restore_fp_status(CPUMIPSState *env) | ||
| 40 | diff --git a/target/mips/msa.c b/target/mips/msa.c | ||
| 41 | index XXXXXXX..XXXXXXX 100644 | ||
| 42 | --- a/target/mips/msa.c | ||
| 43 | +++ b/target/mips/msa.c | ||
| 44 | @@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env) | ||
| 45 | |||
| 46 | /* set proper signanling bit meaning ("1" means "quiet") */ | ||
| 47 | set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); | ||
| 48 | + | ||
| 49 | + /* Inf * 0 + NaN returns the input NaN */ | ||
| 50 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, | ||
| 51 | + &env->active_tc.msa_fp_status); | ||
| 52 | } | ||
| 53 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 54 | index XXXXXXX..XXXXXXX 100644 | ||
| 55 | --- a/fpu/softfloat-specialize.c.inc | ||
| 56 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 57 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 58 | /* | ||
| 59 | * Temporarily fall back to ifdef ladder | ||
| 60 | */ | ||
| 61 | -#if defined(TARGET_MIPS) | ||
| 62 | - if (snan_bit_is_one(status)) { | ||
| 63 | - /* | ||
| 64 | - * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) | ||
| 65 | - * case sets InvalidOp and returns the default NaN | ||
| 66 | - */ | ||
| 67 | - rule = float_infzeronan_dnan_always; | ||
| 68 | - } else { | ||
| 69 | - /* | ||
| 70 | - * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
| 71 | - * case sets InvalidOp and returns the input value 'c' | ||
| 72 | - */ | ||
| 73 | - rule = float_infzeronan_dnan_never; | ||
| 74 | - } | ||
| 75 | -#elif defined(TARGET_SPARC) || \ | ||
| 76 | +#if defined(TARGET_SPARC) || \ | ||
| 77 | defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
| 78 | defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
| 79 | /* | ||
| 80 | -- | ||
| 81 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the FloatInfZeroNaNRule explicitly for the SPARC target, | ||
| 2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
| 1 | 3 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-10-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/sparc/cpu.c | 2 ++ | ||
| 9 | fpu/softfloat-specialize.c.inc | 3 +-- | ||
| 10 | 2 files changed, 3 insertions(+), 2 deletions(-) | ||
| 11 | |||
| 12 | diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/sparc/cpu.c | ||
| 15 | +++ b/target/sparc/cpu.c | ||
| 16 | @@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) | ||
| 17 | * the CPU state struct so it won't get zeroed on reset. | ||
| 18 | */ | ||
| 19 | set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); | ||
| 20 | + /* For inf * 0 + NaN, return the input NaN */ | ||
| 21 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
| 22 | |||
| 23 | cpu_exec_realizefn(cs, &local_err); | ||
| 24 | if (local_err != NULL) { | ||
| 25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 26 | index XXXXXXX..XXXXXXX 100644 | ||
| 27 | --- a/fpu/softfloat-specialize.c.inc | ||
| 28 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 30 | /* | ||
| 31 | * Temporarily fall back to ifdef ladder | ||
| 32 | */ | ||
| 33 | -#if defined(TARGET_SPARC) || \ | ||
| 34 | - defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
| 35 | +#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
| 36 | defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
| 37 | /* | ||
| 38 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
| 39 | -- | ||
| 40 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the FloatInfZeroNaNRule explicitly for the xtensa target, | ||
| 2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
| 1 | 3 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-11-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/xtensa/cpu.c | 2 ++ | ||
| 9 | fpu/softfloat-specialize.c.inc | 2 +- | ||
| 10 | 2 files changed, 3 insertions(+), 1 deletion(-) | ||
| 11 | |||
| 12 | diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/xtensa/cpu.c | ||
| 15 | +++ b/target/xtensa/cpu.c | ||
| 16 | @@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type) | ||
| 17 | reset_mmu(env); | ||
| 18 | cs->halted = env->runstall; | ||
| 19 | #endif | ||
| 20 | + /* For inf * 0 + NaN, return the input NaN */ | ||
| 21 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
| 22 | set_no_signaling_nans(!dfpu, &env->fp_status); | ||
| 23 | xtensa_use_first_nan(env, !dfpu); | ||
| 24 | } | ||
| 25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 26 | index XXXXXXX..XXXXXXX 100644 | ||
| 27 | --- a/fpu/softfloat-specialize.c.inc | ||
| 28 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 30 | /* | ||
| 31 | * Temporarily fall back to ifdef ladder | ||
| 32 | */ | ||
| 33 | -#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
| 34 | +#if defined(TARGET_HPPA) || \ | ||
| 35 | defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
| 36 | /* | ||
| 37 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
| 38 | -- | ||
| 39 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the FloatInfZeroNaNRule explicitly for the x86 target. | ||
| 1 | 2 | ||
| 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 5 | Message-id: 20241202131347.498124-12-peter.maydell@linaro.org | ||
| 6 | --- | ||
| 7 | target/i386/tcg/fpu_helper.c | 7 +++++++ | ||
| 8 | fpu/softfloat-specialize.c.inc | 2 +- | ||
| 9 | 2 files changed, 8 insertions(+), 1 deletion(-) | ||
| 10 | |||
| 11 | diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c | ||
| 12 | index XXXXXXX..XXXXXXX 100644 | ||
| 13 | --- a/target/i386/tcg/fpu_helper.c | ||
| 14 | +++ b/target/i386/tcg/fpu_helper.c | ||
| 15 | @@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env) | ||
| 16 | */ | ||
| 17 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status); | ||
| 18 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status); | ||
| 19 | + /* | ||
| 20 | + * Only SSE has multiply-add instructions. In the SDM Section 14.5.2 | ||
| 21 | + * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is | ||
| 22 | + * specified -- for 0 * inf + NaN the input NaN is selected, and if | ||
| 23 | + * there are multiple input NaNs they are selected in the order a, b, c. | ||
| 24 | + */ | ||
| 25 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); | ||
| 26 | } | ||
| 27 | |||
| 28 | static inline uint8_t save_exception_flags(CPUX86State *env) | ||
| 29 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 30 | index XXXXXXX..XXXXXXX 100644 | ||
| 31 | --- a/fpu/softfloat-specialize.c.inc | ||
| 32 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 33 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 34 | * Temporarily fall back to ifdef ladder | ||
| 35 | */ | ||
| 36 | #if defined(TARGET_HPPA) || \ | ||
| 37 | - defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
| 38 | + defined(TARGET_LOONGARCH) | ||
| 39 | /* | ||
| 40 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
| 41 | * case sets InvalidOp and returns the input value 'c' | ||
| 42 | -- | ||
| 43 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the FloatInfZeroNaNRule explicitly for the loongarch target. | ||
| 1 | 2 | ||
| 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 5 | Message-id: 20241202131347.498124-13-peter.maydell@linaro.org | ||
| 6 | --- | ||
| 7 | target/loongarch/tcg/fpu_helper.c | 5 +++++ | ||
| 8 | fpu/softfloat-specialize.c.inc | 7 +------ | ||
| 9 | 2 files changed, 6 insertions(+), 6 deletions(-) | ||
| 10 | |||
| 11 | diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c | ||
| 12 | index XXXXXXX..XXXXXXX 100644 | ||
| 13 | --- a/target/loongarch/tcg/fpu_helper.c | ||
| 14 | +++ b/target/loongarch/tcg/fpu_helper.c | ||
| 15 | @@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env) | ||
| 16 | &env->fp_status); | ||
| 17 | set_flush_to_zero(0, &env->fp_status); | ||
| 18 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); | ||
| 19 | + /* | ||
| 20 | + * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
| 21 | + * case sets InvalidOp and returns the input value 'c' | ||
| 22 | + */ | ||
| 23 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
| 24 | } | ||
| 25 | |||
| 26 | int ieee_ex_to_loongarch(int xcpt) | ||
| 27 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 28 | index XXXXXXX..XXXXXXX 100644 | ||
| 29 | --- a/fpu/softfloat-specialize.c.inc | ||
| 30 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 31 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 32 | /* | ||
| 33 | * Temporarily fall back to ifdef ladder | ||
| 34 | */ | ||
| 35 | -#if defined(TARGET_HPPA) || \ | ||
| 36 | - defined(TARGET_LOONGARCH) | ||
| 37 | - /* | ||
| 38 | - * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
| 39 | - * case sets InvalidOp and returns the input value 'c' | ||
| 40 | - */ | ||
| 41 | +#if defined(TARGET_HPPA) | ||
| 42 | rule = float_infzeronan_dnan_never; | ||
| 43 | #endif | ||
| 44 | } | ||
| 45 | -- | ||
| 46 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the FloatInfZeroNaNRule explicitly for the HPPA target, | ||
| 2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
| 1 | 3 | ||
| 4 | As this is the last target to be converted to explicitly setting | ||
| 5 | the rule, we can remove the fallback code in pickNaNMulAdd() | ||
| 6 | entirely. | ||
| 7 | |||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 10 | Message-id: 20241202131347.498124-14-peter.maydell@linaro.org | ||
| 11 | --- | ||
| 12 | target/hppa/fpu_helper.c | 2 ++ | ||
| 13 | fpu/softfloat-specialize.c.inc | 13 +------------ | ||
| 14 | 2 files changed, 3 insertions(+), 12 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/target/hppa/fpu_helper.c | ||
| 19 | +++ b/target/hppa/fpu_helper.c | ||
| 20 | @@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env) | ||
| 21 | * HPPA does note implement a CPU reset method at all... | ||
| 22 | */ | ||
| 23 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); | ||
| 24 | + /* For inf * 0 + NaN, return the input NaN */ | ||
| 25 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
| 26 | } | ||
| 27 | |||
| 28 | void cpu_hppa_loaded_fr0(CPUHPPAState *env) | ||
| 29 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 30 | index XXXXXXX..XXXXXXX 100644 | ||
| 31 | --- a/fpu/softfloat-specialize.c.inc | ||
| 32 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 33 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
| 34 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 35 | bool infzero, float_status *status) | ||
| 36 | { | ||
| 37 | - FloatInfZeroNaNRule rule = status->float_infzeronan_rule; | ||
| 38 | - | ||
| 39 | /* | ||
| 40 | * We guarantee not to require the target to tell us how to | ||
| 41 | * pick a NaN if we're always returning the default NaN. | ||
| 42 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 43 | */ | ||
| 44 | assert(!status->default_nan_mode); | ||
| 45 | |||
| 46 | - if (rule == float_infzeronan_none) { | ||
| 47 | - /* | ||
| 48 | - * Temporarily fall back to ifdef ladder | ||
| 49 | - */ | ||
| 50 | -#if defined(TARGET_HPPA) | ||
| 51 | - rule = float_infzeronan_dnan_never; | ||
| 52 | -#endif | ||
| 53 | - } | ||
| 54 | - | ||
| 55 | if (infzero) { | ||
| 56 | /* | ||
| 57 | * Inf * 0 + NaN -- some implementations return the default NaN here, | ||
| 58 | * and some return the input NaN. | ||
| 59 | */ | ||
| 60 | - switch (rule) { | ||
| 61 | + switch (status->float_infzeronan_rule) { | ||
| 62 | case float_infzeronan_dnan_never: | ||
| 63 | return 2; | ||
| 64 | case float_infzeronan_dnan_always: | ||
| 65 | -- | ||
| 66 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | The new implementation of pickNaNMulAdd() will find it convenient | ||
| 2 | to know whether at least one of the three arguments to the muladd | ||
| 3 | was a signaling NaN. We already calculate that in the caller, | ||
| 4 | so pass it in as a new bool have_snan. | ||
| 1 | 5 | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20241202131347.498124-15-peter.maydell@linaro.org | ||
| 9 | --- | ||
| 10 | fpu/softfloat-parts.c.inc | 5 +++-- | ||
| 11 | fpu/softfloat-specialize.c.inc | 2 +- | ||
| 12 | 2 files changed, 4 insertions(+), 3 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/fpu/softfloat-parts.c.inc | ||
| 17 | +++ b/fpu/softfloat-parts.c.inc | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
| 19 | { | ||
| 20 | int which; | ||
| 21 | bool infzero = (ab_mask == float_cmask_infzero); | ||
| 22 | + bool have_snan = (abc_mask & float_cmask_snan); | ||
| 23 | |||
| 24 | - if (unlikely(abc_mask & float_cmask_snan)) { | ||
| 25 | + if (unlikely(have_snan)) { | ||
| 26 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); | ||
| 27 | } | ||
| 28 | |||
| 29 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
| 30 | if (s->default_nan_mode) { | ||
| 31 | which = 3; | ||
| 32 | } else { | ||
| 33 | - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); | ||
| 34 | + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s); | ||
| 35 | } | ||
| 36 | |||
| 37 | if (which == 3) { | ||
| 38 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 39 | index XXXXXXX..XXXXXXX 100644 | ||
| 40 | --- a/fpu/softfloat-specialize.c.inc | ||
| 41 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 42 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
| 43 | | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN | ||
| 44 | *----------------------------------------------------------------------------*/ | ||
| 45 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 46 | - bool infzero, float_status *status) | ||
| 47 | + bool infzero, bool have_snan, float_status *status) | ||
| 48 | { | ||
| 49 | /* | ||
| 50 | * We guarantee not to require the target to tell us how to | ||
| 51 | -- | ||
| 52 | 2.34.1 | diff view generated by jsdifflib |
| 1 | From: Danny Canter <danny_canter@apple.com> | 1 | IEEE 758 does not define a fixed rule for which NaN to pick as the |
|---|---|---|---|
| 2 | 2 | result if both operands of a 3-operand fused multiply-add operation | |
| 3 | This patch's main focus is to use the previously added | 3 | are NaNs. As a result different architectures have ended up with |
| 4 | hvf_get_physical_address_range to inform VM creation | 4 | different rules for propagating NaNs. |
| 5 | about the IPA size we need for the VM, so we can extend | 5 | |
| 6 | the default 36b IPA size and support VMs with 64+GB of | 6 | QEMU currently hardcodes the NaN propagation logic into the binary |
| 7 | RAM. This is done by freezing the memory map, computing | 7 | because pickNaNMulAdd() has an ifdef ladder for different targets. |
| 8 | the highest GPA and then (depending on if the platform | 8 | We want to make the propagation rule instead be selectable at |
| 9 | supports an IPA size that large) telling the kernel to | 9 | runtime, because: |
| 10 | use a size >= for the VM. In pursuit of this a couple of | 10 | * this will let us have multiple targets in one QEMU binary |
| 11 | things related to how we handle the physical address range | 11 | * the Arm FEAT_AFP architectural feature includes letting |
| 12 | we expose to guests were altered, but for an explanation of | 12 | the guest select a NaN propagation rule at runtime |
| 13 | what we were doing: | 13 | |
| 14 | 14 | In this commit we add an enum for the propagation rule, the field in | |
| 15 | Today, to get the IPA size we were reading id_aa64mmfr0_el1's | 15 | float_status, and the corresponding getters and setters. We change |
| 16 | PARange field from a newly made vcpu. Unfortunately, HVF just | 16 | pickNaNMulAdd to honour this, but because all targets still leave |
| 17 | returns the hosts PARange directly for the initial value and | 17 | this field at its default 0 value, the fallback logic will pick the |
| 18 | not the IPA size that will actually back the VM, so we believe | 18 | rule type with the old ifdef ladder. |
| 19 | we have much more address space than we actually do today it seems. | 19 | |
| 20 | 20 | It's valid not to set a propagation rule if default_nan_mode is | |
| 21 | Starting in macOS 13.0 some APIs were introduced to be able to | 21 | enabled, because in that case there's no need to pick a NaN; all the |
| 22 | query the maximum IPA size the kernel supports, and to set the IPA | 22 | callers of pickNaNMulAdd() catch this case and skip calling it. |
| 23 | size for a given VM. However, this still has a couple of issues | 23 | |
| 24 | on < macOS 15. Up until macOS 15 (and if the hardware supported | ||
| 25 | it) the max IPA size was 39 bits which is not a valid PARange | ||
| 26 | value, so we can't clamp down what we advertise in the vcpu's | ||
| 27 | id_aa64mmfr0_el1 to our IPA size. Starting in macOS 15 however, | ||
| 28 | the maximum IPA size is 40 bits (if it's supported in the hardware | ||
| 29 | as well) which is also a valid PARange value so we can set our IPA | ||
| 30 | size to the maximum as well as clamp down the PARange we advertise | ||
| 31 | to the guest. This allows VMs with 64+ GB of RAM and should fix the | ||
| 32 | oddness of the PARange situation as well. | ||
| 33 | |||
| 34 | Signed-off-by: Danny Canter <danny_canter@apple.com> | ||
| 35 | Message-id: 20240828111552.93482-4-danny_canter@apple.com | ||
| 36 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 37 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 25 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 26 | Message-id: 20241202131347.498124-16-peter.maydell@linaro.org | ||
| 38 | --- | 27 | --- |
| 39 | target/arm/hvf_arm.h | 19 +++++++++++++ | 28 | include/fpu/softfloat-helpers.h | 11 +++ |
| 40 | target/arm/internals.h | 19 +++++++++++++ | 29 | include/fpu/softfloat-types.h | 55 +++++++++++ |
| 41 | accel/hvf/hvf-accel-ops.c | 12 ++++++++- | 30 | fpu/softfloat-specialize.c.inc | 167 ++++++++------------------------ |
| 42 | hw/arm/virt.c | 31 +++++++++++++++++++++- | 31 | 3 files changed, 107 insertions(+), 126 deletions(-) |
| 43 | target/arm/hvf/hvf.c | 56 ++++++++++++++++++++++++++++++++++++++- | 32 | |
| 44 | target/arm/ptw.c | 15 +++++++++++ | 33 | diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h |
| 45 | 6 files changed, 149 insertions(+), 3 deletions(-) | ||
| 46 | |||
| 47 | diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h | ||
| 48 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
| 49 | --- a/target/arm/hvf_arm.h | 35 | --- a/include/fpu/softfloat-helpers.h |
| 50 | +++ b/target/arm/hvf_arm.h | 36 | +++ b/include/fpu/softfloat-helpers.h |
| 51 | @@ -XXX,XX +XXX,XX @@ void hvf_arm_init_debug(void); | 37 | @@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule, |
| 52 | 38 | status->float_2nan_prop_rule = rule; | |
| 53 | void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu); | 39 | } |
| 54 | 40 | ||
| 55 | +#ifdef CONFIG_HVF | 41 | +static inline void set_float_3nan_prop_rule(Float3NaNPropRule rule, |
| 56 | + | 42 | + float_status *status) |
| 57 | +uint32_t hvf_arm_get_default_ipa_bit_size(void); | ||
| 58 | +uint32_t hvf_arm_get_max_ipa_bit_size(void); | ||
| 59 | + | ||
| 60 | +#else | ||
| 61 | + | ||
| 62 | +static inline uint32_t hvf_arm_get_default_ipa_bit_size(void) | ||
| 63 | +{ | 43 | +{ |
| 64 | + return 0; | 44 | + status->float_3nan_prop_rule = rule; |
| 65 | +} | 45 | +} |
| 66 | + | 46 | + |
| 67 | +static inline uint32_t hvf_arm_get_max_ipa_bit_size(void) | 47 | static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, |
| 48 | float_status *status) | ||
| 49 | { | ||
| 50 | @@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status) | ||
| 51 | return status->float_2nan_prop_rule; | ||
| 52 | } | ||
| 53 | |||
| 54 | +static inline Float3NaNPropRule get_float_3nan_prop_rule(float_status *status) | ||
| 68 | +{ | 55 | +{ |
| 69 | + return 0; | 56 | + return status->float_3nan_prop_rule; |
| 70 | +} | 57 | +} |
| 71 | + | 58 | + |
| 72 | +#endif | 59 | static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status) |
| 73 | + | 60 | { |
| 61 | return status->float_infzeronan_rule; | ||
| 62 | diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h | ||
| 63 | index XXXXXXX..XXXXXXX 100644 | ||
| 64 | --- a/include/fpu/softfloat-types.h | ||
| 65 | +++ b/include/fpu/softfloat-types.h | ||
| 66 | @@ -XXX,XX +XXX,XX @@ this code that are retained. | ||
| 67 | #ifndef SOFTFLOAT_TYPES_H | ||
| 68 | #define SOFTFLOAT_TYPES_H | ||
| 69 | |||
| 70 | +#include "hw/registerfields.h" | ||
| 71 | + | ||
| 72 | /* | ||
| 73 | * Software IEC/IEEE floating-point types. | ||
| 74 | */ | ||
| 75 | @@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) { | ||
| 76 | float_2nan_prop_x87, | ||
| 77 | } Float2NaNPropRule; | ||
| 78 | |||
| 79 | +/* | ||
| 80 | + * 3-input NaN propagation rule, for fused multiply-add. Individual | ||
| 81 | + * architectures have different rules for which input NaN is | ||
| 82 | + * propagated to the output when there is more than one NaN on the | ||
| 83 | + * input. | ||
| 84 | + * | ||
| 85 | + * If default_nan_mode is enabled then it is valid not to set a NaN | ||
| 86 | + * propagation rule, because the softfloat code guarantees not to try | ||
| 87 | + * to pick a NaN to propagate in default NaN mode. When not in | ||
| 88 | + * default-NaN mode, it is an error for the target not to set the rule | ||
| 89 | + * in float_status if it uses a muladd, and we will assert if we need | ||
| 90 | + * to handle an input NaN and no rule was selected. | ||
| 91 | + * | ||
| 92 | + * The naming scheme for Float3NaNPropRule values is: | ||
| 93 | + * float_3nan_prop_s_abc: | ||
| 94 | + * = "Prefer SNaN over QNaN, then operand A over B over C" | ||
| 95 | + * float_3nan_prop_abc: | ||
| 96 | + * = "Prefer A over B over C regardless of SNaN vs QNAN" | ||
| 97 | + * | ||
| 98 | + * For QEMU, the multiply-add operation is A * B + C. | ||
| 99 | + */ | ||
| 100 | + | ||
| 101 | +/* | ||
| 102 | + * We set the Float3NaNPropRule enum values up so we can select the | ||
| 103 | + * right value in pickNaNMulAdd in a data driven way. | ||
| 104 | + */ | ||
| 105 | +FIELD(3NAN, 1ST, 0, 2) /* which operand is most preferred ? */ | ||
| 106 | +FIELD(3NAN, 2ND, 2, 2) /* which operand is next most preferred ? */ | ||
| 107 | +FIELD(3NAN, 3RD, 4, 2) /* which operand is least preferred ? */ | ||
| 108 | +FIELD(3NAN, SNAN, 6, 1) /* do we prefer SNaN over QNaN ? */ | ||
| 109 | + | ||
| 110 | +#define PROPRULE(X, Y, Z) \ | ||
| 111 | + ((X << R_3NAN_1ST_SHIFT) | (Y << R_3NAN_2ND_SHIFT) | (Z << R_3NAN_3RD_SHIFT)) | ||
| 112 | + | ||
| 113 | +typedef enum __attribute__((__packed__)) { | ||
| 114 | + float_3nan_prop_none = 0, /* No propagation rule specified */ | ||
| 115 | + float_3nan_prop_abc = PROPRULE(0, 1, 2), | ||
| 116 | + float_3nan_prop_acb = PROPRULE(0, 2, 1), | ||
| 117 | + float_3nan_prop_bac = PROPRULE(1, 0, 2), | ||
| 118 | + float_3nan_prop_bca = PROPRULE(1, 2, 0), | ||
| 119 | + float_3nan_prop_cab = PROPRULE(2, 0, 1), | ||
| 120 | + float_3nan_prop_cba = PROPRULE(2, 1, 0), | ||
| 121 | + float_3nan_prop_s_abc = float_3nan_prop_abc | R_3NAN_SNAN_MASK, | ||
| 122 | + float_3nan_prop_s_acb = float_3nan_prop_acb | R_3NAN_SNAN_MASK, | ||
| 123 | + float_3nan_prop_s_bac = float_3nan_prop_bac | R_3NAN_SNAN_MASK, | ||
| 124 | + float_3nan_prop_s_bca = float_3nan_prop_bca | R_3NAN_SNAN_MASK, | ||
| 125 | + float_3nan_prop_s_cab = float_3nan_prop_cab | R_3NAN_SNAN_MASK, | ||
| 126 | + float_3nan_prop_s_cba = float_3nan_prop_cba | R_3NAN_SNAN_MASK, | ||
| 127 | +} Float3NaNPropRule; | ||
| 128 | + | ||
| 129 | +#undef PROPRULE | ||
| 130 | + | ||
| 131 | /* | ||
| 132 | * Rule for result of fused multiply-add 0 * Inf + NaN. | ||
| 133 | * This must be a NaN, but implementations differ on whether this | ||
| 134 | @@ -XXX,XX +XXX,XX @@ typedef struct float_status { | ||
| 135 | FloatRoundMode float_rounding_mode; | ||
| 136 | FloatX80RoundPrec floatx80_rounding_precision; | ||
| 137 | Float2NaNPropRule float_2nan_prop_rule; | ||
| 138 | + Float3NaNPropRule float_3nan_prop_rule; | ||
| 139 | FloatInfZeroNaNRule float_infzeronan_rule; | ||
| 140 | bool tininess_before_rounding; | ||
| 141 | /* should denormalised results go to zero and set the inexact flag? */ | ||
| 142 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 143 | index XXXXXXX..XXXXXXX 100644 | ||
| 144 | --- a/fpu/softfloat-specialize.c.inc | ||
| 145 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 146 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
| 147 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 148 | bool infzero, bool have_snan, float_status *status) | ||
| 149 | { | ||
| 150 | + FloatClass cls[3] = { a_cls, b_cls, c_cls }; | ||
| 151 | + Float3NaNPropRule rule = status->float_3nan_prop_rule; | ||
| 152 | + int which; | ||
| 153 | + | ||
| 154 | /* | ||
| 155 | * We guarantee not to require the target to tell us how to | ||
| 156 | * pick a NaN if we're always returning the default NaN. | ||
| 157 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 158 | } | ||
| 159 | } | ||
| 160 | |||
| 161 | + if (rule == float_3nan_prop_none) { | ||
| 162 | #if defined(TARGET_ARM) | ||
| 163 | - | ||
| 164 | - /* This looks different from the ARM ARM pseudocode, because the ARM ARM | ||
| 165 | - * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. | ||
| 166 | - */ | ||
| 167 | - if (is_snan(c_cls)) { | ||
| 168 | - return 2; | ||
| 169 | - } else if (is_snan(a_cls)) { | ||
| 170 | - return 0; | ||
| 171 | - } else if (is_snan(b_cls)) { | ||
| 172 | - return 1; | ||
| 173 | - } else if (is_qnan(c_cls)) { | ||
| 174 | - return 2; | ||
| 175 | - } else if (is_qnan(a_cls)) { | ||
| 176 | - return 0; | ||
| 177 | - } else { | ||
| 178 | - return 1; | ||
| 179 | - } | ||
| 180 | + /* | ||
| 181 | + * This looks different from the ARM ARM pseudocode, because the ARM ARM | ||
| 182 | + * puts the operands to a fused mac operation (a*b)+c in the order c,a,b | ||
| 183 | + */ | ||
| 184 | + rule = float_3nan_prop_s_cab; | ||
| 185 | #elif defined(TARGET_MIPS) | ||
| 186 | - if (snan_bit_is_one(status)) { | ||
| 187 | - /* Prefer sNaN over qNaN, in the a, b, c order. */ | ||
| 188 | - if (is_snan(a_cls)) { | ||
| 189 | - return 0; | ||
| 190 | - } else if (is_snan(b_cls)) { | ||
| 191 | - return 1; | ||
| 192 | - } else if (is_snan(c_cls)) { | ||
| 193 | - return 2; | ||
| 194 | - } else if (is_qnan(a_cls)) { | ||
| 195 | - return 0; | ||
| 196 | - } else if (is_qnan(b_cls)) { | ||
| 197 | - return 1; | ||
| 198 | + if (snan_bit_is_one(status)) { | ||
| 199 | + rule = float_3nan_prop_s_abc; | ||
| 200 | } else { | ||
| 201 | - return 2; | ||
| 202 | + rule = float_3nan_prop_s_cab; | ||
| 203 | } | ||
| 204 | - } else { | ||
| 205 | - /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
| 206 | - if (is_snan(c_cls)) { | ||
| 207 | - return 2; | ||
| 208 | - } else if (is_snan(a_cls)) { | ||
| 209 | - return 0; | ||
| 210 | - } else if (is_snan(b_cls)) { | ||
| 211 | - return 1; | ||
| 212 | - } else if (is_qnan(c_cls)) { | ||
| 213 | - return 2; | ||
| 214 | - } else if (is_qnan(a_cls)) { | ||
| 215 | - return 0; | ||
| 216 | - } else { | ||
| 217 | - return 1; | ||
| 218 | - } | ||
| 219 | - } | ||
| 220 | #elif defined(TARGET_LOONGARCH64) | ||
| 221 | - /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
| 222 | - if (is_snan(c_cls)) { | ||
| 223 | - return 2; | ||
| 224 | - } else if (is_snan(a_cls)) { | ||
| 225 | - return 0; | ||
| 226 | - } else if (is_snan(b_cls)) { | ||
| 227 | - return 1; | ||
| 228 | - } else if (is_qnan(c_cls)) { | ||
| 229 | - return 2; | ||
| 230 | - } else if (is_qnan(a_cls)) { | ||
| 231 | - return 0; | ||
| 232 | - } else { | ||
| 233 | - return 1; | ||
| 234 | - } | ||
| 235 | + rule = float_3nan_prop_s_cab; | ||
| 236 | #elif defined(TARGET_PPC) | ||
| 237 | - /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
| 238 | - * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
| 239 | - */ | ||
| 240 | - if (is_nan(a_cls)) { | ||
| 241 | - return 0; | ||
| 242 | - } else if (is_nan(c_cls)) { | ||
| 243 | - return 2; | ||
| 244 | - } else { | ||
| 245 | - return 1; | ||
| 246 | - } | ||
| 247 | + /* | ||
| 248 | + * If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
| 249 | + * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
| 250 | + */ | ||
| 251 | + rule = float_3nan_prop_acb; | ||
| 252 | #elif defined(TARGET_S390X) | ||
| 253 | - if (is_snan(a_cls)) { | ||
| 254 | - return 0; | ||
| 255 | - } else if (is_snan(b_cls)) { | ||
| 256 | - return 1; | ||
| 257 | - } else if (is_snan(c_cls)) { | ||
| 258 | - return 2; | ||
| 259 | - } else if (is_qnan(a_cls)) { | ||
| 260 | - return 0; | ||
| 261 | - } else if (is_qnan(b_cls)) { | ||
| 262 | - return 1; | ||
| 263 | - } else { | ||
| 264 | - return 2; | ||
| 265 | - } | ||
| 266 | + rule = float_3nan_prop_s_abc; | ||
| 267 | #elif defined(TARGET_SPARC) | ||
| 268 | - /* Prefer SNaN over QNaN, order C, B, A. */ | ||
| 269 | - if (is_snan(c_cls)) { | ||
| 270 | - return 2; | ||
| 271 | - } else if (is_snan(b_cls)) { | ||
| 272 | - return 1; | ||
| 273 | - } else if (is_snan(a_cls)) { | ||
| 274 | - return 0; | ||
| 275 | - } else if (is_qnan(c_cls)) { | ||
| 276 | - return 2; | ||
| 277 | - } else if (is_qnan(b_cls)) { | ||
| 278 | - return 1; | ||
| 279 | - } else { | ||
| 280 | - return 0; | ||
| 281 | - } | ||
| 282 | + rule = float_3nan_prop_s_cba; | ||
| 283 | #elif defined(TARGET_XTENSA) | ||
| 284 | - /* | ||
| 285 | - * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns | ||
| 286 | - * an input NaN if we have one (ie c). | ||
| 287 | - */ | ||
| 288 | - if (status->use_first_nan) { | ||
| 289 | - if (is_nan(a_cls)) { | ||
| 290 | - return 0; | ||
| 291 | - } else if (is_nan(b_cls)) { | ||
| 292 | - return 1; | ||
| 293 | + if (status->use_first_nan) { | ||
| 294 | + rule = float_3nan_prop_abc; | ||
| 295 | } else { | ||
| 296 | - return 2; | ||
| 297 | + rule = float_3nan_prop_cba; | ||
| 298 | } | ||
| 299 | - } else { | ||
| 300 | - if (is_nan(c_cls)) { | ||
| 301 | - return 2; | ||
| 302 | - } else if (is_nan(b_cls)) { | ||
| 303 | - return 1; | ||
| 304 | - } else { | ||
| 305 | - return 0; | ||
| 306 | - } | ||
| 307 | - } | ||
| 308 | #else | ||
| 309 | - /* A default implementation: prefer a to b to c. | ||
| 310 | - * This is unlikely to actually match any real implementation. | ||
| 311 | - */ | ||
| 312 | - if (is_nan(a_cls)) { | ||
| 313 | - return 0; | ||
| 314 | - } else if (is_nan(b_cls)) { | ||
| 315 | - return 1; | ||
| 316 | - } else { | ||
| 317 | - return 2; | ||
| 318 | - } | ||
| 319 | + rule = float_3nan_prop_abc; | ||
| 74 | #endif | 320 | #endif |
| 75 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
| 76 | index XXXXXXX..XXXXXXX 100644 | ||
| 77 | --- a/target/arm/internals.h | ||
| 78 | +++ b/target/arm/internals.h | ||
| 79 | @@ -XXX,XX +XXX,XX @@ static inline void update_spsel(CPUARMState *env, uint32_t imm) | ||
| 80 | */ | ||
| 81 | unsigned int arm_pamax(ARMCPU *cpu); | ||
| 82 | |||
| 83 | +/* | ||
| 84 | + * round_down_to_parange_index | ||
| 85 | + * @bit_size: uint8_t | ||
| 86 | + * | ||
| 87 | + * Rounds down the bit_size supplied to the first supported ARM physical | ||
| 88 | + * address range and returns the index for this. The index is intended to | ||
| 89 | + * be used to set ID_AA64MMFR0_EL1's PARANGE bits. | ||
| 90 | + */ | ||
| 91 | +uint8_t round_down_to_parange_index(uint8_t bit_size); | ||
| 92 | + | ||
| 93 | +/* | ||
| 94 | + * round_down_to_parange_bit_size | ||
| 95 | + * @bit_size: uint8_t | ||
| 96 | + * | ||
| 97 | + * Rounds down the bit_size supplied to the first supported ARM physical | ||
| 98 | + * address range bit size and returns this. | ||
| 99 | + */ | ||
| 100 | +uint8_t round_down_to_parange_bit_size(uint8_t bit_size); | ||
| 101 | + | ||
| 102 | /* Return true if extended addresses are enabled. | ||
| 103 | * This is always the case if our translation regime is 64 bit, | ||
| 104 | * but depends on TTBCR.EAE for 32 bit. | ||
| 105 | diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c | ||
| 106 | index XXXXXXX..XXXXXXX 100644 | ||
| 107 | --- a/accel/hvf/hvf-accel-ops.c | ||
| 108 | +++ b/accel/hvf/hvf-accel-ops.c | ||
| 109 | @@ -XXX,XX +XXX,XX @@ | ||
| 110 | #include "exec/address-spaces.h" | ||
| 111 | #include "exec/exec-all.h" | ||
| 112 | #include "gdbstub/enums.h" | ||
| 113 | +#include "hw/boards.h" | ||
| 114 | #include "sysemu/cpus.h" | ||
| 115 | #include "sysemu/hvf.h" | ||
| 116 | #include "sysemu/hvf_int.h" | ||
| 117 | @@ -XXX,XX +XXX,XX @@ static int hvf_accel_init(MachineState *ms) | ||
| 118 | int x; | ||
| 119 | hv_return_t ret; | ||
| 120 | HVFState *s; | ||
| 121 | + int pa_range = 36; | ||
| 122 | + MachineClass *mc = MACHINE_GET_CLASS(ms); | ||
| 123 | |||
| 124 | - ret = hvf_arch_vm_create(ms, 0); | ||
| 125 | + if (mc->hvf_get_physical_address_range) { | ||
| 126 | + pa_range = mc->hvf_get_physical_address_range(ms); | ||
| 127 | + if (pa_range < 0) { | ||
| 128 | + return -EINVAL; | ||
| 129 | + } | ||
| 130 | + } | 321 | + } |
| 131 | + | 322 | + |
| 132 | + ret = hvf_arch_vm_create(ms, (uint32_t)pa_range); | 323 | + assert(rule != float_3nan_prop_none); |
| 133 | assert_hvf_ok(ret); | 324 | + if (have_snan && (rule & R_3NAN_SNAN_MASK)) { |
| 134 | 325 | + /* We have at least one SNaN input and should prefer it */ | |
| 135 | s = g_new0(HVFState, 1); | 326 | + do { |
| 136 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 327 | + which = rule & R_3NAN_1ST_MASK; |
| 137 | index XXXXXXX..XXXXXXX 100644 | 328 | + rule >>= R_3NAN_1ST_LENGTH; |
| 138 | --- a/hw/arm/virt.c | 329 | + } while (!is_snan(cls[which])); |
| 139 | +++ b/hw/arm/virt.c | ||
| 140 | @@ -XXX,XX +XXX,XX @@ | ||
| 141 | #include "hw/intc/arm_gicv3_its_common.h" | ||
| 142 | #include "hw/irq.h" | ||
| 143 | #include "kvm_arm.h" | ||
| 144 | +#include "hvf_arm.h" | ||
| 145 | #include "hw/firmware/smbios.h" | ||
| 146 | #include "qapi/visitor.h" | ||
| 147 | #include "qapi/qapi-visit-common.h" | ||
| 148 | @@ -XXX,XX +XXX,XX @@ static int virt_kvm_type(MachineState *ms, const char *type_str) | ||
| 149 | |||
| 150 | static int virt_hvf_get_physical_address_range(MachineState *ms) | ||
| 151 | { | ||
| 152 | - return 0; | ||
| 153 | + VirtMachineState *vms = VIRT_MACHINE(ms); | ||
| 154 | + | ||
| 155 | + int default_ipa_size = hvf_arm_get_default_ipa_bit_size(); | ||
| 156 | + int max_ipa_size = hvf_arm_get_max_ipa_bit_size(); | ||
| 157 | + | ||
| 158 | + /* We freeze the memory map to compute the highest gpa */ | ||
| 159 | + virt_set_memmap(vms, max_ipa_size); | ||
| 160 | + | ||
| 161 | + int requested_ipa_size = 64 - clz64(vms->highest_gpa); | ||
| 162 | + | ||
| 163 | + /* | ||
| 164 | + * If we're <= the default IPA size just use the default. | ||
| 165 | + * If we're above the default but below the maximum, round up to | ||
| 166 | + * the maximum. hvf_arm_get_max_ipa_bit_size() conveniently only | ||
| 167 | + * returns values that are valid ARM PARange values. | ||
| 168 | + */ | ||
| 169 | + if (requested_ipa_size <= default_ipa_size) { | ||
| 170 | + requested_ipa_size = default_ipa_size; | ||
| 171 | + } else if (requested_ipa_size <= max_ipa_size) { | ||
| 172 | + requested_ipa_size = max_ipa_size; | ||
| 173 | + } else { | 330 | + } else { |
| 174 | + error_report("-m and ,maxmem option values " | 331 | + do { |
| 175 | + "require an IPA range (%d bits) larger than " | 332 | + which = rule & R_3NAN_1ST_MASK; |
| 176 | + "the one supported by the host (%d bits)", | 333 | + rule >>= R_3NAN_1ST_LENGTH; |
| 177 | + requested_ipa_size, max_ipa_size); | 334 | + } while (!is_nan(cls[which])); |
| 178 | + return -1; | ||
| 179 | + } | 335 | + } |
| 180 | + | 336 | + return which; |
| 181 | + return requested_ipa_size; | ||
| 182 | } | 337 | } |
| 183 | 338 | ||
| 184 | static void virt_machine_class_init(ObjectClass *oc, void *data) | 339 | /*---------------------------------------------------------------------------- |
| 185 | diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c | ||
| 186 | index XXXXXXX..XXXXXXX 100644 | ||
| 187 | --- a/target/arm/hvf/hvf.c | ||
| 188 | +++ b/target/arm/hvf/hvf.c | ||
| 189 | @@ -XXX,XX +XXX,XX @@ | ||
| 190 | #include <mach/mach_time.h> | ||
| 191 | |||
| 192 | #include "exec/address-spaces.h" | ||
| 193 | +#include "hw/boards.h" | ||
| 194 | #include "hw/irq.h" | ||
| 195 | #include "qemu/main-loop.h" | ||
| 196 | #include "sysemu/cpus.h" | ||
| 197 | @@ -XXX,XX +XXX,XX @@ void hvf_arm_init_debug(void) | ||
| 198 | |||
| 199 | static void hvf_wfi(CPUState *cpu); | ||
| 200 | |||
| 201 | +static uint32_t chosen_ipa_bit_size; | ||
| 202 | + | ||
| 203 | typedef struct HVFVTimer { | ||
| 204 | /* Vtimer value during migration and paused state */ | ||
| 205 | uint64_t vtimer_val; | ||
| 206 | @@ -XXX,XX +XXX,XX @@ static uint64_t hvf_get_reg(CPUState *cpu, int rt) | ||
| 207 | return val; | ||
| 208 | } | ||
| 209 | |||
| 210 | +static void clamp_id_aa64mmfr0_parange_to_ipa_size(uint64_t *id_aa64mmfr0) | ||
| 211 | +{ | ||
| 212 | + uint32_t ipa_size = chosen_ipa_bit_size ? | ||
| 213 | + chosen_ipa_bit_size : hvf_arm_get_max_ipa_bit_size(); | ||
| 214 | + | ||
| 215 | + /* Clamp down the PARange to the IPA size the kernel supports. */ | ||
| 216 | + uint8_t index = round_down_to_parange_index(ipa_size); | ||
| 217 | + *id_aa64mmfr0 = (*id_aa64mmfr0 & ~R_ID_AA64MMFR0_PARANGE_MASK) | index; | ||
| 218 | +} | ||
| 219 | + | ||
| 220 | static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 221 | { | ||
| 222 | ARMISARegisters host_isar = {}; | ||
| 223 | @@ -XXX,XX +XXX,XX @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 224 | r |= hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr); | ||
| 225 | r |= hv_vcpu_destroy(fd); | ||
| 226 | |||
| 227 | + clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar.id_aa64mmfr0); | ||
| 228 | + | ||
| 229 | ahcf->isar = host_isar; | ||
| 230 | |||
| 231 | /* | ||
| 232 | @@ -XXX,XX +XXX,XX @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 233 | return r == HV_SUCCESS; | ||
| 234 | } | ||
| 235 | |||
| 236 | +uint32_t hvf_arm_get_default_ipa_bit_size(void) | ||
| 237 | +{ | ||
| 238 | + uint32_t default_ipa_size; | ||
| 239 | + hv_return_t ret = hv_vm_config_get_default_ipa_size(&default_ipa_size); | ||
| 240 | + assert_hvf_ok(ret); | ||
| 241 | + | ||
| 242 | + return default_ipa_size; | ||
| 243 | +} | ||
| 244 | + | ||
| 245 | +uint32_t hvf_arm_get_max_ipa_bit_size(void) | ||
| 246 | +{ | ||
| 247 | + uint32_t max_ipa_size; | ||
| 248 | + hv_return_t ret = hv_vm_config_get_max_ipa_size(&max_ipa_size); | ||
| 249 | + assert_hvf_ok(ret); | ||
| 250 | + | ||
| 251 | + /* | ||
| 252 | + * We clamp any IPA size we want to back the VM with to a valid PARange | ||
| 253 | + * value so the guest doesn't try and map memory outside of the valid range. | ||
| 254 | + * This logic just clamps the passed in IPA bit size to the first valid | ||
| 255 | + * PARange value <= to it. | ||
| 256 | + */ | ||
| 257 | + return round_down_to_parange_bit_size(max_ipa_size); | ||
| 258 | +} | ||
| 259 | + | ||
| 260 | void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu) | ||
| 261 | { | ||
| 262 | if (!arm_host_cpu_features.dtb_compatible) { | ||
| 263 | @@ -XXX,XX +XXX,XX @@ void hvf_arch_vcpu_destroy(CPUState *cpu) | ||
| 264 | |||
| 265 | hv_return_t hvf_arch_vm_create(MachineState *ms, uint32_t pa_range) | ||
| 266 | { | ||
| 267 | + hv_return_t ret; | ||
| 268 | hv_vm_config_t config = hv_vm_config_create(); | ||
| 269 | - hv_return_t ret = hv_vm_create(config); | ||
| 270 | + | ||
| 271 | + ret = hv_vm_config_set_ipa_size(config, pa_range); | ||
| 272 | + if (ret != HV_SUCCESS) { | ||
| 273 | + goto cleanup; | ||
| 274 | + } | ||
| 275 | + chosen_ipa_bit_size = pa_range; | ||
| 276 | + | ||
| 277 | + ret = hv_vm_create(config); | ||
| 278 | + | ||
| 279 | +cleanup: | ||
| 280 | os_release(config); | ||
| 281 | |||
| 282 | return ret; | ||
| 283 | @@ -XXX,XX +XXX,XX @@ int hvf_arch_init_vcpu(CPUState *cpu) | ||
| 284 | &arm_cpu->isar.id_aa64mmfr0); | ||
| 285 | assert_hvf_ok(ret); | ||
| 286 | |||
| 287 | + clamp_id_aa64mmfr0_parange_to_ipa_size(&arm_cpu->isar.id_aa64mmfr0); | ||
| 288 | + ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL1, | ||
| 289 | + arm_cpu->isar.id_aa64mmfr0); | ||
| 290 | + assert_hvf_ok(ret); | ||
| 291 | + | ||
| 292 | return 0; | ||
| 293 | } | ||
| 294 | |||
| 295 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
| 296 | index XXXXXXX..XXXXXXX 100644 | ||
| 297 | --- a/target/arm/ptw.c | ||
| 298 | +++ b/target/arm/ptw.c | ||
| 299 | @@ -XXX,XX +XXX,XX @@ static const uint8_t pamax_map[] = { | ||
| 300 | [6] = 52, | ||
| 301 | }; | ||
| 302 | |||
| 303 | +uint8_t round_down_to_parange_index(uint8_t bit_size) | ||
| 304 | +{ | ||
| 305 | + for (int i = ARRAY_SIZE(pamax_map) - 1; i >= 0; i--) { | ||
| 306 | + if (pamax_map[i] <= bit_size) { | ||
| 307 | + return i; | ||
| 308 | + } | ||
| 309 | + } | ||
| 310 | + g_assert_not_reached(); | ||
| 311 | +} | ||
| 312 | + | ||
| 313 | +uint8_t round_down_to_parange_bit_size(uint8_t bit_size) | ||
| 314 | +{ | ||
| 315 | + return pamax_map[round_down_to_parange_index(bit_size)]; | ||
| 316 | +} | ||
| 317 | + | ||
| 318 | /* | ||
| 319 | * The cpu-specific constant value of PAMax; also used by hw/arm/virt. | ||
| 320 | * Note that machvirt_init calls this on a CPU that is inited but not realized! | ||
| 321 | -- | 340 | -- |
| 322 | 2.34.1 | 341 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Explicitly set a rule in the softfloat tests for propagating NaNs in | ||
| 2 | the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and | ||
| 3 | so we should select here the Arm rule of float_3nan_prop_s_cab. | ||
| 1 | 4 | ||
| 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20241202131347.498124-17-peter.maydell@linaro.org | ||
| 8 | --- | ||
| 9 | tests/fp/fp-bench.c | 1 + | ||
| 10 | tests/fp/fp-test.c | 1 + | ||
| 11 | 2 files changed, 2 insertions(+) | ||
| 12 | |||
| 13 | diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/tests/fp/fp-bench.c | ||
| 16 | +++ b/tests/fp/fp-bench.c | ||
| 17 | @@ -XXX,XX +XXX,XX @@ static void run_bench(void) | ||
| 18 | * doesn't specify match those used by the Arm architecture. | ||
| 19 | */ | ||
| 20 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); | ||
| 21 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status); | ||
| 22 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); | ||
| 23 | |||
| 24 | f = bench_funcs[operation][precision]; | ||
| 25 | diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c | ||
| 26 | index XXXXXXX..XXXXXXX 100644 | ||
| 27 | --- a/tests/fp/fp-test.c | ||
| 28 | +++ b/tests/fp/fp-test.c | ||
| 29 | @@ -XXX,XX +XXX,XX @@ void run_test(void) | ||
| 30 | * doesn't specify match those used by the Arm architecture. | ||
| 31 | */ | ||
| 32 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); | ||
| 33 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf); | ||
| 34 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); | ||
| 35 | |||
| 36 | genCases_setLevel(test_level); | ||
| 37 | -- | ||
| 38 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the Float3NaNPropRule explicitly for Arm, and remove the | ||
| 2 | ifdef from pickNaNMulAdd(). | ||
| 1 | 3 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-18-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/arm/cpu.c | 5 +++++ | ||
| 9 | fpu/softfloat-specialize.c.inc | 8 +------- | ||
| 10 | 2 files changed, 6 insertions(+), 7 deletions(-) | ||
| 11 | |||
| 12 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/arm/cpu.c | ||
| 15 | +++ b/target/arm/cpu.c | ||
| 16 | @@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, | ||
| 17 | * * tininess-before-rounding | ||
| 18 | * * 2-input NaN propagation prefers SNaN over QNaN, and then | ||
| 19 | * operand A over operand B (see FPProcessNaNs() pseudocode) | ||
| 20 | + * * 3-input NaN propagation prefers SNaN over QNaN, and then | ||
| 21 | + * operand C over A over B (see FPProcessNaNs3() pseudocode, | ||
| 22 | + * but note that for QEMU muladd is a * b + c, whereas for | ||
| 23 | + * the pseudocode function the arguments are in the order c, a, b. | ||
| 24 | * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, | ||
| 25 | * and the input NaN if it is signalling | ||
| 26 | */ | ||
| 27 | @@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s) | ||
| 28 | { | ||
| 29 | set_float_detect_tininess(float_tininess_before_rounding, s); | ||
| 30 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); | ||
| 31 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, s); | ||
| 32 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); | ||
| 33 | } | ||
| 34 | |||
| 35 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 36 | index XXXXXXX..XXXXXXX 100644 | ||
| 37 | --- a/fpu/softfloat-specialize.c.inc | ||
| 38 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 39 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 40 | } | ||
| 41 | |||
| 42 | if (rule == float_3nan_prop_none) { | ||
| 43 | -#if defined(TARGET_ARM) | ||
| 44 | - /* | ||
| 45 | - * This looks different from the ARM ARM pseudocode, because the ARM ARM | ||
| 46 | - * puts the operands to a fused mac operation (a*b)+c in the order c,a,b | ||
| 47 | - */ | ||
| 48 | - rule = float_3nan_prop_s_cab; | ||
| 49 | -#elif defined(TARGET_MIPS) | ||
| 50 | +#if defined(TARGET_MIPS) | ||
| 51 | if (snan_bit_is_one(status)) { | ||
| 52 | rule = float_3nan_prop_s_abc; | ||
| 53 | } else { | ||
| 54 | -- | ||
| 55 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the Float3NaNPropRule explicitly for loongarch, and remove the | ||
| 2 | ifdef from pickNaNMulAdd(). | ||
| 1 | 3 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-19-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/loongarch/tcg/fpu_helper.c | 1 + | ||
| 9 | fpu/softfloat-specialize.c.inc | 2 -- | ||
| 10 | 2 files changed, 1 insertion(+), 2 deletions(-) | ||
| 11 | |||
| 12 | diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/loongarch/tcg/fpu_helper.c | ||
| 15 | +++ b/target/loongarch/tcg/fpu_helper.c | ||
| 16 | @@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env) | ||
| 17 | * case sets InvalidOp and returns the input value 'c' | ||
| 18 | */ | ||
| 19 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
| 20 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status); | ||
| 21 | } | ||
| 22 | |||
| 23 | int ieee_ex_to_loongarch(int xcpt) | ||
| 24 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 25 | index XXXXXXX..XXXXXXX 100644 | ||
| 26 | --- a/fpu/softfloat-specialize.c.inc | ||
| 27 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 28 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 29 | } else { | ||
| 30 | rule = float_3nan_prop_s_cab; | ||
| 31 | } | ||
| 32 | -#elif defined(TARGET_LOONGARCH64) | ||
| 33 | - rule = float_3nan_prop_s_cab; | ||
| 34 | #elif defined(TARGET_PPC) | ||
| 35 | /* | ||
| 36 | * If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
| 37 | -- | ||
| 38 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the Float3NaNPropRule explicitly for PPC, and remove the | ||
| 2 | ifdef from pickNaNMulAdd(). | ||
| 1 | 3 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-20-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/ppc/cpu_init.c | 8 ++++++++ | ||
| 9 | fpu/softfloat-specialize.c.inc | 6 ------ | ||
| 10 | 2 files changed, 8 insertions(+), 6 deletions(-) | ||
| 11 | |||
| 12 | diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/ppc/cpu_init.c | ||
| 15 | +++ b/target/ppc/cpu_init.c | ||
| 16 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) | ||
| 17 | */ | ||
| 18 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); | ||
| 19 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); | ||
| 20 | + /* | ||
| 21 | + * NaN propagation for fused multiply-add: | ||
| 22 | + * if fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
| 23 | + * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
| 24 | + * whereas QEMU labels the operands as (a * b) + c. | ||
| 25 | + */ | ||
| 26 | + set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status); | ||
| 27 | + set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status); | ||
| 28 | /* | ||
| 29 | * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
| 30 | * to return an input NaN if we have one (ie c) rather than generating | ||
| 31 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 32 | index XXXXXXX..XXXXXXX 100644 | ||
| 33 | --- a/fpu/softfloat-specialize.c.inc | ||
| 34 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 35 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 36 | } else { | ||
| 37 | rule = float_3nan_prop_s_cab; | ||
| 38 | } | ||
| 39 | -#elif defined(TARGET_PPC) | ||
| 40 | - /* | ||
| 41 | - * If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
| 42 | - * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
| 43 | - */ | ||
| 44 | - rule = float_3nan_prop_acb; | ||
| 45 | #elif defined(TARGET_S390X) | ||
| 46 | rule = float_3nan_prop_s_abc; | ||
| 47 | #elif defined(TARGET_SPARC) | ||
| 48 | -- | ||
| 49 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the Float3NaNPropRule explicitly for s390x, and remove the | ||
| 2 | ifdef from pickNaNMulAdd(). | ||
| 1 | 3 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-21-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/s390x/cpu.c | 1 + | ||
| 9 | fpu/softfloat-specialize.c.inc | 2 -- | ||
| 10 | 2 files changed, 1 insertion(+), 2 deletions(-) | ||
| 11 | |||
| 12 | diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/s390x/cpu.c | ||
| 15 | +++ b/target/s390x/cpu.c | ||
| 16 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) | ||
| 17 | set_float_detect_tininess(float_tininess_before_rounding, | ||
| 18 | &env->fpu_status); | ||
| 19 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status); | ||
| 20 | + set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status); | ||
| 21 | set_float_infzeronan_rule(float_infzeronan_dnan_always, | ||
| 22 | &env->fpu_status); | ||
| 23 | /* fall through */ | ||
| 24 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 25 | index XXXXXXX..XXXXXXX 100644 | ||
| 26 | --- a/fpu/softfloat-specialize.c.inc | ||
| 27 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 28 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 29 | } else { | ||
| 30 | rule = float_3nan_prop_s_cab; | ||
| 31 | } | ||
| 32 | -#elif defined(TARGET_S390X) | ||
| 33 | - rule = float_3nan_prop_s_abc; | ||
| 34 | #elif defined(TARGET_SPARC) | ||
| 35 | rule = float_3nan_prop_s_cba; | ||
| 36 | #elif defined(TARGET_XTENSA) | ||
| 37 | -- | ||
| 38 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the Float3NaNPropRule explicitly for SPARC, and remove the | ||
| 2 | ifdef from pickNaNMulAdd(). | ||
| 1 | 3 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-22-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/sparc/cpu.c | 2 ++ | ||
| 9 | fpu/softfloat-specialize.c.inc | 2 -- | ||
| 10 | 2 files changed, 2 insertions(+), 2 deletions(-) | ||
| 11 | |||
| 12 | diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/sparc/cpu.c | ||
| 15 | +++ b/target/sparc/cpu.c | ||
| 16 | @@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) | ||
| 17 | * the CPU state struct so it won't get zeroed on reset. | ||
| 18 | */ | ||
| 19 | set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); | ||
| 20 | + /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */ | ||
| 21 | + set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); | ||
| 22 | /* For inf * 0 + NaN, return the input NaN */ | ||
| 23 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
| 24 | |||
| 25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 26 | index XXXXXXX..XXXXXXX 100644 | ||
| 27 | --- a/fpu/softfloat-specialize.c.inc | ||
| 28 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 30 | } else { | ||
| 31 | rule = float_3nan_prop_s_cab; | ||
| 32 | } | ||
| 33 | -#elif defined(TARGET_SPARC) | ||
| 34 | - rule = float_3nan_prop_s_cba; | ||
| 35 | #elif defined(TARGET_XTENSA) | ||
| 36 | if (status->use_first_nan) { | ||
| 37 | rule = float_3nan_prop_abc; | ||
| 38 | -- | ||
| 39 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the Float3NaNPropRule explicitly for Arm, and remove the | ||
| 2 | ifdef from pickNaNMulAdd(). | ||
| 1 | 3 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-23-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/mips/fpu_helper.h | 4 ++++ | ||
| 9 | target/mips/msa.c | 3 +++ | ||
| 10 | fpu/softfloat-specialize.c.inc | 8 +------- | ||
| 11 | 3 files changed, 8 insertions(+), 7 deletions(-) | ||
| 12 | |||
| 13 | diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/target/mips/fpu_helper.h | ||
| 16 | +++ b/target/mips/fpu_helper.h | ||
| 17 | @@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) | ||
| 18 | { | ||
| 19 | bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); | ||
| 20 | FloatInfZeroNaNRule izn_rule; | ||
| 21 | + Float3NaNPropRule nan3_rule; | ||
| 22 | |||
| 23 | /* | ||
| 24 | * With nan2008, SNaNs are silenced in the usual way. | ||
| 25 | @@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) | ||
| 26 | */ | ||
| 27 | izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always; | ||
| 28 | set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); | ||
| 29 | + nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc; | ||
| 30 | + set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status); | ||
| 31 | + | ||
| 32 | } | ||
| 33 | |||
| 34 | static inline void restore_fp_status(CPUMIPSState *env) | ||
| 35 | diff --git a/target/mips/msa.c b/target/mips/msa.c | ||
| 36 | index XXXXXXX..XXXXXXX 100644 | ||
| 37 | --- a/target/mips/msa.c | ||
| 38 | +++ b/target/mips/msa.c | ||
| 39 | @@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env) | ||
| 40 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, | ||
| 41 | &env->active_tc.msa_fp_status); | ||
| 42 | |||
| 43 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, | ||
| 44 | + &env->active_tc.msa_fp_status); | ||
| 45 | + | ||
| 46 | /* clear float_status exception flags */ | ||
| 47 | set_float_exception_flags(0, &env->active_tc.msa_fp_status); | ||
| 48 | |||
| 49 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 50 | index XXXXXXX..XXXXXXX 100644 | ||
| 51 | --- a/fpu/softfloat-specialize.c.inc | ||
| 52 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 53 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 54 | } | ||
| 55 | |||
| 56 | if (rule == float_3nan_prop_none) { | ||
| 57 | -#if defined(TARGET_MIPS) | ||
| 58 | - if (snan_bit_is_one(status)) { | ||
| 59 | - rule = float_3nan_prop_s_abc; | ||
| 60 | - } else { | ||
| 61 | - rule = float_3nan_prop_s_cab; | ||
| 62 | - } | ||
| 63 | -#elif defined(TARGET_XTENSA) | ||
| 64 | +#if defined(TARGET_XTENSA) | ||
| 65 | if (status->use_first_nan) { | ||
| 66 | rule = float_3nan_prop_abc; | ||
| 67 | } else { | ||
| 68 | -- | ||
| 69 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the Float3NaNPropRule explicitly for xtensa, and remove the | ||
| 2 | ifdef from pickNaNMulAdd(). | ||
| 1 | 3 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-24-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/xtensa/fpu_helper.c | 2 ++ | ||
| 9 | fpu/softfloat-specialize.c.inc | 8 -------- | ||
| 10 | 2 files changed, 2 insertions(+), 8 deletions(-) | ||
| 11 | |||
| 12 | diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/xtensa/fpu_helper.c | ||
| 15 | +++ b/target/xtensa/fpu_helper.c | ||
| 16 | @@ -XXX,XX +XXX,XX @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) | ||
| 17 | set_use_first_nan(use_first, &env->fp_status); | ||
| 18 | set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba, | ||
| 19 | &env->fp_status); | ||
| 20 | + set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba, | ||
| 21 | + &env->fp_status); | ||
| 22 | } | ||
| 23 | |||
| 24 | void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v) | ||
| 25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 26 | index XXXXXXX..XXXXXXX 100644 | ||
| 27 | --- a/fpu/softfloat-specialize.c.inc | ||
| 28 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 30 | } | ||
| 31 | |||
| 32 | if (rule == float_3nan_prop_none) { | ||
| 33 | -#if defined(TARGET_XTENSA) | ||
| 34 | - if (status->use_first_nan) { | ||
| 35 | - rule = float_3nan_prop_abc; | ||
| 36 | - } else { | ||
| 37 | - rule = float_3nan_prop_cba; | ||
| 38 | - } | ||
| 39 | -#else | ||
| 40 | rule = float_3nan_prop_abc; | ||
| 41 | -#endif | ||
| 42 | } | ||
| 43 | |||
| 44 | assert(rule != float_3nan_prop_none); | ||
| 45 | -- | ||
| 46 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the Float3NaNPropRule explicitly for i386. We had no | ||
| 2 | i386-specific behaviour in the old ifdef ladder, so we were using the | ||
| 3 | default "prefer a then b then c" fallback; this is actually the | ||
| 4 | correct per-the-spec handling for i386. | ||
| 1 | 5 | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20241202131347.498124-25-peter.maydell@linaro.org | ||
| 9 | --- | ||
| 10 | target/i386/tcg/fpu_helper.c | 1 + | ||
| 11 | 1 file changed, 1 insertion(+) | ||
| 12 | |||
| 13 | diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/target/i386/tcg/fpu_helper.c | ||
| 16 | +++ b/target/i386/tcg/fpu_helper.c | ||
| 17 | @@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env) | ||
| 18 | * there are multiple input NaNs they are selected in the order a, b, c. | ||
| 19 | */ | ||
| 20 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); | ||
| 21 | + set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status); | ||
| 22 | } | ||
| 23 | |||
| 24 | static inline uint8_t save_exception_flags(CPUX86State *env) | ||
| 25 | -- | ||
| 26 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the Float3NaNPropRule explicitly for HPPA, and remove the | ||
| 2 | ifdef from pickNaNMulAdd(). | ||
| 1 | 3 | ||
| 4 | HPPA is the only target that was using the default branch of the | ||
| 5 | ifdef ladder (other targets either do not use muladd or set | ||
| 6 | default_nan_mode), so we can remove the ifdef fallback entirely now | ||
| 7 | (allowing the "rule not set" case to fall into the default of the | ||
| 8 | switch statement and assert). | ||
| 9 | |||
| 10 | We add a TODO note that the HPPA rule is probably wrong; this is | ||
| 11 | not a behavioural change for this refactoring. | ||
| 12 | |||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 15 | Message-id: 20241202131347.498124-26-peter.maydell@linaro.org | ||
| 16 | --- | ||
| 17 | target/hppa/fpu_helper.c | 8 ++++++++ | ||
| 18 | fpu/softfloat-specialize.c.inc | 4 ---- | ||
| 19 | 2 files changed, 8 insertions(+), 4 deletions(-) | ||
| 20 | |||
| 21 | diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c | ||
| 22 | index XXXXXXX..XXXXXXX 100644 | ||
| 23 | --- a/target/hppa/fpu_helper.c | ||
| 24 | +++ b/target/hppa/fpu_helper.c | ||
| 25 | @@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env) | ||
| 26 | * HPPA does note implement a CPU reset method at all... | ||
| 27 | */ | ||
| 28 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); | ||
| 29 | + /* | ||
| 30 | + * TODO: The HPPA architecture reference only documents its NaN | ||
| 31 | + * propagation rule for 2-operand operations. Testing on real hardware | ||
| 32 | + * might be necessary to confirm whether this order for muladd is correct. | ||
| 33 | + * Not preferring the SNaN is almost certainly incorrect as it diverges | ||
| 34 | + * from the documented rules for 2-operand operations. | ||
| 35 | + */ | ||
| 36 | + set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status); | ||
| 37 | /* For inf * 0 + NaN, return the input NaN */ | ||
| 38 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
| 39 | } | ||
| 40 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 41 | index XXXXXXX..XXXXXXX 100644 | ||
| 42 | --- a/fpu/softfloat-specialize.c.inc | ||
| 43 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 44 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
| 45 | } | ||
| 46 | } | ||
| 47 | |||
| 48 | - if (rule == float_3nan_prop_none) { | ||
| 49 | - rule = float_3nan_prop_abc; | ||
| 50 | - } | ||
| 51 | - | ||
| 52 | assert(rule != float_3nan_prop_none); | ||
| 53 | if (have_snan && (rule & R_3NAN_SNAN_MASK)) { | ||
| 54 | /* We have at least one SNaN input and should prefer it */ | ||
| 55 | -- | ||
| 56 | 2.34.1 | diff view generated by jsdifflib |
| 1 | We used to need the transitional_function machinery to handle bus | 1 | The use_first_nan field in float_status was an xtensa-specific way to |
|---|---|---|---|
| 2 | classes and device classes which still used their legacy reset | 2 | select at runtime from two different NaN propagation rules. Now that |
| 3 | handling. We have now converted all bus classes to three phase | 3 | xtensa is using the target-agnostic NaN propagation rule selection |
| 4 | reset, and simplified the device class legacy reset so it is just an | 4 | that we've just added, we can remove use_first_nan, because there is |
| 5 | adapting wrapper function around registration of a hold phase method. | 5 | no longer any code that reads it. |
| 6 | There are therefore no more users of the transitional_function | ||
| 7 | machinery and we can remove it. | ||
| 8 | 6 | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | Message-id: 20240830145812.1967042-12-peter.maydell@linaro.org | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 9 | Message-id: 20241202131347.498124-27-peter.maydell@linaro.org | ||
| 11 | --- | 10 | --- |
| 12 | include/hw/resettable.h | 13 ------------- | 11 | include/fpu/softfloat-helpers.h | 5 ----- |
| 13 | hw/core/resettable.c | 24 +++--------------------- | 12 | include/fpu/softfloat-types.h | 1 - |
| 14 | 2 files changed, 3 insertions(+), 34 deletions(-) | 13 | target/xtensa/fpu_helper.c | 1 - |
| 14 | 3 files changed, 7 deletions(-) | ||
| 15 | 15 | ||
| 16 | diff --git a/include/hw/resettable.h b/include/hw/resettable.h | 16 | diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h |
| 17 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/include/hw/resettable.h | 18 | --- a/include/fpu/softfloat-helpers.h |
| 19 | +++ b/include/hw/resettable.h | 19 | +++ b/include/fpu/softfloat-helpers.h |
| 20 | @@ -XXX,XX +XXX,XX @@ typedef enum ResetType { | 20 | @@ -XXX,XX +XXX,XX @@ static inline void set_snan_bit_is_one(bool val, float_status *status) |
| 21 | * @get_state: Mandatory method which must return a pointer to a | 21 | status->snan_bit_is_one = val; |
| 22 | * ResettableState. | ||
| 23 | * | ||
| 24 | - * @get_transitional_function: transitional method to handle Resettable objects | ||
| 25 | - * not yet fully moved to this interface. It will be removed as soon as it is | ||
| 26 | - * not needed anymore. This method is optional and may return a pointer to a | ||
| 27 | - * function to be used instead of the phases. If the method exists and returns | ||
| 28 | - * a non-NULL function pointer then that function is executed as a replacement | ||
| 29 | - * of the 'hold' phase method taking the object as argument. The two other phase | ||
| 30 | - * methods are not executed. | ||
| 31 | - * | ||
| 32 | * @child_foreach: Executes a given callback on every Resettable child. Child | ||
| 33 | * in this context means a child in the qbus tree, so the children of a qbus | ||
| 34 | * are the devices on it, and the children of a device are all the buses it | ||
| 35 | @@ -XXX,XX +XXX,XX @@ typedef void (*ResettableEnterPhase)(Object *obj, ResetType type); | ||
| 36 | typedef void (*ResettableHoldPhase)(Object *obj, ResetType type); | ||
| 37 | typedef void (*ResettableExitPhase)(Object *obj, ResetType type); | ||
| 38 | typedef ResettableState * (*ResettableGetState)(Object *obj); | ||
| 39 | -typedef void (*ResettableTrFunction)(Object *obj); | ||
| 40 | -typedef ResettableTrFunction (*ResettableGetTrFunction)(Object *obj); | ||
| 41 | typedef void (*ResettableChildCallback)(Object *, void *opaque, | ||
| 42 | ResetType type); | ||
| 43 | typedef void (*ResettableChildForeach)(Object *obj, | ||
| 44 | @@ -XXX,XX +XXX,XX @@ struct ResettableClass { | ||
| 45 | /* State access method */ | ||
| 46 | ResettableGetState get_state; | ||
| 47 | |||
| 48 | - /* Transitional method for legacy reset compatibility */ | ||
| 49 | - ResettableGetTrFunction get_transitional_function; | ||
| 50 | - | ||
| 51 | /* Hierarchy handling method */ | ||
| 52 | ResettableChildForeach child_foreach; | ||
| 53 | }; | ||
| 54 | diff --git a/hw/core/resettable.c b/hw/core/resettable.c | ||
| 55 | index XXXXXXX..XXXXXXX 100644 | ||
| 56 | --- a/hw/core/resettable.c | ||
| 57 | +++ b/hw/core/resettable.c | ||
| 58 | @@ -XXX,XX +XXX,XX @@ static void resettable_child_foreach(ResettableClass *rc, Object *obj, | ||
| 59 | } | ||
| 60 | } | 22 | } |
| 61 | 23 | ||
| 62 | -/** | 24 | -static inline void set_use_first_nan(bool val, float_status *status) |
| 63 | - * resettable_get_tr_func: | ||
| 64 | - * helper to fetch transitional reset callback if any. | ||
| 65 | - */ | ||
| 66 | -static ResettableTrFunction resettable_get_tr_func(ResettableClass *rc, | ||
| 67 | - Object *obj) | ||
| 68 | -{ | 25 | -{ |
| 69 | - ResettableTrFunction tr_func = NULL; | 26 | - status->use_first_nan = val; |
| 70 | - if (rc->get_transitional_function) { | ||
| 71 | - tr_func = rc->get_transitional_function(obj); | ||
| 72 | - } | ||
| 73 | - return tr_func; | ||
| 74 | -} | 27 | -} |
| 75 | - | 28 | - |
| 76 | static void resettable_phase_enter(Object *obj, void *opaque, ResetType type) | 29 | static inline void set_no_signaling_nans(bool val, float_status *status) |
| 77 | { | 30 | { |
| 78 | ResettableClass *rc = RESETTABLE_GET_CLASS(obj); | 31 | status->no_signaling_nans = val; |
| 79 | @@ -XXX,XX +XXX,XX @@ static void resettable_phase_enter(Object *obj, void *opaque, ResetType type) | 32 | diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h |
| 80 | if (action_needed) { | 33 | index XXXXXXX..XXXXXXX 100644 |
| 81 | trace_resettable_phase_enter_exec(obj, obj_typename, type, | 34 | --- a/include/fpu/softfloat-types.h |
| 82 | !!rc->phases.enter); | 35 | +++ b/include/fpu/softfloat-types.h |
| 83 | - if (rc->phases.enter && !resettable_get_tr_func(rc, obj)) { | 36 | @@ -XXX,XX +XXX,XX @@ typedef struct float_status { |
| 84 | + if (rc->phases.enter) { | 37 | * softfloat-specialize.inc.c) |
| 85 | rc->phases.enter(obj, type); | 38 | */ |
| 86 | } | 39 | bool snan_bit_is_one; |
| 87 | s->hold_phase_pending = true; | 40 | - bool use_first_nan; |
| 88 | @@ -XXX,XX +XXX,XX @@ static void resettable_phase_hold(Object *obj, void *opaque, ResetType type) | 41 | bool no_signaling_nans; |
| 89 | /* exec hold phase */ | 42 | /* should overflowed results subtract re_bias to its exponent? */ |
| 90 | if (s->hold_phase_pending) { | 43 | bool rebias_overflow; |
| 91 | s->hold_phase_pending = false; | 44 | diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c |
| 92 | - ResettableTrFunction tr_func = resettable_get_tr_func(rc, obj); | 45 | index XXXXXXX..XXXXXXX 100644 |
| 93 | trace_resettable_phase_hold_exec(obj, obj_typename, !!rc->phases.hold); | 46 | --- a/target/xtensa/fpu_helper.c |
| 94 | - if (tr_func) { | 47 | +++ b/target/xtensa/fpu_helper.c |
| 95 | - trace_resettable_transitional_function(obj, obj_typename); | 48 | @@ -XXX,XX +XXX,XX @@ static const struct { |
| 96 | - tr_func(obj); | 49 | |
| 97 | - } else if (rc->phases.hold) { | 50 | void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) |
| 98 | + if (rc->phases.hold) { | 51 | { |
| 99 | rc->phases.hold(obj, type); | 52 | - set_use_first_nan(use_first, &env->fp_status); |
| 100 | } | 53 | set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba, |
| 101 | } | 54 | &env->fp_status); |
| 102 | @@ -XXX,XX +XXX,XX @@ static void resettable_phase_exit(Object *obj, void *opaque, ResetType type) | 55 | set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba, |
| 103 | assert(s->count > 0); | ||
| 104 | if (--s->count == 0) { | ||
| 105 | trace_resettable_phase_exit_exec(obj, obj_typename, !!rc->phases.exit); | ||
| 106 | - if (rc->phases.exit && !resettable_get_tr_func(rc, obj)) { | ||
| 107 | + if (rc->phases.exit) { | ||
| 108 | rc->phases.exit(obj, type); | ||
| 109 | } | ||
| 110 | } | ||
| 111 | -- | 56 | -- |
| 112 | 2.34.1 | 57 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL) | ||
| 2 | to get the NaN bit pattern to reset the FPU registers. This | ||
| 3 | works because it happens that our implementation of | ||
| 4 | floatx80_default_nan() doesn't actually look at the float_status | ||
| 5 | pointer except for TARGET_MIPS. However, this isn't guaranteed, | ||
| 6 | and to be able to remove the ifdef in floatx80_default_nan() | ||
| 7 | we're going to need a real float_status here. | ||
| 1 | 8 | ||
| 9 | Rearrange m68k_cpu_reset_hold() so that we initialize env->fp_status | ||
| 10 | earlier, and thus can pass it to floatx80_default_nan(). | ||
| 11 | |||
| 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 14 | Message-id: 20241202131347.498124-28-peter.maydell@linaro.org | ||
| 15 | --- | ||
| 16 | target/m68k/cpu.c | 12 +++++++----- | ||
| 17 | 1 file changed, 7 insertions(+), 5 deletions(-) | ||
| 18 | |||
| 19 | diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c | ||
| 20 | index XXXXXXX..XXXXXXX 100644 | ||
| 21 | --- a/target/m68k/cpu.c | ||
| 22 | +++ b/target/m68k/cpu.c | ||
| 23 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) | ||
| 24 | CPUState *cs = CPU(obj); | ||
| 25 | M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj); | ||
| 26 | CPUM68KState *env = cpu_env(cs); | ||
| 27 | - floatx80 nan = floatx80_default_nan(NULL); | ||
| 28 | + floatx80 nan; | ||
| 29 | int i; | ||
| 30 | |||
| 31 | if (mcc->parent_phases.hold) { | ||
| 32 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) | ||
| 33 | #else | ||
| 34 | cpu_m68k_set_sr(env, SR_S | SR_I); | ||
| 35 | #endif | ||
| 36 | - for (i = 0; i < 8; i++) { | ||
| 37 | - env->fregs[i].d = nan; | ||
| 38 | - } | ||
| 39 | - cpu_m68k_set_fpcr(env, 0); | ||
| 40 | /* | ||
| 41 | * M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL | ||
| 42 | * 3.4 FLOATING-POINT INSTRUCTION DETAILS | ||
| 43 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) | ||
| 44 | * preceding paragraph for nonsignaling NaNs. | ||
| 45 | */ | ||
| 46 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); | ||
| 47 | + | ||
| 48 | + nan = floatx80_default_nan(&env->fp_status); | ||
| 49 | + for (i = 0; i < 8; i++) { | ||
| 50 | + env->fregs[i].d = nan; | ||
| 51 | + } | ||
| 52 | + cpu_m68k_set_fpcr(env, 0); | ||
| 53 | env->fpsr = 0; | ||
| 54 | |||
| 55 | /* TODO: We should set PC from the interrupt vector. */ | ||
| 56 | -- | ||
| 57 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | We create our 128-bit default NaN by calling parts64_default_nan() | ||
| 2 | and then adjusting the result. We can do the same trick for creating | ||
| 3 | the floatx80 default NaN, which lets us drop a target ifdef. | ||
| 1 | 4 | ||
| 5 | floatx80 is used only by: | ||
| 6 | i386 | ||
| 7 | m68k | ||
| 8 | arm nwfpe old floating-point emulation emulation support | ||
| 9 | (which is essentially dead, especially the parts involving floatx80) | ||
| 10 | PPC (only in the xsrqpxp instruction, which just rounds an input | ||
| 11 | value by converting to floatx80 and back, so will never generate | ||
| 12 | the default NaN) | ||
| 13 | |||
| 14 | The floatx80 default NaN as currently implemented is: | ||
| 15 | m68k: sign = 0, exp = 1...1, int = 1, frac = 1....1 | ||
| 16 | i386: sign = 1, exp = 1...1, int = 1, frac = 10...0 | ||
| 17 | |||
| 18 | These are the same as the parts64_default_nan for these architectures. | ||
| 19 | |||
| 20 | This is technically a possible behaviour change for arm linux-user | ||
| 21 | nwfpe emulation emulation, because the default NaN will now have the | ||
| 22 | sign bit clear. But we were already generating a different floatx80 | ||
| 23 | default NaN from the real kernel emulation we are supposedly | ||
| 24 | following, which appears to use an all-bits-1 value: | ||
| 25 | https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L267 | ||
| 26 | |||
| 27 | This won't affect the only "real" use of the nwfpe emulation, which | ||
| 28 | is ancient binaries that used it as part of the old floating point | ||
| 29 | calling convention; that only uses loads and stores of 32 and 64 bit | ||
| 30 | floats, not any of the floatx80 behaviour the original hardware had. | ||
| 31 | We also get the nwfpe float64 default NaN value wrong: | ||
| 32 | https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L166 | ||
| 33 | so if we ever cared about this obscure corner the right fix would be | ||
| 34 | to correct that so nwfpe used its own default-NaN setting rather | ||
| 35 | than the Arm VFP one. | ||
| 36 | |||
| 37 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 38 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 39 | Message-id: 20241202131347.498124-29-peter.maydell@linaro.org | ||
| 40 | --- | ||
| 41 | fpu/softfloat-specialize.c.inc | 20 ++++++++++---------- | ||
| 42 | 1 file changed, 10 insertions(+), 10 deletions(-) | ||
| 43 | |||
| 44 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 45 | index XXXXXXX..XXXXXXX 100644 | ||
| 46 | --- a/fpu/softfloat-specialize.c.inc | ||
| 47 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 48 | @@ -XXX,XX +XXX,XX @@ static void parts128_silence_nan(FloatParts128 *p, float_status *status) | ||
| 49 | floatx80 floatx80_default_nan(float_status *status) | ||
| 50 | { | ||
| 51 | floatx80 r; | ||
| 52 | + /* | ||
| 53 | + * Extrapolate from the choices made by parts64_default_nan to fill | ||
| 54 | + * in the floatx80 format. We assume that floatx80's explicit | ||
| 55 | + * integer bit is always set (this is true for i386 and m68k, | ||
| 56 | + * which are the only real users of this format). | ||
| 57 | + */ | ||
| 58 | + FloatParts64 p64; | ||
| 59 | + parts64_default_nan(&p64, status); | ||
| 60 | |||
| 61 | - /* None of the targets that have snan_bit_is_one use floatx80. */ | ||
| 62 | - assert(!snan_bit_is_one(status)); | ||
| 63 | -#if defined(TARGET_M68K) | ||
| 64 | - r.low = UINT64_C(0xFFFFFFFFFFFFFFFF); | ||
| 65 | - r.high = 0x7FFF; | ||
| 66 | -#else | ||
| 67 | - /* X86 */ | ||
| 68 | - r.low = UINT64_C(0xC000000000000000); | ||
| 69 | - r.high = 0xFFFF; | ||
| 70 | -#endif | ||
| 71 | + r.high = 0x7FFF | (p64.sign << 15); | ||
| 72 | + r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac; | ||
| 73 | return r; | ||
| 74 | } | ||
| 75 | |||
| 76 | -- | ||
| 77 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass | ||
| 2 | a zero-initialized float_status struct to float32_is_quiet_nan() and | ||
| 3 | float64_is_quiet_nan(), with the cryptic comment "for | ||
| 4 | snan_bit_is_one". | ||
| 1 | 5 | ||
| 6 | This pattern appears to have been copied from target/riscv, where it | ||
| 7 | is used because the functions there do not have ready access to the | ||
| 8 | CPU state struct. The comment presumably refers to the fact that the | ||
| 9 | main reason the is_quiet_nan() functions want the float_state is | ||
| 10 | because they want to know about the snan_bit_is_one config. | ||
| 11 | |||
| 12 | In the loongarch helpers, though, we have the CPU state struct | ||
| 13 | to hand. Use the usual env->fp_status here. This avoids our needing | ||
| 14 | to track that we need to update the initializer of the local | ||
| 15 | float_status structs when the core softfloat code adds new | ||
| 16 | options for targets to configure their behaviour. | ||
| 17 | |||
| 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 20 | Message-id: 20241202131347.498124-30-peter.maydell@linaro.org | ||
| 21 | --- | ||
| 22 | target/loongarch/tcg/fpu_helper.c | 6 ++---- | ||
| 23 | 1 file changed, 2 insertions(+), 4 deletions(-) | ||
| 24 | |||
| 25 | diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c | ||
| 26 | index XXXXXXX..XXXXXXX 100644 | ||
| 27 | --- a/target/loongarch/tcg/fpu_helper.c | ||
| 28 | +++ b/target/loongarch/tcg/fpu_helper.c | ||
| 29 | @@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_s(CPULoongArchState *env, uint64_t fj) | ||
| 30 | } else if (float32_is_zero_or_denormal(f)) { | ||
| 31 | return sign ? 1 << 4 : 1 << 8; | ||
| 32 | } else if (float32_is_any_nan(f)) { | ||
| 33 | - float_status s = { }; /* for snan_bit_is_one */ | ||
| 34 | - return float32_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0; | ||
| 35 | + return float32_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0; | ||
| 36 | } else { | ||
| 37 | return sign ? 1 << 3 : 1 << 7; | ||
| 38 | } | ||
| 39 | @@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_d(CPULoongArchState *env, uint64_t fj) | ||
| 40 | } else if (float64_is_zero_or_denormal(f)) { | ||
| 41 | return sign ? 1 << 4 : 1 << 8; | ||
| 42 | } else if (float64_is_any_nan(f)) { | ||
| 43 | - float_status s = { }; /* for snan_bit_is_one */ | ||
| 44 | - return float64_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0; | ||
| 45 | + return float64_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0; | ||
| 46 | } else { | ||
| 47 | return sign ? 1 << 3 : 1 << 7; | ||
| 48 | } | ||
| 49 | -- | ||
| 50 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | In the frem helper, we have a local float_status because we want to | ||
| 2 | execute the floatx80_div() with a custom rounding mode. Instead of | ||
| 3 | zero-initializing the local float_status and then having to set it up | ||
| 4 | with the m68k standard behaviour (including the NaN propagation rule | ||
| 5 | and copying the rounding precision from env->fp_status), initialize | ||
| 6 | it as a complete copy of env->fp_status. This will avoid our having | ||
| 7 | to add new code in this function for every new config knob we add | ||
| 8 | to fp_status. | ||
| 1 | 9 | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 12 | Message-id: 20241202131347.498124-31-peter.maydell@linaro.org | ||
| 13 | --- | ||
| 14 | target/m68k/fpu_helper.c | 6 ++---- | ||
| 15 | 1 file changed, 2 insertions(+), 4 deletions(-) | ||
| 16 | |||
| 17 | diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c | ||
| 18 | index XXXXXXX..XXXXXXX 100644 | ||
| 19 | --- a/target/m68k/fpu_helper.c | ||
| 20 | +++ b/target/m68k/fpu_helper.c | ||
| 21 | @@ -XXX,XX +XXX,XX @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) | ||
| 22 | |||
| 23 | fp_rem = floatx80_rem(val1->d, val0->d, &env->fp_status); | ||
| 24 | if (!floatx80_is_any_nan(fp_rem)) { | ||
| 25 | - float_status fp_status = { }; | ||
| 26 | + /* Use local temporary fp_status to set different rounding mode */ | ||
| 27 | + float_status fp_status = env->fp_status; | ||
| 28 | uint32_t quotient; | ||
| 29 | int sign; | ||
| 30 | |||
| 31 | /* Calculate quotient directly using round to nearest mode */ | ||
| 32 | - set_float_2nan_prop_rule(float_2nan_prop_ab, &fp_status); | ||
| 33 | set_float_rounding_mode(float_round_nearest_even, &fp_status); | ||
| 34 | - set_floatx80_rounding_precision( | ||
| 35 | - get_floatx80_rounding_precision(&env->fp_status), &fp_status); | ||
| 36 | fp_quot.d = floatx80_div(val1->d, val0->d, &fp_status); | ||
| 37 | |||
| 38 | sign = extractFloatx80Sign(fp_quot.d); | ||
| 39 | -- | ||
| 40 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion | ||
| 2 | from float64 to floatx80 using a scratch float_status, because we | ||
| 3 | don't want the conversion to affect the CPU's floating point exception | ||
| 4 | status. Currently we use a zero-initialized float_status. This will | ||
| 5 | get steadily more awkward as we add config knobs to float_status | ||
| 6 | that the target must initialize. Avoid having to add any of that | ||
| 7 | configuration here by instead initializing our local float_status | ||
| 8 | from the env->fp_status. | ||
| 1 | 9 | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 12 | Message-id: 20241202131347.498124-32-peter.maydell@linaro.org | ||
| 13 | --- | ||
| 14 | target/m68k/helper.c | 6 ++++-- | ||
| 15 | 1 file changed, 4 insertions(+), 2 deletions(-) | ||
| 16 | |||
| 17 | diff --git a/target/m68k/helper.c b/target/m68k/helper.c | ||
| 18 | index XXXXXXX..XXXXXXX 100644 | ||
| 19 | --- a/target/m68k/helper.c | ||
| 20 | +++ b/target/m68k/helper.c | ||
| 21 | @@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n) | ||
| 22 | CPUM68KState *env = &cpu->env; | ||
| 23 | |||
| 24 | if (n < 8) { | ||
| 25 | - float_status s = {}; | ||
| 26 | + /* Use scratch float_status so any exceptions don't change CPU state */ | ||
| 27 | + float_status s = env->fp_status; | ||
| 28 | return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s)); | ||
| 29 | } | ||
| 30 | switch (n) { | ||
| 31 | @@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n) | ||
| 32 | CPUM68KState *env = &cpu->env; | ||
| 33 | |||
| 34 | if (n < 8) { | ||
| 35 | - float_status s = {}; | ||
| 36 | + /* Use scratch float_status so any exceptions don't change CPU state */ | ||
| 37 | + float_status s = env->fp_status; | ||
| 38 | env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s); | ||
| 39 | return 8; | ||
| 40 | } | ||
| 41 | -- | ||
| 42 | 2.34.1 | diff view generated by jsdifflib |
| 1 | Convert the virtio-ccw code to three-phase reset. This allows us to | 1 | In the helper functions flcmps and flcmpd we use a scratch float_status |
|---|---|---|---|
| 2 | remove a call to device_class_set_parent_reset(), replacing it with | 2 | so that we don't change the CPU state if the comparison raises any |
| 3 | the three-phase equivalent resettable_class_set_parent_phases(). | 3 | floating point exception flags. Instead of zero-initializing this |
| 4 | Removing all the device_class_set_parent_reset() uses will allow us | 4 | scratch float_status, initialize it as a copy of env->fp_status. This |
| 5 | to remove some of the glue code that interworks between three-phase | 5 | avoids the need to explicitly initialize settings like the NaN |
| 6 | and legacy reset. | 6 | propagation rule or others we might add to softfloat in future. |
| 7 | 7 | ||
| 8 | This is a simple conversion, with no behavioural changes. | 8 | To do this we need to pass the CPU env pointer in to the helper. |
| 9 | 9 | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 12 | Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> | ||
| 13 | Acked-by: Thomas Huth <thuth@redhat.com> | ||
| 14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 15 | Message-id: 20240830145812.1967042-3-peter.maydell@linaro.org | 12 | Message-id: 20241202131347.498124-33-peter.maydell@linaro.org |
| 16 | --- | 13 | --- |
| 17 | hw/s390x/virtio-ccw.h | 2 +- | 14 | target/sparc/helper.h | 4 ++-- |
| 18 | hw/s390x/virtio-ccw.c | 13 ++++++++----- | 15 | target/sparc/fop_helper.c | 8 ++++---- |
| 19 | 2 files changed, 9 insertions(+), 6 deletions(-) | 16 | target/sparc/translate.c | 4 ++-- |
| 17 | 3 files changed, 8 insertions(+), 8 deletions(-) | ||
| 20 | 18 | ||
| 21 | diff --git a/hw/s390x/virtio-ccw.h b/hw/s390x/virtio-ccw.h | 19 | diff --git a/target/sparc/helper.h b/target/sparc/helper.h |
| 22 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
| 23 | --- a/hw/s390x/virtio-ccw.h | 21 | --- a/target/sparc/helper.h |
| 24 | +++ b/hw/s390x/virtio-ccw.h | 22 | +++ b/target/sparc/helper.h |
| 25 | @@ -XXX,XX +XXX,XX @@ struct VirtIOCCWDeviceClass { | 23 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64) |
| 26 | CCWDeviceClass parent_class; | 24 | DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64) |
| 27 | void (*realize)(VirtioCcwDevice *dev, Error **errp); | 25 | DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128) |
| 28 | void (*unrealize)(VirtioCcwDevice *dev); | 26 | DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128) |
| 29 | - void (*parent_reset)(DeviceState *dev); | 27 | -DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32) |
| 30 | + ResettablePhases parent_phases; | 28 | -DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64) |
| 31 | }; | 29 | +DEF_HELPER_FLAGS_3(flcmps, TCG_CALL_NO_RWG_SE, i32, env, f32, f32) |
| 32 | 30 | +DEF_HELPER_FLAGS_3(flcmpd, TCG_CALL_NO_RWG_SE, i32, env, f64, f64) | |
| 33 | /* Performance improves when virtqueue kick processing is decoupled from the | 31 | DEF_HELPER_2(raise_exception, noreturn, env, int) |
| 34 | diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c | 32 | |
| 33 | DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64) | ||
| 34 | diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c | ||
| 35 | index XXXXXXX..XXXXXXX 100644 | 35 | index XXXXXXX..XXXXXXX 100644 |
| 36 | --- a/hw/s390x/virtio-ccw.c | 36 | --- a/target/sparc/fop_helper.c |
| 37 | +++ b/hw/s390x/virtio-ccw.c | 37 | +++ b/target/sparc/fop_helper.c |
| 38 | @@ -XXX,XX +XXX,XX @@ static void virtio_ccw_notify(DeviceState *d, uint16_t vector) | 38 | @@ -XXX,XX +XXX,XX @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2) |
| 39 | } | 39 | return finish_fcmp(env, r, GETPC()); |
| 40 | } | 40 | } |
| 41 | 41 | ||
| 42 | -static void virtio_ccw_reset(DeviceState *d) | 42 | -uint32_t helper_flcmps(float32 src1, float32 src2) |
| 43 | +static void virtio_ccw_reset_hold(Object *obj, ResetType type) | 43 | +uint32_t helper_flcmps(CPUSPARCState *env, float32 src1, float32 src2) |
| 44 | { | 44 | { |
| 45 | - VirtioCcwDevice *dev = VIRTIO_CCW_DEVICE(d); | 45 | /* |
| 46 | + VirtioCcwDevice *dev = VIRTIO_CCW_DEVICE(obj); | 46 | * FLCMP never raises an exception nor modifies any FSR fields. |
| 47 | VirtIOCCWDeviceClass *vdc = VIRTIO_CCW_DEVICE_GET_CLASS(dev); | 47 | * Perform the comparison with a dummy fp environment. |
| 48 | 48 | */ | |
| 49 | virtio_ccw_reset_virtio(dev); | 49 | - float_status discard = { }; |
| 50 | - if (vdc->parent_reset) { | 50 | + float_status discard = env->fp_status; |
| 51 | - vdc->parent_reset(d); | 51 | FloatRelation r; |
| 52 | + | 52 | |
| 53 | + if (vdc->parent_phases.hold) { | 53 | set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard); |
| 54 | + vdc->parent_phases.hold(obj, type); | 54 | @@ -XXX,XX +XXX,XX @@ uint32_t helper_flcmps(float32 src1, float32 src2) |
| 55 | } | 55 | g_assert_not_reached(); |
| 56 | } | 56 | } |
| 57 | 57 | ||
| 58 | @@ -XXX,XX +XXX,XX @@ static void virtio_ccw_device_class_init(ObjectClass *klass, void *data) | 58 | -uint32_t helper_flcmpd(float64 src1, float64 src2) |
| 59 | DeviceClass *dc = DEVICE_CLASS(klass); | 59 | +uint32_t helper_flcmpd(CPUSPARCState *env, float64 src1, float64 src2) |
| 60 | CCWDeviceClass *k = CCW_DEVICE_CLASS(dc); | 60 | { |
| 61 | VirtIOCCWDeviceClass *vdc = VIRTIO_CCW_DEVICE_CLASS(klass); | 61 | - float_status discard = { }; |
| 62 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | 62 | + float_status discard = env->fp_status; |
| 63 | 63 | FloatRelation r; | |
| 64 | k->unplug = virtio_ccw_busdev_unplug; | 64 | |
| 65 | dc->realize = virtio_ccw_busdev_realize; | 65 | set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard); |
| 66 | dc->unrealize = virtio_ccw_busdev_unrealize; | 66 | diff --git a/target/sparc/translate.c b/target/sparc/translate.c |
| 67 | - device_class_set_parent_reset(dc, virtio_ccw_reset, &vdc->parent_reset); | 67 | index XXXXXXX..XXXXXXX 100644 |
| 68 | + resettable_class_set_parent_phases(rc, NULL, virtio_ccw_reset_hold, NULL, | 68 | --- a/target/sparc/translate.c |
| 69 | + &vdc->parent_phases); | 69 | +++ b/target/sparc/translate.c |
| 70 | @@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a) | ||
| 71 | |||
| 72 | src1 = gen_load_fpr_F(dc, a->rs1); | ||
| 73 | src2 = gen_load_fpr_F(dc, a->rs2); | ||
| 74 | - gen_helper_flcmps(cpu_fcc[a->cc], src1, src2); | ||
| 75 | + gen_helper_flcmps(cpu_fcc[a->cc], tcg_env, src1, src2); | ||
| 76 | return advance_pc(dc); | ||
| 70 | } | 77 | } |
| 71 | 78 | ||
| 72 | static const TypeInfo virtio_ccw_device_info = { | 79 | @@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a) |
| 80 | |||
| 81 | src1 = gen_load_fpr_D(dc, a->rs1); | ||
| 82 | src2 = gen_load_fpr_D(dc, a->rs2); | ||
| 83 | - gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2); | ||
| 84 | + gen_helper_flcmpd(cpu_fcc[a->cc], tcg_env, src1, src2); | ||
| 85 | return advance_pc(dc); | ||
| 86 | } | ||
| 87 | |||
| 73 | -- | 88 | -- |
| 74 | 2.34.1 | 89 | 2.34.1 |
| 75 | |||
| 76 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | In the helper_compute_fprf functions, we pass a dummy float_status | ||
| 2 | in to the is_signaling_nan() function. This is unnecessary, because | ||
| 3 | we have convenient access to the CPU env pointer here and that | ||
| 4 | is already set up with the correct values for the snan_bit_is_one | ||
| 5 | and no_signaling_nans config settings. is_signaling_nan() doesn't | ||
| 6 | ever update the fp_status with any exception flags, so there is | ||
| 7 | no reason not to use env->fp_status here. | ||
| 1 | 8 | ||
| 9 | Use env->fp_status instead of the dummy fp_status. | ||
| 10 | |||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 13 | Message-id: 20241202131347.498124-34-peter.maydell@linaro.org | ||
| 14 | --- | ||
| 15 | target/ppc/fpu_helper.c | 3 +-- | ||
| 16 | 1 file changed, 1 insertion(+), 2 deletions(-) | ||
| 17 | |||
| 18 | diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c | ||
| 19 | index XXXXXXX..XXXXXXX 100644 | ||
| 20 | --- a/target/ppc/fpu_helper.c | ||
| 21 | +++ b/target/ppc/fpu_helper.c | ||
| 22 | @@ -XXX,XX +XXX,XX @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \ | ||
| 23 | } else if (tp##_is_infinity(arg)) { \ | ||
| 24 | fprf = neg ? 0x09 << FPSCR_FPRF : 0x05 << FPSCR_FPRF; \ | ||
| 25 | } else { \ | ||
| 26 | - float_status dummy = { }; /* snan_bit_is_one = 0 */ \ | ||
| 27 | - if (tp##_is_signaling_nan(arg, &dummy)) { \ | ||
| 28 | + if (tp##_is_signaling_nan(arg, &env->fp_status)) { \ | ||
| 29 | fprf = 0x00 << FPSCR_FPRF; \ | ||
| 30 | } else { \ | ||
| 31 | fprf = 0x11 << FPSCR_FPRF; \ | ||
| 32 | -- | ||
| 33 | 2.34.1 | diff view generated by jsdifflib |
| 1 | Convert the TYPE_CCW_DEVICE to three-phase reset. This is a | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | device class which is subclassed, so it needs to be three-phase | ||
| 3 | before we can convert the subclass. | ||
| 4 | 2 | ||
| 3 | Now that float_status has a bunch of fp parameters, | ||
| 4 | it is easier to copy an existing structure than create | ||
| 5 | one from scratch. Begin by copying the structure that | ||
| 6 | corresponds to the FPSR and make only the adjustments | ||
| 7 | required for BFloat16 semantics. | ||
| 8 | |||
| 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 12 | Message-id: 20241203203949.483774-2-richard.henderson@linaro.org | ||
| 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 6 | Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> | ||
| 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 8 | Acked-by: Thomas Huth <thuth@redhat.com> | ||
| 9 | Message-id: 20240830145812.1967042-2-peter.maydell@linaro.org | ||
| 10 | --- | 14 | --- |
| 11 | hw/s390x/ccw-device.c | 7 ++++--- | 15 | target/arm/tcg/vec_helper.c | 20 +++++++------------- |
| 12 | 1 file changed, 4 insertions(+), 3 deletions(-) | 16 | 1 file changed, 7 insertions(+), 13 deletions(-) |
| 13 | 17 | ||
| 14 | diff --git a/hw/s390x/ccw-device.c b/hw/s390x/ccw-device.c | 18 | diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c |
| 15 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/hw/s390x/ccw-device.c | 20 | --- a/target/arm/tcg/vec_helper.c |
| 17 | +++ b/hw/s390x/ccw-device.c | 21 | +++ b/target/arm/tcg/vec_helper.c |
| 18 | @@ -XXX,XX +XXX,XX @@ static Property ccw_device_properties[] = { | 22 | @@ -XXX,XX +XXX,XX @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp) |
| 19 | DEFINE_PROP_END_OF_LIST(), | 23 | * no effect on AArch32 instructions. |
| 20 | }; | 24 | */ |
| 21 | 25 | bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF; | |
| 22 | -static void ccw_device_reset(DeviceState *d) | 26 | - *statusp = (float_status){ |
| 23 | +static void ccw_device_reset_hold(Object *obj, ResetType type) | 27 | - .tininess_before_rounding = float_tininess_before_rounding, |
| 24 | { | 28 | - .float_rounding_mode = float_round_to_odd_inf, |
| 25 | - CcwDevice *ccw_dev = CCW_DEVICE(d); | 29 | - .flush_to_zero = true, |
| 26 | + CcwDevice *ccw_dev = CCW_DEVICE(obj); | 30 | - .flush_inputs_to_zero = true, |
| 27 | 31 | - .default_nan_mode = true, | |
| 28 | css_reset_sch(ccw_dev->sch); | 32 | - }; |
| 33 | + | ||
| 34 | + *statusp = env->vfp.fp_status; | ||
| 35 | + set_default_nan_mode(true, statusp); | ||
| 36 | |||
| 37 | if (ebf) { | ||
| 38 | - float_status *fpst = &env->vfp.fp_status; | ||
| 39 | - set_flush_to_zero(get_flush_to_zero(fpst), statusp); | ||
| 40 | - set_flush_inputs_to_zero(get_flush_inputs_to_zero(fpst), statusp); | ||
| 41 | - set_float_rounding_mode(get_float_rounding_mode(fpst), statusp); | ||
| 42 | - | ||
| 43 | /* EBF=1 needs to do a step with round-to-odd semantics */ | ||
| 44 | *oddstatusp = *statusp; | ||
| 45 | set_float_rounding_mode(float_round_to_odd, oddstatusp); | ||
| 46 | + } else { | ||
| 47 | + set_flush_to_zero(true, statusp); | ||
| 48 | + set_flush_inputs_to_zero(true, statusp); | ||
| 49 | + set_float_rounding_mode(float_round_to_odd_inf, statusp); | ||
| 50 | } | ||
| 51 | - | ||
| 52 | return ebf; | ||
| 29 | } | 53 | } |
| 30 | @@ -XXX,XX +XXX,XX @@ static void ccw_device_class_init(ObjectClass *klass, void *data) | ||
| 31 | { | ||
| 32 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 33 | CCWDeviceClass *k = CCW_DEVICE_CLASS(klass); | ||
| 34 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
| 35 | |||
| 36 | k->realize = ccw_device_realize; | ||
| 37 | k->refill_ids = ccw_device_refill_ids; | ||
| 38 | device_class_set_props(dc, ccw_device_properties); | ||
| 39 | - dc->reset = ccw_device_reset; | ||
| 40 | + rc->phases.hold = ccw_device_reset_hold; | ||
| 41 | dc->bus_type = TYPE_VIRTUAL_CSS_BUS; | ||
| 42 | } | ||
| 43 | 54 | ||
| 44 | -- | 55 | -- |
| 45 | 2.34.1 | 56 | 2.34.1 |
| 46 | 57 | ||
| 47 | 58 | diff view generated by jsdifflib |
| 1 | From: Danny Canter <danny_canter@apple.com> | 1 | Currently we hardcode the default NaN value in parts64_default_nan() |
|---|---|---|---|
| 2 | using a compile-time ifdef ladder. This is awkward for two cases: | ||
| 3 | * for single-QEMU-binary we can't hard-code target-specifics like this | ||
| 4 | * for Arm FEAT_AFP the default NaN value depends on FPCR.AH | ||
| 5 | (specifically the sign bit is different) | ||
| 2 | 6 | ||
| 3 | This is preliminary work to split up hv_vm_create | 7 | Add a field to float_status to specify the default NaN value; fall |
| 4 | logic per platform so we can support creating VMs | 8 | back to the old ifdef behaviour if these are not set. |
| 5 | with > 64GB of RAM on Apple Silicon machines. This | ||
| 6 | is done via ARM HVF's hv_vm_config_create() (and | ||
| 7 | other APIs that modify this config that will be | ||
| 8 | coming in future patches). This should have no | ||
| 9 | behavioral difference at all as hv_vm_config_create() | ||
| 10 | just assigns the same default values as if you just | ||
| 11 | passed NULL to the function. | ||
| 12 | 9 | ||
| 13 | Signed-off-by: Danny Canter <danny_canter@apple.com> | 10 | The default NaN value is specified by setting a uint8_t to a |
| 14 | Message-id: 20240828111552.93482-3-danny_canter@apple.com | 11 | pattern corresponding to the sign and upper fraction parts of |
| 15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 12 | the NaN; the lower bits of the fraction are set from bit 0 of |
| 13 | the pattern. | ||
| 14 | |||
| 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 17 | Message-id: 20241202131347.498124-35-peter.maydell@linaro.org | ||
| 17 | --- | 18 | --- |
| 18 | include/sysemu/hvf_int.h | 1 + | 19 | include/fpu/softfloat-helpers.h | 11 +++++++ |
| 19 | accel/hvf/hvf-accel-ops.c | 6 +----- | 20 | include/fpu/softfloat-types.h | 10 ++++++ |
| 20 | target/arm/hvf/hvf.c | 9 +++++++++ | 21 | fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++------------- |
| 21 | target/i386/hvf/hvf.c | 5 +++++ | 22 | 3 files changed, 54 insertions(+), 22 deletions(-) |
| 22 | 4 files changed, 16 insertions(+), 5 deletions(-) | ||
| 23 | 23 | ||
| 24 | diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h | 24 | diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h |
| 25 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
| 26 | --- a/include/sysemu/hvf_int.h | 26 | --- a/include/fpu/softfloat-helpers.h |
| 27 | +++ b/include/sysemu/hvf_int.h | 27 | +++ b/include/fpu/softfloat-helpers.h |
| 28 | @@ -XXX,XX +XXX,XX @@ void assert_hvf_ok_impl(hv_return_t ret, const char *file, unsigned int line, | 28 | @@ -XXX,XX +XXX,XX @@ static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, |
| 29 | #define assert_hvf_ok(EX) assert_hvf_ok_impl((EX), __FILE__, __LINE__, #EX) | 29 | status->float_infzeronan_rule = rule; |
| 30 | const char *hvf_return_string(hv_return_t ret); | ||
| 31 | int hvf_arch_init(void); | ||
| 32 | +hv_return_t hvf_arch_vm_create(MachineState *ms, uint32_t pa_range); | ||
| 33 | int hvf_arch_init_vcpu(CPUState *cpu); | ||
| 34 | void hvf_arch_vcpu_destroy(CPUState *cpu); | ||
| 35 | int hvf_vcpu_exec(CPUState *); | ||
| 36 | diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c | ||
| 37 | index XXXXXXX..XXXXXXX 100644 | ||
| 38 | --- a/accel/hvf/hvf-accel-ops.c | ||
| 39 | +++ b/accel/hvf/hvf-accel-ops.c | ||
| 40 | @@ -XXX,XX +XXX,XX @@ | ||
| 41 | |||
| 42 | HVFState *hvf_state; | ||
| 43 | |||
| 44 | -#ifdef __aarch64__ | ||
| 45 | -#define HV_VM_DEFAULT NULL | ||
| 46 | -#endif | ||
| 47 | - | ||
| 48 | /* Memory slots */ | ||
| 49 | |||
| 50 | hvf_slot *hvf_find_overlap_slot(uint64_t start, uint64_t size) | ||
| 51 | @@ -XXX,XX +XXX,XX @@ static int hvf_accel_init(MachineState *ms) | ||
| 52 | hv_return_t ret; | ||
| 53 | HVFState *s; | ||
| 54 | |||
| 55 | - ret = hv_vm_create(HV_VM_DEFAULT); | ||
| 56 | + ret = hvf_arch_vm_create(ms, 0); | ||
| 57 | assert_hvf_ok(ret); | ||
| 58 | |||
| 59 | s = g_new0(HVFState, 1); | ||
| 60 | diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c | ||
| 61 | index XXXXXXX..XXXXXXX 100644 | ||
| 62 | --- a/target/arm/hvf/hvf.c | ||
| 63 | +++ b/target/arm/hvf/hvf.c | ||
| 64 | @@ -XXX,XX +XXX,XX @@ void hvf_arch_vcpu_destroy(CPUState *cpu) | ||
| 65 | { | ||
| 66 | } | 30 | } |
| 67 | 31 | ||
| 68 | +hv_return_t hvf_arch_vm_create(MachineState *ms, uint32_t pa_range) | 32 | +static inline void set_float_default_nan_pattern(uint8_t dnan_pattern, |
| 33 | + float_status *status) | ||
| 69 | +{ | 34 | +{ |
| 70 | + hv_vm_config_t config = hv_vm_config_create(); | 35 | + status->default_nan_pattern = dnan_pattern; |
| 71 | + hv_return_t ret = hv_vm_create(config); | ||
| 72 | + os_release(config); | ||
| 73 | + | ||
| 74 | + return ret; | ||
| 75 | +} | 36 | +} |
| 76 | + | 37 | + |
| 77 | int hvf_arch_init_vcpu(CPUState *cpu) | 38 | static inline void set_flush_to_zero(bool val, float_status *status) |
| 78 | { | 39 | { |
| 79 | ARMCPU *arm_cpu = ARM_CPU(cpu); | 40 | status->flush_to_zero = val; |
| 80 | diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c | 41 | @@ -XXX,XX +XXX,XX @@ static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status |
| 81 | index XXXXXXX..XXXXXXX 100644 | 42 | return status->float_infzeronan_rule; |
| 82 | --- a/target/i386/hvf/hvf.c | ||
| 83 | +++ b/target/i386/hvf/hvf.c | ||
| 84 | @@ -XXX,XX +XXX,XX @@ int hvf_arch_init(void) | ||
| 85 | return 0; | ||
| 86 | } | 43 | } |
| 87 | 44 | ||
| 88 | +hv_return_t hvf_arch_vm_create(MachineState *ms, uint32_t pa_range) | 45 | +static inline uint8_t get_float_default_nan_pattern(float_status *status) |
| 89 | +{ | 46 | +{ |
| 90 | + return hv_vm_create(HV_VM_DEFAULT); | 47 | + return status->default_nan_pattern; |
| 91 | +} | 48 | +} |
| 92 | + | 49 | + |
| 93 | int hvf_arch_init_vcpu(CPUState *cpu) | 50 | static inline bool get_flush_to_zero(float_status *status) |
| 94 | { | 51 | { |
| 95 | X86CPU *x86cpu = X86_CPU(cpu); | 52 | return status->flush_to_zero; |
| 53 | diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h | ||
| 54 | index XXXXXXX..XXXXXXX 100644 | ||
| 55 | --- a/include/fpu/softfloat-types.h | ||
| 56 | +++ b/include/fpu/softfloat-types.h | ||
| 57 | @@ -XXX,XX +XXX,XX @@ typedef struct float_status { | ||
| 58 | /* should denormalised inputs go to zero and set the input_denormal flag? */ | ||
| 59 | bool flush_inputs_to_zero; | ||
| 60 | bool default_nan_mode; | ||
| 61 | + /* | ||
| 62 | + * The pattern to use for the default NaN. Here the high bit specifies | ||
| 63 | + * the default NaN's sign bit, and bits 6..0 specify the high bits of the | ||
| 64 | + * fractional part. The low bits of the fractional part are copies of bit 0. | ||
| 65 | + * The exponent of the default NaN is (as for any NaN) always all 1s. | ||
| 66 | + * Note that a value of 0 here is not a valid NaN. The target must set | ||
| 67 | + * this to the correct non-zero value, or we will assert when trying to | ||
| 68 | + * create a default NaN. | ||
| 69 | + */ | ||
| 70 | + uint8_t default_nan_pattern; | ||
| 71 | /* | ||
| 72 | * The flags below are not used on all specializations and may | ||
| 73 | * constant fold away (see snan_bit_is_one()/no_signalling_nans() in | ||
| 74 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 75 | index XXXXXXX..XXXXXXX 100644 | ||
| 76 | --- a/fpu/softfloat-specialize.c.inc | ||
| 77 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 78 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
| 79 | { | ||
| 80 | bool sign = 0; | ||
| 81 | uint64_t frac; | ||
| 82 | + uint8_t dnan_pattern = status->default_nan_pattern; | ||
| 83 | |||
| 84 | + if (dnan_pattern == 0) { | ||
| 85 | #if defined(TARGET_SPARC) || defined(TARGET_M68K) | ||
| 86 | - /* !snan_bit_is_one, set all bits */ | ||
| 87 | - frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; | ||
| 88 | -#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ | ||
| 89 | + /* Sign bit clear, all frac bits set */ | ||
| 90 | + dnan_pattern = 0b01111111; | ||
| 91 | +#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ | ||
| 92 | || defined(TARGET_MICROBLAZE) | ||
| 93 | - /* !snan_bit_is_one, set sign and msb */ | ||
| 94 | - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); | ||
| 95 | - sign = 1; | ||
| 96 | + /* Sign bit set, most significant frac bit set */ | ||
| 97 | + dnan_pattern = 0b11000000; | ||
| 98 | #elif defined(TARGET_HPPA) | ||
| 99 | - /* snan_bit_is_one, set msb-1. */ | ||
| 100 | - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); | ||
| 101 | + /* Sign bit clear, msb-1 frac bit set */ | ||
| 102 | + dnan_pattern = 0b00100000; | ||
| 103 | #elif defined(TARGET_HEXAGON) | ||
| 104 | - sign = 1; | ||
| 105 | - frac = ~0ULL; | ||
| 106 | + /* Sign bit set, all frac bits set. */ | ||
| 107 | + dnan_pattern = 0b11111111; | ||
| 108 | #else | ||
| 109 | - /* | ||
| 110 | - * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, | ||
| 111 | - * S390, SH4, TriCore, and Xtensa. Our other supported targets | ||
| 112 | - * do not have floating-point. | ||
| 113 | - */ | ||
| 114 | - if (snan_bit_is_one(status)) { | ||
| 115 | - /* set all bits other than msb */ | ||
| 116 | - frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; | ||
| 117 | - } else { | ||
| 118 | - /* set msb */ | ||
| 119 | - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); | ||
| 120 | - } | ||
| 121 | + /* | ||
| 122 | + * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, | ||
| 123 | + * S390, SH4, TriCore, and Xtensa. Our other supported targets | ||
| 124 | + * do not have floating-point. | ||
| 125 | + */ | ||
| 126 | + if (snan_bit_is_one(status)) { | ||
| 127 | + /* sign bit clear, set all frac bits other than msb */ | ||
| 128 | + dnan_pattern = 0b00111111; | ||
| 129 | + } else { | ||
| 130 | + /* sign bit clear, set frac msb */ | ||
| 131 | + dnan_pattern = 0b01000000; | ||
| 132 | + } | ||
| 133 | #endif | ||
| 134 | + } | ||
| 135 | + assert(dnan_pattern != 0); | ||
| 136 | + | ||
| 137 | + sign = dnan_pattern >> 7; | ||
| 138 | + /* | ||
| 139 | + * Place default_nan_pattern [6:0] into bits [62:56], | ||
| 140 | + * and replecate bit [0] down into [55:0] | ||
| 141 | + */ | ||
| 142 | + frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern); | ||
| 143 | + frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1)); | ||
| 144 | |||
| 145 | *p = (FloatParts64) { | ||
| 146 | .cls = float_class_qnan, | ||
| 96 | -- | 147 | -- |
| 97 | 2.34.1 | 148 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the default NaN pattern explicitly for the tests/fp code. | ||
| 1 | 2 | ||
| 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 5 | Message-id: 20241202131347.498124-36-peter.maydell@linaro.org | ||
| 6 | --- | ||
| 7 | tests/fp/fp-bench.c | 1 + | ||
| 8 | tests/fp/fp-test-log2.c | 1 + | ||
| 9 | tests/fp/fp-test.c | 1 + | ||
| 10 | 3 files changed, 3 insertions(+) | ||
| 11 | |||
| 12 | diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/tests/fp/fp-bench.c | ||
| 15 | +++ b/tests/fp/fp-bench.c | ||
| 16 | @@ -XXX,XX +XXX,XX @@ static void run_bench(void) | ||
| 17 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); | ||
| 18 | set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status); | ||
| 19 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); | ||
| 20 | + set_float_default_nan_pattern(0b01000000, &soft_status); | ||
| 21 | |||
| 22 | f = bench_funcs[operation][precision]; | ||
| 23 | g_assert(f); | ||
| 24 | diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c | ||
| 25 | index XXXXXXX..XXXXXXX 100644 | ||
| 26 | --- a/tests/fp/fp-test-log2.c | ||
| 27 | +++ b/tests/fp/fp-test-log2.c | ||
| 28 | @@ -XXX,XX +XXX,XX @@ int main(int ac, char **av) | ||
| 29 | int i; | ||
| 30 | |||
| 31 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); | ||
| 32 | + set_float_default_nan_pattern(0b01000000, &qsf); | ||
| 33 | set_float_rounding_mode(float_round_nearest_even, &qsf); | ||
| 34 | |||
| 35 | test.d = 0.0; | ||
| 36 | diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c | ||
| 37 | index XXXXXXX..XXXXXXX 100644 | ||
| 38 | --- a/tests/fp/fp-test.c | ||
| 39 | +++ b/tests/fp/fp-test.c | ||
| 40 | @@ -XXX,XX +XXX,XX @@ void run_test(void) | ||
| 41 | */ | ||
| 42 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); | ||
| 43 | set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf); | ||
| 44 | + set_float_default_nan_pattern(0b01000000, &qsf); | ||
| 45 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); | ||
| 46 | |||
| 47 | genCases_setLevel(test_level); | ||
| 48 | -- | ||
| 49 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the default NaN pattern explicitly, and remove the ifdef from | ||
| 2 | parts64_default_nan(). | ||
| 1 | 3 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-37-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/microblaze/cpu.c | 2 ++ | ||
| 9 | fpu/softfloat-specialize.c.inc | 3 +-- | ||
| 10 | 2 files changed, 3 insertions(+), 2 deletions(-) | ||
| 11 | |||
| 12 | diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/microblaze/cpu.c | ||
| 15 | +++ b/target/microblaze/cpu.c | ||
| 16 | @@ -XXX,XX +XXX,XX @@ static void mb_cpu_reset_hold(Object *obj, ResetType type) | ||
| 17 | * this architecture. | ||
| 18 | */ | ||
| 19 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); | ||
| 20 | + /* Default NaN: sign bit set, most significant frac bit set */ | ||
| 21 | + set_float_default_nan_pattern(0b11000000, &env->fp_status); | ||
| 22 | |||
| 23 | #if defined(CONFIG_USER_ONLY) | ||
| 24 | /* start in user mode with interrupts enabled. */ | ||
| 25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 26 | index XXXXXXX..XXXXXXX 100644 | ||
| 27 | --- a/fpu/softfloat-specialize.c.inc | ||
| 28 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 29 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
| 30 | #if defined(TARGET_SPARC) || defined(TARGET_M68K) | ||
| 31 | /* Sign bit clear, all frac bits set */ | ||
| 32 | dnan_pattern = 0b01111111; | ||
| 33 | -#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ | ||
| 34 | - || defined(TARGET_MICROBLAZE) | ||
| 35 | +#elif defined(TARGET_I386) || defined(TARGET_X86_64) | ||
| 36 | /* Sign bit set, most significant frac bit set */ | ||
| 37 | dnan_pattern = 0b11000000; | ||
| 38 | #elif defined(TARGET_HPPA) | ||
| 39 | -- | ||
| 40 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the default NaN pattern explicitly, and remove the ifdef from | ||
| 2 | parts64_default_nan(). | ||
| 1 | 3 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-38-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/i386/tcg/fpu_helper.c | 4 ++++ | ||
| 9 | fpu/softfloat-specialize.c.inc | 3 --- | ||
| 10 | 2 files changed, 4 insertions(+), 3 deletions(-) | ||
| 11 | |||
| 12 | diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/i386/tcg/fpu_helper.c | ||
| 15 | +++ b/target/i386/tcg/fpu_helper.c | ||
| 16 | @@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env) | ||
| 17 | */ | ||
| 18 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); | ||
| 19 | set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status); | ||
| 20 | + /* Default NaN: sign bit set, most significant frac bit set */ | ||
| 21 | + set_float_default_nan_pattern(0b11000000, &env->fp_status); | ||
| 22 | + set_float_default_nan_pattern(0b11000000, &env->mmx_status); | ||
| 23 | + set_float_default_nan_pattern(0b11000000, &env->sse_status); | ||
| 24 | } | ||
| 25 | |||
| 26 | static inline uint8_t save_exception_flags(CPUX86State *env) | ||
| 27 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 28 | index XXXXXXX..XXXXXXX 100644 | ||
| 29 | --- a/fpu/softfloat-specialize.c.inc | ||
| 30 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 31 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
| 32 | #if defined(TARGET_SPARC) || defined(TARGET_M68K) | ||
| 33 | /* Sign bit clear, all frac bits set */ | ||
| 34 | dnan_pattern = 0b01111111; | ||
| 35 | -#elif defined(TARGET_I386) || defined(TARGET_X86_64) | ||
| 36 | - /* Sign bit set, most significant frac bit set */ | ||
| 37 | - dnan_pattern = 0b11000000; | ||
| 38 | #elif defined(TARGET_HPPA) | ||
| 39 | /* Sign bit clear, msb-1 frac bit set */ | ||
| 40 | dnan_pattern = 0b00100000; | ||
| 41 | -- | ||
| 42 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the default NaN pattern explicitly, and remove the ifdef from | ||
| 2 | parts64_default_nan(). | ||
| 1 | 3 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-39-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/hppa/fpu_helper.c | 2 ++ | ||
| 9 | fpu/softfloat-specialize.c.inc | 3 --- | ||
| 10 | 2 files changed, 2 insertions(+), 3 deletions(-) | ||
| 11 | |||
| 12 | diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/hppa/fpu_helper.c | ||
| 15 | +++ b/target/hppa/fpu_helper.c | ||
| 16 | @@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env) | ||
| 17 | set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status); | ||
| 18 | /* For inf * 0 + NaN, return the input NaN */ | ||
| 19 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
| 20 | + /* Default NaN: sign bit clear, msb-1 frac bit set */ | ||
| 21 | + set_float_default_nan_pattern(0b00100000, &env->fp_status); | ||
| 22 | } | ||
| 23 | |||
| 24 | void cpu_hppa_loaded_fr0(CPUHPPAState *env) | ||
| 25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 26 | index XXXXXXX..XXXXXXX 100644 | ||
| 27 | --- a/fpu/softfloat-specialize.c.inc | ||
| 28 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 29 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
| 30 | #if defined(TARGET_SPARC) || defined(TARGET_M68K) | ||
| 31 | /* Sign bit clear, all frac bits set */ | ||
| 32 | dnan_pattern = 0b01111111; | ||
| 33 | -#elif defined(TARGET_HPPA) | ||
| 34 | - /* Sign bit clear, msb-1 frac bit set */ | ||
| 35 | - dnan_pattern = 0b00100000; | ||
| 36 | #elif defined(TARGET_HEXAGON) | ||
| 37 | /* Sign bit set, all frac bits set. */ | ||
| 38 | dnan_pattern = 0b11111111; | ||
| 39 | -- | ||
| 40 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the default NaN pattern explicitly for the alpha target. | ||
| 1 | 2 | ||
| 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 5 | Message-id: 20241202131347.498124-40-peter.maydell@linaro.org | ||
| 6 | --- | ||
| 7 | target/alpha/cpu.c | 2 ++ | ||
| 8 | 1 file changed, 2 insertions(+) | ||
| 9 | |||
| 10 | diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c | ||
| 11 | index XXXXXXX..XXXXXXX 100644 | ||
| 12 | --- a/target/alpha/cpu.c | ||
| 13 | +++ b/target/alpha/cpu.c | ||
| 14 | @@ -XXX,XX +XXX,XX @@ static void alpha_cpu_initfn(Object *obj) | ||
| 15 | * operand in Fa. That is float_2nan_prop_ba. | ||
| 16 | */ | ||
| 17 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); | ||
| 18 | + /* Default NaN: sign bit clear, msb frac bit set */ | ||
| 19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); | ||
| 20 | #if defined(CONFIG_USER_ONLY) | ||
| 21 | env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN; | ||
| 22 | cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD | ||
| 23 | -- | ||
| 24 | 2.34.1 | diff view generated by jsdifflib |
| 1 | Currently we have transitional machinery between legacy reset | 1 | Set the default NaN pattern explicitly for the arm target. |
|---|---|---|---|
| 2 | and three phase reset that works in two directions: | 2 | This includes setting it for the old linux-user nwfpe emulation. |
| 3 | * if you invoke three phase reset on a device which has set | 3 | For nwfpe, our default doesn't match the real kernel, but we |
| 4 | the DeviceClass::legacy_reset method, we detect this in | 4 | avoid making a behaviour change in this commit. |
| 5 | device_get_transitional_reset() and arrange that we call | ||
| 6 | the legacy_reset method during the hold phase of reset | ||
| 7 | * if you invoke legacy reset on a device which implements | ||
| 8 | three phase reset, the default legacy_reset method is | ||
| 9 | device_phases_reset(), which does a three-phase reset | ||
| 10 | of the device | ||
| 11 | |||
| 12 | However, we have now eliminated all the places which could invoke | ||
| 13 | legacy reset on a device, which means that the function | ||
| 14 | device_phases_reset() is never called -- it serves only as the value | ||
| 15 | of DeviceClass::legacy_reset that indicates that the subclass never | ||
| 16 | overrode the legacy reset method. So we can delete it, and instead | ||
| 17 | check for legacy_reset != NULL. | ||
| 18 | 5 | ||
| 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 20 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 21 | Message-id: 20240830145812.1967042-10-peter.maydell@linaro.org | 8 | Message-id: 20241202131347.498124-41-peter.maydell@linaro.org |
| 22 | --- | 9 | --- |
| 23 | hw/core/qdev.c | 51 ++++++++++++-------------------------------------- | 10 | linux-user/arm/nwfpe/fpa11.c | 5 +++++ |
| 24 | 1 file changed, 12 insertions(+), 39 deletions(-) | 11 | target/arm/cpu.c | 2 ++ |
| 12 | 2 files changed, 7 insertions(+) | ||
| 25 | 13 | ||
| 26 | diff --git a/hw/core/qdev.c b/hw/core/qdev.c | 14 | diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c |
| 27 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 28 | --- a/hw/core/qdev.c | 16 | --- a/linux-user/arm/nwfpe/fpa11.c |
| 29 | +++ b/hw/core/qdev.c | 17 | +++ b/linux-user/arm/nwfpe/fpa11.c |
| 30 | @@ -XXX,XX +XXX,XX @@ device_vmstate_if_get_id(VMStateIf *obj) | 18 | @@ -XXX,XX +XXX,XX @@ void resetFPA11(void) |
| 31 | return qdev_get_dev_path(dev); | 19 | * this late date. |
| 20 | */ | ||
| 21 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status); | ||
| 22 | + /* | ||
| 23 | + * Use the same default NaN value as Arm VFP. This doesn't match | ||
| 24 | + * the Linux kernel's nwfpe emulation, which uses an all-1s value. | ||
| 25 | + */ | ||
| 26 | + set_float_default_nan_pattern(0b01000000, &fpa11->fp_status); | ||
| 32 | } | 27 | } |
| 33 | 28 | ||
| 34 | -/** | 29 | void SetRoundingMode(const unsigned int opcode) |
| 35 | - * device_phases_reset: | 30 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
| 36 | - * Transition reset method for devices to allow moving | 31 | index XXXXXXX..XXXXXXX 100644 |
| 37 | - * smoothly from legacy reset method to multi-phases | 32 | --- a/target/arm/cpu.c |
| 38 | - */ | 33 | +++ b/target/arm/cpu.c |
| 39 | -static void device_phases_reset(DeviceState *dev) | 34 | @@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
| 40 | -{ | 35 | * the pseudocode function the arguments are in the order c, a, b. |
| 41 | - ResettableClass *rc = RESETTABLE_GET_CLASS(dev); | 36 | * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, |
| 42 | - | 37 | * and the input NaN if it is signalling |
| 43 | - if (rc->phases.enter) { | 38 | + * * Default NaN has sign bit clear, msb frac bit set |
| 44 | - rc->phases.enter(OBJECT(dev), RESET_TYPE_COLD); | 39 | */ |
| 45 | - } | 40 | static void arm_set_default_fp_behaviours(float_status *s) |
| 46 | - if (rc->phases.hold) { | ||
| 47 | - rc->phases.hold(OBJECT(dev), RESET_TYPE_COLD); | ||
| 48 | - } | ||
| 49 | - if (rc->phases.exit) { | ||
| 50 | - rc->phases.exit(OBJECT(dev), RESET_TYPE_COLD); | ||
| 51 | - } | ||
| 52 | -} | ||
| 53 | - | ||
| 54 | static void device_transitional_reset(Object *obj) | ||
| 55 | { | 41 | { |
| 56 | DeviceClass *dc = DEVICE_GET_CLASS(obj); | 42 | @@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s) |
| 57 | 43 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); | |
| 58 | /* | 44 | set_float_3nan_prop_rule(float_3nan_prop_s_cab, s); |
| 59 | - * This will call either @device_phases_reset (for multi-phases transitioned | 45 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); |
| 60 | - * devices) or a device's specific method for not-yet transitioned devices. | 46 | + set_float_default_nan_pattern(0b01000000, s); |
| 61 | - * In both case, it does not reset children. | ||
| 62 | + * Device still using DeviceClass legacy_reset method. This doesn't | ||
| 63 | + * reset children. device_get_transitional_reset() checked that | ||
| 64 | + * this isn't NULL. | ||
| 65 | */ | ||
| 66 | - if (dc->legacy_reset) { | ||
| 67 | - dc->legacy_reset(DEVICE(obj)); | ||
| 68 | - } | ||
| 69 | + dc->legacy_reset(DEVICE(obj)); | ||
| 70 | } | 47 | } |
| 71 | 48 | ||
| 72 | /** | 49 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
| 73 | @@ -XXX,XX +XXX,XX @@ static void device_transitional_reset(Object *obj) | ||
| 74 | static ResettableTrFunction device_get_transitional_reset(Object *obj) | ||
| 75 | { | ||
| 76 | DeviceClass *dc = DEVICE_GET_CLASS(obj); | ||
| 77 | - if (dc->legacy_reset != device_phases_reset) { | ||
| 78 | + if (dc->legacy_reset) { | ||
| 79 | /* | ||
| 80 | * dc->reset has been overridden by a subclass, | ||
| 81 | * the device is not ready for multi phase yet. | ||
| 82 | @@ -XXX,XX +XXX,XX @@ static void device_class_init(ObjectClass *class, void *data) | ||
| 83 | rc->child_foreach = device_reset_child_foreach; | ||
| 84 | |||
| 85 | /* | ||
| 86 | - * @device_phases_reset is put as the default reset method below, allowing | ||
| 87 | - * to do the multi-phase transition from base classes to leaf classes. It | ||
| 88 | - * allows a legacy-reset Device class to extend a multi-phases-reset | ||
| 89 | - * Device class for the following reason: | ||
| 90 | - * + If a base class B has been moved to multi-phase, then it does not | ||
| 91 | - * override this default reset method and may have defined phase methods. | ||
| 92 | - * + A child class C (extending class B) which uses | ||
| 93 | - * device_class_set_parent_reset() (or similar means) to override the | ||
| 94 | - * reset method will still work as expected. @device_phases_reset function | ||
| 95 | - * will be registered as the parent reset method and effectively call | ||
| 96 | - * parent reset phases. | ||
| 97 | + * A NULL legacy_reset implies a three-phase reset device. Devices can | ||
| 98 | + * only be reset using three-phase aware mechanisms, but we still support | ||
| 99 | + * for transitional purposes leaf classes which set the old legacy_reset | ||
| 100 | + * method via device_class_set_legacy_reset(). If they do so, then | ||
| 101 | + * device_get_transitional_reset() will notice and arrange for the | ||
| 102 | + * DeviceClass::legacy_reset() method to be called during the hold phase. | ||
| 103 | */ | ||
| 104 | - device_class_set_legacy_reset(dc, device_phases_reset); | ||
| 105 | + dc->legacy_reset = NULL; | ||
| 106 | rc->get_transitional_function = device_get_transitional_reset; | ||
| 107 | |||
| 108 | object_class_property_add_bool(class, "realized", | ||
| 109 | -- | 50 | -- |
| 110 | 2.34.1 | 51 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the default NaN pattern explicitly for loongarch. | ||
| 1 | 2 | ||
| 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 5 | Message-id: 20241202131347.498124-42-peter.maydell@linaro.org | ||
| 6 | --- | ||
| 7 | target/loongarch/tcg/fpu_helper.c | 2 ++ | ||
| 8 | 1 file changed, 2 insertions(+) | ||
| 9 | |||
| 10 | diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c | ||
| 11 | index XXXXXXX..XXXXXXX 100644 | ||
| 12 | --- a/target/loongarch/tcg/fpu_helper.c | ||
| 13 | +++ b/target/loongarch/tcg/fpu_helper.c | ||
| 14 | @@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env) | ||
| 15 | */ | ||
| 16 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
| 17 | set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status); | ||
| 18 | + /* Default NaN: sign bit clear, msb frac bit set */ | ||
| 19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); | ||
| 20 | } | ||
| 21 | |||
| 22 | int ieee_ex_to_loongarch(int xcpt) | ||
| 23 | -- | ||
| 24 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the default NaN pattern explicitly for m68k. | ||
| 1 | 2 | ||
| 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 5 | Message-id: 20241202131347.498124-43-peter.maydell@linaro.org | ||
| 6 | --- | ||
| 7 | target/m68k/cpu.c | 2 ++ | ||
| 8 | fpu/softfloat-specialize.c.inc | 2 +- | ||
| 9 | 2 files changed, 3 insertions(+), 1 deletion(-) | ||
| 10 | |||
| 11 | diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c | ||
| 12 | index XXXXXXX..XXXXXXX 100644 | ||
| 13 | --- a/target/m68k/cpu.c | ||
| 14 | +++ b/target/m68k/cpu.c | ||
| 15 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) | ||
| 16 | * preceding paragraph for nonsignaling NaNs. | ||
| 17 | */ | ||
| 18 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); | ||
| 19 | + /* Default NaN: sign bit clear, all frac bits set */ | ||
| 20 | + set_float_default_nan_pattern(0b01111111, &env->fp_status); | ||
| 21 | |||
| 22 | nan = floatx80_default_nan(&env->fp_status); | ||
| 23 | for (i = 0; i < 8; i++) { | ||
| 24 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 25 | index XXXXXXX..XXXXXXX 100644 | ||
| 26 | --- a/fpu/softfloat-specialize.c.inc | ||
| 27 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 28 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
| 29 | uint8_t dnan_pattern = status->default_nan_pattern; | ||
| 30 | |||
| 31 | if (dnan_pattern == 0) { | ||
| 32 | -#if defined(TARGET_SPARC) || defined(TARGET_M68K) | ||
| 33 | +#if defined(TARGET_SPARC) | ||
| 34 | /* Sign bit clear, all frac bits set */ | ||
| 35 | dnan_pattern = 0b01111111; | ||
| 36 | #elif defined(TARGET_HEXAGON) | ||
| 37 | -- | ||
| 38 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the default NaN pattern explicitly for MIPS. Note that this | ||
| 2 | is our only target which currently changes the default NaN | ||
| 3 | at runtime (which it was previously doing indirectly when it | ||
| 4 | changed the snan_bit_is_one setting). | ||
| 1 | 5 | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20241202131347.498124-44-peter.maydell@linaro.org | ||
| 9 | --- | ||
| 10 | target/mips/fpu_helper.h | 7 +++++++ | ||
| 11 | target/mips/msa.c | 3 +++ | ||
| 12 | 2 files changed, 10 insertions(+) | ||
| 13 | |||
| 14 | diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/mips/fpu_helper.h | ||
| 17 | +++ b/target/mips/fpu_helper.h | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) | ||
| 19 | set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); | ||
| 20 | nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc; | ||
| 21 | set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status); | ||
| 22 | + /* | ||
| 23 | + * With nan2008, the default NaN value has the sign bit clear and the | ||
| 24 | + * frac msb set; with the older mode, the sign bit is clear, and all | ||
| 25 | + * frac bits except the msb are set. | ||
| 26 | + */ | ||
| 27 | + set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111, | ||
| 28 | + &env->active_fpu.fp_status); | ||
| 29 | |||
| 30 | } | ||
| 31 | |||
| 32 | diff --git a/target/mips/msa.c b/target/mips/msa.c | ||
| 33 | index XXXXXXX..XXXXXXX 100644 | ||
| 34 | --- a/target/mips/msa.c | ||
| 35 | +++ b/target/mips/msa.c | ||
| 36 | @@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env) | ||
| 37 | /* Inf * 0 + NaN returns the input NaN */ | ||
| 38 | set_float_infzeronan_rule(float_infzeronan_dnan_never, | ||
| 39 | &env->active_tc.msa_fp_status); | ||
| 40 | + /* Default NaN: sign bit clear, frac msb set */ | ||
| 41 | + set_float_default_nan_pattern(0b01000000, | ||
| 42 | + &env->active_tc.msa_fp_status); | ||
| 43 | } | ||
| 44 | -- | ||
| 45 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the default NaN pattern explicitly for openrisc. | ||
| 1 | 2 | ||
| 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 5 | Message-id: 20241202131347.498124-45-peter.maydell@linaro.org | ||
| 6 | --- | ||
| 7 | target/openrisc/cpu.c | 2 ++ | ||
| 8 | 1 file changed, 2 insertions(+) | ||
| 9 | |||
| 10 | diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c | ||
| 11 | index XXXXXXX..XXXXXXX 100644 | ||
| 12 | --- a/target/openrisc/cpu.c | ||
| 13 | +++ b/target/openrisc/cpu.c | ||
| 14 | @@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type) | ||
| 15 | */ | ||
| 16 | set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status); | ||
| 17 | |||
| 18 | + /* Default NaN: sign bit clear, frac msb set */ | ||
| 19 | + set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status); | ||
| 20 | |||
| 21 | #ifndef CONFIG_USER_ONLY | ||
| 22 | cpu->env.picmr = 0x00000000; | ||
| 23 | -- | ||
| 24 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the default NaN pattern explicitly for ppc. | ||
| 1 | 2 | ||
| 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 5 | Message-id: 20241202131347.498124-46-peter.maydell@linaro.org | ||
| 6 | --- | ||
| 7 | target/ppc/cpu_init.c | 4 ++++ | ||
| 8 | 1 file changed, 4 insertions(+) | ||
| 9 | |||
| 10 | diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c | ||
| 11 | index XXXXXXX..XXXXXXX 100644 | ||
| 12 | --- a/target/ppc/cpu_init.c | ||
| 13 | +++ b/target/ppc/cpu_init.c | ||
| 14 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) | ||
| 15 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
| 16 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); | ||
| 17 | |||
| 18 | + /* Default NaN: sign bit clear, set frac msb */ | ||
| 19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); | ||
| 20 | + set_float_default_nan_pattern(0b01000000, &env->vec_status); | ||
| 21 | + | ||
| 22 | for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { | ||
| 23 | ppc_spr_t *spr = &env->spr_cb[i]; | ||
| 24 | |||
| 25 | -- | ||
| 26 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the default NaN pattern explicitly for sh4. Note that sh4 | ||
| 2 | is one of the only three targets (the others being HPPA and | ||
| 3 | sometimes MIPS) that has snan_bit_is_one set. | ||
| 1 | 4 | ||
| 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20241202131347.498124-47-peter.maydell@linaro.org | ||
| 8 | --- | ||
| 9 | target/sh4/cpu.c | 2 ++ | ||
| 10 | 1 file changed, 2 insertions(+) | ||
| 11 | |||
| 12 | diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/sh4/cpu.c | ||
| 15 | +++ b/target/sh4/cpu.c | ||
| 16 | @@ -XXX,XX +XXX,XX @@ static void superh_cpu_reset_hold(Object *obj, ResetType type) | ||
| 17 | set_flush_to_zero(1, &env->fp_status); | ||
| 18 | #endif | ||
| 19 | set_default_nan_mode(1, &env->fp_status); | ||
| 20 | + /* sign bit clear, set all frac bits other than msb */ | ||
| 21 | + set_float_default_nan_pattern(0b00111111, &env->fp_status); | ||
| 22 | } | ||
| 23 | |||
| 24 | static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) | ||
| 25 | -- | ||
| 26 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the default NaN pattern explicitly for rx. | ||
| 1 | 2 | ||
| 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 5 | Message-id: 20241202131347.498124-48-peter.maydell@linaro.org | ||
| 6 | --- | ||
| 7 | target/rx/cpu.c | 2 ++ | ||
| 8 | 1 file changed, 2 insertions(+) | ||
| 9 | |||
| 10 | diff --git a/target/rx/cpu.c b/target/rx/cpu.c | ||
| 11 | index XXXXXXX..XXXXXXX 100644 | ||
| 12 | --- a/target/rx/cpu.c | ||
| 13 | +++ b/target/rx/cpu.c | ||
| 14 | @@ -XXX,XX +XXX,XX @@ static void rx_cpu_reset_hold(Object *obj, ResetType type) | ||
| 15 | * then prefer dest over source", which is float_2nan_prop_s_ab. | ||
| 16 | */ | ||
| 17 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); | ||
| 18 | + /* Default NaN value: sign bit clear, set frac msb */ | ||
| 19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); | ||
| 20 | } | ||
| 21 | |||
| 22 | static ObjectClass *rx_cpu_class_by_name(const char *cpu_model) | ||
| 23 | -- | ||
| 24 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the default NaN pattern explicitly for s390x. | ||
| 1 | 2 | ||
| 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 5 | Message-id: 20241202131347.498124-49-peter.maydell@linaro.org | ||
| 6 | --- | ||
| 7 | target/s390x/cpu.c | 2 ++ | ||
| 8 | 1 file changed, 2 insertions(+) | ||
| 9 | |||
| 10 | diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c | ||
| 11 | index XXXXXXX..XXXXXXX 100644 | ||
| 12 | --- a/target/s390x/cpu.c | ||
| 13 | +++ b/target/s390x/cpu.c | ||
| 14 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) | ||
| 15 | set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status); | ||
| 16 | set_float_infzeronan_rule(float_infzeronan_dnan_always, | ||
| 17 | &env->fpu_status); | ||
| 18 | + /* Default NaN value: sign bit clear, frac msb set */ | ||
| 19 | + set_float_default_nan_pattern(0b01000000, &env->fpu_status); | ||
| 20 | /* fall through */ | ||
| 21 | case RESET_TYPE_S390_CPU_NORMAL: | ||
| 22 | env->psw.mask &= ~PSW_MASK_RI; | ||
| 23 | -- | ||
| 24 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Set the default NaN pattern explicitly for SPARC, and remove | ||
| 2 | the ifdef from parts64_default_nan. | ||
| 1 | 3 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20241202131347.498124-50-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/sparc/cpu.c | 2 ++ | ||
| 9 | fpu/softfloat-specialize.c.inc | 5 +---- | ||
| 10 | 2 files changed, 3 insertions(+), 4 deletions(-) | ||
| 11 | |||
| 12 | diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/sparc/cpu.c | ||
| 15 | +++ b/target/sparc/cpu.c | ||
| 16 | @@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) | ||
| 17 | set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); | ||
| 18 | /* For inf * 0 + NaN, return the input NaN */ | ||
| 19 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
| 20 | + /* Default NaN value: sign bit clear, all frac bits set */ | ||
| 21 | + set_float_default_nan_pattern(0b01111111, &env->fp_status); | ||
| 22 | |||
| 23 | cpu_exec_realizefn(cs, &local_err); | ||
| 24 | if (local_err != NULL) { | ||
| 25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 26 | index XXXXXXX..XXXXXXX 100644 | ||
| 27 | --- a/fpu/softfloat-specialize.c.inc | ||
| 28 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 29 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
| 30 | uint8_t dnan_pattern = status->default_nan_pattern; | ||
| 31 | |||
| 32 | if (dnan_pattern == 0) { | ||
| 33 | -#if defined(TARGET_SPARC) | ||
| 34 | - /* Sign bit clear, all frac bits set */ | ||
| 35 | - dnan_pattern = 0b01111111; | ||
| 36 | -#elif defined(TARGET_HEXAGON) | ||
| 37 | +#if defined(TARGET_HEXAGON) | ||
| 38 | /* Sign bit set, all frac bits set. */ | ||
| 39 | dnan_pattern = 0b11111111; | ||
| 40 | #else | ||
| 41 | -- | ||
| 42 | 2.34.1 | diff view generated by jsdifflib |
| 1 | From: Doug Brown <doug@schmorgal.com> | 1 | Set the default NaN pattern explicitly for xtensa. |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Add support for QEMU_CAN_FRMF_ESI and QEMU_CAN_FRMF_BRS flags, and | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 4 | ensure frame->flags is always initialized to 0. | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 5 | Message-id: 20241202131347.498124-51-peter.maydell@linaro.org | ||
| 6 | --- | ||
| 7 | target/xtensa/cpu.c | 2 ++ | ||
| 8 | 1 file changed, 2 insertions(+) | ||
| 5 | 9 | ||
| 6 | Note that the Xilinx IP core doesn't allow manually setting the ESI bit | 10 | diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c |
| 7 | during transmits, so it's only implemented for the receive case. | ||
| 8 | |||
| 9 | Signed-off-by: Doug Brown <doug@schmorgal.com> | ||
| 10 | Reviewed-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| 11 | Message-id: 20240827034927.66659-5-doug@schmorgal.com | ||
| 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 13 | --- | ||
| 14 | hw/net/can/xlnx-versal-canfd.c | 15 ++++++++++++++- | ||
| 15 | 1 file changed, 14 insertions(+), 1 deletion(-) | ||
| 16 | |||
| 17 | diff --git a/hw/net/can/xlnx-versal-canfd.c b/hw/net/can/xlnx-versal-canfd.c | ||
| 18 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
| 19 | --- a/hw/net/can/xlnx-versal-canfd.c | 12 | --- a/target/xtensa/cpu.c |
| 20 | +++ b/hw/net/can/xlnx-versal-canfd.c | 13 | +++ b/target/xtensa/cpu.c |
| 21 | @@ -XXX,XX +XXX,XX @@ static void regs2frame(XlnxVersalCANFDState *s, qemu_can_frame *frame, | 14 | @@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type) |
| 22 | uint32_t id_reg_val = 0; | 15 | /* For inf * 0 + NaN, return the input NaN */ |
| 23 | bool is_rtr = false; | 16 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); |
| 24 | 17 | set_no_signaling_nans(!dfpu, &env->fp_status); | |
| 25 | + frame->flags = 0; | 18 | + /* Default NaN value: sign bit clear, set frac msb */ |
| 26 | + | 19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); |
| 27 | /* Check that reg_num should be within TX register space. */ | 20 | xtensa_use_first_nan(env, !dfpu); |
| 28 | assert(reg_num <= R_TB_ID_REGISTER + (NUM_REGS_PER_MSG_SPACE * | 21 | } |
| 29 | s->cfg.tx_fifo)); | ||
| 30 | @@ -XXX,XX +XXX,XX @@ static void regs2frame(XlnxVersalCANFDState *s, qemu_can_frame *frame, | ||
| 31 | * 15 49 - 64 | ||
| 32 | */ | ||
| 33 | |||
| 34 | - frame->flags = QEMU_CAN_FRMF_TYPE_FD; | ||
| 35 | + frame->flags |= QEMU_CAN_FRMF_TYPE_FD; | ||
| 36 | |||
| 37 | if (dlc_value < 8) { | ||
| 38 | frame->can_dlc = dlc_value; | ||
| 39 | @@ -XXX,XX +XXX,XX @@ static void regs2frame(XlnxVersalCANFDState *s, qemu_can_frame *frame, | ||
| 40 | assert((dlc_value - 8) < ARRAY_SIZE(canfd_dlc_array)); | ||
| 41 | frame->can_dlc = canfd_dlc_array[dlc_value - 8]; | ||
| 42 | } | ||
| 43 | + | ||
| 44 | + if (FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, BRS)) { | ||
| 45 | + frame->flags |= QEMU_CAN_FRMF_BRS; | ||
| 46 | + } | ||
| 47 | } else { | ||
| 48 | /* | ||
| 49 | * FD Format bit not set that means it is a CAN Frame. | ||
| 50 | @@ -XXX,XX +XXX,XX @@ static void store_rx_sequential(XlnxVersalCANFDState *s, | ||
| 51 | dlc_reg_val = FIELD_DP32(0, RB_DLC_REGISTER, DLC, 8 + i); | ||
| 52 | } | ||
| 53 | } | ||
| 54 | + | ||
| 55 | + if (frame->flags & QEMU_CAN_FRMF_BRS) { | ||
| 56 | + dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, BRS, 1); | ||
| 57 | + } | ||
| 58 | + if (frame->flags & QEMU_CAN_FRMF_ESI) { | ||
| 59 | + dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, ESI, 1); | ||
| 60 | + } | ||
| 61 | } else { | ||
| 62 | is_canfd_frame = false; | ||
| 63 | 22 | ||
| 64 | -- | 23 | -- |
| 65 | 2.34.1 | 24 | 2.34.1 | diff view generated by jsdifflib |
| 1 | Now that all devices which still implement a the legacy reset method | 1 | Set the default NaN pattern explicitly for hexagon. |
|---|---|---|---|
| 2 | register it via device_class_legacy_reset(), we can simplify the | 2 | Remove the ifdef from parts64_default_nan(); the only |
| 3 | handling of these devices. Instead of using the complex | 3 | remaining unconverted targets all use the default case. |
| 4 | Resettable::get_transitional_function machinery, we register a hold | ||
| 5 | phase method which invokes the DeviceClass::legacy_reset method. | ||
| 6 | |||
| 7 | This will allow us to remove all the get_transitional_function | ||
| 8 | handling from resettable.c. | ||
| 9 | 4 | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 12 | Message-id: 20240830145812.1967042-11-peter.maydell@linaro.org | 7 | Message-id: 20241202131347.498124-52-peter.maydell@linaro.org |
| 13 | --- | 8 | --- |
| 14 | hw/core/qdev.c | 55 ++++++++++++++++++++------------------------------ | 9 | target/hexagon/cpu.c | 2 ++ |
| 15 | 1 file changed, 22 insertions(+), 33 deletions(-) | 10 | fpu/softfloat-specialize.c.inc | 5 ----- |
| 11 | 2 files changed, 2 insertions(+), 5 deletions(-) | ||
| 16 | 12 | ||
| 17 | diff --git a/hw/core/qdev.c b/hw/core/qdev.c | 13 | diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c |
| 18 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
| 19 | --- a/hw/core/qdev.c | 15 | --- a/target/hexagon/cpu.c |
| 20 | +++ b/hw/core/qdev.c | 16 | +++ b/target/hexagon/cpu.c |
| 21 | @@ -XXX,XX +XXX,XX @@ device_vmstate_if_get_id(VMStateIf *obj) | 17 | @@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type) |
| 22 | return qdev_get_dev_path(dev); | 18 | |
| 19 | set_default_nan_mode(1, &env->fp_status); | ||
| 20 | set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); | ||
| 21 | + /* Default NaN value: sign bit set, all frac bits set */ | ||
| 22 | + set_float_default_nan_pattern(0b11111111, &env->fp_status); | ||
| 23 | } | 23 | } |
| 24 | 24 | ||
| 25 | -static void device_transitional_reset(Object *obj) | 25 | static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info) |
| 26 | -{ | 26 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
| 27 | - DeviceClass *dc = DEVICE_GET_CLASS(obj); | 27 | index XXXXXXX..XXXXXXX 100644 |
| 28 | - | 28 | --- a/fpu/softfloat-specialize.c.inc |
| 29 | - /* | 29 | +++ b/fpu/softfloat-specialize.c.inc |
| 30 | - * Device still using DeviceClass legacy_reset method. This doesn't | 30 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) |
| 31 | - * reset children. device_get_transitional_reset() checked that | 31 | uint8_t dnan_pattern = status->default_nan_pattern; |
| 32 | - * this isn't NULL. | 32 | |
| 33 | - */ | 33 | if (dnan_pattern == 0) { |
| 34 | - dc->legacy_reset(DEVICE(obj)); | 34 | -#if defined(TARGET_HEXAGON) |
| 35 | -} | 35 | - /* Sign bit set, all frac bits set. */ |
| 36 | - | 36 | - dnan_pattern = 0b11111111; |
| 37 | -/** | 37 | -#else |
| 38 | - * device_get_transitional_reset: | 38 | /* |
| 39 | - * check if the device's class is ready for multi-phase | 39 | * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, |
| 40 | - */ | 40 | * S390, SH4, TriCore, and Xtensa. Our other supported targets |
| 41 | -static ResettableTrFunction device_get_transitional_reset(Object *obj) | 41 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) |
| 42 | -{ | 42 | /* sign bit clear, set frac msb */ |
| 43 | - DeviceClass *dc = DEVICE_GET_CLASS(obj); | 43 | dnan_pattern = 0b01000000; |
| 44 | - if (dc->legacy_reset) { | 44 | } |
| 45 | - /* | 45 | -#endif |
| 46 | - * dc->reset has been overridden by a subclass, | 46 | } |
| 47 | - * the device is not ready for multi phase yet. | 47 | assert(dnan_pattern != 0); |
| 48 | - */ | ||
| 49 | - return device_transitional_reset; | ||
| 50 | - } | ||
| 51 | - return NULL; | ||
| 52 | -} | ||
| 53 | - | ||
| 54 | static void device_class_init(ObjectClass *class, void *data) | ||
| 55 | { | ||
| 56 | DeviceClass *dc = DEVICE_CLASS(class); | ||
| 57 | @@ -XXX,XX +XXX,XX @@ static void device_class_init(ObjectClass *class, void *data) | ||
| 58 | * A NULL legacy_reset implies a three-phase reset device. Devices can | ||
| 59 | * only be reset using three-phase aware mechanisms, but we still support | ||
| 60 | * for transitional purposes leaf classes which set the old legacy_reset | ||
| 61 | - * method via device_class_set_legacy_reset(). If they do so, then | ||
| 62 | - * device_get_transitional_reset() will notice and arrange for the | ||
| 63 | - * DeviceClass::legacy_reset() method to be called during the hold phase. | ||
| 64 | + * method via device_class_set_legacy_reset(). | ||
| 65 | */ | ||
| 66 | dc->legacy_reset = NULL; | ||
| 67 | - rc->get_transitional_function = device_get_transitional_reset; | ||
| 68 | |||
| 69 | object_class_property_add_bool(class, "realized", | ||
| 70 | device_get_realized, device_set_realized); | ||
| 71 | @@ -XXX,XX +XXX,XX @@ static void device_class_init(ObjectClass *class, void *data) | ||
| 72 | offsetof(DeviceState, parent_bus), NULL, 0); | ||
| 73 | } | ||
| 74 | |||
| 75 | +static void do_legacy_reset(Object *obj, ResetType type) | ||
| 76 | +{ | ||
| 77 | + DeviceClass *dc = DEVICE_GET_CLASS(obj); | ||
| 78 | + | ||
| 79 | + dc->legacy_reset(DEVICE(obj)); | ||
| 80 | +} | ||
| 81 | + | ||
| 82 | void device_class_set_legacy_reset(DeviceClass *dc, DeviceReset dev_reset) | ||
| 83 | { | ||
| 84 | + /* | ||
| 85 | + * A legacy DeviceClass::reset has identical semantics to the | ||
| 86 | + * three-phase "hold" method, with no "enter" or "exit" | ||
| 87 | + * behaviour. Classes that use this legacy function must be leaf | ||
| 88 | + * classes that do not chain up to their parent class reset. | ||
| 89 | + * There is no mechanism for resetting a device that does not | ||
| 90 | + * use the three-phase APIs, so the only place which calls | ||
| 91 | + * the legacy_reset hook is do_legacy_reset(). | ||
| 92 | + */ | ||
| 93 | + ResettableClass *rc = RESETTABLE_CLASS(dc); | ||
| 94 | + | ||
| 95 | + rc->phases.enter = NULL; | ||
| 96 | + rc->phases.hold = do_legacy_reset; | ||
| 97 | + rc->phases.exit = NULL; | ||
| 98 | dc->legacy_reset = dev_reset; | ||
| 99 | } | ||
| 100 | 48 | ||
| 101 | -- | 49 | -- |
| 102 | 2.34.1 | 50 | 2.34.1 |
| 103 | |||
| 104 | diff view generated by jsdifflib |
| 1 | The Alpha and HPPA CPU class structs include a 'parent_reset' | 1 | Set the default NaN pattern explicitly for riscv. |
|---|---|---|---|
| 2 | field which is never used; delete them. | ||
| 3 | |||
| 4 | (These targets don't seem to implement reset at all; if they did they | ||
| 5 | should do it using the three-phase reset mechanism, which uses a | ||
| 6 | 'ResettablePhases parent_phases' field instead of the old | ||
| 7 | 'DeviceReset parent_reset' field.) | ||
| 8 | 2 | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 5 | Message-id: 20241202131347.498124-53-peter.maydell@linaro.org |
| 12 | Message-id: 20240830145812.1967042-6-peter.maydell@linaro.org | ||
| 13 | --- | 6 | --- |
| 14 | target/alpha/cpu.h | 2 -- | 7 | target/riscv/cpu.c | 2 ++ |
| 15 | target/hppa/cpu.h | 2 -- | 8 | 1 file changed, 2 insertions(+) |
| 16 | 2 files changed, 4 deletions(-) | ||
| 17 | 9 | ||
| 18 | diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h | 10 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c |
| 19 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
| 20 | --- a/target/alpha/cpu.h | 12 | --- a/target/riscv/cpu.c |
| 21 | +++ b/target/alpha/cpu.h | 13 | +++ b/target/riscv/cpu.c |
| 22 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { | 14 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) |
| 23 | /** | 15 | cs->exception_index = RISCV_EXCP_NONE; |
| 24 | * AlphaCPUClass: | 16 | env->load_res = -1; |
| 25 | * @parent_realize: The parent class' realize handler. | 17 | set_default_nan_mode(1, &env->fp_status); |
| 26 | - * @parent_reset: The parent class' reset handler. | 18 | + /* Default NaN value: sign bit clear, frac msb set */ |
| 27 | * | 19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); |
| 28 | * An Alpha CPU model. | 20 | env->vill = true; |
| 29 | */ | ||
| 30 | @@ -XXX,XX +XXX,XX @@ struct AlphaCPUClass { | ||
| 31 | CPUClass parent_class; | ||
| 32 | |||
| 33 | DeviceRealize parent_realize; | ||
| 34 | - DeviceReset parent_reset; | ||
| 35 | }; | ||
| 36 | 21 | ||
| 37 | #ifndef CONFIG_USER_ONLY | 22 | #ifndef CONFIG_USER_ONLY |
| 38 | diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h | ||
| 39 | index XXXXXXX..XXXXXXX 100644 | ||
| 40 | --- a/target/hppa/cpu.h | ||
| 41 | +++ b/target/hppa/cpu.h | ||
| 42 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { | ||
| 43 | /** | ||
| 44 | * HPPACPUClass: | ||
| 45 | * @parent_realize: The parent class' realize handler. | ||
| 46 | - * @parent_reset: The parent class' reset handler. | ||
| 47 | * | ||
| 48 | * An HPPA CPU model. | ||
| 49 | */ | ||
| 50 | @@ -XXX,XX +XXX,XX @@ struct HPPACPUClass { | ||
| 51 | CPUClass parent_class; | ||
| 52 | |||
| 53 | DeviceRealize parent_realize; | ||
| 54 | - DeviceReset parent_reset; | ||
| 55 | }; | ||
| 56 | |||
| 57 | #include "exec/cpu-all.h" | ||
| 58 | -- | 23 | -- |
| 59 | 2.34.1 | 24 | 2.34.1 |
| 60 | |||
| 61 | diff view generated by jsdifflib |
| 1 | From: Johannes Stoelp <johannes.stoelp@googlemail.com> | 1 | Set the default NaN pattern explicitly for tricore. |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Change the data type of the ioctl _request_ argument from 'int' to | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 4 | 'unsigned long' for the various accel/kvm functions which are | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 5 | essentially wrappers around the ioctl() syscall. | 5 | Message-id: 20241202131347.498124-54-peter.maydell@linaro.org |
| 6 | --- | ||
| 7 | target/tricore/helper.c | 2 ++ | ||
| 8 | 1 file changed, 2 insertions(+) | ||
| 6 | 9 | ||
| 7 | The correct type for ioctl()'s 'request' argument is confused: | 10 | diff --git a/target/tricore/helper.c b/target/tricore/helper.c |
| 8 | * POSIX defines the request argument as 'int' | ||
| 9 | * glibc uses 'unsigned long' in the prototype in sys/ioctl.h | ||
| 10 | * the glibc info documentation uses 'int' | ||
| 11 | * the Linux manpage uses 'unsigned long' | ||
| 12 | * the Linux implementation of the syscall uses 'unsigned int' | ||
| 13 | |||
| 14 | If we wrap ioctl() with another function which uses 'int' as the | ||
| 15 | type for the request argument, then requests with the 0x8000_0000 | ||
| 16 | bit set will be sign-extended when the 'int' is cast to | ||
| 17 | 'unsigned long' for the call to ioctl(). | ||
| 18 | |||
| 19 | On x86_64 one such example is the KVM_IRQ_LINE_STATUS request. | ||
| 20 | Bit requests with the _IOC_READ direction bit set, will have the high | ||
| 21 | bit set. | ||
| 22 | |||
| 23 | Fortunately the Linux Kernel truncates the upper 32bit of the request | ||
| 24 | on 64bit machines (because it uses 'unsigned int', and see also Linus | ||
| 25 | Torvalds' comments in | ||
| 26 | https://sourceware.org/bugzilla/show_bug.cgi?id=14362 ) | ||
| 27 | so this doesn't cause active problems for us. However it is more | ||
| 28 | consistent to follow the glibc ioctl() prototype when we define | ||
| 29 | functions that are essentially wrappers around ioctl(). | ||
| 30 | |||
| 31 | This resolves a Coverity issue where it points out that in | ||
| 32 | kvm_get_xsave() we assign a value (KVM_GET_XSAVE or KVM_GET_XSAVE2) | ||
| 33 | to an 'int' variable which can't hold it without overflow. | ||
| 34 | |||
| 35 | Resolves: Coverity CID 1547759 | ||
| 36 | Signed-off-by: Johannes Stoelp <johannes.stoelp@gmail.com> | ||
| 37 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 38 | Reviewed-by: Eric Blake <eblake@redhat.com> | ||
| 39 | Message-id: 20240815122747.3053871-1-peter.maydell@linaro.org | ||
| 40 | [PMM: Rebased patch, adjusted commit message, included note about | ||
| 41 | Coverity fix, updated the type of the local var in kvm_get_xsave, | ||
| 42 | updated the comment in the KVMState struct definition] | ||
| 43 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 44 | --- | ||
| 45 | include/sysemu/kvm.h | 8 ++++---- | ||
| 46 | include/sysemu/kvm_int.h | 17 +++++++++++++---- | ||
| 47 | accel/kvm/kvm-all.c | 8 ++++---- | ||
| 48 | target/i386/kvm/kvm.c | 3 ++- | ||
| 49 | accel/kvm/trace-events | 8 ++++---- | ||
| 50 | 5 files changed, 27 insertions(+), 17 deletions(-) | ||
| 51 | |||
| 52 | diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h | ||
| 53 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
| 54 | --- a/include/sysemu/kvm.h | 12 | --- a/target/tricore/helper.c |
| 55 | +++ b/include/sysemu/kvm.h | 13 | +++ b/target/tricore/helper.c |
| 56 | @@ -XXX,XX +XXX,XX @@ static inline int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_t | 14 | @@ -XXX,XX +XXX,XX @@ void fpu_set_state(CPUTriCoreState *env) |
| 57 | 15 | set_flush_to_zero(1, &env->fp_status); | |
| 58 | /* internal API */ | 16 | set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); |
| 59 | 17 | set_default_nan_mode(1, &env->fp_status); | |
| 60 | -int kvm_ioctl(KVMState *s, int type, ...); | 18 | + /* Default NaN pattern: sign bit clear, frac msb set */ |
| 61 | +int kvm_ioctl(KVMState *s, unsigned long type, ...); | 19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); |
| 62 | |||
| 63 | -int kvm_vm_ioctl(KVMState *s, int type, ...); | ||
| 64 | +int kvm_vm_ioctl(KVMState *s, unsigned long type, ...); | ||
| 65 | |||
| 66 | -int kvm_vcpu_ioctl(CPUState *cpu, int type, ...); | ||
| 67 | +int kvm_vcpu_ioctl(CPUState *cpu, unsigned long type, ...); | ||
| 68 | |||
| 69 | /** | ||
| 70 | * kvm_device_ioctl - call an ioctl on a kvm device | ||
| 71 | @@ -XXX,XX +XXX,XX @@ int kvm_vcpu_ioctl(CPUState *cpu, int type, ...); | ||
| 72 | * | ||
| 73 | * Returns: -errno on error, nonnegative on success | ||
| 74 | */ | ||
| 75 | -int kvm_device_ioctl(int fd, int type, ...); | ||
| 76 | +int kvm_device_ioctl(int fd, unsigned long type, ...); | ||
| 77 | |||
| 78 | /** | ||
| 79 | * kvm_vm_check_attr - check for existence of a specific vm attribute | ||
| 80 | diff --git a/include/sysemu/kvm_int.h b/include/sysemu/kvm_int.h | ||
| 81 | index XXXXXXX..XXXXXXX 100644 | ||
| 82 | --- a/include/sysemu/kvm_int.h | ||
| 83 | +++ b/include/sysemu/kvm_int.h | ||
| 84 | @@ -XXX,XX +XXX,XX @@ struct KVMState | ||
| 85 | bool sync_mmu; | ||
| 86 | bool guest_state_protected; | ||
| 87 | uint64_t manual_dirty_log_protect; | ||
| 88 | - /* The man page (and posix) say ioctl numbers are signed int, but | ||
| 89 | - * they're not. Linux, glibc and *BSD all treat ioctl numbers as | ||
| 90 | - * unsigned, and treating them as signed here can break things */ | ||
| 91 | - unsigned irq_set_ioctl; | ||
| 92 | + /* | ||
| 93 | + * Older POSIX says that ioctl numbers are signed int, but in | ||
| 94 | + * practice they are not. (Newer POSIX doesn't specify ioctl | ||
| 95 | + * at all.) Linux, glibc and *BSD all treat ioctl numbers as | ||
| 96 | + * unsigned, and real-world ioctl values like KVM_GET_XSAVE have | ||
| 97 | + * bit 31 set, which means that passing them via an 'int' will | ||
| 98 | + * result in sign-extension when they get converted back to the | ||
| 99 | + * 'unsigned long' which the ioctl() prototype uses. Luckily Linux | ||
| 100 | + * always treats the argument as an unsigned 32-bit int, so any | ||
| 101 | + * possible sign-extension is deliberately ignored, but for | ||
| 102 | + * consistency we keep to the same type that glibc is using. | ||
| 103 | + */ | ||
| 104 | + unsigned long irq_set_ioctl; | ||
| 105 | unsigned int sigmask_len; | ||
| 106 | GHashTable *gsimap; | ||
| 107 | #ifdef KVM_CAP_IRQ_ROUTING | ||
| 108 | diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c | ||
| 109 | index XXXXXXX..XXXXXXX 100644 | ||
| 110 | --- a/accel/kvm/kvm-all.c | ||
| 111 | +++ b/accel/kvm/kvm-all.c | ||
| 112 | @@ -XXX,XX +XXX,XX @@ int kvm_cpu_exec(CPUState *cpu) | ||
| 113 | return ret; | ||
| 114 | } | 20 | } |
| 115 | 21 | ||
| 116 | -int kvm_ioctl(KVMState *s, int type, ...) | 22 | uint32_t psw_read(CPUTriCoreState *env) |
| 117 | +int kvm_ioctl(KVMState *s, unsigned long type, ...) | ||
| 118 | { | ||
| 119 | int ret; | ||
| 120 | void *arg; | ||
| 121 | @@ -XXX,XX +XXX,XX @@ int kvm_ioctl(KVMState *s, int type, ...) | ||
| 122 | return ret; | ||
| 123 | } | ||
| 124 | |||
| 125 | -int kvm_vm_ioctl(KVMState *s, int type, ...) | ||
| 126 | +int kvm_vm_ioctl(KVMState *s, unsigned long type, ...) | ||
| 127 | { | ||
| 128 | int ret; | ||
| 129 | void *arg; | ||
| 130 | @@ -XXX,XX +XXX,XX @@ int kvm_vm_ioctl(KVMState *s, int type, ...) | ||
| 131 | return ret; | ||
| 132 | } | ||
| 133 | |||
| 134 | -int kvm_vcpu_ioctl(CPUState *cpu, int type, ...) | ||
| 135 | +int kvm_vcpu_ioctl(CPUState *cpu, unsigned long type, ...) | ||
| 136 | { | ||
| 137 | int ret; | ||
| 138 | void *arg; | ||
| 139 | @@ -XXX,XX +XXX,XX @@ int kvm_vcpu_ioctl(CPUState *cpu, int type, ...) | ||
| 140 | return ret; | ||
| 141 | } | ||
| 142 | |||
| 143 | -int kvm_device_ioctl(int fd, int type, ...) | ||
| 144 | +int kvm_device_ioctl(int fd, unsigned long type, ...) | ||
| 145 | { | ||
| 146 | int ret; | ||
| 147 | void *arg; | ||
| 148 | diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c | ||
| 149 | index XXXXXXX..XXXXXXX 100644 | ||
| 150 | --- a/target/i386/kvm/kvm.c | ||
| 151 | +++ b/target/i386/kvm/kvm.c | ||
| 152 | @@ -XXX,XX +XXX,XX @@ static int kvm_get_xsave(X86CPU *cpu) | ||
| 153 | { | ||
| 154 | CPUX86State *env = &cpu->env; | ||
| 155 | void *xsave = env->xsave_buf; | ||
| 156 | - int type, ret; | ||
| 157 | + unsigned long type; | ||
| 158 | + int ret; | ||
| 159 | |||
| 160 | type = has_xsave2 ? KVM_GET_XSAVE2 : KVM_GET_XSAVE; | ||
| 161 | ret = kvm_vcpu_ioctl(CPU(cpu), type, xsave); | ||
| 162 | diff --git a/accel/kvm/trace-events b/accel/kvm/trace-events | ||
| 163 | index XXXXXXX..XXXXXXX 100644 | ||
| 164 | --- a/accel/kvm/trace-events | ||
| 165 | +++ b/accel/kvm/trace-events | ||
| 166 | @@ -XXX,XX +XXX,XX @@ | ||
| 167 | # See docs/devel/tracing.rst for syntax documentation. | ||
| 168 | |||
| 169 | # kvm-all.c | ||
| 170 | -kvm_ioctl(int type, void *arg) "type 0x%x, arg %p" | ||
| 171 | -kvm_vm_ioctl(int type, void *arg) "type 0x%x, arg %p" | ||
| 172 | -kvm_vcpu_ioctl(int cpu_index, int type, void *arg) "cpu_index %d, type 0x%x, arg %p" | ||
| 173 | +kvm_ioctl(unsigned long type, void *arg) "type 0x%lx, arg %p" | ||
| 174 | +kvm_vm_ioctl(unsigned long type, void *arg) "type 0x%lx, arg %p" | ||
| 175 | +kvm_vcpu_ioctl(int cpu_index, unsigned long type, void *arg) "cpu_index %d, type 0x%lx, arg %p" | ||
| 176 | kvm_run_exit(int cpu_index, uint32_t reason) "cpu_index %d, reason %d" | ||
| 177 | -kvm_device_ioctl(int fd, int type, void *arg) "dev fd %d, type 0x%x, arg %p" | ||
| 178 | +kvm_device_ioctl(int fd, unsigned long type, void *arg) "dev fd %d, type 0x%lx, arg %p" | ||
| 179 | kvm_failed_reg_get(uint64_t id, const char *msg) "Warning: Unable to retrieve ONEREG %" PRIu64 " from KVM: %s" | ||
| 180 | kvm_failed_reg_set(uint64_t id, const char *msg) "Warning: Unable to set ONEREG %" PRIu64 " to KVM: %s" | ||
| 181 | kvm_init_vcpu(int cpu_index, unsigned long arch_cpu_id) "index: %d id: %lu" | ||
| 182 | -- | 23 | -- |
| 183 | 2.34.1 | 24 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Now that all our targets have bene converted to explicitly specify | ||
| 2 | their pattern for the default NaN value we can remove the remaining | ||
| 3 | fallback code in parts64_default_nan(). | ||
| 1 | 4 | ||
| 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20241202131347.498124-55-peter.maydell@linaro.org | ||
| 8 | --- | ||
| 9 | fpu/softfloat-specialize.c.inc | 14 -------------- | ||
| 10 | 1 file changed, 14 deletions(-) | ||
| 11 | |||
| 12 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/fpu/softfloat-specialize.c.inc | ||
| 15 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 16 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
| 17 | uint64_t frac; | ||
| 18 | uint8_t dnan_pattern = status->default_nan_pattern; | ||
| 19 | |||
| 20 | - if (dnan_pattern == 0) { | ||
| 21 | - /* | ||
| 22 | - * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, | ||
| 23 | - * S390, SH4, TriCore, and Xtensa. Our other supported targets | ||
| 24 | - * do not have floating-point. | ||
| 25 | - */ | ||
| 26 | - if (snan_bit_is_one(status)) { | ||
| 27 | - /* sign bit clear, set all frac bits other than msb */ | ||
| 28 | - dnan_pattern = 0b00111111; | ||
| 29 | - } else { | ||
| 30 | - /* sign bit clear, set frac msb */ | ||
| 31 | - dnan_pattern = 0b01000000; | ||
| 32 | - } | ||
| 33 | - } | ||
| 34 | assert(dnan_pattern != 0); | ||
| 35 | |||
| 36 | sign = dnan_pattern >> 7; | ||
| 37 | -- | ||
| 38 | 2.34.1 | diff view generated by jsdifflib |
| 1 | From: Alireza Sanaee <alireza.sanaee@huawei.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | This patch allows for easier manipulation of the cache description | 3 | Inline pickNaNMulAdd into its only caller. This makes |
| 4 | register, CCSIDR. Which is helpful for testing as well. Currently, | 4 | one assert redundant with the immediately preceding IF. |
| 5 | numbers get hard-coded and might be prone to errors. | ||
| 6 | 5 | ||
| 7 | Therefore, this patch adds a wrapper for different types of CPUs | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | available in tcg to decribe caches. One function `make_ccsidr` supports | ||
| 9 | two cases by carrying a parameter as FORMAT that can be LEGACY and | ||
| 10 | CCIDX which determines the specification of the register. | ||
| 11 | |||
| 12 | For CCSIDR register, 32 bit version follows specification [1]. | ||
| 13 | Conversely, 64 bit version follows specification [2]. | ||
| 14 | |||
| 15 | [1] B4.1.19, ARM Architecture Reference Manual ARMv7-A and ARMv7-R | ||
| 16 | edition, https://developer.arm.com/documentation/ddi0406 | ||
| 17 | [2] D23.2.29, ARM Architecture Reference Manual for A-profile Architecture, | ||
| 18 | https://developer.arm.com/documentation/ddi0487/latest/ | ||
| 19 | |||
| 20 | Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com> | ||
| 21 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 22 | Message-id: 20240903144550.280-1-alireza.sanaee@huawei.com | 8 | Message-id: 20241203203949.483774-3-richard.henderson@linaro.org |
| 9 | [PMM: keep comment from old code in new location] | ||
| 23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 24 | --- | 11 | --- |
| 25 | target/arm/cpu-features.h | 50 ++++++++++++++++++ | 12 | fpu/softfloat-parts.c.inc | 41 +++++++++++++++++++++++++- |
| 26 | target/arm/cpu64.c | 19 ++++--- | 13 | fpu/softfloat-specialize.c.inc | 54 ---------------------------------- |
| 27 | target/arm/tcg/cpu64.c | 108 +++++++++++++++++++------------------- | 14 | 2 files changed, 40 insertions(+), 55 deletions(-) |
| 28 | 3 files changed, 117 insertions(+), 60 deletions(-) | ||
| 29 | 15 | ||
| 30 | diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h | 16 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
| 31 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 32 | --- a/target/arm/cpu-features.h | 18 | --- a/fpu/softfloat-parts.c.inc |
| 33 | +++ b/target/arm/cpu-features.h | 19 | +++ b/fpu/softfloat-parts.c.inc |
| 34 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
| 35 | #define TARGET_ARM_FEATURES_H | 21 | } |
| 36 | 22 | ||
| 37 | #include "hw/registerfields.h" | 23 | if (s->default_nan_mode) { |
| 38 | +#include "qemu/host-utils.h" | 24 | + /* |
| 39 | 25 | + * We guarantee not to require the target to tell us how to | |
| 40 | /* | 26 | + * pick a NaN if we're always returning the default NaN. |
| 41 | * Naming convention for isar_feature functions: | 27 | + * But if we're not in default-NaN mode then the target must |
| 42 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_evt(const ARMISARegisters *id) | 28 | + * specify. |
| 43 | return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id); | 29 | + */ |
| 30 | which = 3; | ||
| 31 | + } else if (infzero) { | ||
| 32 | + /* | ||
| 33 | + * Inf * 0 + NaN -- some implementations return the | ||
| 34 | + * default NaN here, and some return the input NaN. | ||
| 35 | + */ | ||
| 36 | + switch (s->float_infzeronan_rule) { | ||
| 37 | + case float_infzeronan_dnan_never: | ||
| 38 | + which = 2; | ||
| 39 | + break; | ||
| 40 | + case float_infzeronan_dnan_always: | ||
| 41 | + which = 3; | ||
| 42 | + break; | ||
| 43 | + case float_infzeronan_dnan_if_qnan: | ||
| 44 | + which = is_qnan(c->cls) ? 3 : 2; | ||
| 45 | + break; | ||
| 46 | + default: | ||
| 47 | + g_assert_not_reached(); | ||
| 48 | + } | ||
| 49 | } else { | ||
| 50 | - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s); | ||
| 51 | + FloatClass cls[3] = { a->cls, b->cls, c->cls }; | ||
| 52 | + Float3NaNPropRule rule = s->float_3nan_prop_rule; | ||
| 53 | + | ||
| 54 | + assert(rule != float_3nan_prop_none); | ||
| 55 | + if (have_snan && (rule & R_3NAN_SNAN_MASK)) { | ||
| 56 | + /* We have at least one SNaN input and should prefer it */ | ||
| 57 | + do { | ||
| 58 | + which = rule & R_3NAN_1ST_MASK; | ||
| 59 | + rule >>= R_3NAN_1ST_LENGTH; | ||
| 60 | + } while (!is_snan(cls[which])); | ||
| 61 | + } else { | ||
| 62 | + do { | ||
| 63 | + which = rule & R_3NAN_1ST_MASK; | ||
| 64 | + rule >>= R_3NAN_1ST_LENGTH; | ||
| 65 | + } while (!is_nan(cls[which])); | ||
| 66 | + } | ||
| 67 | } | ||
| 68 | |||
| 69 | if (which == 3) { | ||
| 70 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 71 | index XXXXXXX..XXXXXXX 100644 | ||
| 72 | --- a/fpu/softfloat-specialize.c.inc | ||
| 73 | +++ b/fpu/softfloat-specialize.c.inc | ||
| 74 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
| 75 | } | ||
| 44 | } | 76 | } |
| 45 | 77 | ||
| 46 | +typedef enum { | 78 | -/*---------------------------------------------------------------------------- |
| 47 | + CCSIDR_FORMAT_LEGACY, | 79 | -| Select which NaN to propagate for a three-input operation. |
| 48 | + CCSIDR_FORMAT_CCIDX, | 80 | -| For the moment we assume that no CPU needs the 'larger significand' |
| 49 | +} CCSIDRFormat; | 81 | -| information. |
| 50 | + | 82 | -| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN |
| 51 | +static inline uint64_t make_ccsidr(CCSIDRFormat format, unsigned assoc, | 83 | -*----------------------------------------------------------------------------*/ |
| 52 | + unsigned linesize, unsigned cachesize, | 84 | -static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
| 53 | + uint8_t flags) | 85 | - bool infzero, bool have_snan, float_status *status) |
| 54 | +{ | ||
| 55 | + unsigned lg_linesize = ctz32(linesize); | ||
| 56 | + unsigned sets; | ||
| 57 | + uint64_t ccsidr = 0; | ||
| 58 | + | ||
| 59 | + assert(assoc != 0); | ||
| 60 | + assert(is_power_of_2(linesize)); | ||
| 61 | + assert(lg_linesize >= 4 && lg_linesize <= 7 + 4); | ||
| 62 | + | ||
| 63 | + /* sets * associativity * linesize == cachesize. */ | ||
| 64 | + sets = cachesize / (assoc * linesize); | ||
| 65 | + assert(cachesize % (assoc * linesize) == 0); | ||
| 66 | + | ||
| 67 | + if (format == CCSIDR_FORMAT_LEGACY) { | ||
| 68 | + /* | ||
| 69 | + * The 32-bit CCSIDR format is: | ||
| 70 | + * [27:13] number of sets - 1 | ||
| 71 | + * [12:3] associativity - 1 | ||
| 72 | + * [2:0] log2(linesize) - 4 | ||
| 73 | + * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc | ||
| 74 | + */ | ||
| 75 | + ccsidr = deposit32(ccsidr, 28, 4, flags); | ||
| 76 | + ccsidr = deposit32(ccsidr, 13, 15, sets - 1); | ||
| 77 | + ccsidr = deposit32(ccsidr, 3, 10, assoc - 1); | ||
| 78 | + ccsidr = deposit32(ccsidr, 0, 3, lg_linesize - 4); | ||
| 79 | + } else { | ||
| 80 | + /* | ||
| 81 | + * The 64-bit CCSIDR_EL1 format is: | ||
| 82 | + * [55:32] number of sets - 1 | ||
| 83 | + * [23:3] associativity - 1 | ||
| 84 | + * [2:0] log2(linesize) - 4 | ||
| 85 | + * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc | ||
| 86 | + */ | ||
| 87 | + ccsidr = deposit64(ccsidr, 32, 24, sets - 1); | ||
| 88 | + ccsidr = deposit64(ccsidr, 3, 21, assoc - 1); | ||
| 89 | + ccsidr = deposit64(ccsidr, 0, 3, lg_linesize - 4); | ||
| 90 | + } | ||
| 91 | + | ||
| 92 | + return ccsidr; | ||
| 93 | +} | ||
| 94 | + | ||
| 95 | /* | ||
| 96 | * Forward to the above feature tests given an ARMCPU pointer. | ||
| 97 | */ | ||
| 98 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
| 99 | index XXXXXXX..XXXXXXX 100644 | ||
| 100 | --- a/target/arm/cpu64.c | ||
| 101 | +++ b/target/arm/cpu64.c | ||
| 102 | @@ -XXX,XX +XXX,XX @@ | ||
| 103 | #include "cpu.h" | ||
| 104 | #include "cpregs.h" | ||
| 105 | #include "qemu/module.h" | ||
| 106 | +#include "qemu/units.h" | ||
| 107 | #include "sysemu/kvm.h" | ||
| 108 | #include "sysemu/hvf.h" | ||
| 109 | #include "sysemu/qtest.h" | ||
| 110 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj) | ||
| 111 | cpu->isar.dbgdevid1 = 0x2; | ||
| 112 | cpu->isar.reset_pmcr_el0 = 0x41013000; | ||
| 113 | cpu->clidr = 0x0a200023; | ||
| 114 | - cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ | ||
| 115 | - cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ | ||
| 116 | - cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ | ||
| 117 | + /* 32KB L1 dcache */ | ||
| 118 | + cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); | ||
| 119 | + /* 48KB L1 icache */ | ||
| 120 | + cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2); | ||
| 121 | + /* 2048KB L2 cache */ | ||
| 122 | + cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7); | ||
| 123 | cpu->dcz_blocksize = 4; /* 64 bytes */ | ||
| 124 | cpu->gic_num_lrs = 4; | ||
| 125 | cpu->gic_vpribits = 5; | ||
| 126 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj) | ||
| 127 | cpu->isar.dbgdevid1 = 0x1; | ||
| 128 | cpu->isar.reset_pmcr_el0 = 0x41033000; | ||
| 129 | cpu->clidr = 0x0a200023; | ||
| 130 | - cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ | ||
| 131 | - cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ | ||
| 132 | - cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */ | ||
| 133 | + /* 32KB L1 dcache */ | ||
| 134 | + cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); | ||
| 135 | + /* 32KB L1 icache */ | ||
| 136 | + cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 1, 64, 32 * KiB, 2); | ||
| 137 | + /* 1024KB L2 cache */ | ||
| 138 | + cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, 7); | ||
| 139 | cpu->dcz_blocksize = 4; /* 64 bytes */ | ||
| 140 | cpu->gic_num_lrs = 4; | ||
| 141 | cpu->gic_vpribits = 5; | ||
| 142 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c | ||
| 143 | index XXXXXXX..XXXXXXX 100644 | ||
| 144 | --- a/target/arm/tcg/cpu64.c | ||
| 145 | +++ b/target/arm/tcg/cpu64.c | ||
| 146 | @@ -XXX,XX +XXX,XX @@ | ||
| 147 | #include "cpu-features.h" | ||
| 148 | #include "cpregs.h" | ||
| 149 | |||
| 150 | -static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize, | ||
| 151 | - unsigned cachesize) | ||
| 152 | -{ | 86 | -{ |
| 153 | - unsigned lg_linesize = ctz32(linesize); | 87 | - FloatClass cls[3] = { a_cls, b_cls, c_cls }; |
| 154 | - unsigned sets; | 88 | - Float3NaNPropRule rule = status->float_3nan_prop_rule; |
| 89 | - int which; | ||
| 155 | - | 90 | - |
| 156 | - /* | 91 | - /* |
| 157 | - * The 64-bit CCSIDR_EL1 format is: | 92 | - * We guarantee not to require the target to tell us how to |
| 158 | - * [55:32] number of sets - 1 | 93 | - * pick a NaN if we're always returning the default NaN. |
| 159 | - * [23:3] associativity - 1 | 94 | - * But if we're not in default-NaN mode then the target must |
| 160 | - * [2:0] log2(linesize) - 4 | 95 | - * specify. |
| 161 | - * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc | ||
| 162 | - */ | 96 | - */ |
| 163 | - assert(assoc != 0); | 97 | - assert(!status->default_nan_mode); |
| 164 | - assert(is_power_of_2(linesize)); | ||
| 165 | - assert(lg_linesize >= 4 && lg_linesize <= 7 + 4); | ||
| 166 | - | 98 | - |
| 167 | - /* sets * associativity * linesize == cachesize. */ | 99 | - if (infzero) { |
| 168 | - sets = cachesize / (assoc * linesize); | 100 | - /* |
| 169 | - assert(cachesize % (assoc * linesize) == 0); | 101 | - * Inf * 0 + NaN -- some implementations return the default NaN here, |
| 102 | - * and some return the input NaN. | ||
| 103 | - */ | ||
| 104 | - switch (status->float_infzeronan_rule) { | ||
| 105 | - case float_infzeronan_dnan_never: | ||
| 106 | - return 2; | ||
| 107 | - case float_infzeronan_dnan_always: | ||
| 108 | - return 3; | ||
| 109 | - case float_infzeronan_dnan_if_qnan: | ||
| 110 | - return is_qnan(c_cls) ? 3 : 2; | ||
| 111 | - default: | ||
| 112 | - g_assert_not_reached(); | ||
| 113 | - } | ||
| 114 | - } | ||
| 170 | - | 115 | - |
| 171 | - return ((uint64_t)(sets - 1) << 32) | 116 | - assert(rule != float_3nan_prop_none); |
| 172 | - | ((assoc - 1) << 3) | 117 | - if (have_snan && (rule & R_3NAN_SNAN_MASK)) { |
| 173 | - | (lg_linesize - 4); | 118 | - /* We have at least one SNaN input and should prefer it */ |
| 119 | - do { | ||
| 120 | - which = rule & R_3NAN_1ST_MASK; | ||
| 121 | - rule >>= R_3NAN_1ST_LENGTH; | ||
| 122 | - } while (!is_snan(cls[which])); | ||
| 123 | - } else { | ||
| 124 | - do { | ||
| 125 | - which = rule & R_3NAN_1ST_MASK; | ||
| 126 | - rule >>= R_3NAN_1ST_LENGTH; | ||
| 127 | - } while (!is_nan(cls[which])); | ||
| 128 | - } | ||
| 129 | - return which; | ||
| 174 | -} | 130 | -} |
| 175 | - | 131 | - |
| 176 | static void aarch64_a35_initfn(Object *obj) | 132 | /*---------------------------------------------------------------------------- |
| 177 | { | 133 | | Returns 1 if the double-precision floating-point value `a' is a quiet |
| 178 | ARMCPU *cpu = ARM_CPU(obj); | 134 | | NaN; otherwise returns 0. |
| 179 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a35_initfn(Object *obj) | ||
| 180 | cpu->isar.reset_pmcr_el0 = 0x410a3000; | ||
| 181 | |||
| 182 | /* From B2.29 Cache ID registers */ | ||
| 183 | - cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ | ||
| 184 | - cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ | ||
| 185 | - cpu->ccsidr[2] = 0x703fe03a; /* 512KB L2 cache */ | ||
| 186 | + /* 32KB L1 dcache */ | ||
| 187 | + cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); | ||
| 188 | + /* 32KB L1 icache */ | ||
| 189 | + cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 2); | ||
| 190 | + /* 512KB L2 cache */ | ||
| 191 | + cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 512 * KiB, 7); | ||
| 192 | |||
| 193 | /* From B3.5 VGIC Type register */ | ||
| 194 | cpu->gic_num_lrs = 4; | ||
| 195 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a55_initfn(Object *obj) | ||
| 196 | cpu->revidr = 0; | ||
| 197 | |||
| 198 | /* From B2.23 CCSIDR_EL1 */ | ||
| 199 | - cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ | ||
| 200 | - cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */ | ||
| 201 | - cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */ | ||
| 202 | + /* 32KB L1 dcache */ | ||
| 203 | + cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); | ||
| 204 | + /* 32KB L1 icache */ | ||
| 205 | + cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 2); | ||
| 206 | + /* 512KB L2 cache */ | ||
| 207 | + cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 512 * KiB, 7); | ||
| 208 | |||
| 209 | /* From B2.96 SCTLR_EL3 */ | ||
| 210 | cpu->reset_sctlr = 0x30c50838; | ||
| 211 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj) | ||
| 212 | cpu->isar.dbgdevid1 = 0x2; | ||
| 213 | cpu->isar.reset_pmcr_el0 = 0x41023000; | ||
| 214 | cpu->clidr = 0x0a200023; | ||
| 215 | - cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ | ||
| 216 | - cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ | ||
| 217 | - cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ | ||
| 218 | + /* 32KB L1 dcache */ | ||
| 219 | + cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); | ||
| 220 | + /* 48KB L1 dcache */ | ||
| 221 | + cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2); | ||
| 222 | + /* 1MB L2 cache */ | ||
| 223 | + cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, 7); | ||
| 224 | cpu->dcz_blocksize = 4; /* 64 bytes */ | ||
| 225 | cpu->gic_num_lrs = 4; | ||
| 226 | cpu->gic_vpribits = 5; | ||
| 227 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj) | ||
| 228 | cpu->revidr = 0; | ||
| 229 | |||
| 230 | /* From B2.18 CCSIDR_EL1 */ | ||
| 231 | - cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ | ||
| 232 | - cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ | ||
| 233 | - cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */ | ||
| 234 | + /* 64KB L1 dcache */ | ||
| 235 | + cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); | ||
| 236 | + /* 64KB L1 icache */ | ||
| 237 | + cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2); | ||
| 238 | + /* 512KB L2 cache */ | ||
| 239 | + cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 512 * KiB, 7); | ||
| 240 | |||
| 241 | /* From B2.93 SCTLR_EL3 */ | ||
| 242 | cpu->reset_sctlr = 0x30c50838; | ||
| 243 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj) | ||
| 244 | cpu->isar.id_aa64isar1 = 0x0000000000010001; | ||
| 245 | cpu->isar.id_aa64zfr0 = 0x0000000000000000; | ||
| 246 | cpu->clidr = 0x0000000080000023; | ||
| 247 | - cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */ | ||
| 248 | - cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */ | ||
| 249 | - cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */ | ||
| 250 | + /* 64KB L1 dcache */ | ||
| 251 | + cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB, 7); | ||
| 252 | + /* 64KB L1 icache */ | ||
| 253 | + cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB, 2); | ||
| 254 | + /* 8MB L2 cache */ | ||
| 255 | + cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 256, 8 * MiB, 7); | ||
| 256 | cpu->dcz_blocksize = 6; /* 256 bytes */ | ||
| 257 | cpu->gic_num_lrs = 4; | ||
| 258 | cpu->gic_vpribits = 5; | ||
| 259 | @@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_n1_initfn(Object *obj) | ||
| 260 | cpu->revidr = 0; | ||
| 261 | |||
| 262 | /* From B2.23 CCSIDR_EL1 */ | ||
| 263 | - cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ | ||
| 264 | - cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ | ||
| 265 | - cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */ | ||
| 266 | + /* 64KB L1 dcache */ | ||
| 267 | + cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); | ||
| 268 | + /* 64KB L1 icache */ | ||
| 269 | + cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2); | ||
| 270 | + /* 1MB L2 dcache */ | ||
| 271 | + cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7); | ||
| 272 | |||
| 273 | /* From B2.98 SCTLR_EL3 */ | ||
| 274 | cpu->reset_sctlr = 0x30c50838; | ||
| 275 | @@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj) | ||
| 276 | * L2: 8-way set associative, 64 byte line size, either 512K or 1MB. | ||
| 277 | * L3: No L3 (this matches the CLIDR_EL1 value). | ||
| 278 | */ | ||
| 279 | - cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */ | ||
| 280 | - cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */ | ||
| 281 | - cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB); /* L2 cache */ | ||
| 282 | + /* 64KB L1 dcache */ | ||
| 283 | + cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0); | ||
| 284 | + /* 64KB L1 icache */ | ||
| 285 | + cpu->ccsidr[1] = cpu->ccsidr[0]; | ||
| 286 | + /* 1MB L2 cache */ | ||
| 287 | + cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 1 * MiB, 0); | ||
| 288 | |||
| 289 | /* From 3.2.115 SCTLR_EL3 */ | ||
| 290 | cpu->reset_sctlr = 0x30c50838; | ||
| 291 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a710_initfn(Object *obj) | ||
| 292 | * L1: 4-way set associative 64-byte line size, total either 32K or 64K. | ||
| 293 | * L2: 8-way set associative 64 byte line size, total either 256K or 512K. | ||
| 294 | */ | ||
| 295 | - cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */ | ||
| 296 | - cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */ | ||
| 297 | - cpu->ccsidr[2] = make_ccsidr64(8, 64, 512 * KiB); /* L2 cache */ | ||
| 298 | + /* L1 dcache */ | ||
| 299 | + cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0); | ||
| 300 | + /* L1 icache */ | ||
| 301 | + cpu->ccsidr[1] = cpu->ccsidr[0]; | ||
| 302 | + /* L2 cache */ | ||
| 303 | + cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, 0); | ||
| 304 | |||
| 305 | /* FIXME: Not documented -- copied from neoverse-v1 */ | ||
| 306 | cpu->reset_sctlr = 0x30c50838; | ||
| 307 | @@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_n2_initfn(Object *obj) | ||
| 308 | * L1: 4-way set associative 64-byte line size, total 64K. | ||
| 309 | * L2: 8-way set associative 64 byte line size, total either 512K or 1024K. | ||
| 310 | */ | ||
| 311 | - cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */ | ||
| 312 | - cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */ | ||
| 313 | - cpu->ccsidr[2] = make_ccsidr64(8, 64, 512 * KiB); /* L2 cache */ | ||
| 314 | - | ||
| 315 | + /* L1 dcache */ | ||
| 316 | + cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0); | ||
| 317 | + /* L1 icache */ | ||
| 318 | + cpu->ccsidr[1] = cpu->ccsidr[0]; | ||
| 319 | + /* L2 cache */ | ||
| 320 | + cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, 0); | ||
| 321 | /* FIXME: Not documented -- copied from neoverse-v1 */ | ||
| 322 | cpu->reset_sctlr = 0x30c50838; | ||
| 323 | |||
| 324 | -- | 135 | -- |
| 325 | 2.34.1 | 136 | 2.34.1 |
| 326 | 137 | ||
| 327 | 138 | diff view generated by jsdifflib |
| 1 | Define a device_class_set_legacy_reset() function which | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | sets the DeviceClass::reset field. This serves two purposes: | ||
| 3 | * it makes it clearer to the person writing code that | ||
| 4 | DeviceClass::reset is now legacy and they should look for | ||
| 5 | the new alternative (which is Resettable) | ||
| 6 | * it makes it easier to rename the reset field (which in turn | ||
| 7 | makes it easier to find places that call it) | ||
| 8 | 2 | ||
| 9 | The Coccinelle script can be used to automatically convert code that | 3 | Remove "3" as a special case for which and simply |
| 10 | was doing an open-coded assignment to DeviceClass::reset to call | 4 | branch to return the desired value. |
| 11 | device_class_set_legacy_reset() instead. | ||
| 12 | 5 | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 8 | Message-id: 20241203203949.483774-4-richard.henderson@linaro.org | ||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 14 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 15 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 16 | Message-id: 20240830145812.1967042-7-peter.maydell@linaro.org | ||
| 17 | --- | 10 | --- |
| 18 | scripts/coccinelle/device-reset.cocci | 30 +++++++++++++++++++++++++++ | 11 | fpu/softfloat-parts.c.inc | 20 ++++++++++---------- |
| 19 | include/hw/qdev-core.h | 13 ++++++++++++ | 12 | 1 file changed, 10 insertions(+), 10 deletions(-) |
| 20 | hw/core/qdev.c | 5 +++++ | ||
| 21 | 3 files changed, 48 insertions(+) | ||
| 22 | create mode 100644 scripts/coccinelle/device-reset.cocci | ||
| 23 | 13 | ||
| 24 | diff --git a/scripts/coccinelle/device-reset.cocci b/scripts/coccinelle/device-reset.cocci | 14 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
| 25 | new file mode 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 26 | index XXXXXXX..XXXXXXX | 16 | --- a/fpu/softfloat-parts.c.inc |
| 27 | --- /dev/null | 17 | +++ b/fpu/softfloat-parts.c.inc |
| 28 | +++ b/scripts/coccinelle/device-reset.cocci | 18 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
| 29 | @@ -XXX,XX +XXX,XX @@ | 19 | * But if we're not in default-NaN mode then the target must |
| 30 | +// Convert opencoded DeviceClass::reset assignments to calls to | 20 | * specify. |
| 31 | +// device_class_set_legacy_reset() | 21 | */ |
| 32 | +// | 22 | - which = 3; |
| 33 | +// Copyright Linaro Ltd 2024 | 23 | + goto default_nan; |
| 34 | +// This work is licensed under the terms of the GNU GPLv2 or later. | 24 | } else if (infzero) { |
| 35 | +// | 25 | /* |
| 36 | +// spatch --macro-file scripts/cocci-macro-file.h \ | 26 | * Inf * 0 + NaN -- some implementations return the |
| 37 | +// --sp-file scripts/coccinelle/device-reset.cocci \ | 27 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
| 38 | +// --keep-comments --smpl-spacing --in-place --include-headers --dir hw | 28 | */ |
| 39 | +// | 29 | switch (s->float_infzeronan_rule) { |
| 40 | +// For simplicity we assume some things about the code we're modifying | 30 | case float_infzeronan_dnan_never: |
| 41 | +// that happen to be true for all our targets: | 31 | - which = 2; |
| 42 | +// * all cpu_class_set_parent_reset() callsites have a 'DeviceClass *dc' local | 32 | break; |
| 43 | +// * the parent reset field in the target CPU class is 'parent_reset' | 33 | case float_infzeronan_dnan_always: |
| 44 | +// * no reset function already has a 'dev' local | 34 | - which = 3; |
| 35 | - break; | ||
| 36 | + goto default_nan; | ||
| 37 | case float_infzeronan_dnan_if_qnan: | ||
| 38 | - which = is_qnan(c->cls) ? 3 : 2; | ||
| 39 | + if (is_qnan(c->cls)) { | ||
| 40 | + goto default_nan; | ||
| 41 | + } | ||
| 42 | break; | ||
| 43 | default: | ||
| 44 | g_assert_not_reached(); | ||
| 45 | } | ||
| 46 | + which = 2; | ||
| 47 | } else { | ||
| 48 | FloatClass cls[3] = { a->cls, b->cls, c->cls }; | ||
| 49 | Float3NaNPropRule rule = s->float_3nan_prop_rule; | ||
| 50 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
| 51 | } | ||
| 52 | } | ||
| 53 | |||
| 54 | - if (which == 3) { | ||
| 55 | - parts_default_nan(a, s); | ||
| 56 | - return a; | ||
| 57 | - } | ||
| 58 | - | ||
| 59 | switch (which) { | ||
| 60 | case 0: | ||
| 61 | break; | ||
| 62 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
| 63 | parts_silence_nan(a, s); | ||
| 64 | } | ||
| 65 | return a; | ||
| 45 | + | 66 | + |
| 46 | +@@ | 67 | + default_nan: |
| 47 | +identifier dc, resetfn; | 68 | + parts_default_nan(a, s); |
| 48 | +@@ | 69 | + return a; |
| 49 | + DeviceClass *dc; | ||
| 50 | + ... | ||
| 51 | +- dc->reset = resetfn; | ||
| 52 | ++ device_class_set_legacy_reset(dc, resetfn); | ||
| 53 | +@@ | ||
| 54 | +identifier dc, resetfn; | ||
| 55 | +@@ | ||
| 56 | + DeviceClass *dc; | ||
| 57 | + ... | ||
| 58 | +- dc->reset = &resetfn; | ||
| 59 | ++ device_class_set_legacy_reset(dc, resetfn); | ||
| 60 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h | ||
| 61 | index XXXXXXX..XXXXXXX 100644 | ||
| 62 | --- a/include/hw/qdev-core.h | ||
| 63 | +++ b/include/hw/qdev-core.h | ||
| 64 | @@ -XXX,XX +XXX,XX @@ void device_class_set_parent_realize(DeviceClass *dc, | ||
| 65 | DeviceRealize dev_realize, | ||
| 66 | DeviceRealize *parent_realize); | ||
| 67 | |||
| 68 | +/** | ||
| 69 | + * device_class_set_legacy_reset(): set the DeviceClass::reset method | ||
| 70 | + * @dc: The device class | ||
| 71 | + * @dev_reset: the reset function | ||
| 72 | + * | ||
| 73 | + * This function sets the DeviceClass::reset method. This is widely | ||
| 74 | + * used in existing code, but new code should prefer to use the | ||
| 75 | + * Resettable API as documented in docs/devel/reset.rst. | ||
| 76 | + * In addition, devices which need to chain to their parent class's | ||
| 77 | + * reset methods or which need to be subclassed must use Resettable. | ||
| 78 | + */ | ||
| 79 | +void device_class_set_legacy_reset(DeviceClass *dc, | ||
| 80 | + DeviceReset dev_reset); | ||
| 81 | |||
| 82 | /** | ||
| 83 | * device_class_set_parent_unrealize() - set up for chaining unrealize fns | ||
| 84 | diff --git a/hw/core/qdev.c b/hw/core/qdev.c | ||
| 85 | index XXXXXXX..XXXXXXX 100644 | ||
| 86 | --- a/hw/core/qdev.c | ||
| 87 | +++ b/hw/core/qdev.c | ||
| 88 | @@ -XXX,XX +XXX,XX @@ static void device_class_init(ObjectClass *class, void *data) | ||
| 89 | offsetof(DeviceState, parent_bus), NULL, 0); | ||
| 90 | } | 70 | } |
| 91 | 71 | ||
| 92 | +void device_class_set_legacy_reset(DeviceClass *dc, DeviceReset dev_reset) | 72 | /* |
| 93 | +{ | ||
| 94 | + dc->reset = dev_reset; | ||
| 95 | +} | ||
| 96 | + | ||
| 97 | void device_class_set_parent_realize(DeviceClass *dc, | ||
| 98 | DeviceRealize dev_realize, | ||
| 99 | DeviceRealize *parent_realize) | ||
| 100 | -- | 73 | -- |
| 101 | 2.34.1 | 74 | 2.34.1 |
| 102 | 75 | ||
| 103 | 76 | diff view generated by jsdifflib |
| 1 | From: Doug Brown <doug@schmorgal.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Use QEMU's helper functions can_dlc2len() and can_len2dlc() for | 3 | Assign the pointer return value to 'a' directly, |
| 4 | translating between the raw DLC value and the SocketCAN length value. | 4 | rather than going through an intermediary index. |
| 5 | This also has the side effect of correctly handling received CAN FD | ||
| 6 | frames with a DLC of 0-8, which was broken previously. | ||
| 7 | 5 | ||
| 8 | Signed-off-by: Doug Brown <doug@schmorgal.com> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 9 | Reviewed-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 10 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | 8 | Message-id: 20241203203949.483774-5-richard.henderson@linaro.org |
| 11 | Message-id: 20240827034927.66659-7-doug@schmorgal.com | ||
| 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 13 | --- | 10 | --- |
| 14 | hw/net/can/xlnx-versal-canfd.c | 67 ++-------------------------------- | 11 | fpu/softfloat-parts.c.inc | 32 ++++++++++---------------------- |
| 15 | 1 file changed, 4 insertions(+), 63 deletions(-) | 12 | 1 file changed, 10 insertions(+), 22 deletions(-) |
| 16 | 13 | ||
| 17 | diff --git a/hw/net/can/xlnx-versal-canfd.c b/hw/net/can/xlnx-versal-canfd.c | 14 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
| 18 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 19 | --- a/hw/net/can/xlnx-versal-canfd.c | 16 | --- a/fpu/softfloat-parts.c.inc |
| 20 | +++ b/hw/net/can/xlnx-versal-canfd.c | 17 | +++ b/fpu/softfloat-parts.c.inc |
| 21 | @@ -XXX,XX +XXX,XX @@ REG32(RB_DW15_REGISTER_1, 0x4144) | 18 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
| 22 | FIELD(RB_DW15_REGISTER_1, DATA_BYTES62, 8, 8) | 19 | FloatPartsN *c, float_status *s, |
| 23 | FIELD(RB_DW15_REGISTER_1, DATA_BYTES63, 0, 8) | 20 | int ab_mask, int abc_mask) |
| 24 | |||
| 25 | -static uint8_t canfd_dlc_array[8] = {8, 12, 16, 20, 24, 32, 48, 64}; | ||
| 26 | - | ||
| 27 | static void canfd_update_irq(XlnxVersalCANFDState *s) | ||
| 28 | { | 21 | { |
| 29 | const bool irq = (s->regs[R_INTERRUPT_STATUS_REGISTER] & | 22 | - int which; |
| 30 | @@ -XXX,XX +XXX,XX @@ static void regs2frame(XlnxVersalCANFDState *s, qemu_can_frame *frame, | 23 | bool infzero = (ab_mask == float_cmask_infzero); |
| 31 | } | 24 | bool have_snan = (abc_mask & float_cmask_snan); |
| 32 | 25 | + FloatPartsN *ret; | |
| 33 | if (FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, FDF)) { | 26 | |
| 34 | - /* | 27 | if (unlikely(have_snan)) { |
| 35 | - * CANFD frame. | 28 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); |
| 36 | - * Converting dlc(0 to 15) 4 Byte data to plain length(i.e. 0 to 64) | 29 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
| 37 | - * 1 Byte data. This is done to make it work with SocketCAN. | 30 | default: |
| 38 | - * On actual CANFD frame, this value can't be more than 0xF. | 31 | g_assert_not_reached(); |
| 39 | - * Conversion table for DLC to plain length: | ||
| 40 | - * | ||
| 41 | - * DLC Plain Length | ||
| 42 | - * 0 - 8 0 - 8 | ||
| 43 | - * 9 9 - 12 | ||
| 44 | - * 10 13 - 16 | ||
| 45 | - * 11 17 - 20 | ||
| 46 | - * 12 21 - 24 | ||
| 47 | - * 13 25 - 32 | ||
| 48 | - * 14 33 - 48 | ||
| 49 | - * 15 49 - 64 | ||
| 50 | - */ | ||
| 51 | - | ||
| 52 | frame->flags |= QEMU_CAN_FRMF_TYPE_FD; | ||
| 53 | |||
| 54 | - if (dlc_value < 8) { | ||
| 55 | - frame->can_dlc = dlc_value; | ||
| 56 | - } else { | ||
| 57 | - assert((dlc_value - 8) < ARRAY_SIZE(canfd_dlc_array)); | ||
| 58 | - frame->can_dlc = canfd_dlc_array[dlc_value - 8]; | ||
| 59 | - } | ||
| 60 | - | ||
| 61 | if (FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, BRS)) { | ||
| 62 | frame->flags |= QEMU_CAN_FRMF_BRS; | ||
| 63 | } | 32 | } |
| 33 | - which = 2; | ||
| 34 | + ret = c; | ||
| 64 | } else { | 35 | } else { |
| 65 | - /* | 36 | - FloatClass cls[3] = { a->cls, b->cls, c->cls }; |
| 66 | - * FD Format bit not set that means it is a CAN Frame. | 37 | + FloatPartsN *val[3] = { a, b, c }; |
| 67 | - * Conversion table for classic CAN: | 38 | Float3NaNPropRule rule = s->float_3nan_prop_rule; |
| 68 | - * | 39 | |
| 69 | - * DLC Plain Length | 40 | assert(rule != float_3nan_prop_none); |
| 70 | - * 0 - 7 0 - 7 | 41 | if (have_snan && (rule & R_3NAN_SNAN_MASK)) { |
| 71 | - * 8 - 15 8 | 42 | /* We have at least one SNaN input and should prefer it */ |
| 72 | - */ | 43 | do { |
| 73 | - | 44 | - which = rule & R_3NAN_1ST_MASK; |
| 74 | - if (dlc_value > 8) { | 45 | + ret = val[rule & R_3NAN_1ST_MASK]; |
| 75 | - frame->can_dlc = 8; | 46 | rule >>= R_3NAN_1ST_LENGTH; |
| 76 | - qemu_log_mask(LOG_GUEST_ERROR, "Maximum DLC value for Classic CAN" | 47 | - } while (!is_snan(cls[which])); |
| 77 | - " frame is 8. Only 8 byte data will be sent.\n"); | 48 | + } while (!is_snan(ret->cls)); |
| 78 | - } else { | 49 | } else { |
| 79 | - frame->can_dlc = dlc_value; | 50 | do { |
| 80 | - } | 51 | - which = rule & R_3NAN_1ST_MASK; |
| 81 | - | 52 | + ret = val[rule & R_3NAN_1ST_MASK]; |
| 82 | if (is_rtr) { | 53 | rule >>= R_3NAN_1ST_LENGTH; |
| 83 | frame->can_id |= QEMU_CAN_RTR_FLAG; | 54 | - } while (!is_nan(cls[which])); |
| 55 | + } while (!is_nan(ret->cls)); | ||
| 84 | } | 56 | } |
| 85 | } | 57 | } |
| 86 | 58 | ||
| 87 | + frame->can_dlc = can_dlc2len(dlc_value); | 59 | - switch (which) { |
| 88 | + | 60 | - case 0: |
| 89 | for (j = 0; j < frame->can_dlc; j++) { | 61 | - break; |
| 90 | val = 8 * (3 - i); | 62 | - case 1: |
| 91 | 63 | - a = b; | |
| 92 | @@ -XXX,XX +XXX,XX @@ static void store_rx_sequential(XlnxVersalCANFDState *s, | 64 | - break; |
| 93 | bool rx_fifo_id, uint8_t filter_index) | 65 | - case 2: |
| 94 | { | 66 | - a = c; |
| 95 | int i; | 67 | - break; |
| 96 | - bool is_canfd_frame; | 68 | - default: |
| 97 | uint8_t dlc = frame->can_dlc; | 69 | - g_assert_not_reached(); |
| 98 | uint8_t rx_reg_num = 0; | 70 | + if (is_snan(ret->cls)) { |
| 99 | uint32_t dlc_reg_val = 0; | 71 | + parts_silence_nan(ret, s); |
| 100 | @@ -XXX,XX +XXX,XX @@ static void store_rx_sequential(XlnxVersalCANFDState *s, | 72 | } |
| 101 | 73 | - if (is_snan(a->cls)) { | |
| 102 | s->regs[store_location] = frame_to_reg_id(frame); | 74 | - parts_silence_nan(a, s); |
| 103 | 75 | - } | |
| 104 | - dlc = frame->can_dlc; | 76 | - return a; |
| 105 | + dlc_reg_val = FIELD_DP32(0, RB_DLC_REGISTER, DLC, can_len2dlc(dlc)); | 77 | + return ret; |
| 106 | 78 | ||
| 107 | if (frame->flags & QEMU_CAN_FRMF_TYPE_FD) { | 79 | default_nan: |
| 108 | - is_canfd_frame = true; | 80 | parts_default_nan(a, s); |
| 109 | - | ||
| 110 | - /* Store dlc value in Xilinx specific format. */ | ||
| 111 | - for (i = 0; i < ARRAY_SIZE(canfd_dlc_array); i++) { | ||
| 112 | - if (canfd_dlc_array[i] == frame->can_dlc) { | ||
| 113 | - dlc_reg_val = FIELD_DP32(0, RB_DLC_REGISTER, DLC, 8 + i); | ||
| 114 | - } | ||
| 115 | - } | ||
| 116 | + dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, FDF, 1); | ||
| 117 | |||
| 118 | if (frame->flags & QEMU_CAN_FRMF_BRS) { | ||
| 119 | dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, BRS, 1); | ||
| 120 | @@ -XXX,XX +XXX,XX @@ static void store_rx_sequential(XlnxVersalCANFDState *s, | ||
| 121 | if (frame->flags & QEMU_CAN_FRMF_ESI) { | ||
| 122 | dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, ESI, 1); | ||
| 123 | } | ||
| 124 | - } else { | ||
| 125 | - is_canfd_frame = false; | ||
| 126 | - | ||
| 127 | - if (frame->can_dlc > 8) { | ||
| 128 | - dlc = 8; | ||
| 129 | - } | ||
| 130 | - | ||
| 131 | - dlc_reg_val = FIELD_DP32(0, RB_DLC_REGISTER, DLC, dlc); | ||
| 132 | } | ||
| 133 | |||
| 134 | - dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, FDF, is_canfd_frame); | ||
| 135 | dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, TIMESTAMP, rx_timestamp); | ||
| 136 | dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, MATCHED_FILTER_INDEX, | ||
| 137 | filter_index); | ||
| 138 | -- | 81 | -- |
| 139 | 2.34.1 | 82 | 2.34.1 |
| 83 | |||
| 84 | diff view generated by jsdifflib |
| 1 | From: Jan Klötzke <jan.kloetzke@kernkonzept.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | On GICv2 and later, level triggered interrupts are pending when either | 3 | While all indices into val[] should be in [0-2], the mask |
| 4 | the interrupt line is asserted or the interrupt was made pending by a | 4 | applied is two bits. To help static analysis see there is |
| 5 | GICD_ISPENDRn write. Making a level triggered interrupt pending by | 5 | no possibility of read beyond the end of the array, pad the |
| 6 | software persists until either the interrupt is acknowledged or cleared | 6 | array to 4 entries, with the final being (implicitly) NULL. |
| 7 | by writing GICD_ICPENDRn. As long as the interrupt line is asserted, | ||
| 8 | the interrupt is pending in any case. | ||
| 9 | 7 | ||
| 10 | This logic is transparently implemented in gic_test_pending() for | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 11 | GICv1 and GICv2. The function combines the "pending" irq_state flag | 9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 12 | (used for edge triggered interrupts and software requests) and the | 10 | Message-id: 20241203203949.483774-6-richard.henderson@linaro.org |
| 13 | line status (tracked in the "level" field). However, we also | ||
| 14 | incorrectly set the pending flag on a guest write to GICD_ISENABLERn | ||
| 15 | if the line of a level triggered interrupt was asserted. This keeps | ||
| 16 | the interrupt pending even if the line is de-asserted after some | ||
| 17 | time. | ||
| 18 | |||
| 19 | This incorrect logic is a leftover of the initial 11MPCore GIC | ||
| 20 | implementation. That handles things slightly differently to the | ||
| 21 | architected GICv1 and GICv2. The 11MPCore TRM does not give a lot of | ||
| 22 | detail on the corner cases of its GIC's behaviour, and historically | ||
| 23 | we have not wanted to investigate exactly what it does in reality, so | ||
| 24 | QEMU's GIC model takes the approach of "retain our existing behaviour | ||
| 25 | for 11MPCore, and implement the architectural standard for later GIC | ||
| 26 | revisions". | ||
| 27 | |||
| 28 | On that basis, commit 8d999995e45c10 in 2013 is where we added the | ||
| 29 | "level-triggered interrupt with the line asserted" handling to | ||
| 30 | gic_test_pending(), and we deliberately kept the old behaviour of | ||
| 31 | gic_test_pending() for REV_11MPCORE. That commit should have added | ||
| 32 | the "only if 11MPCore" condition to the setting of the pending bit on | ||
| 33 | writes to GICD_ISENABLERn, but forgot it. | ||
| 34 | |||
| 35 | Add the missing "if REV_11MPCORE" condition, so that our behaviour | ||
| 36 | on GICv1 and GICv2 matches the GIC architecture requirements. | ||
| 37 | |||
| 38 | Cc: qemu-stable@nongnu.org | ||
| 39 | Fixes: 8d999995e45c10 ("arm_gic: Fix GIC pending behavior") | ||
| 40 | Signed-off-by: Jan Klötzke <jan.kloetzke@kernkonzept.com> | ||
| 41 | Message-id: 20240911114826.3558302-1-jan.kloetzke@kernkonzept.com | ||
| 42 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 43 | [PMM: expanded comment a little and converted to coding-style form; | ||
| 44 | expanded commit message with the historical backstory] | ||
| 45 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 46 | --- | 12 | --- |
| 47 | hw/intc/arm_gic.c | 11 ++++++++--- | 13 | fpu/softfloat-parts.c.inc | 2 +- |
| 48 | 1 file changed, 8 insertions(+), 3 deletions(-) | 14 | 1 file changed, 1 insertion(+), 1 deletion(-) |
| 49 | 15 | ||
| 50 | diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c | 16 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
| 51 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 52 | --- a/hw/intc/arm_gic.c | 18 | --- a/fpu/softfloat-parts.c.inc |
| 53 | +++ b/hw/intc/arm_gic.c | 19 | +++ b/fpu/softfloat-parts.c.inc |
| 54 | @@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset, | 20 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
| 55 | trace_gic_enable_irq(irq + i); | 21 | } |
| 56 | } | 22 | ret = c; |
| 57 | GIC_DIST_SET_ENABLED(irq + i, cm); | 23 | } else { |
| 58 | - /* If a raised level triggered IRQ enabled then mark | 24 | - FloatPartsN *val[3] = { a, b, c }; |
| 59 | - is as pending. */ | 25 | + FloatPartsN *val[R_3NAN_1ST_MASK + 1] = { a, b, c }; |
| 60 | - if (GIC_DIST_TEST_LEVEL(irq + i, mask) | 26 | Float3NaNPropRule rule = s->float_3nan_prop_rule; |
| 61 | + /* | 27 | |
| 62 | + * If a raised level triggered IRQ enabled then mark | 28 | assert(rule != float_3nan_prop_none); |
| 63 | + * it as pending on 11MPCore. For other GIC revisions we | ||
| 64 | + * handle the "level triggered and line asserted" check | ||
| 65 | + * at the other end in gic_test_pending(). | ||
| 66 | + */ | ||
| 67 | + if (s->revision == REV_11MPCORE | ||
| 68 | + && GIC_DIST_TEST_LEVEL(irq + i, mask) | ||
| 69 | && !GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) { | ||
| 70 | DPRINTF("Set %d pending mask %x\n", irq + i, mask); | ||
| 71 | GIC_DIST_SET_PENDING(irq + i, mask); | ||
| 72 | -- | 29 | -- |
| 73 | 2.34.1 | 30 | 2.34.1 |
| 74 | 31 | ||
| 75 | 32 | diff view generated by jsdifflib |
| 1 | From: Danny Canter <danny_canter@apple.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | This addition will be necessary for some HVF related work to follow. | 3 | This function is part of the public interface and |
| 4 | For HVF on ARM there exists a set of APIs in macOS 13 to be able to | 4 | is not "specialized" to any target in any way. |
| 5 | adjust the IPA size for a given VM. This is useful as by default HVF | ||
| 6 | uses 36 bits as the IPA size, so to support guests with > 64GB of RAM | ||
| 7 | we'll need to reach for this. | ||
| 8 | 5 | ||
| 9 | To have all the info necessary to carry this out however, we need some | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 10 | plumbing to be able to grab the memory map and compute the highest GPA | ||
| 11 | prior to creating the VM. This is almost exactly like what kvm_type is | ||
| 12 | used for on ARM today, and is also what this will be used for. We will | ||
| 13 | compute the highest GPA and find what IPA size we'd need to satisfy this, | ||
| 14 | and if it's valid (macOS today caps at 40b) we'll set this to be the IPA | ||
| 15 | size in coming patches. This new method is only needed (today at least) | ||
| 16 | on ARM, and obviously only for HVF/macOS, so admittedly it is much less | ||
| 17 | generic than kvm_type today, but it seemed a somewhat sane way to get | ||
| 18 | the information we need from the memmap at VM creation time. | ||
| 19 | |||
| 20 | Signed-off-by: Danny Canter <danny_canter@apple.com> | ||
| 21 | Message-id: 20240828111552.93482-2-danny_canter@apple.com | ||
| 22 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 23 | [PMM: removed explicit setting of field to NULL on x86] | 8 | Message-id: 20241203203949.483774-7-richard.henderson@linaro.org |
| 24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 25 | --- | 10 | --- |
| 26 | include/hw/boards.h | 5 +++++ | 11 | fpu/softfloat.c | 52 ++++++++++++++++++++++++++++++++++ |
| 27 | hw/arm/virt.c | 9 ++++++++- | 12 | fpu/softfloat-specialize.c.inc | 52 ---------------------------------- |
| 28 | 2 files changed, 13 insertions(+), 1 deletion(-) | 13 | 2 files changed, 52 insertions(+), 52 deletions(-) |
| 29 | 14 | ||
| 30 | diff --git a/include/hw/boards.h b/include/hw/boards.h | 15 | diff --git a/fpu/softfloat.c b/fpu/softfloat.c |
| 31 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
| 32 | --- a/include/hw/boards.h | 17 | --- a/fpu/softfloat.c |
| 33 | +++ b/include/hw/boards.h | 18 | +++ b/fpu/softfloat.c |
| 34 | @@ -XXX,XX +XXX,XX @@ typedef struct { | 19 | @@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr, |
| 35 | * Return the type of KVM corresponding to the kvm-type string option or | 20 | *zExpPtr = 1 - shiftCount; |
| 36 | * computed based on other criteria such as the host kernel capabilities. | ||
| 37 | * kvm-type may be NULL if it is not needed. | ||
| 38 | + * @hvf_get_physical_address_range: | ||
| 39 | + * Returns the physical address range in bits to use for the HVF virtual | ||
| 40 | + * machine based on the current boards memory map. This may be NULL if it | ||
| 41 | + * is not needed. | ||
| 42 | * @numa_mem_supported: | ||
| 43 | * true if '--numa node.mem' option is supported and false otherwise | ||
| 44 | * @hotplug_allowed: | ||
| 45 | @@ -XXX,XX +XXX,XX @@ struct MachineClass { | ||
| 46 | void (*reset)(MachineState *state, ShutdownCause reason); | ||
| 47 | void (*wakeup)(MachineState *state); | ||
| 48 | int (*kvm_type)(MachineState *machine, const char *arg); | ||
| 49 | + int (*hvf_get_physical_address_range)(MachineState *machine); | ||
| 50 | |||
| 51 | BlockInterfaceType block_default_type; | ||
| 52 | int units_per_default_bus; | ||
| 53 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
| 54 | index XXXXXXX..XXXXXXX 100644 | ||
| 55 | --- a/hw/arm/virt.c | ||
| 56 | +++ b/hw/arm/virt.c | ||
| 57 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
| 58 | |||
| 59 | /* | ||
| 60 | * In accelerated mode, the memory map is computed earlier in kvm_type() | ||
| 61 | - * to create a VM with the right number of IPA bits. | ||
| 62 | + * for Linux, or hvf_get_physical_address_range() for macOS to create a | ||
| 63 | + * VM with the right number of IPA bits. | ||
| 64 | */ | ||
| 65 | if (!vms->memmap) { | ||
| 66 | Object *cpuobj; | ||
| 67 | @@ -XXX,XX +XXX,XX @@ static int virt_kvm_type(MachineState *ms, const char *type_str) | ||
| 68 | return fixed_ipa ? 0 : requested_pa_size; | ||
| 69 | } | 21 | } |
| 70 | 22 | ||
| 71 | +static int virt_hvf_get_physical_address_range(MachineState *ms) | 23 | +/*---------------------------------------------------------------------------- |
| 24 | +| Takes two extended double-precision floating-point values `a' and `b', one | ||
| 25 | +| of which is a NaN, and returns the appropriate NaN result. If either `a' or | ||
| 26 | +| `b' is a signaling NaN, the invalid exception is raised. | ||
| 27 | +*----------------------------------------------------------------------------*/ | ||
| 28 | + | ||
| 29 | +floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) | ||
| 72 | +{ | 30 | +{ |
| 73 | + return 0; | 31 | + bool aIsLargerSignificand; |
| 32 | + FloatClass a_cls, b_cls; | ||
| 33 | + | ||
| 34 | + /* This is not complete, but is good enough for pickNaN. */ | ||
| 35 | + a_cls = (!floatx80_is_any_nan(a) | ||
| 36 | + ? float_class_normal | ||
| 37 | + : floatx80_is_signaling_nan(a, status) | ||
| 38 | + ? float_class_snan | ||
| 39 | + : float_class_qnan); | ||
| 40 | + b_cls = (!floatx80_is_any_nan(b) | ||
| 41 | + ? float_class_normal | ||
| 42 | + : floatx80_is_signaling_nan(b, status) | ||
| 43 | + ? float_class_snan | ||
| 44 | + : float_class_qnan); | ||
| 45 | + | ||
| 46 | + if (is_snan(a_cls) || is_snan(b_cls)) { | ||
| 47 | + float_raise(float_flag_invalid, status); | ||
| 48 | + } | ||
| 49 | + | ||
| 50 | + if (status->default_nan_mode) { | ||
| 51 | + return floatx80_default_nan(status); | ||
| 52 | + } | ||
| 53 | + | ||
| 54 | + if (a.low < b.low) { | ||
| 55 | + aIsLargerSignificand = 0; | ||
| 56 | + } else if (b.low < a.low) { | ||
| 57 | + aIsLargerSignificand = 1; | ||
| 58 | + } else { | ||
| 59 | + aIsLargerSignificand = (a.high < b.high) ? 1 : 0; | ||
| 60 | + } | ||
| 61 | + | ||
| 62 | + if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { | ||
| 63 | + if (is_snan(b_cls)) { | ||
| 64 | + return floatx80_silence_nan(b, status); | ||
| 65 | + } | ||
| 66 | + return b; | ||
| 67 | + } else { | ||
| 68 | + if (is_snan(a_cls)) { | ||
| 69 | + return floatx80_silence_nan(a, status); | ||
| 70 | + } | ||
| 71 | + return a; | ||
| 72 | + } | ||
| 74 | +} | 73 | +} |
| 75 | + | 74 | + |
| 76 | static void virt_machine_class_init(ObjectClass *oc, void *data) | 75 | /*---------------------------------------------------------------------------- |
| 77 | { | 76 | | Takes an abstract floating-point value having sign `zSign', exponent `zExp', |
| 78 | MachineClass *mc = MACHINE_CLASS(oc); | 77 | | and extended significand formed by the concatenation of `zSig0' and `zSig1', |
| 79 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data) | 78 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
| 80 | mc->valid_cpu_types = valid_cpu_types; | 79 | index XXXXXXX..XXXXXXX 100644 |
| 81 | mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; | 80 | --- a/fpu/softfloat-specialize.c.inc |
| 82 | mc->kvm_type = virt_kvm_type; | 81 | +++ b/fpu/softfloat-specialize.c.inc |
| 83 | + mc->hvf_get_physical_address_range = virt_hvf_get_physical_address_range; | 82 | @@ -XXX,XX +XXX,XX @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status) |
| 84 | assert(!mc->get_hotplug_handler); | 83 | return a; |
| 85 | mc->get_hotplug_handler = virt_machine_get_hotplug_handler; | 84 | } |
| 86 | hc->pre_plug = virt_machine_device_pre_plug_cb; | 85 | |
| 86 | -/*---------------------------------------------------------------------------- | ||
| 87 | -| Takes two extended double-precision floating-point values `a' and `b', one | ||
| 88 | -| of which is a NaN, and returns the appropriate NaN result. If either `a' or | ||
| 89 | -| `b' is a signaling NaN, the invalid exception is raised. | ||
| 90 | -*----------------------------------------------------------------------------*/ | ||
| 91 | - | ||
| 92 | -floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) | ||
| 93 | -{ | ||
| 94 | - bool aIsLargerSignificand; | ||
| 95 | - FloatClass a_cls, b_cls; | ||
| 96 | - | ||
| 97 | - /* This is not complete, but is good enough for pickNaN. */ | ||
| 98 | - a_cls = (!floatx80_is_any_nan(a) | ||
| 99 | - ? float_class_normal | ||
| 100 | - : floatx80_is_signaling_nan(a, status) | ||
| 101 | - ? float_class_snan | ||
| 102 | - : float_class_qnan); | ||
| 103 | - b_cls = (!floatx80_is_any_nan(b) | ||
| 104 | - ? float_class_normal | ||
| 105 | - : floatx80_is_signaling_nan(b, status) | ||
| 106 | - ? float_class_snan | ||
| 107 | - : float_class_qnan); | ||
| 108 | - | ||
| 109 | - if (is_snan(a_cls) || is_snan(b_cls)) { | ||
| 110 | - float_raise(float_flag_invalid, status); | ||
| 111 | - } | ||
| 112 | - | ||
| 113 | - if (status->default_nan_mode) { | ||
| 114 | - return floatx80_default_nan(status); | ||
| 115 | - } | ||
| 116 | - | ||
| 117 | - if (a.low < b.low) { | ||
| 118 | - aIsLargerSignificand = 0; | ||
| 119 | - } else if (b.low < a.low) { | ||
| 120 | - aIsLargerSignificand = 1; | ||
| 121 | - } else { | ||
| 122 | - aIsLargerSignificand = (a.high < b.high) ? 1 : 0; | ||
| 123 | - } | ||
| 124 | - | ||
| 125 | - if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { | ||
| 126 | - if (is_snan(b_cls)) { | ||
| 127 | - return floatx80_silence_nan(b, status); | ||
| 128 | - } | ||
| 129 | - return b; | ||
| 130 | - } else { | ||
| 131 | - if (is_snan(a_cls)) { | ||
| 132 | - return floatx80_silence_nan(a, status); | ||
| 133 | - } | ||
| 134 | - return a; | ||
| 135 | - } | ||
| 136 | -} | ||
| 137 | - | ||
| 138 | /*---------------------------------------------------------------------------- | ||
| 139 | | Returns 1 if the quadruple-precision floating-point value `a' is a quiet | ||
| 140 | | NaN; otherwise returns 0. | ||
| 87 | -- | 141 | -- |
| 88 | 2.34.1 | 142 | 2.34.1 | diff view generated by jsdifflib |
| 1 | From: Doug Brown <doug@schmorgal.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Previously the emulated CAN ID register was being set to the exact same | 3 | Unpacking and repacking the parts may be slightly more work |
| 4 | value stored in qemu_can_frame.can_id. This doesn't work correctly | 4 | than we did before, but we get to reuse more code. For a |
| 5 | because the Xilinx IP core uses a different bit arrangement than | 5 | code path handling exceptional values, this is an improvement. |
| 6 | qemu_can_frame for all of its ID registers. Correct this problem for | ||
| 7 | both RX and TX, including RX filtering. | ||
| 8 | 6 | ||
| 9 | Signed-off-by: Doug Brown <doug@schmorgal.com> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 10 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | 8 | Message-id: 20241203203949.483774-8-richard.henderson@linaro.org |
| 11 | Acked-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| 12 | Message-id: 20240827034927.66659-4-doug@schmorgal.com | ||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 14 | --- | 11 | --- |
| 15 | hw/net/can/xlnx-versal-canfd.c | 53 ++++++++++++++++++++++++++++++++-- | 12 | fpu/softfloat.c | 43 +++++-------------------------------------- |
| 16 | 1 file changed, 50 insertions(+), 3 deletions(-) | 13 | 1 file changed, 5 insertions(+), 38 deletions(-) |
| 17 | 14 | ||
| 18 | diff --git a/hw/net/can/xlnx-versal-canfd.c b/hw/net/can/xlnx-versal-canfd.c | 15 | diff --git a/fpu/softfloat.c b/fpu/softfloat.c |
| 19 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
| 20 | --- a/hw/net/can/xlnx-versal-canfd.c | 17 | --- a/fpu/softfloat.c |
| 21 | +++ b/hw/net/can/xlnx-versal-canfd.c | 18 | +++ b/fpu/softfloat.c |
| 22 | @@ -XXX,XX +XXX,XX @@ static void regs2frame(XlnxVersalCANFDState *s, qemu_can_frame *frame, | 19 | @@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr, |
| 23 | uint32_t val = 0; | 20 | |
| 24 | uint32_t dlc_reg_val = 0; | 21 | floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) |
| 25 | uint32_t dlc_value = 0; | 22 | { |
| 26 | + uint32_t id_reg_val = 0; | 23 | - bool aIsLargerSignificand; |
| 27 | + bool is_rtr = false; | 24 | - FloatClass a_cls, b_cls; |
| 28 | 25 | + FloatParts128 pa, pb, *pr; | |
| 29 | /* Check that reg_num should be within TX register space. */ | 26 | |
| 30 | assert(reg_num <= R_TB_ID_REGISTER + (NUM_REGS_PER_MSG_SPACE * | 27 | - /* This is not complete, but is good enough for pickNaN. */ |
| 31 | @@ -XXX,XX +XXX,XX @@ static void regs2frame(XlnxVersalCANFDState *s, qemu_can_frame *frame, | 28 | - a_cls = (!floatx80_is_any_nan(a) |
| 32 | dlc_reg_val = s->regs[reg_num + 1]; | 29 | - ? float_class_normal |
| 33 | dlc_value = FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, DLC); | 30 | - : floatx80_is_signaling_nan(a, status) |
| 34 | 31 | - ? float_class_snan | |
| 35 | - frame->can_id = s->regs[reg_num]; | 32 | - : float_class_qnan); |
| 36 | + id_reg_val = s->regs[reg_num]; | 33 | - b_cls = (!floatx80_is_any_nan(b) |
| 37 | + if (FIELD_EX32(id_reg_val, TB_ID_REGISTER, IDE)) { | 34 | - ? float_class_normal |
| 38 | + frame->can_id = (FIELD_EX32(id_reg_val, TB_ID_REGISTER, ID) << 18) | | 35 | - : floatx80_is_signaling_nan(b, status) |
| 39 | + (FIELD_EX32(id_reg_val, TB_ID_REGISTER, ID_EXT)) | | 36 | - ? float_class_snan |
| 40 | + QEMU_CAN_EFF_FLAG; | 37 | - : float_class_qnan); |
| 41 | + if (FIELD_EX32(id_reg_val, TB_ID_REGISTER, RTR_RRS)) { | 38 | - |
| 42 | + is_rtr = true; | 39 | - if (is_snan(a_cls) || is_snan(b_cls)) { |
| 43 | + } | 40 | - float_raise(float_flag_invalid, status); |
| 44 | + } else { | 41 | - } |
| 45 | + frame->can_id = FIELD_EX32(id_reg_val, TB_ID_REGISTER, ID); | 42 | - |
| 46 | + if (FIELD_EX32(id_reg_val, TB_ID_REGISTER, SRR_RTR_RRS)) { | 43 | - if (status->default_nan_mode) { |
| 47 | + is_rtr = true; | 44 | + if (!floatx80_unpack_canonical(&pa, a, status) || |
| 48 | + } | 45 | + !floatx80_unpack_canonical(&pb, b, status)) { |
| 49 | + } | 46 | return floatx80_default_nan(status); |
| 50 | |||
| 51 | if (FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, FDF)) { | ||
| 52 | /* | ||
| 53 | @@ -XXX,XX +XXX,XX @@ static void regs2frame(XlnxVersalCANFDState *s, qemu_can_frame *frame, | ||
| 54 | } else { | ||
| 55 | frame->can_dlc = dlc_value; | ||
| 56 | } | ||
| 57 | + | ||
| 58 | + if (is_rtr) { | ||
| 59 | + frame->can_id |= QEMU_CAN_RTR_FLAG; | ||
| 60 | + } | ||
| 61 | } | 47 | } |
| 62 | 48 | ||
| 63 | for (j = 0; j < frame->can_dlc; j++) { | 49 | - if (a.low < b.low) { |
| 64 | @@ -XXX,XX +XXX,XX @@ static void process_cancellation_requests(XlnxVersalCANFDState *s) | 50 | - aIsLargerSignificand = 0; |
| 65 | canfd_update_irq(s); | 51 | - } else if (b.low < a.low) { |
| 52 | - aIsLargerSignificand = 1; | ||
| 53 | - } else { | ||
| 54 | - aIsLargerSignificand = (a.high < b.high) ? 1 : 0; | ||
| 55 | - } | ||
| 56 | - | ||
| 57 | - if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { | ||
| 58 | - if (is_snan(b_cls)) { | ||
| 59 | - return floatx80_silence_nan(b, status); | ||
| 60 | - } | ||
| 61 | - return b; | ||
| 62 | - } else { | ||
| 63 | - if (is_snan(a_cls)) { | ||
| 64 | - return floatx80_silence_nan(a, status); | ||
| 65 | - } | ||
| 66 | - return a; | ||
| 67 | - } | ||
| 68 | + pr = parts_pick_nan(&pa, &pb, status); | ||
| 69 | + return floatx80_round_pack_canonical(pr, status); | ||
| 66 | } | 70 | } |
| 67 | 71 | ||
| 68 | +static uint32_t frame_to_reg_id(const qemu_can_frame *frame) | 72 | /*---------------------------------------------------------------------------- |
| 69 | +{ | ||
| 70 | + uint32_t id_reg_val = 0; | ||
| 71 | + const bool is_canfd_frame = frame->flags & QEMU_CAN_FRMF_TYPE_FD; | ||
| 72 | + const bool is_rtr = !is_canfd_frame && (frame->can_id & QEMU_CAN_RTR_FLAG); | ||
| 73 | + | ||
| 74 | + if (frame->can_id & QEMU_CAN_EFF_FLAG) { | ||
| 75 | + id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, ID, | ||
| 76 | + (frame->can_id & QEMU_CAN_EFF_MASK) >> 18); | ||
| 77 | + id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, ID_EXT, | ||
| 78 | + frame->can_id & QEMU_CAN_EFF_MASK); | ||
| 79 | + id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, IDE, 1); | ||
| 80 | + id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, SRR_RTR_RRS, 1); | ||
| 81 | + if (is_rtr) { | ||
| 82 | + id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, RTR_RRS, 1); | ||
| 83 | + } | ||
| 84 | + } else { | ||
| 85 | + id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, ID, | ||
| 86 | + frame->can_id & QEMU_CAN_SFF_MASK); | ||
| 87 | + if (is_rtr) { | ||
| 88 | + id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, SRR_RTR_RRS, 1); | ||
| 89 | + } | ||
| 90 | + } | ||
| 91 | + | ||
| 92 | + return id_reg_val; | ||
| 93 | +} | ||
| 94 | + | ||
| 95 | static void store_rx_sequential(XlnxVersalCANFDState *s, | ||
| 96 | const qemu_can_frame *frame, | ||
| 97 | uint32_t fill_level, uint32_t read_index, | ||
| 98 | @@ -XXX,XX +XXX,XX @@ static void store_rx_sequential(XlnxVersalCANFDState *s, | ||
| 99 | NUM_REGS_PER_MSG_SPACE)); | ||
| 100 | } | ||
| 101 | |||
| 102 | - s->regs[store_location] = frame->can_id; | ||
| 103 | + s->regs[store_location] = frame_to_reg_id(frame); | ||
| 104 | |||
| 105 | dlc = frame->can_dlc; | ||
| 106 | |||
| 107 | @@ -XXX,XX +XXX,XX @@ static void update_rx_sequential(XlnxVersalCANFDState *s, | ||
| 108 | if (s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER]) { | ||
| 109 | uint32_t acceptance_filter_status = | ||
| 110 | s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER]; | ||
| 111 | + const uint32_t reg_id = frame_to_reg_id(frame); | ||
| 112 | |||
| 113 | for (i = 0; i < 32; i++) { | ||
| 114 | if (acceptance_filter_status & 0x1) { | ||
| 115 | uint32_t msg_id_masked = s->regs[R_AFMR_REGISTER + 2 * i] & | ||
| 116 | - frame->can_id; | ||
| 117 | + reg_id; | ||
| 118 | uint32_t afir_id_masked = s->regs[R_AFIR_REGISTER + 2 * i] & | ||
| 119 | s->regs[R_AFMR_REGISTER + 2 * i]; | ||
| 120 | uint16_t std_msg_id_masked = FIELD_EX32(msg_id_masked, | ||
| 121 | -- | 73 | -- |
| 122 | 2.34.1 | 74 | 2.34.1 | diff view generated by jsdifflib |
| 1 | Rename the DeviceClass::reset field to legacy_reset; this is helpful | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | both in flagging up that it's best not used in new code and in | 2 | |
| 3 | making it easy to search for where it's being used still. | 3 | Inline pickNaN into its only caller. This makes one assert |
| 4 | 4 | redundant with the immediately preceding IF. | |
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 8 | Message-id: 20241203203949.483774-9-richard.henderson@linaro.org | ||
| 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20240830145812.1967042-9-peter.maydell@linaro.org | ||
| 9 | --- | 10 | --- |
| 10 | include/hw/qdev-core.h | 4 ++-- | 11 | fpu/softfloat-parts.c.inc | 82 +++++++++++++++++++++++++---- |
| 11 | hw/core/qdev.c | 8 ++++---- | 12 | fpu/softfloat-specialize.c.inc | 96 ---------------------------------- |
| 12 | 2 files changed, 6 insertions(+), 6 deletions(-) | 13 | 2 files changed, 73 insertions(+), 105 deletions(-) |
| 13 | 14 | ||
| 14 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h | 15 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
| 15 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/include/hw/qdev-core.h | 17 | --- a/fpu/softfloat-parts.c.inc |
| 17 | +++ b/include/hw/qdev-core.h | 18 | +++ b/fpu/softfloat-parts.c.inc |
| 18 | @@ -XXX,XX +XXX,XX @@ struct DeviceClass { | 19 | @@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s) |
| 19 | 20 | static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, | |
| 20 | /* callbacks */ | 21 | float_status *s) |
| 21 | /** | 22 | { |
| 22 | - * @reset: deprecated device reset method pointer | 23 | + int cmp, which; |
| 23 | + * @legacy_reset: deprecated device reset method pointer | 24 | + |
| 24 | * | 25 | if (is_snan(a->cls) || is_snan(b->cls)) { |
| 25 | * Modern code should use the ResettableClass interface to | 26 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); |
| 26 | * implement a multi-phase reset. | 27 | } |
| 27 | * | 28 | |
| 28 | * TODO: remove once every reset callback is unused | 29 | if (s->default_nan_mode) { |
| 29 | */ | 30 | parts_default_nan(a, s); |
| 30 | - DeviceReset reset; | 31 | - } else { |
| 31 | + DeviceReset legacy_reset; | 32 | - int cmp = frac_cmp(a, b); |
| 32 | DeviceRealize realize; | 33 | - if (cmp == 0) { |
| 33 | DeviceUnrealize unrealize; | 34 | - cmp = a->sign < b->sign; |
| 34 | 35 | - } | |
| 35 | diff --git a/hw/core/qdev.c b/hw/core/qdev.c | 36 | + return a; |
| 37 | + } | ||
| 38 | |||
| 39 | - if (pickNaN(a->cls, b->cls, cmp > 0, s)) { | ||
| 40 | - a = b; | ||
| 41 | - } | ||
| 42 | + cmp = frac_cmp(a, b); | ||
| 43 | + if (cmp == 0) { | ||
| 44 | + cmp = a->sign < b->sign; | ||
| 45 | + } | ||
| 46 | + | ||
| 47 | + switch (s->float_2nan_prop_rule) { | ||
| 48 | + case float_2nan_prop_s_ab: | ||
| 49 | if (is_snan(a->cls)) { | ||
| 50 | - parts_silence_nan(a, s); | ||
| 51 | + which = 0; | ||
| 52 | + } else if (is_snan(b->cls)) { | ||
| 53 | + which = 1; | ||
| 54 | + } else if (is_qnan(a->cls)) { | ||
| 55 | + which = 0; | ||
| 56 | + } else { | ||
| 57 | + which = 1; | ||
| 58 | } | ||
| 59 | + break; | ||
| 60 | + case float_2nan_prop_s_ba: | ||
| 61 | + if (is_snan(b->cls)) { | ||
| 62 | + which = 1; | ||
| 63 | + } else if (is_snan(a->cls)) { | ||
| 64 | + which = 0; | ||
| 65 | + } else if (is_qnan(b->cls)) { | ||
| 66 | + which = 1; | ||
| 67 | + } else { | ||
| 68 | + which = 0; | ||
| 69 | + } | ||
| 70 | + break; | ||
| 71 | + case float_2nan_prop_ab: | ||
| 72 | + which = is_nan(a->cls) ? 0 : 1; | ||
| 73 | + break; | ||
| 74 | + case float_2nan_prop_ba: | ||
| 75 | + which = is_nan(b->cls) ? 1 : 0; | ||
| 76 | + break; | ||
| 77 | + case float_2nan_prop_x87: | ||
| 78 | + /* | ||
| 79 | + * This implements x87 NaN propagation rules: | ||
| 80 | + * SNaN + QNaN => return the QNaN | ||
| 81 | + * two SNaNs => return the one with the larger significand, silenced | ||
| 82 | + * two QNaNs => return the one with the larger significand | ||
| 83 | + * SNaN and a non-NaN => return the SNaN, silenced | ||
| 84 | + * QNaN and a non-NaN => return the QNaN | ||
| 85 | + * | ||
| 86 | + * If we get down to comparing significands and they are the same, | ||
| 87 | + * return the NaN with the positive sign bit (if any). | ||
| 88 | + */ | ||
| 89 | + if (is_snan(a->cls)) { | ||
| 90 | + if (is_snan(b->cls)) { | ||
| 91 | + which = cmp > 0 ? 0 : 1; | ||
| 92 | + } else { | ||
| 93 | + which = is_qnan(b->cls) ? 1 : 0; | ||
| 94 | + } | ||
| 95 | + } else if (is_qnan(a->cls)) { | ||
| 96 | + if (is_snan(b->cls) || !is_qnan(b->cls)) { | ||
| 97 | + which = 0; | ||
| 98 | + } else { | ||
| 99 | + which = cmp > 0 ? 0 : 1; | ||
| 100 | + } | ||
| 101 | + } else { | ||
| 102 | + which = 1; | ||
| 103 | + } | ||
| 104 | + break; | ||
| 105 | + default: | ||
| 106 | + g_assert_not_reached(); | ||
| 107 | + } | ||
| 108 | + | ||
| 109 | + if (which) { | ||
| 110 | + a = b; | ||
| 111 | + } | ||
| 112 | + if (is_snan(a->cls)) { | ||
| 113 | + parts_silence_nan(a, s); | ||
| 114 | } | ||
| 115 | return a; | ||
| 116 | } | ||
| 117 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
| 36 | index XXXXXXX..XXXXXXX 100644 | 118 | index XXXXXXX..XXXXXXX 100644 |
| 37 | --- a/hw/core/qdev.c | 119 | --- a/fpu/softfloat-specialize.c.inc |
| 38 | +++ b/hw/core/qdev.c | 120 | +++ b/fpu/softfloat-specialize.c.inc |
| 39 | @@ -XXX,XX +XXX,XX @@ static void device_transitional_reset(Object *obj) | 121 | @@ -XXX,XX +XXX,XX @@ bool float32_is_signaling_nan(float32 a_, float_status *status) |
| 40 | * devices) or a device's specific method for not-yet transitioned devices. | ||
| 41 | * In both case, it does not reset children. | ||
| 42 | */ | ||
| 43 | - if (dc->reset) { | ||
| 44 | - dc->reset(DEVICE(obj)); | ||
| 45 | + if (dc->legacy_reset) { | ||
| 46 | + dc->legacy_reset(DEVICE(obj)); | ||
| 47 | } | 122 | } |
| 48 | } | 123 | } |
| 49 | 124 | ||
| 50 | @@ -XXX,XX +XXX,XX @@ static void device_transitional_reset(Object *obj) | 125 | -/*---------------------------------------------------------------------------- |
| 51 | static ResettableTrFunction device_get_transitional_reset(Object *obj) | 126 | -| Select which NaN to propagate for a two-input operation. |
| 52 | { | 127 | -| IEEE754 doesn't specify all the details of this, so the |
| 53 | DeviceClass *dc = DEVICE_GET_CLASS(obj); | 128 | -| algorithm is target-specific. |
| 54 | - if (dc->reset != device_phases_reset) { | 129 | -| The routine is passed various bits of information about the |
| 55 | + if (dc->legacy_reset != device_phases_reset) { | 130 | -| two NaNs and should return 0 to select NaN a and 1 for NaN b. |
| 56 | /* | 131 | -| Note that signalling NaNs are always squashed to quiet NaNs |
| 57 | * dc->reset has been overridden by a subclass, | 132 | -| by the caller, by calling floatXX_silence_nan() before |
| 58 | * the device is not ready for multi phase yet. | 133 | -| returning them. |
| 59 | @@ -XXX,XX +XXX,XX @@ static void device_class_init(ObjectClass *class, void *data) | 134 | -| |
| 60 | 135 | -| aIsLargerSignificand is only valid if both a and b are NaNs | |
| 61 | void device_class_set_legacy_reset(DeviceClass *dc, DeviceReset dev_reset) | 136 | -| of some kind, and is true if a has the larger significand, |
| 62 | { | 137 | -| or if both a and b have the same significand but a is |
| 63 | - dc->reset = dev_reset; | 138 | -| positive but b is negative. It is only needed for the x87 |
| 64 | + dc->legacy_reset = dev_reset; | 139 | -| tie-break rule. |
| 65 | } | 140 | -*----------------------------------------------------------------------------*/ |
| 66 | 141 | - | |
| 67 | void device_class_set_parent_realize(DeviceClass *dc, | 142 | -static int pickNaN(FloatClass a_cls, FloatClass b_cls, |
| 143 | - bool aIsLargerSignificand, float_status *status) | ||
| 144 | -{ | ||
| 145 | - /* | ||
| 146 | - * We guarantee not to require the target to tell us how to | ||
| 147 | - * pick a NaN if we're always returning the default NaN. | ||
| 148 | - * But if we're not in default-NaN mode then the target must | ||
| 149 | - * specify via set_float_2nan_prop_rule(). | ||
| 150 | - */ | ||
| 151 | - assert(!status->default_nan_mode); | ||
| 152 | - | ||
| 153 | - switch (status->float_2nan_prop_rule) { | ||
| 154 | - case float_2nan_prop_s_ab: | ||
| 155 | - if (is_snan(a_cls)) { | ||
| 156 | - return 0; | ||
| 157 | - } else if (is_snan(b_cls)) { | ||
| 158 | - return 1; | ||
| 159 | - } else if (is_qnan(a_cls)) { | ||
| 160 | - return 0; | ||
| 161 | - } else { | ||
| 162 | - return 1; | ||
| 163 | - } | ||
| 164 | - break; | ||
| 165 | - case float_2nan_prop_s_ba: | ||
| 166 | - if (is_snan(b_cls)) { | ||
| 167 | - return 1; | ||
| 168 | - } else if (is_snan(a_cls)) { | ||
| 169 | - return 0; | ||
| 170 | - } else if (is_qnan(b_cls)) { | ||
| 171 | - return 1; | ||
| 172 | - } else { | ||
| 173 | - return 0; | ||
| 174 | - } | ||
| 175 | - break; | ||
| 176 | - case float_2nan_prop_ab: | ||
| 177 | - if (is_nan(a_cls)) { | ||
| 178 | - return 0; | ||
| 179 | - } else { | ||
| 180 | - return 1; | ||
| 181 | - } | ||
| 182 | - break; | ||
| 183 | - case float_2nan_prop_ba: | ||
| 184 | - if (is_nan(b_cls)) { | ||
| 185 | - return 1; | ||
| 186 | - } else { | ||
| 187 | - return 0; | ||
| 188 | - } | ||
| 189 | - break; | ||
| 190 | - case float_2nan_prop_x87: | ||
| 191 | - /* | ||
| 192 | - * This implements x87 NaN propagation rules: | ||
| 193 | - * SNaN + QNaN => return the QNaN | ||
| 194 | - * two SNaNs => return the one with the larger significand, silenced | ||
| 195 | - * two QNaNs => return the one with the larger significand | ||
| 196 | - * SNaN and a non-NaN => return the SNaN, silenced | ||
| 197 | - * QNaN and a non-NaN => return the QNaN | ||
| 198 | - * | ||
| 199 | - * If we get down to comparing significands and they are the same, | ||
| 200 | - * return the NaN with the positive sign bit (if any). | ||
| 201 | - */ | ||
| 202 | - if (is_snan(a_cls)) { | ||
| 203 | - if (is_snan(b_cls)) { | ||
| 204 | - return aIsLargerSignificand ? 0 : 1; | ||
| 205 | - } | ||
| 206 | - return is_qnan(b_cls) ? 1 : 0; | ||
| 207 | - } else if (is_qnan(a_cls)) { | ||
| 208 | - if (is_snan(b_cls) || !is_qnan(b_cls)) { | ||
| 209 | - return 0; | ||
| 210 | - } else { | ||
| 211 | - return aIsLargerSignificand ? 0 : 1; | ||
| 212 | - } | ||
| 213 | - } else { | ||
| 214 | - return 1; | ||
| 215 | - } | ||
| 216 | - default: | ||
| 217 | - g_assert_not_reached(); | ||
| 218 | - } | ||
| 219 | -} | ||
| 220 | - | ||
| 221 | /*---------------------------------------------------------------------------- | ||
| 222 | | Returns 1 if the double-precision floating-point value `a' is a quiet | ||
| 223 | | NaN; otherwise returns 0. | ||
| 68 | -- | 224 | -- |
| 69 | 2.34.1 | 225 | 2.34.1 |
| 70 | 226 | ||
| 71 | 227 | diff view generated by jsdifflib |
| 1 | From: Doug Brown <doug@schmorgal.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The read index should not be changed when storing a new message into the | 3 | Remember if there was an SNaN, and use that to simplify |
| 4 | RX or TX FIFO. Changing it at this point will cause the reader to get | 4 | float_2nan_prop_s_{ab,ba} to only the snan component. |
| 5 | out of sync. The wrapping of the read index is already handled by the | 5 | Then, fall through to the corresponding |
| 6 | pre-write functions for the FIFO status registers anyway. | 6 | float_2nan_prop_{ab,ba} case to handle any remaining |
| 7 | nans, which must be quiet. | ||
| 7 | 8 | ||
| 8 | Additionally, the calculation for wrapping the store index was off by | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 9 | one, which caused new messages to be written to the wrong location in | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | the FIFO. This caused incorrect messages to be delivered. | 11 | Message-id: 20241203203949.483774-10-richard.henderson@linaro.org |
| 11 | |||
| 12 | Signed-off-by: Doug Brown <doug@schmorgal.com> | ||
| 13 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | ||
| 14 | Message-id: 20240827034927.66659-8-doug@schmorgal.com | ||
| 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 16 | --- | 13 | --- |
| 17 | hw/net/can/xlnx-versal-canfd.c | 36 +++------------------------------- | 14 | fpu/softfloat-parts.c.inc | 32 ++++++++++++-------------------- |
| 18 | 1 file changed, 3 insertions(+), 33 deletions(-) | 15 | 1 file changed, 12 insertions(+), 20 deletions(-) |
| 19 | 16 | ||
| 20 | diff --git a/hw/net/can/xlnx-versal-canfd.c b/hw/net/can/xlnx-versal-canfd.c | 17 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
| 21 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
| 22 | --- a/hw/net/can/xlnx-versal-canfd.c | 19 | --- a/fpu/softfloat-parts.c.inc |
| 23 | +++ b/hw/net/can/xlnx-versal-canfd.c | 20 | +++ b/fpu/softfloat-parts.c.inc |
| 24 | @@ -XXX,XX +XXX,XX @@ static void update_rx_sequential(XlnxVersalCANFDState *s, | 21 | @@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s) |
| 25 | read_index = ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, RI); | 22 | static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
| 26 | store_index = read_index + fill_level; | 23 | float_status *s) |
| 27 | 24 | { | |
| 28 | - if (read_index == s->cfg.rx0_fifo - 1) { | 25 | + bool have_snan = false; |
| 29 | - /* | 26 | int cmp, which; |
| 30 | - * When ri is s->cfg.rx0_fifo - 1 i.e. max, it goes cyclic that | 27 | |
| 31 | - * means we reset the ri to 0x0. | 28 | if (is_snan(a->cls) || is_snan(b->cls)) { |
| 32 | - */ | 29 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); |
| 33 | - read_index = 0; | 30 | + have_snan = true; |
| 34 | - ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, RI, | 31 | } |
| 35 | - read_index); | 32 | |
| 36 | - } | 33 | if (s->default_nan_mode) { |
| 37 | - | 34 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
| 38 | if (store_index > s->cfg.rx0_fifo - 1) { | 35 | |
| 39 | - store_index -= s->cfg.rx0_fifo - 1; | 36 | switch (s->float_2nan_prop_rule) { |
| 40 | + store_index -= s->cfg.rx0_fifo; | 37 | case float_2nan_prop_s_ab: |
| 41 | } | 38 | - if (is_snan(a->cls)) { |
| 42 | 39 | - which = 0; | |
| 43 | store_location = R_RB_ID_REGISTER + | 40 | - } else if (is_snan(b->cls)) { |
| 44 | @@ -XXX,XX +XXX,XX @@ static void update_rx_sequential(XlnxVersalCANFDState *s, | 41 | - which = 1; |
| 45 | RI_1); | 42 | - } else if (is_qnan(a->cls)) { |
| 46 | store_index = read_index + fill_level; | 43 | - which = 0; |
| 47 | 44 | - } else { | |
| 48 | - if (read_index == s->cfg.rx1_fifo - 1) { | 45 | - which = 1; |
| 49 | - /* | 46 | + if (have_snan) { |
| 50 | - * When ri is s->cfg.rx1_fifo - 1 i.e. max, it goes cyclic that | 47 | + which = is_snan(a->cls) ? 0 : 1; |
| 51 | - * means we reset the ri to 0x0. | 48 | + break; |
| 52 | - */ | 49 | } |
| 53 | - read_index = 0; | 50 | - break; |
| 54 | - ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, RI_1, | 51 | - case float_2nan_prop_s_ba: |
| 55 | - read_index); | 52 | - if (is_snan(b->cls)) { |
| 56 | - } | 53 | - which = 1; |
| 57 | - | 54 | - } else if (is_snan(a->cls)) { |
| 58 | if (store_index > s->cfg.rx1_fifo - 1) { | 55 | - which = 0; |
| 59 | - store_index -= s->cfg.rx1_fifo - 1; | 56 | - } else if (is_qnan(b->cls)) { |
| 60 | + store_index -= s->cfg.rx1_fifo; | 57 | - which = 1; |
| 61 | } | 58 | - } else { |
| 62 | 59 | - which = 0; | |
| 63 | store_location = R_RB_ID_REGISTER_1 + | 60 | - } |
| 64 | @@ -XXX,XX +XXX,XX @@ static void tx_fifo_stamp(XlnxVersalCANFDState *s, uint32_t tb0_regid) | 61 | - break; |
| 65 | " Discarding the message\n"); | 62 | + /* fall through */ |
| 66 | ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXEOFLW, 1); | 63 | case float_2nan_prop_ab: |
| 67 | } else { | 64 | which = is_nan(a->cls) ? 0 : 1; |
| 68 | - if (read_index == s->cfg.tx_fifo - 1) { | 65 | break; |
| 69 | - /* | 66 | + case float_2nan_prop_s_ba: |
| 70 | - * When ri is s->cfg.tx_fifo - 1 i.e. max, it goes cyclic that | 67 | + if (have_snan) { |
| 71 | - * means we reset the ri to 0x0. | 68 | + which = is_snan(b->cls) ? 1 : 0; |
| 72 | - */ | 69 | + break; |
| 73 | - read_index = 0; | 70 | + } |
| 74 | - ARRAY_FIELD_DP32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_RI, | 71 | + /* fall through */ |
| 75 | - read_index); | 72 | case float_2nan_prop_ba: |
| 76 | - } | 73 | which = is_nan(b->cls) ? 1 : 0; |
| 77 | - | 74 | break; |
| 78 | if (store_index > s->cfg.tx_fifo - 1) { | ||
| 79 | - store_index -= s->cfg.tx_fifo - 1; | ||
| 80 | + store_index -= s->cfg.tx_fifo; | ||
| 81 | } | ||
| 82 | |||
| 83 | assert(store_index < s->cfg.tx_fifo); | ||
| 84 | -- | 75 | -- |
| 85 | 2.34.1 | 76 | 2.34.1 | diff view generated by jsdifflib |
| 1 | From: Doug Brown <doug@schmorgal.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The endianness of the CAN data was backwards in each group of 4 bytes. | 3 | Move the fractional comparison to the end of the |
| 4 | For example, the following data: | 4 | float_2nan_prop_x87 case. This is not required for |
| 5 | any other 2nan propagation rule. Reorganize the | ||
| 6 | x87 case itself to break out of the switch when the | ||
| 7 | fractional comparison is not required. | ||
| 5 | 8 | ||
| 6 | 00 11 22 33 44 55 66 77 | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 7 | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | |
| 8 | was showing up like this: | 11 | Message-id: 20241203203949.483774-11-richard.henderson@linaro.org |
| 9 | |||
| 10 | 33 22 11 00 77 66 55 44 | ||
| 11 | |||
| 12 | Fix both the TX and RX code to put the data in the correct order. | ||
| 13 | |||
| 14 | Signed-off-by: Doug Brown <doug@schmorgal.com> | ||
| 15 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | ||
| 16 | Acked-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
| 17 | Message-id: 20240827034927.66659-6-doug@schmorgal.com | ||
| 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 19 | --- | 13 | --- |
| 20 | hw/net/can/xlnx-versal-canfd.c | 14 +++++++------- | 14 | fpu/softfloat-parts.c.inc | 19 +++++++++---------- |
| 21 | 1 file changed, 7 insertions(+), 7 deletions(-) | 15 | 1 file changed, 9 insertions(+), 10 deletions(-) |
| 22 | 16 | ||
| 23 | diff --git a/hw/net/can/xlnx-versal-canfd.c b/hw/net/can/xlnx-versal-canfd.c | 17 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
| 24 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
| 25 | --- a/hw/net/can/xlnx-versal-canfd.c | 19 | --- a/fpu/softfloat-parts.c.inc |
| 26 | +++ b/hw/net/can/xlnx-versal-canfd.c | 20 | +++ b/fpu/softfloat-parts.c.inc |
| 27 | @@ -XXX,XX +XXX,XX @@ static void regs2frame(XlnxVersalCANFDState *s, qemu_can_frame *frame, | 21 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
| 22 | return a; | ||
| 28 | } | 23 | } |
| 29 | 24 | ||
| 30 | for (j = 0; j < frame->can_dlc; j++) { | 25 | - cmp = frac_cmp(a, b); |
| 31 | - val = 8 * i; | 26 | - if (cmp == 0) { |
| 32 | + val = 8 * (3 - i); | 27 | - cmp = a->sign < b->sign; |
| 33 | 28 | - } | |
| 34 | frame->data[j] = extract32(s->regs[reg_num + 2 + (j / 4)], val, 8); | 29 | - |
| 35 | i++; | 30 | switch (s->float_2nan_prop_rule) { |
| 36 | @@ -XXX,XX +XXX,XX @@ static void store_rx_sequential(XlnxVersalCANFDState *s, | 31 | case float_2nan_prop_s_ab: |
| 37 | case 0: | 32 | if (have_snan) { |
| 38 | rx_reg_num = i / 4; | 33 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
| 39 | 34 | * return the NaN with the positive sign bit (if any). | |
| 40 | - data_reg_val = FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES3, | 35 | */ |
| 41 | + data_reg_val = FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES0, | 36 | if (is_snan(a->cls)) { |
| 42 | frame->data[i]); | 37 | - if (is_snan(b->cls)) { |
| 43 | break; | 38 | - which = cmp > 0 ? 0 : 1; |
| 44 | case 1: | 39 | - } else { |
| 45 | - data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES2, | 40 | + if (!is_snan(b->cls)) { |
| 46 | - frame->data[i]); | 41 | which = is_qnan(b->cls) ? 1 : 0; |
| 47 | - break; | ||
| 48 | - case 2: | ||
| 49 | data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES1, | ||
| 50 | frame->data[i]); | ||
| 51 | break; | ||
| 52 | + case 2: | ||
| 53 | + data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES2, | ||
| 54 | + frame->data[i]); | ||
| 55 | + break; | 42 | + break; |
| 56 | case 3: | 43 | } |
| 57 | - data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES0, | 44 | } else if (is_qnan(a->cls)) { |
| 58 | + data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES3, | 45 | if (is_snan(b->cls) || !is_qnan(b->cls)) { |
| 59 | frame->data[i]); | 46 | which = 0; |
| 60 | /* | 47 | - } else { |
| 61 | * Last Bytes data which means we have all 4 bytes ready to | 48 | - which = cmp > 0 ? 0 : 1; |
| 49 | + break; | ||
| 50 | } | ||
| 51 | } else { | ||
| 52 | which = 1; | ||
| 53 | + break; | ||
| 54 | } | ||
| 55 | + cmp = frac_cmp(a, b); | ||
| 56 | + if (cmp == 0) { | ||
| 57 | + cmp = a->sign < b->sign; | ||
| 58 | + } | ||
| 59 | + which = cmp > 0 ? 0 : 1; | ||
| 60 | break; | ||
| 61 | default: | ||
| 62 | g_assert_not_reached(); | ||
| 62 | -- | 63 | -- |
| 63 | 2.34.1 | 64 | 2.34.1 | diff view generated by jsdifflib |
| 1 | There are no callers of device_class_set_parent_reset() left in the tree, | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | as they've all been converted to use three-phase reset and the | ||
| 3 | corresponding resettable_class_set_parent_phases() function. | ||
| 4 | Remove device_class_set_parent_reset(). | ||
| 5 | 2 | ||
| 3 | Replace the "index" selecting between A and B with a result variable | ||
| 4 | of the proper type. This improves clarity within the function. | ||
| 5 | |||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 8 | Message-id: 20241203203949.483774-12-richard.henderson@linaro.org | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Message-id: 20240830145812.1967042-5-peter.maydell@linaro.org | ||
| 10 | --- | 10 | --- |
| 11 | include/hw/qdev-core.h | 16 ---------------- | 11 | fpu/softfloat-parts.c.inc | 28 +++++++++++++--------------- |
| 12 | hw/core/qdev.c | 8 -------- | 12 | 1 file changed, 13 insertions(+), 15 deletions(-) |
| 13 | 2 files changed, 24 deletions(-) | ||
| 14 | 13 | ||
| 15 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h | 14 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
| 16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/include/hw/qdev-core.h | 16 | --- a/fpu/softfloat-parts.c.inc |
| 18 | +++ b/include/hw/qdev-core.h | 17 | +++ b/fpu/softfloat-parts.c.inc |
| 19 | @@ -XXX,XX +XXX,XX @@ char *qdev_get_own_fw_dev_path_from_handler(BusState *bus, DeviceState *dev); | 18 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
| 20 | */ | 19 | float_status *s) |
| 21 | void device_class_set_props(DeviceClass *dc, Property *props); | 20 | { |
| 22 | 21 | bool have_snan = false; | |
| 23 | -/** | 22 | - int cmp, which; |
| 24 | - * device_class_set_parent_reset() - legacy set device reset handlers | 23 | + FloatPartsN *ret; |
| 25 | - * @dc: device class | 24 | + int cmp; |
| 26 | - * @dev_reset: function pointer to reset handler | 25 | |
| 27 | - * @parent_reset: function pointer to parents reset handler | 26 | if (is_snan(a->cls) || is_snan(b->cls)) { |
| 28 | - * | 27 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); |
| 29 | - * Modern code should use the ResettableClass interface to | 28 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
| 30 | - * implement a multi-phase reset instead. | 29 | switch (s->float_2nan_prop_rule) { |
| 31 | - * | 30 | case float_2nan_prop_s_ab: |
| 32 | - * TODO: remove the function when DeviceClass's reset method | 31 | if (have_snan) { |
| 33 | - * is not used anymore. | 32 | - which = is_snan(a->cls) ? 0 : 1; |
| 34 | - */ | 33 | + ret = is_snan(a->cls) ? a : b; |
| 35 | -void device_class_set_parent_reset(DeviceClass *dc, | 34 | break; |
| 36 | - DeviceReset dev_reset, | 35 | } |
| 37 | - DeviceReset *parent_reset); | 36 | /* fall through */ |
| 38 | - | 37 | case float_2nan_prop_ab: |
| 39 | /** | 38 | - which = is_nan(a->cls) ? 0 : 1; |
| 40 | * device_class_set_parent_realize() - set up for chaining realize fns | 39 | + ret = is_nan(a->cls) ? a : b; |
| 41 | * @dc: The device class | 40 | break; |
| 42 | diff --git a/hw/core/qdev.c b/hw/core/qdev.c | 41 | case float_2nan_prop_s_ba: |
| 43 | index XXXXXXX..XXXXXXX 100644 | 42 | if (have_snan) { |
| 44 | --- a/hw/core/qdev.c | 43 | - which = is_snan(b->cls) ? 1 : 0; |
| 45 | +++ b/hw/core/qdev.c | 44 | + ret = is_snan(b->cls) ? b : a; |
| 46 | @@ -XXX,XX +XXX,XX @@ static void device_class_init(ObjectClass *class, void *data) | 45 | break; |
| 47 | offsetof(DeviceState, parent_bus), NULL, 0); | 46 | } |
| 47 | /* fall through */ | ||
| 48 | case float_2nan_prop_ba: | ||
| 49 | - which = is_nan(b->cls) ? 1 : 0; | ||
| 50 | + ret = is_nan(b->cls) ? b : a; | ||
| 51 | break; | ||
| 52 | case float_2nan_prop_x87: | ||
| 53 | /* | ||
| 54 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, | ||
| 55 | */ | ||
| 56 | if (is_snan(a->cls)) { | ||
| 57 | if (!is_snan(b->cls)) { | ||
| 58 | - which = is_qnan(b->cls) ? 1 : 0; | ||
| 59 | + ret = is_qnan(b->cls) ? b : a; | ||
| 60 | break; | ||
| 61 | } | ||
| 62 | } else if (is_qnan(a->cls)) { | ||
| 63 | if (is_snan(b->cls) || !is_qnan(b->cls)) { | ||
| 64 | - which = 0; | ||
| 65 | + ret = a; | ||
| 66 | break; | ||
| 67 | } | ||
| 68 | } else { | ||
| 69 | - which = 1; | ||
| 70 | + ret = b; | ||
| 71 | break; | ||
| 72 | } | ||
| 73 | cmp = frac_cmp(a, b); | ||
| 74 | if (cmp == 0) { | ||
| 75 | cmp = a->sign < b->sign; | ||
| 76 | } | ||
| 77 | - which = cmp > 0 ? 0 : 1; | ||
| 78 | + ret = cmp > 0 ? a : b; | ||
| 79 | break; | ||
| 80 | default: | ||
| 81 | g_assert_not_reached(); | ||
| 82 | } | ||
| 83 | |||
| 84 | - if (which) { | ||
| 85 | - a = b; | ||
| 86 | + if (is_snan(ret->cls)) { | ||
| 87 | + parts_silence_nan(ret, s); | ||
| 88 | } | ||
| 89 | - if (is_snan(a->cls)) { | ||
| 90 | - parts_silence_nan(a, s); | ||
| 91 | - } | ||
| 92 | - return a; | ||
| 93 | + return ret; | ||
| 48 | } | 94 | } |
| 49 | 95 | ||
| 50 | -void device_class_set_parent_reset(DeviceClass *dc, | 96 | static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
| 51 | - DeviceReset dev_reset, | ||
| 52 | - DeviceReset *parent_reset) | ||
| 53 | -{ | ||
| 54 | - *parent_reset = dc->reset; | ||
| 55 | - dc->reset = dev_reset; | ||
| 56 | -} | ||
| 57 | - | ||
| 58 | void device_class_set_parent_realize(DeviceClass *dc, | ||
| 59 | DeviceRealize dev_realize, | ||
| 60 | DeviceRealize *parent_realize) | ||
| 61 | -- | 97 | -- |
| 62 | 2.34.1 | 98 | 2.34.1 |
| 63 | 99 | ||
| 64 | 100 | diff view generated by jsdifflib |
| 1 | From: Francisco Iglesias <francisco.iglesias@amd.com> | 1 | From: Leif Lindholm <quic_llindhol@quicinc.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Update my xilinx.com email address to my amd.com address. | 3 | I'm migrating to Qualcomm's new open source email infrastructure, so |
| 4 | update my email address, and update the mailmap to match. | ||
| 4 | 5 | ||
| 5 | Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com> | 6 | Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com> |
| 6 | Message-id: 20240906181645.40359-3-francisco.iglesias@amd.com | 7 | Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> |
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> |
| 9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 10 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 11 | Message-id: 20241205114047.1125842-1-leif.lindholm@oss.qualcomm.com | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 9 | --- | 13 | --- |
| 10 | MAINTAINERS | 2 +- | 14 | MAINTAINERS | 2 +- |
| 11 | 1 file changed, 1 insertion(+), 1 deletion(-) | 15 | .mailmap | 5 +++-- |
| 16 | 2 files changed, 4 insertions(+), 3 deletions(-) | ||
| 12 | 17 | ||
| 13 | diff --git a/MAINTAINERS b/MAINTAINERS | 18 | diff --git a/MAINTAINERS b/MAINTAINERS |
| 14 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
| 15 | --- a/MAINTAINERS | 20 | --- a/MAINTAINERS |
| 16 | +++ b/MAINTAINERS | 21 | +++ b/MAINTAINERS |
| 17 | @@ -XXX,XX +XXX,XX @@ F: include/hw/display/dpcd.h | 22 | @@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h |
| 18 | F: docs/system/arm/xlnx-versal-virt.rst | 23 | SBSA-REF |
| 19 | 24 | M: Radoslaw Biernacki <rad@semihalf.com> | |
| 20 | Xilinx Versal OSPI | 25 | M: Peter Maydell <peter.maydell@linaro.org> |
| 21 | -M: Francisco Iglesias <francisco.iglesias@xilinx.com> | 26 | -R: Leif Lindholm <quic_llindhol@quicinc.com> |
| 22 | +M: Francisco Iglesias <francisco.iglesias@amd.com> | 27 | +R: Leif Lindholm <leif.lindholm@oss.qualcomm.com> |
| 28 | R: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> | ||
| 29 | L: qemu-arm@nongnu.org | ||
| 23 | S: Maintained | 30 | S: Maintained |
| 24 | F: hw/ssi/xlnx-versal-ospi.c | 31 | diff --git a/.mailmap b/.mailmap |
| 25 | F: include/hw/ssi/xlnx-versal-ospi.h | 32 | index XXXXXXX..XXXXXXX 100644 |
| 33 | --- a/.mailmap | ||
| 34 | +++ b/.mailmap | ||
| 35 | @@ -XXX,XX +XXX,XX @@ Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com> | ||
| 36 | Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn> | ||
| 37 | James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com> | ||
| 38 | Juan Quintela <quintela@trasno.org> <quintela@redhat.com> | ||
| 39 | -Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org> | ||
| 40 | -Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com> | ||
| 41 | +Leif Lindholm <leif.lindholm@oss.qualcomm.com> <quic_llindhol@quicinc.com> | ||
| 42 | +Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif.lindholm@linaro.org> | ||
| 43 | +Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif@nuviainc.com> | ||
| 44 | Luc Michel <luc@lmichel.fr> <luc.michel@git.antfield.fr> | ||
| 45 | Luc Michel <luc@lmichel.fr> <luc.michel@greensocs.com> | ||
| 46 | Luc Michel <luc@lmichel.fr> <lmichel@kalray.eu> | ||
| 26 | -- | 47 | -- |
| 27 | 2.34.1 | 48 | 2.34.1 |
| 49 | |||
| 50 | diff view generated by jsdifflib |
| 1 | From: Francisco Iglesias <francisco.iglesias@amd.com> | 1 | From: Vikram Garhwal <vikram.garhwal@bytedance.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Vikram's email is bouncing, pause his maintainership until a new email is | 3 | Previously, maintainer role was paused due to inactive email id. Commit id: |
| 4 | provided. | 4 | c009d715721861984c4987bcc78b7ee183e86d75. |
| 5 | 5 | ||
| 6 | Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com> | 6 | Signed-off-by: Vikram Garhwal <vikram.garhwal@bytedance.com> |
| 7 | Message-id: 20240906181645.40359-2-francisco.iglesias@amd.com | 7 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> |
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Message-id: 20241204184205.12952-1-vikram.garhwal@bytedance.com |
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | --- | 10 | --- |
| 11 | MAINTAINERS | 2 -- | 11 | MAINTAINERS | 2 ++ |
| 12 | 1 file changed, 2 deletions(-) | 12 | 1 file changed, 2 insertions(+) |
| 13 | 13 | ||
| 14 | diff --git a/MAINTAINERS b/MAINTAINERS | 14 | diff --git a/MAINTAINERS b/MAINTAINERS |
| 15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/MAINTAINERS | 16 | --- a/MAINTAINERS |
| 17 | +++ b/MAINTAINERS | 17 | +++ b/MAINTAINERS |
| 18 | @@ -XXX,XX +XXX,XX @@ F: tests/qtest/intel-hda-test.c | 18 | @@ -XXX,XX +XXX,XX @@ F: tests/qtest/fuzz-sb16-test.c |
| 19 | F: tests/qtest/fuzz-sb16-test.c | ||
| 20 | 19 | ||
| 21 | Xilinx CAN | 20 | Xilinx CAN |
| 22 | -M: Vikram Garhwal <vikram.garhwal@amd.com> | ||
| 23 | M: Francisco Iglesias <francisco.iglesias@amd.com> | 21 | M: Francisco Iglesias <francisco.iglesias@amd.com> |
| 22 | +M: Vikram Garhwal <vikram.garhwal@bytedance.com> | ||
| 24 | S: Maintained | 23 | S: Maintained |
| 25 | F: hw/net/can/xlnx-* | 24 | F: hw/net/can/xlnx-* |
| 25 | F: include/hw/net/xlnx-* | ||
| 26 | @@ -XXX,XX +XXX,XX @@ F: include/hw/rx/ | 26 | @@ -XXX,XX +XXX,XX @@ F: include/hw/rx/ |
| 27 | |||
| 28 | CAN bus subsystem and hardware | 27 | CAN bus subsystem and hardware |
| 29 | M: Pavel Pisa <pisa@cmp.felk.cvut.cz> | 28 | M: Pavel Pisa <pisa@cmp.felk.cvut.cz> |
| 30 | -M: Vikram Garhwal <fnu.vikram@xilinx.com> | 29 | M: Francisco Iglesias <francisco.iglesias@amd.com> |
| 30 | +M: Vikram Garhwal <vikram.garhwal@bytedance.com> | ||
| 31 | S: Maintained | 31 | S: Maintained |
| 32 | W: https://canbus.pages.fel.cvut.cz/ | 32 | W: https://canbus.pages.fel.cvut.cz/ |
| 33 | F: net/can/* | 33 | F: net/can/* |
| 34 | -- | 34 | -- |
| 35 | 2.34.1 | 35 | 2.34.1 | diff view generated by jsdifflib |