On Wed, 11 Sept 2024 at 23:30, Sergey Makarov <s.makarov@syntacore.com> wrote:
>
> *** Patchset goal ***
>
> This patchset aims to improve standard conformance for SiFive PLIC
> implementation.
>
> *** Testing cases ***
>
> Currently there are no automated tests for these changes, but there
> are several test cases, with which these changes may be checked:
> 1. Zeroth priority register can be checked by reading it after
> writing to it. Without patch its value would be the same which
> is written there, but with it it would be zero;
> 2. Trigger call of `sifive_plic_irq_request` with level 0.
> Without second patch it will clear pending bit, but with it
> pending bit won't be cleared.
> If anyone knows how this can be turned into automated test, help
> would be appreciated.
>
> Sergey Makarov (2):
> hw/intc: Make zeroth priority register read-only
> hw/intc: Don't clear pending bits on IRQ lowering
>
> hw/intc/sifive_plic.c | 15 +++++++++++----
> 1 file changed, 11 insertions(+), 4 deletions(-)
When you're writing cover letter and patch subject lines,
please can you make them say what part of the codebase
they're touching? This cover letter doesn't say anything in
the subject line that would tell the reader it's about riscv,
for instance, and nor do the patch line subjects.
This is helpful because people scan subject lines to see
whether the patchset is something they're interested in
or not.
thanks
-- PMM