[v2] target/arm: AdvSIMD decodetree conversion, part 4

[PATCH v2 15/29] target/arm: Fix whitespace near gen_srshr64_i64

Posted by Richard Henderson 2 months, 2 weeks ago

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/tcg/gengvec.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c
index 33c5084ea6..3abdc57202 100644
--- a/target/arm/tcg/gengvec.c
+++ b/target/arm/tcg/gengvec.c
@@ -304,7 +304,7 @@ void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
     tcg_gen_add_i32(d, d, t);
 }
 
- void gen_srshr64_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
+void gen_srshr64_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
 {
     TCGv_i64 t = tcg_temp_new_i64();
 
-- 
2.43.0

Re: [PATCH v2 15/29] target/arm: Fix whitespace near gen_srshr64_i64

Posted by Philippe Mathieu-Daudé 2 months, 2 weeks ago

On 9/9/24 18:22, Richard Henderson wrote:
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/arm/tcg/gengvec.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)

(https://lore.kernel.org/qemu-devel/d86b4c48-dcb0-4651-92c4-8117f9f50543@linaro.org/)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>