On 9/3/24 10:35, Jamin Lin wrote:
> Currently, users can set the INTC mapping table with
> enumerated device id and device irq to get the INTC orgate
> input pins. However, some devices use the continuous source numbers in the
> same INTC orgate. To reduce the enumerated device id definition,
> create a new API to get the INTC orgate input pin
> if users only provide the device id with its bus number index.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> hw/arm/aspeed_ast27x0.c | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 4257b5e8af..a5eb78524f 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -193,6 +193,27 @@ static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev)
> return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]);
> }
>
> +static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev,
> + int index)
> +{
> + Aspeed27x0SoCState *a = ASPEED27X0_SOC(s);
> + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) {
> + if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) {
> + assert(aspeed_soc_ast2700_gic_intcmap[i].ptr);
> + return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]),
> + aspeed_soc_ast2700_gic_intcmap[i].ptr[dev] + index);
> + }
> + }
> +
> + /*
> + * Invalid orgate index, device irq should be 128 to 136.
> + */
> + g_assert_not_reached();
> +}
> +
> static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr,
> unsigned int size)
> {