On 9/3/24 10:35, Jamin Lin wrote:
> Add I2C model for AST2700 I2C support.
> The I2C controller registers base address is start at
> 0x14C0_F000 and its address space is 0x2000.
>
> The AST2700 I2C controller has one source INTC per bus.
> I2C buses interrupt are connected to GICINT130_INTC
> from bit 0 to bit 15.
> I2C bus 0 is connected to GICINT130_INTC at bit 0.
> I2C bus 15 is connected to GICINT130_INTC at bit 15.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> hw/arm/aspeed_ast27x0.c | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index a5eb78524f..761ee11657 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -61,6 +61,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_GIC_DIST] = 0x12200000,
> [ASPEED_GIC_REDIST] = 0x12280000,
> [ASPEED_DEV_ADC] = 0x14C00000,
> + [ASPEED_DEV_I2C] = 0x14C0F000,
> };
>
> #define AST2700_MAX_IRQ 288
> @@ -369,6 +370,9 @@ static void aspeed_soc_ast2700_init(Object *obj)
>
> snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
> object_initialize_child(obj, "adc", &s->adc, typename);
> +
> + snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
> + object_initialize_child(obj, "i2c", &s->i2c, typename);
> }
>
> /*
> @@ -452,6 +456,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc);
> g_autofree char *sram_name = NULL;
> + qemu_irq irq;
>
> /* Default boot region (SPI memory or ROMs) */
> memory_region_init(&s->spi_boot_container, OBJECT(s),
> @@ -634,6 +639,25 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
> aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
>
> + /* I2C */
> + object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
> + &error_abort);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
> + return;
> + }
> + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
> + for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
> + /*
> + * The AST2700 I2C controller has one source INTC per bus.
> + * I2C buses interrupt are connected to GICINT130_INTC
> + * from bit 0 to bit 15.
> + * I2C bus 0 is connected to GICINT130_INTC at bit 0.
> + * I2C bus 15 is connected to GICINT130_INTC at bit 15.
> + */
> + irq = aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
> + }
> +
> create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000);
> create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000);
> create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000);