From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>

This patch set introduces support for the RISC-V vector extension
in TCG backend for RISC-V targets.

v2:
  1. Remove [PATCH v1 03/15] and use a simpler approach with fixed
  constraints at initialization in the backend instead of modifying
  register allocation constraints in tcg.c. See details in 2.

  2. Change the available vector registers, and the constraint registers
  which are defined in "tcg-target-con-str.h", to the minimum for all
  vector instructions; for TCG_TYPE_V256 (vlen=64, lmul=4, omitting v0),
  max 7 registers, and TCG_TYPE_V128/64 also use only 7.

  3. Remove all inline markers; let the compiler decide.

  4. Merge thread variables to use only prev_vtype.

  5. Increase use of whole load/store instructions when bit width ≥ vlen.

  6. Add vmv<nr>r.v to move registers when bit width ≥ vlen.

  7. Configure vtype with separate operation length (vl) and element
  width (SEW); IRs not changing SEW should inherit SEW from the previous IR
  (e.g., load/store/move/dup/dupm, and/or/xor/not). Place set_vec_config
  in the switch.

  8. Change vlen detection to include element width.

  9. Use neg instead of sub in cmp_vec expand.

  10. Complete all expansions in cmp_vec's expand function, not in
  tcg_out_vec_op.

  11. Move some asserts into tcg_out_opc_*.

  12. Remove the check for riscv_vlen >= 64 when enabling vector support. 

  13. Move not_vec to patch 7.

  14. Change OPC_VRSUB_VX to OPC_VRSUB_VI

  15. Move the vsetvli out of the SIGILL probe.

  16. Move the initialization of the riscv_vlen to the cpuinfo_init.

v1:
  https://lists.gnu.org/archive/html/qemu-riscv/2024-08/msg00205.html

Swung0x48 (1):
  tcg/riscv: Add basic support for vector

TANG Tiancheng (13):
  tcg/op-gvec: Fix iteration step in 32-bit operation
  util: Add RISC-V vector extension probe in cpuinfo
  tcg/riscv: Add riscv vset{i}vli support
  tcg/riscv: Implement vector load/store
  tcg/riscv: Implement vector mov/dup{m/i}
  tcg/riscv: Add support for basic vector opcodes
  tcg/riscv: Implement vector cmp ops
  tcg/riscv: Implement vector neg ops
  tcg/riscv: Implement vector sat/mul ops
  tcg/riscv: Implement vector min/max ops
  tcg/riscv: Implement vector shs/v ops
  tcg/riscv: Implement vector roti/v/x shi ops
  tcg/riscv: Enable native vector support for TCG host

 host/include/riscv/host/cpuinfo.h |   2 +
 tcg/riscv/tcg-target-con-set.h    |   9 +
 tcg/riscv/tcg-target-con-str.h    |   2 +
 tcg/riscv/tcg-target.c.inc        | 961 ++++++++++++++++++++++++++++--
 tcg/riscv/tcg-target.h            |  80 ++-
 tcg/riscv/tcg-target.opc.h        |  20 +
 tcg/tcg-op-gvec.c                 |   2 +-
 util/cpuinfo-riscv.c              |  26 +-
 8 files changed, 1032 insertions(+), 70 deletions(-)
 create mode 100644 tcg/riscv/tcg-target.opc.h

-- 
2.43.0