set priv to be PRV_U for qemu-user on riscv. And set default value for
*envcfg CSR.

Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
 linux-user/riscv/cpu_loop.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
index 52c49c2e42..7a68e8717b 100644
--- a/linux-user/riscv/cpu_loop.c
+++ b/linux-user/riscv/cpu_loop.c
@@ -32,6 +32,10 @@ void cpu_loop(CPURISCVState *env)
     int trapnr;
     target_ulong ret;
 
+    env->priv = PRV_U;
+    env->senvcfg = 0;
+    env->menvcfg = 0;
+
     for (;;) {
         cpu_exec_start(cs);
         trapnr = cpu_exec(cs);
-- 
2.44.0

On Wed, Aug 28, 2024 at 9:20 AM Deepak Gupta <debug@rivosinc.com> wrote:
>
> set priv to be PRV_U for qemu-user on riscv. And set default value for
> *envcfg CSR.
>
> Signed-off-by: Deepak Gupta <debug@rivosinc.com>

You can probably just squash this with the previous patch

> ---
>  linux-user/riscv/cpu_loop.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
> index 52c49c2e42..7a68e8717b 100644
> --- a/linux-user/riscv/cpu_loop.c
> +++ b/linux-user/riscv/cpu_loop.c
> @@ -32,6 +32,10 @@ void cpu_loop(CPURISCVState *env)
>      int trapnr;
>      target_ulong ret;
>
> +    env->priv = PRV_U;
> +    env->senvcfg = 0;
> +    env->menvcfg = 0;

I don't think this is the right place.

This should be handled by a CPU reset, which is still called for linux
user mode.

Alistair

> +
>      for (;;) {
>          cpu_exec_start(cs);
>          trapnr = cpu_exec(cs);
> --
> 2.44.0
>
>

On Wed, Aug 28, 2024 at 10:10:44AM +1000, Alistair Francis wrote:
>On Wed, Aug 28, 2024 at 9:20 AM Deepak Gupta <debug@rivosinc.com> wrote:
>>
>> set priv to be PRV_U for qemu-user on riscv. And set default value for
>> *envcfg CSR.
>>
>> Signed-off-by: Deepak Gupta <debug@rivosinc.com>
>
>You can probably just squash this with the previous patch
>

It's just that they are in different directories. One is target/riscv and another
linux-user/riscv. That's why I kept them separate.

>> ---
>>  linux-user/riscv/cpu_loop.c | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
>> index 52c49c2e42..7a68e8717b 100644
>> --- a/linux-user/riscv/cpu_loop.c
>> +++ b/linux-user/riscv/cpu_loop.c
>> @@ -32,6 +32,10 @@ void cpu_loop(CPURISCVState *env)
>>      int trapnr;
>>      target_ulong ret;
>>
>> +    env->priv = PRV_U;
>> +    env->senvcfg = 0;
>> +    env->menvcfg = 0;
>
>I don't think this is the right place.
>
>This should be handled by a CPU reset, which is still called for linux
>user mode.

It is the right place for setting priv to PRV_U?
or you want me to place it elsewhere ?


Sure
for reset values of *envcfg, I can rely on `riscv_cpu_reset_hold`

>
>Alistair
>
>> +
>>      for (;;) {
>>          cpu_exec_start(cs);
>>          trapnr = cpu_exec(cs);
>> --
>> 2.44.0
>>
>>

On 8/28/24 10:16, Deepak Gupta wrote:
>> This should be handled by a CPU reset, which is still called for linux
>> user mode.
> 
> It is the right place for setting priv to PRV_U?
> or you want me to place it elsewhere ?
> 
> 
> Sure
> for reset values of *envcfg, I can rely on `riscv_cpu_reset_hold`

Doing this in reset_hold seems correct to me.

Compare target/arm/cpu.c, arm_cpu_reset_hold:

>     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
>         /* 64 bit CPUs always start in 64 bit mode */
>         env->aarch64 = true;
> #if defined(CONFIG_USER_ONLY)
>         env->pstate = PSTATE_MODE_EL0t;
>         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
>         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
>         /* Enable all PAC keys.  */
>         env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
>                                   SCTLR_EnDA | SCTLR_EnDB);
...

That assignment to pstate is equivalent to "priv = PRV_U", and sctlr_el[] fills roughly 
the same role as [ms]envcfg.


r~