On Tue, Aug 27, 2024 at 1:32 AM Deepak Gupta <debug@rivosinc.com> wrote:
>
> Signed-off-by: Deepak Gupta <debug@rivosinc.com>
> Co-developed-by: Jim Shu <jim.shu@sifive.com>
> Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 18 +++++++++++++++++-
> disas/riscv.h | 2 ++
> 2 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index c8364c2b07..c7c92acef7 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -974,6 +974,7 @@ typedef enum {
> rv_op_amomaxu_h = 943,
> rv_op_amocas_b = 944,
> rv_op_amocas_h = 945,
> + rv_op_lpad = 946,
> } rv_op;
>
> /* register names */
> @@ -2232,6 +2233,7 @@ const rv_opcode_data rvi_opcode_data[] = {
> { "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> { "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> { "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> + { "lpad", rv_codec_lp, rv_fmt_imm, NULL, 0, 0, 0 },
> };
>
> /* CSR names */
> @@ -2925,7 +2927,13 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 7: op = rv_op_andi; break;
> }
> break;
> - case 5: op = rv_op_auipc; break;
> + case 5:
> + op = rv_op_auipc;
> + if (dec->cfg->ext_zicfilp &&
> + (((inst >> 7) & 0b11111) == 0b00000)) {
> + op = rv_op_lpad;
> + }
> + break;
> case 6:
> switch ((inst >> 12) & 0b111) {
> case 0: op = rv_op_addiw; break;
> @@ -4482,6 +4490,11 @@ static uint32_t operand_tbl_index(rv_inst inst)
> return ((inst << 54) >> 56);
> }
>
> +static uint32_t operand_lpl(rv_inst inst)
> +{
> + return inst >> 12;
> +}
> +
> /* decode operands */
>
> static void decode_inst_operands(rv_decode *dec, rv_isa isa)
> @@ -4869,6 +4882,9 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa)
> dec->imm = sextract32(operand_rs2(inst), 0, 5);
> dec->imm1 = operand_imm2(inst);
> break;
> + case rv_codec_lp:
> + dec->imm = operand_lpl(inst);
> + break;
> };
> }
>
> diff --git a/disas/riscv.h b/disas/riscv.h
> index 16a08e4895..1182457aff 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -166,6 +166,7 @@ typedef enum {
> rv_codec_r2_immhl,
> rv_codec_r2_imm2_imm5,
> rv_codec_fli,
> + rv_codec_lp,
> } rv_codec;
>
> /* structures */
> @@ -228,6 +229,7 @@ enum {
> #define rv_fmt_rs1_rs2 "O\t1,2"
> #define rv_fmt_rd_imm "O\t0,i"
> #define rv_fmt_rd_uimm "O\t0,Ui"
> +#define rv_fmt_imm "O\ti"
> #define rv_fmt_rd_offset "O\t0,o"
> #define rv_fmt_rd_uoffset "O\t0,Uo"
> #define rv_fmt_rd_rs1_rs2 "O\t0,1,2"
> --
> 2.44.0
>
>