On Tue, Aug 27, 2024 at 1:31 AM Deepak Gupta <debug@rivosinc.com> wrote:
>
> zicfilp protects forward control flow (if enabled) by enforcing all
> indirect call and jmp must land on a landing pad instruction `lpad`. If
> target of an indirect call or jmp is not `lpad` then cpu/hart must raise
> a sw check exception with tval = 2.
>
> This patch implements the mechanism using TCG. Target architecture branch
> instruction must define the end of a TB. Using this property, during
> translation of branch instruction, TB flag = FCFI_LP_EXPECTED can be set.
> Translation of target TB can check if FCFI_LP_EXPECTED flag is set and a
> flag (fcfi_lp_expected) can be set in DisasContext. If `lpad` gets
> translated, fcfi_lp_expected flag in DisasContext can be cleared. Else
> it'll fault.
>
> Signed-off-by: Deepak Gupta <debug@rivosinc.com>
> Co-developed-by: Jim Shu <jim.shu@sifive.com>
> Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 3 +++
> target/riscv/cpu_bits.h | 3 +++
> target/riscv/cpu_helper.c | 10 ++++++++++
> target/riscv/translate.c | 23 +++++++++++++++++++++++
> 4 files changed, 39 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 11c6513a90..edf540339a 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -606,6 +606,9 @@ FIELD(TB_FLAGS, ITRIGGER, 22, 1)
> FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1)
> FIELD(TB_FLAGS, PRIV, 24, 2)
> FIELD(TB_FLAGS, AXL, 26, 2)
> +/* zicfilp needs a TB flag to track indirect branches */
> +FIELD(TB_FLAGS, FCFI_ENABLED, 28, 1)
> +FIELD(TB_FLAGS, FCFI_LP_EXPECTED, 29, 1)
>
> #ifdef TARGET_RISCV32
> #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index b05ebe6f29..900769ce60 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -685,6 +685,9 @@ typedef enum RISCVException {
> RISCV_EXCP_SEMIHOST = 0x3f,
> } RISCVException;
>
> +/* zicfilp defines lp violation results in sw check with tval = 2*/
> +#define RISCV_EXCP_SW_CHECK_FCFI_TVAL 2
> +
> #define RISCV_EXCP_INT_FLAG 0x80000000
> #define RISCV_EXCP_INT_MASK 0x7fffffff
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 121fef1be6..172c945bf3 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -133,6 +133,16 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
> flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
> }
>
> + if (cpu_get_fcfien(env)) {
> + /*
> + * For Forward CFI, only the expectation of a lpad at
> + * the start of the block is tracked via env->elp. env->elp
> + * is turned on during jalr translation.
> + */
> + flags = FIELD_DP32(flags, TB_FLAGS, FCFI_LP_EXPECTED, env->elp);
> + flags = FIELD_DP32(flags, TB_FLAGS, FCFI_ENABLED, 1);
> + }
> +
> #ifdef CONFIG_USER_ONLY
> fs = EXT_STATUS_DIRTY;
> vs = EXT_STATUS_DIRTY;
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index acba90f170..b5c0511b4b 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -116,6 +116,9 @@ typedef struct DisasContext {
> bool frm_valid;
> bool insn_start_updated;
> const GPtrArray *decoders;
> + /* zicfilp extension. fcfi_enabled, lp expected or not */
> + bool fcfi_enabled;
> + bool fcfi_lp_expected;
> } DisasContext;
>
> static inline bool has_ext(DisasContext *ctx, uint32_t ext)
> @@ -1238,6 +1241,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
> ctx->ztso = cpu->cfg.ext_ztso;
> ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
> + ctx->fcfi_lp_expected = FIELD_EX32(tb_flags, TB_FLAGS, FCFI_LP_EXPECTED);
> + ctx->fcfi_enabled = FIELD_EX32(tb_flags, TB_FLAGS, FCFI_ENABLED);
> ctx->zero = tcg_constant_tl(0);
> ctx->virt_inst_excp = false;
> ctx->decoders = cpu->decoders;
> @@ -1270,6 +1275,24 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
> decode_opc(env, ctx, opcode16);
> ctx->base.pc_next += ctx->cur_insn_len;
>
> + /*
> + * If 'fcfi_lp_expected' is still true after processing the instruction,
> + * then we did not see an 'lpad' instruction, and must raise an exception.
> + * Insert code to raise the exception at the start of the insn; any other
> + * code the insn may have emitted will be deleted as dead code following
> + * the noreturn exception
> + */
> + if (ctx->fcfi_lp_expected) {
> + /* Emit after insn_start, i.e. before the op following insn_start. */
> + tcg_ctx->emit_before_op = QTAILQ_NEXT(ctx->base.insn_start, link);
> + tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL),
> + tcg_env, offsetof(CPURISCVState, sw_check_code));
> + gen_helper_raise_exception(tcg_env,
> + tcg_constant_i32(RISCV_EXCP_SW_CHECK));
> + tcg_ctx->emit_before_op = NULL;
> + ctx->base.is_jmp = DISAS_NORETURN;
> + }
> +
> /* Only the first insn within a TB is allowed to cross a page boundary. */
> if (ctx->base.is_jmp == DISAS_NEXT) {
> if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) {
> --
> 2.44.0
>
>