[v4] RISC-V: Add preliminary textra trigger CSR functions

[PATCH v4 0/2] RISC-V: Add preliminary textra trigger CSR functions

Posted by Alvin Chang via 3 months ago

According to RISC-V Debug specification, the optional textra32 and textra64
trigger CSRs can be used to configure additional matching conditions for the
triggers.

This series support to write MHVALUE and MHSELECT fields into textra32 and
textra64 trigger CSRs. Besides, the additional matching condition between
textra.MHVALUE and mcontext CSR is also implemented.

Changes from v3:
- Simplify the comparison between mcontext and textra.MHVALUE

Changes from v2:
- Remove redundant log

Changes from v1:
- Log that mhselect only supports 0 or 4 for now
- Simplify writing of tdata3

Alvin Chang (2):
  target/riscv: Preliminary textra trigger CSR writting support
  target/riscv: Add textra matching condition for the triggers

 target/riscv/cpu_bits.h |  10 ++++
 target/riscv/debug.c    | 114 +++++++++++++++++++++++++++++++++++++---
 target/riscv/debug.h    |   3 ++
 3 files changed, 120 insertions(+), 7 deletions(-)

-- 
2.34.1

Re: [PATCH v4 0/2] RISC-V: Add preliminary textra trigger CSR functions

Posted by Alistair Francis 2 months, 2 weeks ago

On Mon, Aug 26, 2024 at 12:48 PM Alvin Chang via <qemu-devel@nongnu.org> wrote:
>
> According to RISC-V Debug specification, the optional textra32 and textra64
> trigger CSRs can be used to configure additional matching conditions for the
> triggers.
>
> This series support to write MHVALUE and MHSELECT fields into textra32 and
> textra64 trigger CSRs. Besides, the additional matching condition between
> textra.MHVALUE and mcontext CSR is also implemented.
>
> Changes from v3:
> - Simplify the comparison between mcontext and textra.MHVALUE
>
> Changes from v2:
> - Remove redundant log
>
> Changes from v1:
> - Log that mhselect only supports 0 or 4 for now
> - Simplify writing of tdata3
>
> Alvin Chang (2):
>   target/riscv: Preliminary textra trigger CSR writting support
>   target/riscv: Add textra matching condition for the triggers

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu_bits.h |  10 ++++
>  target/riscv/debug.c    | 114 +++++++++++++++++++++++++++++++++++++---
>  target/riscv/debug.h    |   3 ++
>  3 files changed, 120 insertions(+), 7 deletions(-)
>
> --
> 2.34.1
>
>