v5 for riscv zicfilp and zicfiss extensions support in qemu.
Links for previous versions
[1] - v1 https://lists.nongnu.org/archive/html/qemu-devel/2024-07/msg06017.html
[2] - v2 https://lore.kernel.org/all/ed23bcbc-fdc4-4492-803c-daa95880375a@linaro.org/T/
[3] - v3 https://lists.nongnu.org/archive/html/qemu-devel/2024-08/msg01005.html
[4] - v4 https://lore.kernel.org/all/20240816010711.3055425-6-debug@rivosinc.com/T/
---
v5:
- Simplified elp tracking and lpad implementation as per suggestion by richard
- Simplified shadow stack mmu checks as per suggestion by richard
- Converged zicfiss compressed and non-comressed instructions to same translation
- Removed trace hooks. Don't need for upstream.
v4:
- elp state in cpu is true/false instead of enum and elp cleared
unconditionally on trap entry. elp in *status cleared unconditionally on
trap return.
- Moved logic for branch tracking in instruction translation from tb_start.
- fixed zicfiss dependency on 'A'
- `cpu_get_fcfien/bcfien` helpers checks fixed to check for extension first.
- removed trace hook enums. Instead added dedicated trace helpers wherever needed.
- fixed/simplified instruction format in decoder for lpad, sspush, sspopchk
- simplified tlb index logic for shadow stack instructions. Removed SUM TB_FLAG
- access to ssp CSR is gated on `cpu_get_bcfien` instead of duplicated logic
- removed vDSO related changes for now.
v3:
- Removed prctl specific patches because they need to be upstream
in kernel first.
- As suggested by Richard, added TB flag if fcfi enabled
- Re-worked translation for landing pad and shadow stack instructions
to not require helper.
- tcg helpers only for cfi violation cases so that trace hooks can be
placed.
- Style changes.
- fixes assert condition in accel/tcg
v2:
- added missed file (in v1) for shadow stack instructions implementation.
Deepak Gupta (15):
target/riscv: Add zicfilp extension
target/riscv: Introduce elp state and enabling controls for zicfilp
target/riscv: save and restore elp state on priv transitions
target/riscv: additional code information for sw check
target/riscv: tracking indirect branches (fcfi) for zicfilp
target/riscv: zicfilp `lpad` impl and branch tracking
disas/riscv: enable `lpad` disassembly
target/riscv: Add zicfiss extension
target/riscv: introduce ssp and enabling controls for zicfiss
target/riscv: tb flag for shadow stack instructions
target/riscv: mmu changes for zicfiss shadow stack protection
target/riscv: implement zicfiss instructions
target/riscv: compressed encodings for sspush and sspopchk
disas/riscv: enable disassembly for zicfiss instructions
disas/riscv: enable disassembly for compressed sspush/sspopchk
disas/riscv.c | 77 +++++++++-
disas/riscv.h | 4 +
target/riscv/cpu.c | 17 +++
target/riscv/cpu.h | 15 ++
target/riscv/cpu_bits.h | 17 +++
target/riscv/cpu_cfg.h | 2 +
target/riscv/cpu_helper.c | 140 +++++++++++++++++-
target/riscv/cpu_user.h | 1 +
target/riscv/csr.c | 84 +++++++++++
target/riscv/insn16.decode | 4 +
target/riscv/insn32.decode | 26 +++-
target/riscv/insn_trans/trans_rva.c.inc | 41 +++++
target/riscv/insn_trans/trans_rvi.c.inc | 55 +++++++
target/riscv/insn_trans/trans_rvzicfiss.c.inc | 73 +++++++++
target/riscv/internals.h | 3 +
target/riscv/op_helper.c | 18 +++
target/riscv/pmp.c | 5 +
target/riscv/pmp.h | 3 +-
target/riscv/tcg/tcg-cpu.c | 24 +++
target/riscv/translate.c | 30 +++-
20 files changed, 625 insertions(+), 14 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvzicfiss.c.inc
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2.44.0