The following changes since commit 4c395ac42e55ff8e9fd4c992e351a04b10785503:

Merge tag 'pull-tcg-20240808' of https://gitlab.com/rth7680/qemu into staging (2024-08-08 09:07:00 +1000)

https://github.com/quic/qemu tags/pull-hex-20240807

for you to fetch changes up to 47f3361a3af9d709218038a23b8907525310d2c3:

target/hexagon: switch to dc set_props() list (2024-08-07 20:37:21 -0700)

Hexagon updates: lldb preds, v66 CPU, F2_conv* fix

Anton Johansson (1):

target/hexagon/idef-parser: Remove self-assignment

Brian Cain (3):

MAINTAINERS: Add my hexagon git tree

target/hexagon: define a v66 CPU

target/hexagon: switch to dc set_props() list

Matheus Tavares Bernardino (1):

Hexagon: fix F2_conv_* instructions for negative zero

Hexagon: lldb read/write predicate registers p0/p1/p2/p3

MAINTAINERS | 1 +

gdb-xml/hexagon-core.xml | 6 +++++-

target/hexagon/cpu-qom.h | 1 +

target/hexagon/cpu.c | 20 ++++++++++----------

target/hexagon/gdbstub.c | 19 ++++++++++++++++++-

target/hexagon/idef-parser/idef-parser.y | 1 -

target/hexagon/op_helper.c | 18 +++++++++---------

tests/tcg/hexagon/usr.c | 12 +++++++++++-

8 files changed, 55 insertions(+), 23 deletions(-)

From: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>

The implementation for these instructions handles -0 as an invalid float

point value, whereas the Hexagon hardware considers it the same as +0

(which is valid). Let's fix that and add a regression test.

Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>

Reviewed-by: Brian Cain <bcain@quicinc.com>

Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>

Signed-off-by: Brian Cain <bcain@quicinc.com>

target/hexagon/op_helper.c | 18 +++++++++---------

tests/tcg/hexagon/usr.c | 12 +++++++++++-

2 files changed, 20 insertions(+), 10 deletions(-)

@@ -XXX,XX +XXX,XX @@

/*

- * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.

+ * Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights Reserved.

*

* This program is free software; you can redistribute it and/or modify

* it under the terms of the GNU General Public License as published by

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(conv_sf2uw)(CPUHexagonState *env, float32 RsV)

uint32_t RdV;

arch_fpop_start(env);

/* Hexagon checks the sign before rounding */

- if (float32_is_neg(RsV) && !float32_is_any_nan(RsV)) {

+ if (float32_is_neg(RsV) && !float32_is_any_nan(RsV) && !float32_is_zero(RsV)) {

float_raise(float_flag_invalid, &env->fp_status);

RdV = 0;

} else {

@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(conv_sf2ud)(CPUHexagonState *env, float32 RsV)

uint64_t RddV;

arch_fpop_start(env);

/* Hexagon checks the sign before rounding */

- if (float32_is_neg(RsV) && !float32_is_any_nan(RsV)) {

+ if (float32_is_neg(RsV) && !float32_is_any_nan(RsV) && !float32_is_zero(RsV)) {

float_raise(float_flag_invalid, &env->fp_status);

RddV = 0;

} else {

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(conv_df2uw)(CPUHexagonState *env, float64 RssV)

uint32_t RdV;

arch_fpop_start(env);

/* Hexagon checks the sign before rounding */

- if (float64_is_neg(RssV) && !float64_is_any_nan(RssV)) {

+ if (float64_is_neg(RssV) && !float64_is_any_nan(RssV) && !float64_is_zero(RssV)) {

float_raise(float_flag_invalid, &env->fp_status);

RdV = 0;

} else {

@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(conv_df2ud)(CPUHexagonState *env, float64 RssV)

uint64_t RddV;

arch_fpop_start(env);

/* Hexagon checks the sign before rounding */

- if (float64_is_neg(RssV) && !float64_is_any_nan(RssV)) {

+ if (float64_is_neg(RssV) && !float64_is_any_nan(RssV) && !float64_is_zero(RssV)) {

float_raise(float_flag_invalid, &env->fp_status);

RddV = 0;

} else {

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(conv_sf2uw_chop)(CPUHexagonState *env, float32 RsV)

uint32_t RdV;

arch_fpop_start(env);

/* Hexagon checks the sign before rounding */

- if (float32_is_neg(RsV) && !float32_is_any_nan(RsV)) {

+ if (float32_is_neg(RsV) && !float32_is_any_nan(RsV) && !float32_is_zero(RsV)) {

float_raise(float_flag_invalid, &env->fp_status);

RdV = 0;

} else {

@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(conv_sf2ud_chop)(CPUHexagonState *env, float32 RsV)

uint64_t RddV;

arch_fpop_start(env);

/* Hexagon checks the sign before rounding */

- if (float32_is_neg(RsV) && !float32_is_any_nan(RsV)) {

+ if (float32_is_neg(RsV) && !float32_is_any_nan(RsV) && !float32_is_zero(RsV)) {

float_raise(float_flag_invalid, &env->fp_status);

RddV = 0;

} else {

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(conv_df2uw_chop)(CPUHexagonState *env, float64 RssV)

uint32_t RdV;

arch_fpop_start(env);

/* Hexagon checks the sign before rounding */

- if (float64_is_neg(RssV) && !float64_is_any_nan(RssV)) {

+ if (float64_is_neg(RssV) && !float64_is_any_nan(RssV) && !float64_is_zero(RssV)) {

float_raise(float_flag_invalid, &env->fp_status);

RdV = 0;

} else {

@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(conv_df2ud_chop)(CPUHexagonState *env, float64 RssV)

uint64_t RddV;

arch_fpop_start(env);

/* Hexagon checks the sign before rounding */

- if (float64_is_neg(RssV) && !float64_is_any_nan(RssV)) {

+ if (float64_is_neg(RssV) && !float64_is_any_nan(RssV) && !float64_is_zero(RssV)) {

float_raise(float_flag_invalid, &env->fp_status);

RddV = 0;

} else {

diff --git a/tests/tcg/hexagon/usr.c b/tests/tcg/hexagon/usr.c

index XXXXXXX..XXXXXXX 100644

--- a/tests/tcg/hexagon/usr.c

+++ b/tests/tcg/hexagon/usr.c

@@ -XXX,XX +XXX,XX @@

/*

- * Copyright(c) 2022-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.

+ * Copyright(c) 2022-2024 Qualcomm Innovation Center, Inc. All Rights Reserved.

*

* This program is free software; you can redistribute it and/or modify

* it under the terms of the GNU General Public License as published by

@@ -XXX,XX +XXX,XX @@ int main()

TEST_P_OP_R(conv_sf2d_chop, SF_QNaN, 0xffffffffffffffffULL, USR_FPINVF);

TEST_P_OP_R(conv_sf2d_chop, SF_SNaN, 0xffffffffffffffffULL, USR_FPINVF);

+ TEST_R_OP_R(conv_sf2uw, SF_zero_neg, 0, USR_CLEAR);

+ TEST_R_OP_R(conv_sf2uw_chop, SF_zero_neg, 0, USR_CLEAR);

+ TEST_P_OP_R(conv_sf2ud, SF_zero_neg, 0, USR_CLEAR);

+ TEST_P_OP_R(conv_sf2ud_chop, SF_zero_neg, 0, USR_CLEAR);

+

TEST_R_OP_P(conv_df2sf, DF_QNaN, SF_HEX_NaN, USR_CLEAR);

TEST_R_OP_P(conv_df2sf, DF_SNaN, SF_HEX_NaN, USR_FPINVF);

TEST_R_OP_P(conv_df2uw, DF_QNaN, 0xffffffff, USR_FPINVF);

@@ -XXX,XX +XXX,XX @@ int main()

TEST_R_OP_P(conv_df2uw_chop, DF_QNaN, 0xffffffff, USR_FPINVF);

TEST_R_OP_P(conv_df2uw_chop, DF_SNaN, 0xffffffff, USR_FPINVF);

+ TEST_R_OP_P(conv_df2uw, DF_zero_neg, 0, USR_CLEAR);

+ TEST_R_OP_P(conv_df2uw_chop, DF_zero_neg, 0, USR_CLEAR);

+ TEST_P_OP_P(conv_df2ud, DF_zero_neg, 0, USR_CLEAR);

+ TEST_P_OP_P(conv_df2ud_chop, DF_zero_neg, 0, USR_CLEAR);

+

/* Test for typo in HELPER(conv_df2uw_chop) */

TEST_R_OP_P(conv_df2uw_chop, 0xffffff7f00000001ULL, 0xffffffff, USR_FPINVF);

From: Taylor Simpson <ltaylorsimpson@gmail.com>

hexagon-core.xml only exposes register p3_0 which is an alias that

aggregates the predicate registers. It is more convenient for users

to interact directly with the predicate registers.

Tested with lldb downloaded from this location

https://github.com/llvm/llvm-project/releases/download/llvmorg-18.1.4/clang+llvm-18.1.4-x86_64-linux-gnu-ubuntu-18.04.tar.xz

BEFORE:

(lldb) reg read p3_0

p3_0 = 0x00000000

(lldb) reg read p0

error: Invalid register name 'p0'.

(lldb) reg write p1 0xf

error: Register not found for 'p1'.

AFTER:

(lldb) reg read p3_0

p3_0 = 0x00000000

(lldb) reg read p0

p0 = 0x00

(lldb) reg read -s 1

Predicate Registers:

p0 = 0x00

p1 = 0x00

p2 = 0x00

p3 = 0x00

(lldb) reg write p1 0xf

(lldb) reg read p3_0

p3_0 = 0x00000f00

(lldb) reg write p3_0 0xff00ff00

(lldb) reg read -s 1

Predicate Registers:

p0 = 0x00

p1 = 0xff

p2 = 0x00

p3 = 0xff

Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>

Reviewed-by: Brian Cain <bcain@quicinc.com>

Reviewed-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>

Message-Id: <20240613182209.140082-1-ltaylorsimpson@gmail.com>

Signed-off-by: Brian Cain <bcain@quicinc.com>

---

gdb-xml/hexagon-core.xml | 6 +++++-

target/hexagon/gdbstub.c | 19 ++++++++++++++++++-

2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/gdb-xml/hexagon-core.xml b/gdb-xml/hexagon-core.xml

--- a/gdb-xml/hexagon-core.xml

+++ b/gdb-xml/hexagon-core.xml

<?xml version="1.0"?>

<!--

- Copyright(c) 2023 Qualcomm Innovation Center, Inc. All Rights Reserved.

+ Copyright(c) 2023-2024 Qualcomm Innovation Center, Inc. All Rights Reserved.

This work is licensed under the terms of the GNU GPL, version 2 or

(at your option) any later version. See the COPYING file in the

<reg name="c29" bitsize="32" offset="244" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="61"/>

<reg name="utimerlo" bitsize="32" offset="248" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="62"/>

<reg name="utimerhi" bitsize="32" offset="252" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="63"/>

+ <reg name="p0" bitsize="8" offset="256" encoding="uint" format="hex" group="Predicate Registers" dwarf_regnum="64"/>

+ <reg name="p1" bitsize="8" offset="257" encoding="uint" format="hex" group="Predicate Registers" dwarf_regnum="65"/>

+ <reg name="p2" bitsize="8" offset="258" encoding="uint" format="hex" group="Predicate Registers" dwarf_regnum="66"/>

+ <reg name="p3" bitsize="8" offset="259" encoding="uint" format="hex" group="Predicate Registers" dwarf_regnum="67"/>

</feature>

diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c

--- a/target/hexagon/gdbstub.c

+++ b/target/hexagon/gdbstub.c

@@ -XXX,XX +XXX,XX @@

/*

- * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.

+ * Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights Reserved.

*

* This program is free software; you can redistribute it and/or modify

* it under the terms of the GNU General Public License as published by

@@ -XXX,XX +XXX,XX @@ int hexagon_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)

return gdb_get_regl(mem_buf, env->gpr[n]);

@@ -XXX,XX +XXX,XX @@ int hexagon_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)

return sizeof(target_ulong);

+ n -= TOTAL_PER_THREAD_REGS;

+

+ if (n < NUM_PREGS) {

+ env->pred[n] = ldtul_p(mem_buf) & 0xff;

+ return sizeof(uint8_t);

+ }

+

+ n -= NUM_PREGS;

+

g_assert_not_reached();

Define a hexagon_cpu_properties list to match the idiom used

by other targets.

target/hexagon/cpu.c | 18 ++++++++----------

1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c

--- a/target/hexagon/cpu.c

+++ b/target/hexagon/cpu.c

@@ -XXX,XX +XXX,XX @@ static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model)

return oc;

}

-static Property hexagon_lldb_compat_property =

- DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false);

-static Property hexagon_lldb_stack_adjust_property =

- DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust,

- 0, qdev_prop_uint32, target_ulong);

-static Property hexagon_short_circuit_property =

- DEFINE_PROP_BOOL("short-circuit", HexagonCPU, short_circuit, true);

+static Property hexagon_cpu_properties[] = {

+ DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false),

+ DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust, 0,

+ qdev_prop_uint32, target_ulong),

+ DEFINE_PROP_BOOL("short-circuit", HexagonCPU, short_circuit, true),

+ DEFINE_PROP_END_OF_LIST()

const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {

"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",

@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp)

static void hexagon_cpu_init(Object *obj)

{

- qdev_property_add_static(DEVICE(obj), &hexagon_lldb_compat_property);

- qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_property);

- qdev_property_add_static(DEVICE(obj), &hexagon_short_circuit_property);

}

#include "hw/core/tcg-cpu-ops.h"

@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data)

device_class_set_parent_realize(dc, hexagon_cpu_realize,

&mcc->parent_realize);

+ device_class_set_props(dc, hexagon_cpu_properties);

resettable_class_set_parent_phases(rc, NULL, hexagon_cpu_reset_hold, NULL,

&mcc->parent_phases);

For now, v66 behavior is the same as other CPUs.

Signed-off-by: Brian Cain <bcain@quicinc.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>

target/hexagon/cpu-qom.h | 1 +

target/hexagon/cpu.c | 2 ++

2 files changed, 3 insertions(+)

diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h

--- a/target/hexagon/cpu-qom.h

+++ b/target/hexagon/cpu-qom.h

@@ -XXX,XX +XXX,XX @@

#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU

#define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX)

+#define TYPE_HEXAGON_CPU_V66 HEXAGON_CPU_TYPE_NAME("v66")

#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67")

#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68")

#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69")

diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c

--- a/target/hexagon/cpu.c

+++ b/target/hexagon/cpu.c

@@ -XXX,XX +XXX,XX @@

#include "tcg/tcg.h"

#include "exec/gdbstub.h"

+static void hexagon_v66_cpu_init(Object *obj) { }

static void hexagon_v67_cpu_init(Object *obj) { }

static void hexagon_v68_cpu_init(Object *obj) { }

static void hexagon_v69_cpu_init(Object *obj) { }

@@ -XXX,XX +XXX,XX @@ static const TypeInfo hexagon_cpu_type_infos[] = {

.class_size = sizeof(HexagonCPUClass),

.class_init = hexagon_cpu_class_init,

},

+ DEFINE_CPU(TYPE_HEXAGON_CPU_V66, hexagon_v66_cpu_init),

DEFINE_CPU(TYPE_HEXAGON_CPU_V67, hexagon_v67_cpu_init),

DEFINE_CPU(TYPE_HEXAGON_CPU_V68, hexagon_v68_cpu_init),

DEFINE_CPU(TYPE_HEXAGON_CPU_V69, hexagon_v69_cpu_init),

The self assignment is clearly useless, and @1.last_column does not have

to be set for an expression with only a single token, so remove it.

Reviewed-by: Brian Cain <bcain@quicinc.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Message-Id: <20230713120853.27023-1-anjo@rev.ng>

Signed-off-by: Brian Cain <bcain@quicinc.com>

target/hexagon/idef-parser/idef-parser.y | 1 -

1 file changed, 1 deletion(-)

diff --git a/target/hexagon/idef-parser/idef-parser.y b/target/hexagon/idef-parser/idef-parser.y

--- a/target/hexagon/idef-parser/idef-parser.y

+++ b/target/hexagon/idef-parser/idef-parser.y

@@ -XXX,XX +XXX,XX @@ rvalue : FAIL

lvalue : FAIL

{

- @1.last_column = @1.last_column;

yyassert(c, &@1, false, "Encountered a FAIL token as lvalue.\n");

}

| REG