On 8/1/24 22:30, Michael Kowal wrote:
> From: Frederic Barrat <fbarrat@linux.ibm.com>
>
> The 'PGoFirst' field of a Notify Virtual Processor tells if the NVP
> belongs to a VP group.
>
> Also, print the Reporting Cache Line address, if defined.
>
> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
> Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
> ---
> include/hw/ppc/xive2_regs.h | 1 +
> hw/intc/xive2.c | 10 ++++++++--
> 2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h
> index 7acf7dccf3..d71a54f9ff 100644
> --- a/include/hw/ppc/xive2_regs.h
> +++ b/include/hw/ppc/xive2_regs.h
> @@ -151,6 +151,7 @@ typedef struct Xive2Nvp {
> #define NVP2_W0_VALID PPC_BIT32(0)
> #define NVP2_W0_HW PPC_BIT32(7)
> #define NVP2_W0_ESC_END PPC_BIT32(25) /* 'N' bit 0:ESB 1:END */
> +#define NVP2_W0_PGOFIRST PPC_BITMASK32(26, 31)
> uint32_t w1;
> #define NVP2_W1_CO PPC_BIT32(13)
> #define NVP2_W1_CO_PRIV PPC_BITMASK32(14, 15)
> diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
> index dd3ae102fb..034baabf1e 100644
> --- a/hw/intc/xive2.c
> +++ b/hw/intc/xive2.c
> @@ -161,14 +161,20 @@ void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, GString *buf)
> {
> uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5);
> uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5);
> + uint64_t cache_line = xive2_nvp_reporting_addr(nvp);
>
> if (!xive2_nvp_is_valid(nvp)) {
> return;
> }
>
> - g_string_append_printf(buf, " %08x end:%02x/%04x IPB:%02x",
> + g_string_append_printf(buf, " %08x end:%02x/%04x IPB:%02x PGoFirst:%02x",
> nvp_idx, eq_blk, eq_idx,
> - xive_get_field32(NVP2_W2_IPB, nvp->w2));
> + xive_get_field32(NVP2_W2_IPB, nvp->w2),
> + xive_get_field32(NVP2_W0_PGOFIRST, nvp->w0));
> + if (cache_line) {
> + g_string_append_printf(buf, " CL:%016lx", cache_line);
Please use PRIx64.
Thanks,
C.
> + }
> +
> /*
> * When the NVP is HW controlled, more fields are updated
> */