On 8/1/24 22:30, Michael Kowal wrote:
> From: Glenn Miles <milesg@linux.vnet.ibm.com>
>
> PHYP uses 8-byte writes to the 2nd doubleword of the OS context
> line when dispatching an OS level virtual processor. This
> support was not used by OPAL/Linux and so was never added.
>
> Without this support, the XIVE code doesn't notice that a new
> context is being pushed and fails to check for unpresented
> pending interrupts for that context.
>
> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
> Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> hw/intc/xive.c | 2 ++
> hw/intc/xive2.c | 24 +++++++++++++++++++-----
> 2 files changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index d951aac3a0..99c8bea598 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -596,6 +596,8 @@ static const XiveTmOp xive2_tm_operations[] = {
> NULL },
> { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive2_tm_push_os_ctx,
> NULL },
> + { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 8, xive2_tm_push_os_ctx,
> + NULL },
> { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_LGS, 1, xive_tm_set_os_lgs,
> NULL },
> { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr,
> diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
> index af9699ec88..76f2f36973 100644
> --- a/hw/intc/xive2.c
> +++ b/hw/intc/xive2.c
> @@ -612,17 +612,31 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx,
> void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
> hwaddr offset, uint64_t value, unsigned size)
> {
> - uint32_t cam = value;
> - uint32_t qw1w2 = cpu_to_be32(cam);
> + uint32_t cam;
> + uint32_t qw1w2;
> + uint64_t qw1dw1;
> uint8_t nvp_blk;
> uint32_t nvp_idx;
> bool vo;
> bool do_restore;
>
> - xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore);
> -
> /* First update the thead context */
> - memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
> + switch (size) {
> + case 4:
> + cam = value;
> + qw1w2 = cpu_to_be32(cam);
> + memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
> + break;
> + case 8:
> + cam = value >> 32;
> + qw1dw1 = cpu_to_be64(value);
> + memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1dw1, 8);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> +
> + xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore);
>
> /* Check the interrupt pending bits */
> if (vo) {