hw/arm/mps2-tz.c: fix RX/TX interrupts order

[PATCH] hw/arm/mps2-tz.c: fix RX/TX interrupts order

Posted by marco@palumbi.it 3 months, 3 weeks ago

From: Marco Palumbi <Marco.Palumbi@tii.ae>

The order of the RX and TX interrupts are swapped.
This commit fixes the order as per the following documents:
 * https://developer.arm.com/documentation/dai0505/latest/
 * https://developer.arm.com/documentation/dai0521/latest/
 * https://developer.arm.com/documentation/dai0524/latest/
 * https://developer.arm.com/documentation/dai0547/latest/

Signed-off-by: Marco Palumbi <Marco.Palumbi@tii.ae>
---
 hw/arm/mps2-tz.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index a2d18afd79..aec57c0d68 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -435,7 +435,7 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
                                const char *name, hwaddr size,
                                const int *irqs, const PPCExtraData *extradata)
 {
-    /* The irq[] array is tx, rx, combined, in that order */
+    /* The irq[] array is rx, tx, combined, in that order */
     MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
     CMSDKAPBUART *uart = opaque;
     int i = uart - &mms->uart[0];
@@ -447,8 +447,8 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
     qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->apb_periph_frq);
     sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal);
     s = SYS_BUS_DEVICE(uart);
-    sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0]));
-    sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1]));
+    sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[1]));
+    sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[0]));
     sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2));
     sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1));
     sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqs[2]));
-- 
2.43.0

Re: [PATCH] hw/arm/mps2-tz.c: fix RX/TX interrupts order

Posted by Peter Maydell 3 months, 3 weeks ago

On Tue, 30 Jul 2024 at 08:32, <marco@palumbi.it> wrote:
>
> From: Marco Palumbi <Marco.Palumbi@tii.ae>
>
> The order of the RX and TX interrupts are swapped.
> This commit fixes the order as per the following documents:
>  * https://developer.arm.com/documentation/dai0505/latest/
>  * https://developer.arm.com/documentation/dai0521/latest/
>  * https://developer.arm.com/documentation/dai0524/latest/
>  * https://developer.arm.com/documentation/dai0547/latest/
>
> Signed-off-by: Marco Palumbi <Marco.Palumbi@tii.ae>

Thanks for this patch, I've applied it to my target-arm.next
queue.

I checked the other boards that use the cmsdk UART, and they
all get the tx/rx interrupt order right, so this is the
only place that needed fixing. I suspect that the guest
images I tested didn't care about the separate tx/rx
interrupts and only used the combined irq.

thanks
-- PMM

RE: [PATCH] hw/arm/mps2-tz.c: fix RX/TX interrupts order

Posted by Marco Palumbi 3 months, 3 weeks ago

Thanks Peter for your time!


Marco Palumbi
Senior Cryptography Engineer

PO Box: 9639
Masdar City, Abu Dhabi, UAE

M: +39 349 786 0737
E: marco.palumbi@tii.ae 

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-----Original Message-----
From: Peter Maydell <peter.maydell@linaro.org> 
Sent: Wednesday, July 31, 2024 1:38 PM
To: marco@palumbi.it
Cc: qemu-devel@nongnu.org; Marco Palumbi <Marco.Palumbi@tii.ae>; qemu-arm@nongnu.org; qemu-stable@nongnu.org; qemu-trivial@nongnu.org
Subject: Re: [PATCH] hw/arm/mps2-tz.c: fix RX/TX interrupts order

On Tue, 30 Jul 2024 at 08:32, <marco@palumbi.it> wrote:
>
> From: Marco Palumbi <Marco.Palumbi@tii.ae>
>
> The order of the RX and TX interrupts are swapped.
> This commit fixes the order as per the following documents:
>  * 
> https://are01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fprot
> ect.checkpoint.com%2Fv2%2F___https%3A%2F%2Fdeveloper.arm.com%2Fdocumen
> tation%2Fdai0505%2Flatest%2F___.bWVjMTp0ZWNobm9sb2d5aW5ub3ZhdGlvbmluc3
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>  * 
> https://are01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fprot
> ect.checkpoint.com%2Fv2%2F___https%3A%2F%2Fdeveloper.arm.com%2Fdocumen
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> i46Gm%2BgBzQIOB6nOqL16P3Deblg3OcRw%3D&reserved=0
>  * 
> https://are01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fprot
> ect.checkpoint.com%2Fv2%2F___https%3A%2F%2Fdeveloper.arm.com%2Fdocumen
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> 638580227306425926%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjo
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>  * 
> https://are01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fprot
> ect.checkpoint.com%2Fv2%2F___https%3A%2F%2Fdeveloper.arm.com%2Fdocumen
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> 0q4VhuPmflWyFLCtMTjg6DWe3j9h381w%3D&reserved=0
>
> Signed-off-by: Marco Palumbi <Marco.Palumbi@tii.ae>

Thanks for this patch, I've applied it to my target-arm.next queue.

I checked the other boards that use the cmsdk UART, and they all get the tx/rx interrupt order right, so this is the only place that needed fixing. I suspect that the guest images I tested didn't care about the separate tx/rx interrupts and only used the combined irq.

thanks
-- PMM