On Thu, Jul 25, 2024 at 3:56 AM Thomas Huth <thuth@redhat.com> wrote:
>
> The avocado test defined test functions for both, riscv32 and riscv64.
> Since we can run the whole file with multiple targets in the new
> framework, we can now consolidate the functions so we have to only
> define one function per machine now.
>
> Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tests/avocado/riscv_opensbi.py | 63 --------------------------
> tests/functional/meson.build | 8 ++++
> tests/functional/test_riscv_opensbi.py | 36 +++++++++++++++
> 3 files changed, 44 insertions(+), 63 deletions(-)
> delete mode 100644 tests/avocado/riscv_opensbi.py
> create mode 100755 tests/functional/test_riscv_opensbi.py
>
> diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py
> deleted file mode 100644
> index bfff9cc3c3..0000000000
> --- a/tests/avocado/riscv_opensbi.py
> +++ /dev/null
> @@ -1,63 +0,0 @@
> -# OpenSBI boot test for RISC-V machines
> -#
> -# Copyright (c) 2022, Ventana Micro
> -#
> -# This work is licensed under the terms of the GNU GPL, version 2 or
> -# later. See the COPYING file in the top-level directory.
> -
> -from avocado_qemu import QemuSystemTest
> -from avocado_qemu import wait_for_console_pattern
> -
> -class RiscvOpenSBI(QemuSystemTest):
> - """
> - :avocado: tags=accel:tcg
> - """
> - timeout = 5
> -
> - def boot_opensbi(self):
> - self.vm.set_console()
> - self.vm.launch()
> - wait_for_console_pattern(self, 'Platform Name')
> - wait_for_console_pattern(self, 'Boot HART MEDELEG')
> -
> - def test_riscv32_spike(self):
> - """
> - :avocado: tags=arch:riscv32
> - :avocado: tags=machine:spike
> - """
> - self.boot_opensbi()
> -
> - def test_riscv64_spike(self):
> - """
> - :avocado: tags=arch:riscv64
> - :avocado: tags=machine:spike
> - """
> - self.boot_opensbi()
> -
> - def test_riscv32_sifive_u(self):
> - """
> - :avocado: tags=arch:riscv32
> - :avocado: tags=machine:sifive_u
> - """
> - self.boot_opensbi()
> -
> - def test_riscv64_sifive_u(self):
> - """
> - :avocado: tags=arch:riscv64
> - :avocado: tags=machine:sifive_u
> - """
> - self.boot_opensbi()
> -
> - def test_riscv32_virt(self):
> - """
> - :avocado: tags=arch:riscv32
> - :avocado: tags=machine:virt
> - """
> - self.boot_opensbi()
> -
> - def test_riscv64_virt(self):
> - """
> - :avocado: tags=arch:riscv64
> - :avocado: tags=machine:virt
> - """
> - self.boot_opensbi()
> diff --git a/tests/functional/meson.build b/tests/functional/meson.build
> index a2c0398b03..ebc6e2d1c6 100644
> --- a/tests/functional/meson.build
> +++ b/tests/functional/meson.build
> @@ -55,6 +55,14 @@ tests_ppc_thorough = [
> 'ppc_bamboo',
> ]
>
> +tests_riscv32_quick = [
> + 'riscv_opensbi',
> +]
> +
> +tests_riscv64_quick = [
> + 'riscv_opensbi',
> +]
> +
> tests_s390x_thorough = [
> 's390x_ccw_virtio',
> 's390x_topology',
> diff --git a/tests/functional/test_riscv_opensbi.py b/tests/functional/test_riscv_opensbi.py
> new file mode 100755
> index 0000000000..d077e40f42
> --- /dev/null
> +++ b/tests/functional/test_riscv_opensbi.py
> @@ -0,0 +1,36 @@
> +#!/usr/bin/env python3
> +#
> +# OpenSBI boot test for RISC-V machines
> +#
> +# Copyright (c) 2022, Ventana Micro
> +#
> +# This work is licensed under the terms of the GNU GPL, version 2 or
> +# later. See the COPYING file in the top-level directory.
> +
> +from qemu_test import QemuSystemTest
> +from qemu_test import wait_for_console_pattern
> +
> +class RiscvOpenSBI(QemuSystemTest):
> +
> + timeout = 5
> +
> + def boot_opensbi(self):
> + self.vm.set_console()
> + self.vm.launch()
> + wait_for_console_pattern(self, 'Platform Name')
> + wait_for_console_pattern(self, 'Boot HART MEDELEG')
> +
> + def test_riscv_spike(self):
> + self.set_machine('spike')
> + self.boot_opensbi()
> +
> + def test_riscv_sifive_u(self):
> + self.set_machine('sifive_u')
> + self.boot_opensbi()
> +
> + def test_riscv_virt(self):
> + self.set_machine('virt')
> + self.boot_opensbi()
> +
> +if __name__ == '__main__':
> + QemuSystemTest.main()
> --
> 2.45.2
>
>