From: Kaiwen Xue <kaiwenx@rivosinc.com>
This adds the properties for sxcsrind. Definitions of new registers and
implementations will come with future patches.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a90808a3bace..ebc19090b40d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -183,12 +183,14 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
+ ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_12_0, ext_smcsrind),
ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11),
ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
+ ISA_EXT_DATA_ENTRY(sscsrind, PRIV_VERSION_1_12_0, ext_sscsrind),
ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 8b272fb826ef..b8a5174bc871 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -77,6 +77,8 @@ struct RISCVCPUConfig {
bool ext_smstateen;
bool ext_sstc;
bool ext_smcntrpmf;
+ bool ext_smcsrind;
+ bool ext_sscsrind;
bool ext_svadu;
bool ext_svinval;
bool ext_svnapot;
--
2.34.1
On Wed, Jul 24, 2024 at 9:31 AM Atish Patra <atishp@rivosinc.com> wrote: > > From: Kaiwen Xue <kaiwenx@rivosinc.com> > > This adds the properties for sxcsrind. Definitions of new registers and > implementations will come with future patches. > > Signed-off-by: Atish Patra <atishp@rivosinc.com> > Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> > --- > target/riscv/cpu.c | 2 ++ > target/riscv/cpu_cfg.h | 2 ++ > 2 files changed, 4 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index a90808a3bace..ebc19090b40d 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -183,12 +183,14 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), > ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), > + ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_12_0, ext_smcsrind), This is actually part of the unpriv spec, so it's a bit weird that it depends on the priv spec. But that's how it's all set up. But shouldn't this be PRIV_VERSION_1_13_0? Alistair
On Fri, Jul 26, 2024 at 12:42 AM Alistair Francis <alistair23@gmail.com> wrote: > > On Wed, Jul 24, 2024 at 9:31 AM Atish Patra <atishp@rivosinc.com> wrote: > > > > From: Kaiwen Xue <kaiwenx@rivosinc.com> > > > > This adds the properties for sxcsrind. Definitions of new registers and > > implementations will come with future patches. > > > > Signed-off-by: Atish Patra <atishp@rivosinc.com> > > Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> > > --- > > target/riscv/cpu.c | 2 ++ > > target/riscv/cpu_cfg.h | 2 ++ > > 2 files changed, 4 insertions(+) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index a90808a3bace..ebc19090b40d 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -183,12 +183,14 @@ const RISCVIsaExtData isa_edata_arr[] = { > > ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), > > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), > > ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), > > + ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_12_0, ext_smcsrind), > > This is actually part of the unpriv spec, so it's a bit weird that it > depends on the priv spec. But that's how it's all set up. > Smcsrind is part of priv spec[1]. Am I missing something ? https://drive.google.com/file/d/17GeetSnT5wW3xNuAHI95-SI1gPGd5sJ_/view > But shouldn't this be PRIV_VERSION_1_13_0? > Yes. Sorry I forgot about that. smcntrpmf should also be PRIV_VERSION_1_13_0. I will send a fix patch along with the v2 for assert fix. > Alistair
On Sat, Jul 27, 2024 at 11:33 AM Atish Kumar Patra <atishp@rivosinc.com> wrote: > > On Fri, Jul 26, 2024 at 12:42 AM Alistair Francis <alistair23@gmail.com> wrote: > > > > On Wed, Jul 24, 2024 at 9:31 AM Atish Patra <atishp@rivosinc.com> wrote: > > > > > > From: Kaiwen Xue <kaiwenx@rivosinc.com> > > > > > > This adds the properties for sxcsrind. Definitions of new registers and > > > implementations will come with future patches. > > > > > > Signed-off-by: Atish Patra <atishp@rivosinc.com> > > > Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> > > > --- > > > target/riscv/cpu.c | 2 ++ > > > target/riscv/cpu_cfg.h | 2 ++ > > > 2 files changed, 4 insertions(+) > > > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > > index a90808a3bace..ebc19090b40d 100644 > > > --- a/target/riscv/cpu.c > > > +++ b/target/riscv/cpu.c > > > @@ -183,12 +183,14 @@ const RISCVIsaExtData isa_edata_arr[] = { > > > ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), > > > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), > > > ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), > > > + ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_12_0, ext_smcsrind), > > > > This is actually part of the unpriv spec, so it's a bit weird that it > > depends on the priv spec. But that's how it's all set up. > > > > Smcsrind is part of priv spec[1]. Am I missing something ? > > https://drive.google.com/file/d/17GeetSnT5wW3xNuAHI95-SI1gPGd5sJ_/view Ah, I just saw "This specification has been merged into the Unprivileged Specification" at https://github.com/riscvarchive/riscv-indirect-csr-access Alistair > > > But shouldn't this be PRIV_VERSION_1_13_0? > > > > Yes. Sorry I forgot about that. smcntrpmf should also be PRIV_VERSION_1_13_0. > I will send a fix patch along with the v2 for assert fix. > > > Alistair
On Wed, Jul 31, 2024 at 2:24 AM Alistair Francis <alistair23@gmail.com> wrote: > > On Sat, Jul 27, 2024 at 11:33 AM Atish Kumar Patra <atishp@rivosinc.com> wrote: > > > > On Fri, Jul 26, 2024 at 12:42 AM Alistair Francis <alistair23@gmail.com> wrote: > > > > > > On Wed, Jul 24, 2024 at 9:31 AM Atish Patra <atishp@rivosinc.com> wrote: > > > > > > > > From: Kaiwen Xue <kaiwenx@rivosinc.com> > > > > > > > > This adds the properties for sxcsrind. Definitions of new registers and > > > > implementations will come with future patches. > > > > > > > > Signed-off-by: Atish Patra <atishp@rivosinc.com> > > > > Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> > > > > --- > > > > target/riscv/cpu.c | 2 ++ > > > > target/riscv/cpu_cfg.h | 2 ++ > > > > 2 files changed, 4 insertions(+) > > > > > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > > > index a90808a3bace..ebc19090b40d 100644 > > > > --- a/target/riscv/cpu.c > > > > +++ b/target/riscv/cpu.c > > > > @@ -183,12 +183,14 @@ const RISCVIsaExtData isa_edata_arr[] = { > > > > ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), > > > > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), > > > > ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), > > > > + ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_12_0, ext_smcsrind), > > > > > > This is actually part of the unpriv spec, so it's a bit weird that it > > > depends on the priv spec. But that's how it's all set up. > > > > > > > Smcsrind is part of priv spec[1]. Am I missing something ? > > > > https://drive.google.com/file/d/17GeetSnT5wW3xNuAHI95-SI1gPGd5sJ_/view > > Ah, I just saw > > "This specification has been merged into the Unprivileged Specification" at > > https://github.com/riscvarchive/riscv-indirect-csr-access > Probably a typo. I pinged RVI folks as the repo is already read only now. I can't create an issue either. > Alistair > > > > > > But shouldn't this be PRIV_VERSION_1_13_0? > > > > > > > Yes. Sorry I forgot about that. smcntrpmf should also be PRIV_VERSION_1_13_0. > > I will send a fix patch along with the v2 for assert fix. > > > > > Alistair
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