We may need 32-bit max or 32-bit any CPU for RV64 QEMU. Thus we add
these two CPUs for RV64 QEMU.
The reason we don't expose them to RV32 QEMU is that we already have
max or any cpu with the same configuration. Another reason is that
we want to follow the RISC-V custom where addw instruction doesn't
exist in RV32 CPU.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Suggested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu-qom.h | 2 ++
target/riscv/cpu.c | 13 ++++++++-----
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 3670cfe6d9..9f91743b78 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -31,6 +31,8 @@
#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
#define TYPE_RISCV_CPU_MAX RISCV_CPU_TYPE_NAME("max")
+#define TYPE_RISCV_CPU_ANY32 RISCV_CPU_TYPE_NAME("any32")
+#define TYPE_RISCV_CPU_MAX32 RISCV_CPU_TYPE_NAME("max32")
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0df145d90f..ab2512bb19 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -464,11 +464,9 @@ static void riscv_max_cpu_init(Object *obj)
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
-#ifdef TARGET_RISCV32
- set_satp_mode_max_supported(cpu, VM_1_10_SV32);
-#else
- set_satp_mode_max_supported(cpu, VM_1_10_SV57);
-#endif
+ set_satp_mode_max_supported(RISCV_CPU(obj),
+ riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
+ VM_1_10_SV32 : VM_1_10_SV57);
#endif
}
@@ -2962,6 +2960,11 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, MXL_RV32, rv32e_bare_cpu_init),
#endif
+#if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY32, MXL_RV32, riscv_any_cpu_init),
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX32, MXL_RV32, riscv_max_cpu_init),
+#endif
+
#if defined(TARGET_RISCV64)
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_cpu_init),
--
2.25.1On Sat, 20 Jul 2024 at 00:18, LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote: > > We may need 32-bit max or 32-bit any CPU for RV64 QEMU. Thus we add > these two CPUs for RV64 QEMU. > > The reason we don't expose them to RV32 QEMU is that we already have > max or any cpu with the same configuration. Another reason is that > we want to follow the RISC-V custom where addw instruction doesn't > exist in RV32 CPU. You might want to consider whether you'd rather have this be "-cpu max,64=off" (replace "64" with whatever feature name the architecture uses for 64-bit support). That's the way I would plan to handle it for Arm (with "-cpu max,aarch64=off"; that works for KVM right now and if we ever wanted to handle it for TCG would be how I'd want the command line syntax to go). -- PMM
On Sat, Jul 20, 2024 at 07:11:48AM GMT, LIU Zhiwei wrote:
> We may need 32-bit max or 32-bit any CPU for RV64 QEMU. Thus we add
> these two CPUs for RV64 QEMU.
>
> The reason we don't expose them to RV32 QEMU is that we already have
> max or any cpu with the same configuration. Another reason is that
> we want to follow the RISC-V custom where addw instruction doesn't
> exist in RV32 CPU.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Suggested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/cpu-qom.h | 2 ++
> target/riscv/cpu.c | 13 ++++++++-----
> 2 files changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 3670cfe6d9..9f91743b78 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -31,6 +31,8 @@
>
> #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
> #define TYPE_RISCV_CPU_MAX RISCV_CPU_TYPE_NAME("max")
> +#define TYPE_RISCV_CPU_ANY32 RISCV_CPU_TYPE_NAME("any32")
'any' is on its way out[1], so we probably shouldn't bother adding any32
at all with this series
[1] https://lore.kernel.org/all/20240724130717.95629-1-philmd@linaro.org/
Thanks,
drew
On 2024/7/24 23:01, Andrew Jones wrote:
> On Sat, Jul 20, 2024 at 07:11:48AM GMT, LIU Zhiwei wrote:
>> We may need 32-bit max or 32-bit any CPU for RV64 QEMU. Thus we add
>> these two CPUs for RV64 QEMU.
>>
>> The reason we don't expose them to RV32 QEMU is that we already have
>> max or any cpu with the same configuration. Another reason is that
>> we want to follow the RISC-V custom where addw instruction doesn't
>> exist in RV32 CPU.
>>
>> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
>> Suggested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>> ---
>> target/riscv/cpu-qom.h | 2 ++
>> target/riscv/cpu.c | 13 ++++++++-----
>> 2 files changed, 10 insertions(+), 5 deletions(-)
>>
>> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
>> index 3670cfe6d9..9f91743b78 100644
>> --- a/target/riscv/cpu-qom.h
>> +++ b/target/riscv/cpu-qom.h
>> @@ -31,6 +31,8 @@
>>
>> #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
>> #define TYPE_RISCV_CPU_MAX RISCV_CPU_TYPE_NAME("max")
>> +#define TYPE_RISCV_CPU_ANY32 RISCV_CPU_TYPE_NAME("any32")
> 'any' is on its way out[1], so we probably shouldn't bother adding any32
> at all with this series
>
> [1] https://lore.kernel.org/all/20240724130717.95629-1-philmd@linaro.org/
Agree.
Thanks,
Zhiwei
>
> Thanks,
> drew
On 7/19/24 8:11 PM, LIU Zhiwei wrote:
> We may need 32-bit max or 32-bit any CPU for RV64 QEMU. Thus we add
> these two CPUs for RV64 QEMU.
>
> The reason we don't expose them to RV32 QEMU is that we already have
> max or any cpu with the same configuration. Another reason is that
> we want to follow the RISC-V custom where addw instruction doesn't
> exist in RV32 CPU.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Suggested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/cpu-qom.h | 2 ++
> target/riscv/cpu.c | 13 ++++++++-----
> 2 files changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 3670cfe6d9..9f91743b78 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -31,6 +31,8 @@
>
> #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
> #define TYPE_RISCV_CPU_MAX RISCV_CPU_TYPE_NAME("max")
> +#define TYPE_RISCV_CPU_ANY32 RISCV_CPU_TYPE_NAME("any32")
> +#define TYPE_RISCV_CPU_MAX32 RISCV_CPU_TYPE_NAME("max32")
> #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
> #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
> #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0df145d90f..ab2512bb19 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -464,11 +464,9 @@ static void riscv_max_cpu_init(Object *obj)
>
> env->priv_ver = PRIV_VERSION_LATEST;
> #ifndef CONFIG_USER_ONLY
> -#ifdef TARGET_RISCV32
> - set_satp_mode_max_supported(cpu, VM_1_10_SV32);
> -#else
> - set_satp_mode_max_supported(cpu, VM_1_10_SV57);
> -#endif
> + set_satp_mode_max_supported(RISCV_CPU(obj),
> + riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
> + VM_1_10_SV32 : VM_1_10_SV57);
> #endif
> }
>
> @@ -2962,6 +2960,11 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, MXL_RV32, rv32e_bare_cpu_init),
> #endif
>
> +#if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
> + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY32, MXL_RV32, riscv_any_cpu_init),
> + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX32, MXL_RV32, riscv_max_cpu_init),
> +#endif
> +
> #if defined(TARGET_RISCV64)
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_cpu_init),
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