The following changes since commit 58ee924b97d1c0898555647a31820c5a20d55a73:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2024-07-17 15:40:28 +1000)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240718-1
for you to fetch changes up to daff9f7f7a457f78ce455e6abf19c2a37dfe7630:
roms/opensbi: Update to v1.5 (2024-07-18 12:08:45 +1000)
----------------------------------------------------------------
RISC-V PR for 9.1
* Support the zimop, zcmop, zama16b and zabha extensions
* Validate the mode when setting vstvec CSR
* Add decode support for Zawrs extension
* Update the KVM regs to Linux 6.10-rc5
* Add smcntrpmf extension support
* Raise an exception when CSRRS/CSRRC writes a read-only CSR
* Re-insert and deprecate 'riscv,delegate' in virt machine device tree
* roms/opensbi: Update to v1.5
----------------------------------------------------------------
Atish Patra (7):
target/riscv: Fix the predicate functions for mhpmeventhX CSRs
target/riscv: Only set INH fields if priv mode is available
target/riscv: Implement privilege mode filtering for cycle/instret
target/riscv: Save counter values during countinhibit update
target/riscv: Enforce WARL behavior for scounteren/hcounteren
target/riscv: Do not setup pmu timer if OF is disabled
target/riscv: Expose the Smcntrpmf config
Balaji Ravikumar (1):
disas/riscv: Add decode for Zawrs extension
Daniel Henrique Barboza (3):
target/riscv/kvm: update KVM regs to Linux 6.10-rc5
hw/riscv/virt.c: re-insert and deprecate 'riscv,delegate'
roms/opensbi: Update to v1.5
Jiayi Li (1):
target/riscv: Validate the mode in write_vstvec
Kaiwen Xue (3):
target/riscv: Add cycle & instret privilege mode filtering properties
target/riscv: Add cycle & instret privilege mode filtering definitions
target/riscv: Add cycle & instret privilege mode filtering support
LIU Zhiwei (11):
target/riscv: Add zimop extension
disas/riscv: Support zimop disassemble
target/riscv: Add zcmop extension
disas/riscv: Support zcmop disassemble
target/riscv: Support Zama16b extension
target/riscv: Move gen_amo before implement Zabha
target/riscv: Add AMO instructions for Zabha
target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
target/riscv: Add amocas.[b|h] for Zabha
target/riscv: Expose zabha extension as a cpu property
disas/riscv: Support zabha disassemble
Rajnesh Kanwal (3):
target/riscv: Combine set_mode and set_virt functions.
target/riscv: Start counters from both mhpmcounter and mcountinhibit
target/riscv: More accurately model priv mode filtering.
Yu-Ming Chang (1):
target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
docs/about/deprecated.rst | 11 +
target/riscv/cpu.h | 24 +-
target/riscv/cpu_bits.h | 41 ++
target/riscv/cpu_cfg.h | 5 +
target/riscv/pmu.h | 4 +
target/riscv/insn16.decode | 1 +
target/riscv/insn32.decode | 33 ++
disas/riscv.c | 187 +++++++++
hw/riscv/virt.c | 9 +
target/riscv/cpu.c | 10 +
target/riscv/cpu_helper.c | 66 ++--
target/riscv/csr.c | 501 ++++++++++++++++++++-----
target/riscv/kvm/kvm-cpu.c | 2 +
target/riscv/machine.c | 5 +-
target/riscv/op_helper.c | 23 +-
target/riscv/pmu.c | 181 ++++++++-
target/riscv/tcg/tcg-cpu.c | 5 +
target/riscv/translate.c | 38 ++
target/riscv/insn_trans/trans_rva.c.inc | 51 +--
target/riscv/insn_trans/trans_rvd.c.inc | 14 +-
target/riscv/insn_trans/trans_rvf.c.inc | 14 +-
target/riscv/insn_trans/trans_rvi.c.inc | 6 +
target/riscv/insn_trans/trans_rvzabha.c.inc | 145 +++++++
target/riscv/insn_trans/trans_rvzacas.c.inc | 13 -
target/riscv/insn_trans/trans_rvzcmop.c.inc | 29 ++
target/riscv/insn_trans/trans_rvzimop.c.inc | 37 ++
pc-bios/opensbi-riscv32-generic-fw_dynamic.bin | Bin 267416 -> 268312 bytes
pc-bios/opensbi-riscv64-generic-fw_dynamic.bin | Bin 270808 -> 272504 bytes
roms/opensbi | 2 +-
29 files changed, 1246 insertions(+), 211 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvzabha.c.inc
create mode 100644 target/riscv/insn_trans/trans_rvzcmop.c.inc
create mode 100644 target/riscv/insn_trans/trans_rvzimop.c.inc