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[PATCH v3 1/9] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC

Sunil V L posted 9 patches 4 months, 1 week ago
Maintainers: Sunil V L <sunilvl@ventanamicro.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, "Michael S. Tsirkin" <mst@redhat.com>, Igor Mammedov <imammedo@redhat.com>, Ani Sinha <anisinha@redhat.com>
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[PATCH v3 1/9] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC
Posted by Sunil V L 4 months, 1 week ago 
As per the requirement ACPI_080 in the RISC-V Boot and Runtime Services
(BRS) specification [1],  PLIC and APLIC should be in namespace as well.
So, add them using the defined HID.

[1] - https://github.com/riscv-non-isa/riscv-brs/blob/main/acpi.adoc
      (commit : 241575b3189c5d9e60b5e55e78cf0443092713bf)

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt-acpi-build.c | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 0925528160..5f5082a35b 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -141,6 +141,30 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
     }
 }
 
+static void acpi_dsdt_add_plic_aplic(Aml *scope, uint8_t socket_count,
+                                     uint64_t mmio_base, uint64_t mmio_size,
+                                     const char *hid)
+{
+    uint64_t plic_aplic_addr;
+    uint32_t gsi_base;
+    uint8_t  socket;
+
+    for (socket = 0; socket < socket_count; socket++) {
+        plic_aplic_addr = mmio_base + mmio_size * socket;
+        gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
+        Aml *dev = aml_device("IC%.02X", socket);
+        aml_append(dev, aml_name_decl("_HID", aml_string("%s", hid)));
+        aml_append(dev, aml_name_decl("_UID", aml_int(socket)));
+        aml_append(dev, aml_name_decl("_GSB", aml_int(gsi_base)));
+
+        Aml *crs = aml_resource_template();
+        aml_append(crs, aml_memory32_fixed(plic_aplic_addr, mmio_size,
+                                           AML_READ_WRITE));
+        aml_append(dev, aml_name_decl("_CRS", crs));
+        aml_append(scope, dev);
+    }
+}
+
 static void
 acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
                     uint32_t uart_irq)
@@ -411,6 +435,14 @@ static void build_dsdt(GArray *table_data,
 
     socket_count = riscv_socket_count(ms);
 
+    if (s->aia_type == VIRT_AIA_TYPE_NONE) {
+        acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_PLIC].base,
+                                 memmap[VIRT_PLIC].size, "RSCV0001");
+    } else {
+        acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_APLIC_S].base,
+                                 memmap[VIRT_APLIC_S].size, "RSCV0002");
+    }
+
     acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], UART0_IRQ);
 
     if (socket_count == 1) {
-- 
2.43.0
Re: [PATCH v3 1/9] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC
Posted by Igor Mammedov 4 months, 1 week ago 
On Mon, 15 Jul 2024 22:41:21 +0530
Sunil V L <sunilvl@ventanamicro.com> wrote:

> As per the requirement ACPI_080 in the RISC-V Boot and Runtime Services
> (BRS) specification [1],  PLIC and APLIC should be in namespace as well.
> So, add them using the defined HID.
> 
> [1] - https://github.com/riscv-non-isa/riscv-brs/blob/main/acpi.adoc
>       (commit : 241575b3189c5d9e60b5e55e78cf0443092713bf)

in spec links 'See RVI ACPI IDs' and right below it 'additional guidance',
do lead nowhere hence do not clarify anything.

> 
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Acked-by: Alistair Francis <alistair.francis@wdc.com>

Acked-by: Igor Mammedov <imammedo@redhat.com>

> ---
>  hw/riscv/virt-acpi-build.c | 32 ++++++++++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index 0925528160..5f5082a35b 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -141,6 +141,30 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
>      }
>  }
>  
> +static void acpi_dsdt_add_plic_aplic(Aml *scope, uint8_t socket_count,
> +                                     uint64_t mmio_base, uint64_t mmio_size,
> +                                     const char *hid)
> +{
> +    uint64_t plic_aplic_addr;
> +    uint32_t gsi_base;
> +    uint8_t  socket;
> +
> +    for (socket = 0; socket < socket_count; socket++) {
> +        plic_aplic_addr = mmio_base + mmio_size * socket;
> +        gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
> +        Aml *dev = aml_device("IC%.02X", socket);
> +        aml_append(dev, aml_name_decl("_HID", aml_string("%s", hid)));
> +        aml_append(dev, aml_name_decl("_UID", aml_int(socket)));
> +        aml_append(dev, aml_name_decl("_GSB", aml_int(gsi_base)));
> +
> +        Aml *crs = aml_resource_template();
> +        aml_append(crs, aml_memory32_fixed(plic_aplic_addr, mmio_size,
> +                                           AML_READ_WRITE));
> +        aml_append(dev, aml_name_decl("_CRS", crs));
> +        aml_append(scope, dev);
> +    }
> +}
> +
>  static void
>  acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
>                      uint32_t uart_irq)
> @@ -411,6 +435,14 @@ static void build_dsdt(GArray *table_data,
>  
>      socket_count = riscv_socket_count(ms);
>  
> +    if (s->aia_type == VIRT_AIA_TYPE_NONE) {
> +        acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_PLIC].base,
> +                                 memmap[VIRT_PLIC].size, "RSCV0001");
> +    } else {
> +        acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_APLIC_S].base,
> +                                 memmap[VIRT_APLIC_S].size, "RSCV0002");
> +    }
> +
>      acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], UART0_IRQ);
>  
>      if (socket_count == 1) {
Re: [PATCH v3 1/9] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC
Posted by Sunil V L 4 months, 1 week ago 
On Tue, Jul 16, 2024 at 12:24:05PM +0200, Igor Mammedov wrote:
> On Mon, 15 Jul 2024 22:41:21 +0530
> Sunil V L <sunilvl@ventanamicro.com> wrote:
> 
> > As per the requirement ACPI_080 in the RISC-V Boot and Runtime Services
> > (BRS) specification [1],  PLIC and APLIC should be in namespace as well.
> > So, add them using the defined HID.
> > 
> > [1] - https://github.com/riscv-non-isa/riscv-brs/blob/main/acpi.adoc
> >       (commit : 241575b3189c5d9e60b5e55e78cf0443092713bf)
> 
> in spec links 'See RVI ACPI IDs' and right below it 'additional guidance',
> do lead nowhere hence do not clarify anything.
> 
Thanks Igor. I didn't realize links work only in the final PDF generated
from the sources. Let me point to the PDF itself where these
requirements were documented first.

Thanks,
Sunil
> > 
> > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> > Acked-by: Alistair Francis <alistair.francis@wdc.com>
> 
> Acked-by: Igor Mammedov <imammedo@redhat.com>
> 
> > ---
> >  hw/riscv/virt-acpi-build.c | 32 ++++++++++++++++++++++++++++++++
> >  1 file changed, 32 insertions(+)
> > 
> > diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> > index 0925528160..5f5082a35b 100644
> > --- a/hw/riscv/virt-acpi-build.c
> > +++ b/hw/riscv/virt-acpi-build.c
> > @@ -141,6 +141,30 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
> >      }
> >  }
> >  
> > +static void acpi_dsdt_add_plic_aplic(Aml *scope, uint8_t socket_count,
> > +                                     uint64_t mmio_base, uint64_t mmio_size,
> > +                                     const char *hid)
> > +{
> > +    uint64_t plic_aplic_addr;
> > +    uint32_t gsi_base;
> > +    uint8_t  socket;
> > +
> > +    for (socket = 0; socket < socket_count; socket++) {
> > +        plic_aplic_addr = mmio_base + mmio_size * socket;
> > +        gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
> > +        Aml *dev = aml_device("IC%.02X", socket);
> > +        aml_append(dev, aml_name_decl("_HID", aml_string("%s", hid)));
> > +        aml_append(dev, aml_name_decl("_UID", aml_int(socket)));
> > +        aml_append(dev, aml_name_decl("_GSB", aml_int(gsi_base)));
> > +
> > +        Aml *crs = aml_resource_template();
> > +        aml_append(crs, aml_memory32_fixed(plic_aplic_addr, mmio_size,
> > +                                           AML_READ_WRITE));
> > +        aml_append(dev, aml_name_decl("_CRS", crs));
> > +        aml_append(scope, dev);
> > +    }
> > +}
> > +
> >  static void
> >  acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
> >                      uint32_t uart_irq)
> > @@ -411,6 +435,14 @@ static void build_dsdt(GArray *table_data,
> >  
> >      socket_count = riscv_socket_count(ms);
> >  
> > +    if (s->aia_type == VIRT_AIA_TYPE_NONE) {
> > +        acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_PLIC].base,
> > +                                 memmap[VIRT_PLIC].size, "RSCV0001");
> > +    } else {
> > +        acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_APLIC_S].base,
> > +                                 memmap[VIRT_APLIC_S].size, "RSCV0002");
> > +    }
> > +
> >      acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], UART0_IRQ);
> >  
> >      if (socket_count == 1) {
>

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