[PULL 00/24] target-arm queue
[PULL 00/72] target-arm queue
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The following changes since commit 59084feb256c617063e0dbe7e64821ae8852d7cf:
1
First arm pullreq of the cycle; this is mostly my softfloat NaN
2
handling series. (Lots more in my to-review queue, but I don't
3
like pullreqs growing too close to a hundred patches at a time :-))
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4
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Merge tag 'pull-aspeed-20240709' of https://github.com/legoater/qemu into staging (2024-07-09 07:13:55 -0700)
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thanks
6
-- PMM
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The following changes since commit 97f2796a3736ed37a1b85dc1c76a6c45b829dd17:
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10
Open 10.0 development tree (2024-12-10 17:41:17 +0000)
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11
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240711
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241211
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15
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for you to fetch changes up to 7f49089158a4db644fcbadfa90cd3d30a4868735:
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for you to fetch changes up to 1abe28d519239eea5cf9620bb13149423e5665f8:
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17
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target/arm: Convert PMULL to decodetree (2024-07-11 11:41:34 +0100)
18
MAINTAINERS: Add correct email address for Vikram Garhwal (2024-12-11 15:31:09 +0000)
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19
13
----------------------------------------------------------------
20
----------------------------------------------------------------
14
target-arm queue:
21
target-arm queue:
15
* Refactor FPCR/FPSR handling in preparation for FEAT_AFP
22
* hw/net/lan9118: Extract PHY model, reuse with imx_fec, fix bugs
16
* More decodetree conversions
23
* fpu: Make muladd NaN handling runtime-selected, not compile-time
17
* target/arm: Use cpu_env in cpu_untagged_addr
24
* fpu: Make default NaN pattern runtime-selected, not compile-time
18
* target/arm: Set arm_v7m_tcg_ops cpu_exec_halt to arm_cpu_exec_halt()
25
* fpu: Minor NaN-related cleanups
19
* hw/char/pl011: Avoid division-by-zero in pl011_get_baudrate()
26
* MAINTAINERS: email address updates
20
* hw/misc/bcm2835_thermal: Fix access size handling in bcm2835_thermal_ops
21
* accel/tcg: Make TCGCPUOps::cpu_exec_halt mandatory
22
* STM32L4x5: Handle USART interrupts correctly
23
27
24
----------------------------------------------------------------
28
----------------------------------------------------------------
25
Inès Varhol (3):
29
Bernhard Beschow (5):
26
hw/misc: In STM32L4x5 EXTI, consolidate 2 constants
30
hw/net/lan9118: Extract lan9118_phy
27
hw/misc: In STM32L4x5 EXTI, handle direct interrupts
31
hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
28
hw/arm: In STM32L4x5 SOC, connect USART devices to EXTI
32
hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
33
hw/net/lan9118_phy: Reuse MII constants
34
hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
29
35
30
Peter Maydell (12):
36
Leif Lindholm (1):
31
target/arm: Correct comments about M-profile FPSCR
37
MAINTAINERS: update email address for Leif Lindholm
32
target/arm: Make vfp_get_fpscr() call vfp_get_{fpcr, fpsr}
33
target/arm: Make vfp_set_fpscr() call vfp_set_{fpcr, fpsr}
34
target/arm: Support migration when FPSR/FPCR won't fit in the FPSCR
35
target/arm: Implement store_cpu_field_low32() macro
36
target/arm: Store FPSR and FPCR in separate CPU state fields
37
target/arm: Rename FPCR_ QC, NZCV macros to FPSR_
38
target/arm: Rename FPSR_MASK and FPCR_MASK and define them symbolically
39
target/arm: Allow FPCR bits that aren't in FPSCR
40
target/arm: Set arm_v7m_tcg_ops cpu_exec_halt to arm_cpu_exec_halt()
41
target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation
42
accel/tcg: Make TCGCPUOps::cpu_exec_halt mandatory
43
38
44
Richard Henderson (7):
39
Peter Maydell (54):
45
target/arm: Use cpu_env in cpu_untagged_addr
40
fpu: handle raising Invalid for infzero in pick_nan_muladd
46
target/arm: Convert SMULL, UMULL, SMLAL, UMLAL, SMLSL, UMLSL to decodetree
41
fpu: Check for default_nan_mode before calling pickNaNMulAdd
47
target/arm: Convert SADDL, SSUBL, SABDL, SABAL, and unsigned to decodetree
42
softfloat: Allow runtime choice of inf * 0 + NaN result
48
target/arm: Convert SQDMULL, SQDMLAL, SQDMLSL to decodetree
43
tests/fp: Explicitly set inf-zero-nan rule
49
target/arm: Convert SADDW, SSUBW, UADDW, USUBW to decodetree
44
target/arm: Set FloatInfZeroNaNRule explicitly
50
target/arm: Convert ADDHN, SUBHN, RADDHN, RSUBHN to decodetree
45
target/s390: Set FloatInfZeroNaNRule explicitly
51
target/arm: Convert PMULL to decodetree
46
target/ppc: Set FloatInfZeroNaNRule explicitly
47
target/mips: Set FloatInfZeroNaNRule explicitly
48
target/sparc: Set FloatInfZeroNaNRule explicitly
49
target/xtensa: Set FloatInfZeroNaNRule explicitly
50
target/x86: Set FloatInfZeroNaNRule explicitly
51
target/loongarch: Set FloatInfZeroNaNRule explicitly
52
target/hppa: Set FloatInfZeroNaNRule explicitly
53
softfloat: Pass have_snan to pickNaNMulAdd
54
softfloat: Allow runtime choice of NaN propagation for muladd
55
tests/fp: Explicitly set 3-NaN propagation rule
56
target/arm: Set Float3NaNPropRule explicitly
57
target/loongarch: Set Float3NaNPropRule explicitly
58
target/ppc: Set Float3NaNPropRule explicitly
59
target/s390x: Set Float3NaNPropRule explicitly
60
target/sparc: Set Float3NaNPropRule explicitly
61
target/mips: Set Float3NaNPropRule explicitly
62
target/xtensa: Set Float3NaNPropRule explicitly
63
target/i386: Set Float3NaNPropRule explicitly
64
target/hppa: Set Float3NaNPropRule explicitly
65
fpu: Remove use_first_nan field from float_status
66
target/m68k: Don't pass NULL float_status to floatx80_default_nan()
67
softfloat: Create floatx80 default NaN from parts64_default_nan
68
target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
69
target/m68k: In frem helper, initialize local float_status from env->fp_status
70
target/m68k: Init local float_status from env fp_status in gdb get/set reg
71
target/sparc: Initialize local scratch float_status from env->fp_status
72
target/ppc: Use env->fp_status in helper_compute_fprf functions
73
fpu: Allow runtime choice of default NaN value
74
tests/fp: Set default NaN pattern explicitly
75
target/microblaze: Set default NaN pattern explicitly
76
target/i386: Set default NaN pattern explicitly
77
target/hppa: Set default NaN pattern explicitly
78
target/alpha: Set default NaN pattern explicitly
79
target/arm: Set default NaN pattern explicitly
80
target/loongarch: Set default NaN pattern explicitly
81
target/m68k: Set default NaN pattern explicitly
82
target/mips: Set default NaN pattern explicitly
83
target/openrisc: Set default NaN pattern explicitly
84
target/ppc: Set default NaN pattern explicitly
85
target/sh4: Set default NaN pattern explicitly
86
target/rx: Set default NaN pattern explicitly
87
target/s390x: Set default NaN pattern explicitly
88
target/sparc: Set default NaN pattern explicitly
89
target/xtensa: Set default NaN pattern explicitly
90
target/hexagon: Set default NaN pattern explicitly
91
target/riscv: Set default NaN pattern explicitly
92
target/tricore: Set default NaN pattern explicitly
93
fpu: Remove default handling for dnan_pattern
52
94
53
Zheyu Ma (2):
95
Richard Henderson (11):
54
hw/char/pl011: Avoid division-by-zero in pl011_get_baudrate()
96
target/arm: Copy entire float_status in is_ebf
55
hw/misc/bcm2835_thermal: Fix access size handling in bcm2835_thermal_ops
97
softfloat: Inline pickNaNMulAdd
98
softfloat: Use goto for default nan case in pick_nan_muladd
99
softfloat: Remove which from parts_pick_nan_muladd
100
softfloat: Pad array size in pick_nan_muladd
101
softfloat: Move propagateFloatx80NaN to softfloat.c
102
softfloat: Use parts_pick_nan in propagateFloatx80NaN
103
softfloat: Inline pickNaN
104
softfloat: Share code between parts_pick_nan cases
105
softfloat: Sink frac_cmp in parts_pick_nan until needed
106
softfloat: Replace WHICH with RET in parts_pick_nan
56
107
57
include/hw/core/tcg-cpu-ops.h | 9 +-
108
Vikram Garhwal (1):
58
include/hw/misc/stm32l4x5_exti.h | 4 +-
109
MAINTAINERS: Add correct email address for Vikram Garhwal
59
target/arm/cpu.h | 113 ++--
60
target/arm/internals.h | 3 +
61
target/arm/tcg/translate-a32.h | 7 +
62
target/arm/tcg/translate.h | 3 +-
63
target/riscv/internals.h | 3 +
64
target/arm/tcg/a64.decode | 77 +++
65
accel/tcg/cpu-exec.c | 11 +-
66
hw/arm/stm32l4x5_soc.c | 24 +-
67
hw/char/pl011.c | 13 +-
68
hw/misc/bcm2835_thermal.c | 2 +
69
hw/misc/stm32l4x5_exti.c | 13 +-
70
target/alpha/cpu.c | 1 +
71
target/arm/cpu.c | 2 +-
72
target/arm/machine.c | 135 ++++-
73
target/arm/tcg/cpu-v7m.c | 1 +
74
target/arm/tcg/mve_helper.c | 12 +-
75
target/arm/tcg/translate-a64.c | 1155 ++++++++++++-------------------------
76
target/arm/tcg/translate-m-nocp.c | 22 +-
77
target/arm/tcg/translate-vfp.c | 4 +-
78
target/arm/vfp_helper.c | 187 +++---
79
target/avr/cpu.c | 1 +
80
target/cris/cpu.c | 2 +
81
target/hppa/cpu.c | 1 +
82
target/loongarch/cpu.c | 1 +
83
target/m68k/cpu.c | 1 +
84
target/microblaze/cpu.c | 1 +
85
target/mips/cpu.c | 1 +
86
target/openrisc/cpu.c | 1 +
87
target/ppc/cpu_init.c | 2 +
88
target/riscv/cpu.c | 2 +-
89
target/riscv/tcg/tcg-cpu.c | 2 +
90
target/rx/cpu.c | 1 +
91
target/s390x/cpu.c | 1 +
92
target/sh4/cpu.c | 1 +
93
target/sparc/cpu.c | 1 +
94
target/tricore/cpu.c | 1 +
95
target/xtensa/cpu.c | 1 +
96
39 files changed, 893 insertions(+), 929 deletions(-)
97
110
111
MAINTAINERS | 4 +-
112
include/fpu/softfloat-helpers.h | 38 +++-
113
include/fpu/softfloat-types.h | 89 +++++++-
114
include/hw/net/imx_fec.h | 9 +-
115
include/hw/net/lan9118_phy.h | 37 ++++
116
include/hw/net/mii.h | 6 +
117
target/mips/fpu_helper.h | 20 ++
118
target/sparc/helper.h | 4 +-
119
fpu/softfloat.c | 19 ++
120
hw/net/imx_fec.c | 146 ++------------
121
hw/net/lan9118.c | 137 ++-----------
122
hw/net/lan9118_phy.c | 222 ++++++++++++++++++++
123
linux-user/arm/nwfpe/fpa11.c | 5 +
124
target/alpha/cpu.c | 2 +
125
target/arm/cpu.c | 10 +
126
target/arm/tcg/vec_helper.c | 20 +-
127
target/hexagon/cpu.c | 2 +
128
target/hppa/fpu_helper.c | 12 ++
129
target/i386/tcg/fpu_helper.c | 12 ++
130
target/loongarch/tcg/fpu_helper.c | 14 +-
131
target/m68k/cpu.c | 14 +-
132
target/m68k/fpu_helper.c | 6 +-
133
target/m68k/helper.c | 6 +-
134
target/microblaze/cpu.c | 2 +
135
target/mips/msa.c | 10 +
136
target/openrisc/cpu.c | 2 +
137
target/ppc/cpu_init.c | 19 ++
138
target/ppc/fpu_helper.c | 3 +-
139
target/riscv/cpu.c | 2 +
140
target/rx/cpu.c | 2 +
141
target/s390x/cpu.c | 5 +
142
target/sh4/cpu.c | 2 +
143
target/sparc/cpu.c | 6 +
144
target/sparc/fop_helper.c | 8 +-
145
target/sparc/translate.c | 4 +-
146
target/tricore/helper.c | 2 +
147
target/xtensa/cpu.c | 4 +
148
target/xtensa/fpu_helper.c | 3 +-
149
tests/fp/fp-bench.c | 7 +
150
tests/fp/fp-test-log2.c | 1 +
151
tests/fp/fp-test.c | 7 +
152
fpu/softfloat-parts.c.inc | 152 +++++++++++---
153
fpu/softfloat-specialize.c.inc | 412 ++------------------------------------
154
.mailmap | 5 +-
155
hw/net/Kconfig | 5 +
156
hw/net/meson.build | 1 +
157
hw/net/trace-events | 10 +-
158
47 files changed, 778 insertions(+), 730 deletions(-)
159
create mode 100644 include/hw/net/lan9118_phy.h
160
create mode 100644 hw/net/lan9118_phy.c
diff view generated by jsdifflib
[PULL 23/24] target/arm: Convert ADDHN, SUBHN, RADDHN, RSUBHN to decodetree
[PULL 01/72] hw/net/lan9118: Extract lan9118_phy
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
A very similar implementation of the same device exists in imx_fec. Prepare for
4
a common implementation by extracting a device model into its own files.
5
6
Some migration state has been moved into the new device model which breaks
7
migration compatibility for the following machines:
8
* smdkc210
9
* realview-*
10
* vexpress-*
11
* kzm
12
* mps2-*
13
14
While breaking migration ABI, fix the size of the MII registers to be 16 bit,
15
as defined by IEEE 802.3u.
16
17
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
18
Tested-by: Guenter Roeck <linux@roeck-us.net>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20240709000610.382391-6-richard.henderson@linaro.org
20
Message-id: 20241102125724.532843-2-shentey@gmail.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
22
---
8
target/arm/tcg/a64.decode | 5 ++
23
include/hw/net/lan9118_phy.h | 37 ++++++++
9
target/arm/tcg/translate-a64.c | 127 +++++++++++++++------------------
24
hw/net/lan9118.c | 137 +++++-----------------------
10
2 files changed, 61 insertions(+), 71 deletions(-)
25
hw/net/lan9118_phy.c | 169 +++++++++++++++++++++++++++++++++++
26
hw/net/Kconfig | 4 +
27
hw/net/meson.build | 1 +
28
5 files changed, 233 insertions(+), 115 deletions(-)
29
create mode 100644 include/hw/net/lan9118_phy.h
30
create mode 100644 hw/net/lan9118_phy.c
11
31
12
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
32
diff --git a/include/hw/net/lan9118_phy.h b/include/hw/net/lan9118_phy.h
33
new file mode 100644
34
index XXXXXXX..XXXXXXX
35
--- /dev/null
36
+++ b/include/hw/net/lan9118_phy.h
37
@@ -XXX,XX +XXX,XX @@
38
+/*
39
+ * SMSC LAN9118 PHY emulation
40
+ *
41
+ * Copyright (c) 2009 CodeSourcery, LLC.
42
+ * Written by Paul Brook
43
+ *
44
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
45
+ * See the COPYING file in the top-level directory.
46
+ */
47
+
48
+#ifndef HW_NET_LAN9118_PHY_H
49
+#define HW_NET_LAN9118_PHY_H
50
+
51
+#include "qom/object.h"
52
+#include "hw/sysbus.h"
53
+
54
+#define TYPE_LAN9118_PHY "lan9118-phy"
55
+OBJECT_DECLARE_SIMPLE_TYPE(Lan9118PhyState, LAN9118_PHY)
56
+
57
+typedef struct Lan9118PhyState {
58
+ SysBusDevice parent_obj;
59
+
60
+ uint16_t status;
61
+ uint16_t control;
62
+ uint16_t advertise;
63
+ uint16_t ints;
64
+ uint16_t int_mask;
65
+ qemu_irq irq;
66
+ bool link_down;
67
+} Lan9118PhyState;
68
+
69
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down);
70
+void lan9118_phy_reset(Lan9118PhyState *s);
71
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg);
72
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val);
73
+
74
+#endif
75
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
13
index XXXXXXX..XXXXXXX 100644
76
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/tcg/a64.decode
77
--- a/hw/net/lan9118.c
15
+++ b/target/arm/tcg/a64.decode
78
+++ b/hw/net/lan9118.c
16
@@ -XXX,XX +XXX,XX @@ UADDW 0.10 1110 ..1 ..... 00010 0 ..... ..... @qrrr_e
79
@@ -XXX,XX +XXX,XX @@
17
SSUBW 0.00 1110 ..1 ..... 00110 0 ..... ..... @qrrr_e
80
#include "net/net.h"
18
USUBW 0.10 1110 ..1 ..... 00110 0 ..... ..... @qrrr_e
81
#include "net/eth.h"
19
82
#include "hw/irq.h"
20
+ADDHN 0.00 1110 ..1 ..... 01000 0 ..... ..... @qrrr_e
83
+#include "hw/net/lan9118_phy.h"
21
+RADDHN 0.10 1110 ..1 ..... 01000 0 ..... ..... @qrrr_e
84
#include "hw/net/lan9118.h"
22
+SUBHN 0.00 1110 ..1 ..... 01100 0 ..... ..... @qrrr_e
85
#include "hw/ptimer.h"
23
+RSUBHN 0.10 1110 ..1 ..... 01100 0 ..... ..... @qrrr_e
86
#include "hw/qdev-properties.h"
24
+
87
@@ -XXX,XX +XXX,XX @@ do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
25
### Advanced SIMD scalar x indexed element
88
#define MAC_CR_RXEN 0x00000004
26
89
#define MAC_CR_RESERVED 0x7f404213
27
FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h
90
28
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
91
-#define PHY_INT_ENERGYON 0x80
29
index XXXXXXX..XXXXXXX 100644
92
-#define PHY_INT_AUTONEG_COMPLETE 0x40
30
--- a/target/arm/tcg/translate-a64.c
93
-#define PHY_INT_FAULT 0x20
31
+++ b/target/arm/tcg/translate-a64.c
94
-#define PHY_INT_DOWN 0x10
32
@@ -XXX,XX +XXX,XX @@ TRANS(UADDW, do_addsub_wide, a, 0, false)
95
-#define PHY_INT_AUTONEG_LP 0x08
33
TRANS(SSUBW, do_addsub_wide, a, MO_SIGN, true)
96
-#define PHY_INT_PARFAULT 0x04
34
TRANS(USUBW, do_addsub_wide, a, 0, true)
97
-#define PHY_INT_AUTONEG_PAGE 0x02
35
98
-
36
+static bool do_addsub_highnarrow(DisasContext *s, arg_qrrr_e *a,
99
#define GPT_TIMER_EN 0x20000000
37
+ bool sub, bool round)
100
38
+{
39
+ TCGv_i64 tcg_op0, tcg_op1;
40
+ MemOp esz = a->esz;
41
+ int half = 8 >> esz;
42
+ bool top = a->q;
43
+ int ebits = 8 << esz;
44
+ uint64_t rbit = 1ull << (ebits - 1);
45
+ int top_swap, top_half;
46
+
47
+ /* There are no 128x128->64 bit operations. */
48
+ if (esz >= MO_64) {
49
+ return false;
50
+ }
51
+ if (!fp_access_check(s)) {
52
+ return true;
53
+ }
54
+ tcg_op0 = tcg_temp_new_i64();
55
+ tcg_op1 = tcg_temp_new_i64();
56
+
57
+ /*
58
+ * For top half inputs, iterate backward; forward for bottom half.
59
+ * This means the store to the destination will not occur until
60
+ * overlapping input inputs are consumed.
61
+ */
62
+ top_swap = top ? half - 1 : 0;
63
+ top_half = top ? half : 0;
64
+
65
+ for (int elt_fwd = 0; elt_fwd < half; ++elt_fwd) {
66
+ int elt = elt_fwd ^ top_swap;
67
+
68
+ read_vec_element(s, tcg_op1, a->rm, elt, esz + 1);
69
+ read_vec_element(s, tcg_op0, a->rn, elt, esz + 1);
70
+ if (sub) {
71
+ tcg_gen_sub_i64(tcg_op0, tcg_op0, tcg_op1);
72
+ } else {
73
+ tcg_gen_add_i64(tcg_op0, tcg_op0, tcg_op1);
74
+ }
75
+ if (round) {
76
+ tcg_gen_addi_i64(tcg_op0, tcg_op0, rbit);
77
+ }
78
+ tcg_gen_shri_i64(tcg_op0, tcg_op0, ebits);
79
+ write_vec_element(s, tcg_op0, a->rd, elt + top_half, esz);
80
+ }
81
+ clear_vec_high(s, top, a->rd);
82
+ return true;
83
+}
84
+
85
+TRANS(ADDHN, do_addsub_highnarrow, a, false, false)
86
+TRANS(SUBHN, do_addsub_highnarrow, a, true, false)
87
+TRANS(RADDHN, do_addsub_highnarrow, a, false, true)
88
+TRANS(RSUBHN, do_addsub_highnarrow, a, true, true)
89
+
90
/*
101
/*
91
* Advanced SIMD scalar/vector x indexed element
102
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
92
*/
103
uint32_t mac_mii_data;
93
@@ -XXX,XX +XXX,XX @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn)
104
uint32_t mac_flow;
105
106
- uint32_t phy_status;
107
- uint32_t phy_control;
108
- uint32_t phy_advertise;
109
- uint32_t phy_int;
110
- uint32_t phy_int_mask;
111
+ Lan9118PhyState mii;
112
+ IRQState mii_irq;
113
114
int32_t eeprom_writable;
115
uint8_t eeprom[128];
116
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
117
118
static const VMStateDescription vmstate_lan9118 = {
119
.name = "lan9118",
120
- .version_id = 2,
121
- .minimum_version_id = 1,
122
+ .version_id = 3,
123
+ .minimum_version_id = 3,
124
.fields = (const VMStateField[]) {
125
VMSTATE_PTIMER(timer, lan9118_state),
126
VMSTATE_UINT32(irq_cfg, lan9118_state),
127
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118 = {
128
VMSTATE_UINT32(mac_mii_acc, lan9118_state),
129
VMSTATE_UINT32(mac_mii_data, lan9118_state),
130
VMSTATE_UINT32(mac_flow, lan9118_state),
131
- VMSTATE_UINT32(phy_status, lan9118_state),
132
- VMSTATE_UINT32(phy_control, lan9118_state),
133
- VMSTATE_UINT32(phy_advertise, lan9118_state),
134
- VMSTATE_UINT32(phy_int, lan9118_state),
135
- VMSTATE_UINT32(phy_int_mask, lan9118_state),
136
VMSTATE_INT32(eeprom_writable, lan9118_state),
137
VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128),
138
VMSTATE_INT32(tx_fifo_size, lan9118_state),
139
@@ -XXX,XX +XXX,XX @@ static void lan9118_reload_eeprom(lan9118_state *s)
140
lan9118_mac_changed(s);
141
}
142
143
-static void phy_update_irq(lan9118_state *s)
144
+static void lan9118_update_irq(void *opaque, int n, int level)
145
{
146
- if (s->phy_int & s->phy_int_mask) {
147
+ lan9118_state *s = opaque;
148
+
149
+ if (level) {
150
s->int_sts |= PHY_INT;
151
} else {
152
s->int_sts &= ~PHY_INT;
153
@@ -XXX,XX +XXX,XX @@ static void phy_update_irq(lan9118_state *s)
154
lan9118_update(s);
155
}
156
157
-static void phy_update_link(lan9118_state *s)
158
-{
159
- /* Autonegotiation status mirrors link status. */
160
- if (qemu_get_queue(s->nic)->link_down) {
161
- s->phy_status &= ~0x0024;
162
- s->phy_int |= PHY_INT_DOWN;
163
- } else {
164
- s->phy_status |= 0x0024;
165
- s->phy_int |= PHY_INT_ENERGYON;
166
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
167
- }
168
- phy_update_irq(s);
169
-}
170
-
171
static void lan9118_set_link(NetClientState *nc)
172
{
173
- phy_update_link(qemu_get_nic_opaque(nc));
174
-}
175
-
176
-static void phy_reset(lan9118_state *s)
177
-{
178
- s->phy_status = 0x7809;
179
- s->phy_control = 0x3000;
180
- s->phy_advertise = 0x01e1;
181
- s->phy_int_mask = 0;
182
- s->phy_int = 0;
183
- phy_update_link(s);
184
+ lan9118_phy_update_link(&LAN9118(qemu_get_nic_opaque(nc))->mii,
185
+ nc->link_down);
186
}
187
188
static void lan9118_reset(DeviceState *d)
189
@@ -XXX,XX +XXX,XX @@ static void lan9118_reset(DeviceState *d)
190
s->read_word_n = 0;
191
s->write_word_n = 0;
192
193
- phy_reset(s);
194
-
195
s->eeprom_writable = 0;
196
lan9118_reload_eeprom(s);
197
}
198
@@ -XXX,XX +XXX,XX @@ static void do_tx_packet(lan9118_state *s)
199
uint32_t status;
200
201
/* FIXME: Honor TX disable, and allow queueing of packets. */
202
- if (s->phy_control & 0x4000) {
203
+ if (s->mii.control & 0x4000) {
204
/* This assumes the receive routine doesn't touch the VLANClient. */
205
qemu_receive_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len);
206
} else {
207
@@ -XXX,XX +XXX,XX @@ static void tx_fifo_push(lan9118_state *s, uint32_t val)
94
}
208
}
95
}
209
}
96
210
97
-/* Generate code to do a "long" addition or subtraction, ie one done in
211
-static uint32_t do_phy_read(lan9118_state *s, int reg)
98
- * TCGv_i64 on vector lanes twice the width specified by size.
99
- */
100
-static void gen_neon_addl(int size, bool is_sub, TCGv_i64 tcg_res,
101
- TCGv_i64 tcg_op1, TCGv_i64 tcg_op2)
102
-{
212
-{
103
- static NeonGenTwo64OpFn * const fns[3][2] = {
213
- uint32_t val;
104
- { gen_helper_neon_addl_u16, gen_helper_neon_subl_u16 },
214
-
105
- { gen_helper_neon_addl_u32, gen_helper_neon_subl_u32 },
215
- switch (reg) {
106
- { tcg_gen_add_i64, tcg_gen_sub_i64 },
216
- case 0: /* Basic Control */
107
- };
217
- return s->phy_control;
108
- NeonGenTwo64OpFn *genfn;
218
- case 1: /* Basic Status */
109
- assert(size < 3);
219
- return s->phy_status;
110
-
220
- case 2: /* ID1 */
111
- genfn = fns[size][is_sub];
221
- return 0x0007;
112
- genfn(tcg_res, tcg_op1, tcg_op2);
222
- case 3: /* ID2 */
223
- return 0xc0d1;
224
- case 4: /* Auto-neg advertisement */
225
- return s->phy_advertise;
226
- case 5: /* Auto-neg Link Partner Ability */
227
- return 0x0f71;
228
- case 6: /* Auto-neg Expansion */
229
- return 1;
230
- /* TODO 17, 18, 27, 29, 30, 31 */
231
- case 29: /* Interrupt source. */
232
- val = s->phy_int;
233
- s->phy_int = 0;
234
- phy_update_irq(s);
235
- return val;
236
- case 30: /* Interrupt mask */
237
- return s->phy_int_mask;
238
- default:
239
- qemu_log_mask(LOG_GUEST_ERROR,
240
- "do_phy_read: PHY read reg %d\n", reg);
241
- return 0;
242
- }
113
-}
243
-}
114
-
244
-
115
-static void do_narrow_round_high_u32(TCGv_i32 res, TCGv_i64 in)
245
-static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
116
-{
246
-{
117
- tcg_gen_addi_i64(in, in, 1U << 31);
247
- switch (reg) {
118
- tcg_gen_extrh_i64_i32(res, in);
248
- case 0: /* Basic Control */
249
- if (val & 0x8000) {
250
- phy_reset(s);
251
- break;
252
- }
253
- s->phy_control = val & 0x7980;
254
- /* Complete autonegotiation immediately. */
255
- if (val & 0x1000) {
256
- s->phy_status |= 0x0020;
257
- }
258
- break;
259
- case 4: /* Auto-neg advertisement */
260
- s->phy_advertise = (val & 0x2d7f) | 0x80;
261
- break;
262
- /* TODO 17, 18, 27, 31 */
263
- case 30: /* Interrupt mask */
264
- s->phy_int_mask = val & 0xff;
265
- phy_update_irq(s);
266
- break;
267
- default:
268
- qemu_log_mask(LOG_GUEST_ERROR,
269
- "do_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
270
- }
119
-}
271
-}
120
-
272
-
121
-static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size,
273
static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
122
- int opcode, int rd, int rn, int rm)
274
{
123
-{
275
switch (reg) {
124
- TCGv_i32 tcg_res[2];
276
@@ -XXX,XX +XXX,XX @@ static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
125
- int part = is_q ? 2 : 0;
277
if (val & 2) {
126
- int pass;
278
DPRINTF("PHY write %d = 0x%04x\n",
127
-
279
(val >> 6) & 0x1f, s->mac_mii_data);
128
- for (pass = 0; pass < 2; pass++) {
280
- do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data);
129
- TCGv_i64 tcg_op1 = tcg_temp_new_i64();
281
+ lan9118_phy_write(&s->mii, (val >> 6) & 0x1f, s->mac_mii_data);
130
- TCGv_i64 tcg_op2 = tcg_temp_new_i64();
282
} else {
131
- TCGv_i64 tcg_wideres = tcg_temp_new_i64();
283
- s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f);
132
- static NeonGenNarrowFn * const narrowfns[3][2] = {
284
+ s->mac_mii_data = lan9118_phy_read(&s->mii, (val >> 6) & 0x1f);
133
- { gen_helper_neon_narrow_high_u8,
285
DPRINTF("PHY read %d = 0x%04x\n",
134
- gen_helper_neon_narrow_round_high_u8 },
286
(val >> 6) & 0x1f, s->mac_mii_data);
135
- { gen_helper_neon_narrow_high_u16,
287
}
136
- gen_helper_neon_narrow_round_high_u16 },
288
@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
137
- { tcg_gen_extrh_i64_i32, do_narrow_round_high_u32 },
289
break;
138
- };
290
case CSR_PMT_CTRL:
139
- NeonGenNarrowFn *gennarrow = narrowfns[size][is_u];
291
if (val & 0x400) {
140
-
292
- phy_reset(s);
141
- read_vec_element(s, tcg_op1, rn, pass, MO_64);
293
+ lan9118_phy_reset(&s->mii);
142
- read_vec_element(s, tcg_op2, rm, pass, MO_64);
294
}
143
-
295
s->pmt_ctrl &= ~0x34e;
144
- gen_neon_addl(size, (opcode == 6), tcg_wideres, tcg_op1, tcg_op2);
296
s->pmt_ctrl |= (val & 0x34e);
145
-
297
@@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp)
146
- tcg_res[pass] = tcg_temp_new_i32();
298
const MemoryRegionOps *mem_ops =
147
- gennarrow(tcg_res[pass], tcg_wideres);
299
s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops;
148
- }
300
149
-
301
+ qemu_init_irq(&s->mii_irq, lan9118_update_irq, s, 0);
150
- for (pass = 0; pass < 2; pass++) {
302
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
151
- write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32);
303
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
152
- }
304
+ return;
153
- clear_vec_high(s, is_q, rd);
305
+ }
154
-}
306
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
155
-
307
+
156
/* AdvSIMD three different
308
memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s,
157
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
309
"lan9118-mmio", 0x100);
158
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
310
sysbus_init_mmio(sbd, &s->mmio);
159
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
311
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
160
int rd = extract32(insn, 0, 5);
312
new file mode 100644
161
313
index XXXXXXX..XXXXXXX
162
switch (opcode) {
314
--- /dev/null
163
- case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
315
+++ b/hw/net/lan9118_phy.c
164
- case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
316
@@ -XXX,XX +XXX,XX @@
165
- /* 128 x 128 -> 64 */
317
+/*
166
- if (size == 3) {
318
+ * SMSC LAN9118 PHY emulation
167
- unallocated_encoding(s);
319
+ *
168
- return;
320
+ * Copyright (c) 2009 CodeSourcery, LLC.
169
- }
321
+ * Written by Paul Brook
170
- if (!fp_access_check(s)) {
322
+ *
171
- return;
323
+ * This code is licensed under the GNU GPL v2
172
- }
324
+ *
173
- handle_3rd_narrowing(s, is_q, is_u, size, opcode, rd, rn, rm);
325
+ * Contributions after 2012-01-13 are licensed under the terms of the
174
- break;
326
+ * GNU GPL, version 2 or (at your option) any later version.
175
case 14: /* PMULL, PMULL2 */
327
+ */
176
if (is_u) {
328
+
177
unallocated_encoding(s);
329
+#include "qemu/osdep.h"
178
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
330
+#include "hw/net/lan9118_phy.h"
179
case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
331
+#include "hw/irq.h"
180
case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
332
+#include "hw/resettable.h"
181
case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
333
+#include "migration/vmstate.h"
182
+ case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
334
+#include "qemu/log.h"
183
case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
335
+
184
+ case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
336
+#define PHY_INT_ENERGYON (1 << 7)
185
case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
337
+#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
186
case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
338
+#define PHY_INT_FAULT (1 << 5)
187
case 9: /* SQDMLAL, SQDMLAL2 */
339
+#define PHY_INT_DOWN (1 << 4)
340
+#define PHY_INT_AUTONEG_LP (1 << 3)
341
+#define PHY_INT_PARFAULT (1 << 2)
342
+#define PHY_INT_AUTONEG_PAGE (1 << 1)
343
+
344
+static void lan9118_phy_update_irq(Lan9118PhyState *s)
345
+{
346
+ qemu_set_irq(s->irq, !!(s->ints & s->int_mask));
347
+}
348
+
349
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
350
+{
351
+ uint16_t val;
352
+
353
+ switch (reg) {
354
+ case 0: /* Basic Control */
355
+ return s->control;
356
+ case 1: /* Basic Status */
357
+ return s->status;
358
+ case 2: /* ID1 */
359
+ return 0x0007;
360
+ case 3: /* ID2 */
361
+ return 0xc0d1;
362
+ case 4: /* Auto-neg advertisement */
363
+ return s->advertise;
364
+ case 5: /* Auto-neg Link Partner Ability */
365
+ return 0x0f71;
366
+ case 6: /* Auto-neg Expansion */
367
+ return 1;
368
+ /* TODO 17, 18, 27, 29, 30, 31 */
369
+ case 29: /* Interrupt source. */
370
+ val = s->ints;
371
+ s->ints = 0;
372
+ lan9118_phy_update_irq(s);
373
+ return val;
374
+ case 30: /* Interrupt mask */
375
+ return s->int_mask;
376
+ default:
377
+ qemu_log_mask(LOG_GUEST_ERROR,
378
+ "lan9118_phy_read: PHY read reg %d\n", reg);
379
+ return 0;
380
+ }
381
+}
382
+
383
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
384
+{
385
+ switch (reg) {
386
+ case 0: /* Basic Control */
387
+ if (val & 0x8000) {
388
+ lan9118_phy_reset(s);
389
+ break;
390
+ }
391
+ s->control = val & 0x7980;
392
+ /* Complete autonegotiation immediately. */
393
+ if (val & 0x1000) {
394
+ s->status |= 0x0020;
395
+ }
396
+ break;
397
+ case 4: /* Auto-neg advertisement */
398
+ s->advertise = (val & 0x2d7f) | 0x80;
399
+ break;
400
+ /* TODO 17, 18, 27, 31 */
401
+ case 30: /* Interrupt mask */
402
+ s->int_mask = val & 0xff;
403
+ lan9118_phy_update_irq(s);
404
+ break;
405
+ default:
406
+ qemu_log_mask(LOG_GUEST_ERROR,
407
+ "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
408
+ }
409
+}
410
+
411
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
412
+{
413
+ s->link_down = link_down;
414
+
415
+ /* Autonegotiation status mirrors link status. */
416
+ if (link_down) {
417
+ s->status &= ~0x0024;
418
+ s->ints |= PHY_INT_DOWN;
419
+ } else {
420
+ s->status |= 0x0024;
421
+ s->ints |= PHY_INT_ENERGYON;
422
+ s->ints |= PHY_INT_AUTONEG_COMPLETE;
423
+ }
424
+ lan9118_phy_update_irq(s);
425
+}
426
+
427
+void lan9118_phy_reset(Lan9118PhyState *s)
428
+{
429
+ s->control = 0x3000;
430
+ s->status = 0x7809;
431
+ s->advertise = 0x01e1;
432
+ s->int_mask = 0;
433
+ s->ints = 0;
434
+ lan9118_phy_update_link(s, s->link_down);
435
+}
436
+
437
+static void lan9118_phy_reset_hold(Object *obj, ResetType type)
438
+{
439
+ Lan9118PhyState *s = LAN9118_PHY(obj);
440
+
441
+ lan9118_phy_reset(s);
442
+}
443
+
444
+static void lan9118_phy_init(Object *obj)
445
+{
446
+ Lan9118PhyState *s = LAN9118_PHY(obj);
447
+
448
+ qdev_init_gpio_out(DEVICE(s), &s->irq, 1);
449
+}
450
+
451
+static const VMStateDescription vmstate_lan9118_phy = {
452
+ .name = "lan9118-phy",
453
+ .version_id = 1,
454
+ .minimum_version_id = 1,
455
+ .fields = (const VMStateField[]) {
456
+ VMSTATE_UINT16(control, Lan9118PhyState),
457
+ VMSTATE_UINT16(status, Lan9118PhyState),
458
+ VMSTATE_UINT16(advertise, Lan9118PhyState),
459
+ VMSTATE_UINT16(ints, Lan9118PhyState),
460
+ VMSTATE_UINT16(int_mask, Lan9118PhyState),
461
+ VMSTATE_BOOL(link_down, Lan9118PhyState),
462
+ VMSTATE_END_OF_LIST()
463
+ }
464
+};
465
+
466
+static void lan9118_phy_class_init(ObjectClass *klass, void *data)
467
+{
468
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
469
+ DeviceClass *dc = DEVICE_CLASS(klass);
470
+
471
+ rc->phases.hold = lan9118_phy_reset_hold;
472
+ dc->vmsd = &vmstate_lan9118_phy;
473
+}
474
+
475
+static const TypeInfo types[] = {
476
+ {
477
+ .name = TYPE_LAN9118_PHY,
478
+ .parent = TYPE_SYS_BUS_DEVICE,
479
+ .instance_size = sizeof(Lan9118PhyState),
480
+ .instance_init = lan9118_phy_init,
481
+ .class_init = lan9118_phy_class_init,
482
+ }
483
+};
484
+
485
+DEFINE_TYPES(types)
486
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
487
index XXXXXXX..XXXXXXX 100644
488
--- a/hw/net/Kconfig
489
+++ b/hw/net/Kconfig
490
@@ -XXX,XX +XXX,XX @@ config VMXNET3_PCI
491
config SMC91C111
492
bool
493
494
+config LAN9118_PHY
495
+ bool
496
+
497
config LAN9118
498
bool
499
+ select LAN9118_PHY
500
select PTIMER
501
502
config NE2000_ISA
503
diff --git a/hw/net/meson.build b/hw/net/meson.build
504
index XXXXXXX..XXXXXXX 100644
505
--- a/hw/net/meson.build
506
+++ b/hw/net/meson.build
507
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_VMXNET3_PCI', if_true: files('vmxnet3.c'))
508
509
system_ss.add(when: 'CONFIG_SMC91C111', if_true: files('smc91c111.c'))
510
system_ss.add(when: 'CONFIG_LAN9118', if_true: files('lan9118.c'))
511
+system_ss.add(when: 'CONFIG_LAN9118_PHY', if_true: files('lan9118_phy.c'))
512
system_ss.add(when: 'CONFIG_NE2000_ISA', if_true: files('ne2000-isa.c'))
513
system_ss.add(when: 'CONFIG_OPENCORES_ETH', if_true: files('opencores_eth.c'))
514
system_ss.add(when: 'CONFIG_XGMAC', if_true: files('xgmac.c'))
188
--
515
--
189
2.34.1
516
2.34.1
diff view generated by jsdifflib
New patch
[PULL 02/72] hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
1
From: Bernhard Beschow <shentey@gmail.com>
1
2
3
imx_fec models the same PHY as lan9118_phy. The code is almost the same with
4
imx_fec having more logging and tracing. Merge these improvements into
5
lan9118_phy and reuse in imx_fec to fix the code duplication.
6
7
Some migration state how resides in the new device model which breaks migration
8
compatibility for the following machines:
9
* imx25-pdk
10
* sabrelite
11
* mcimx7d-sabre
12
* mcimx6ul-evk
13
14
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
15
Tested-by: Guenter Roeck <linux@roeck-us.net>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Message-id: 20241102125724.532843-3-shentey@gmail.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
include/hw/net/imx_fec.h | 9 ++-
21
hw/net/imx_fec.c | 146 ++++-----------------------------------
22
hw/net/lan9118_phy.c | 82 ++++++++++++++++------
23
hw/net/Kconfig | 1 +
24
hw/net/trace-events | 10 +--
25
5 files changed, 85 insertions(+), 163 deletions(-)
26
27
diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
28
index XXXXXXX..XXXXXXX 100644
29
--- a/include/hw/net/imx_fec.h
30
+++ b/include/hw/net/imx_fec.h
31
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXFECState, IMX_FEC)
32
#define TYPE_IMX_ENET "imx.enet"
33
34
#include "hw/sysbus.h"
35
+#include "hw/net/lan9118_phy.h"
36
+#include "hw/irq.h"
37
#include "net/net.h"
38
39
#define ENET_EIR 1
40
@@ -XXX,XX +XXX,XX @@ struct IMXFECState {
41
uint32_t tx_descriptor[ENET_TX_RING_NUM];
42
uint32_t tx_ring_num;
43
44
- uint32_t phy_status;
45
- uint32_t phy_control;
46
- uint32_t phy_advertise;
47
- uint32_t phy_int;
48
- uint32_t phy_int_mask;
49
+ Lan9118PhyState mii;
50
+ IRQState mii_irq;
51
uint32_t phy_num;
52
bool phy_connected;
53
struct IMXFECState *phy_consumer;
54
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/net/imx_fec.c
57
+++ b/hw/net/imx_fec.c
58
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth_txdescs = {
59
60
static const VMStateDescription vmstate_imx_eth = {
61
.name = TYPE_IMX_FEC,
62
- .version_id = 2,
63
- .minimum_version_id = 2,
64
+ .version_id = 3,
65
+ .minimum_version_id = 3,
66
.fields = (const VMStateField[]) {
67
VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX),
68
VMSTATE_UINT32(rx_descriptor, IMXFECState),
69
VMSTATE_UINT32(tx_descriptor[0], IMXFECState),
70
- VMSTATE_UINT32(phy_status, IMXFECState),
71
- VMSTATE_UINT32(phy_control, IMXFECState),
72
- VMSTATE_UINT32(phy_advertise, IMXFECState),
73
- VMSTATE_UINT32(phy_int, IMXFECState),
74
- VMSTATE_UINT32(phy_int_mask, IMXFECState),
75
VMSTATE_END_OF_LIST()
76
},
77
.subsections = (const VMStateDescription * const []) {
78
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth = {
79
},
80
};
81
82
-#define PHY_INT_ENERGYON (1 << 7)
83
-#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
84
-#define PHY_INT_FAULT (1 << 5)
85
-#define PHY_INT_DOWN (1 << 4)
86
-#define PHY_INT_AUTONEG_LP (1 << 3)
87
-#define PHY_INT_PARFAULT (1 << 2)
88
-#define PHY_INT_AUTONEG_PAGE (1 << 1)
89
-
90
static void imx_eth_update(IMXFECState *s);
91
92
/*
93
@@ -XXX,XX +XXX,XX @@ static void imx_eth_update(IMXFECState *s);
94
* For now we don't handle any GPIO/interrupt line, so the OS will
95
* have to poll for the PHY status.
96
*/
97
-static void imx_phy_update_irq(IMXFECState *s)
98
+static void imx_phy_update_irq(void *opaque, int n, int level)
99
{
100
- imx_eth_update(s);
101
-}
102
-
103
-static void imx_phy_update_link(IMXFECState *s)
104
-{
105
- /* Autonegotiation status mirrors link status. */
106
- if (qemu_get_queue(s->nic)->link_down) {
107
- trace_imx_phy_update_link("down");
108
- s->phy_status &= ~0x0024;
109
- s->phy_int |= PHY_INT_DOWN;
110
- } else {
111
- trace_imx_phy_update_link("up");
112
- s->phy_status |= 0x0024;
113
- s->phy_int |= PHY_INT_ENERGYON;
114
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
115
- }
116
- imx_phy_update_irq(s);
117
+ imx_eth_update(opaque);
118
}
119
120
static void imx_eth_set_link(NetClientState *nc)
121
{
122
- imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc)));
123
-}
124
-
125
-static void imx_phy_reset(IMXFECState *s)
126
-{
127
- trace_imx_phy_reset();
128
-
129
- s->phy_status = 0x7809;
130
- s->phy_control = 0x3000;
131
- s->phy_advertise = 0x01e1;
132
- s->phy_int_mask = 0;
133
- s->phy_int = 0;
134
- imx_phy_update_link(s);
135
+ lan9118_phy_update_link(&IMX_FEC(qemu_get_nic_opaque(nc))->mii,
136
+ nc->link_down);
137
}
138
139
static uint32_t imx_phy_read(IMXFECState *s, int reg)
140
{
141
- uint32_t val;
142
uint32_t phy = reg / 32;
143
144
if (!s->phy_connected) {
145
@@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
146
147
reg %= 32;
148
149
- switch (reg) {
150
- case 0: /* Basic Control */
151
- val = s->phy_control;
152
- break;
153
- case 1: /* Basic Status */
154
- val = s->phy_status;
155
- break;
156
- case 2: /* ID1 */
157
- val = 0x0007;
158
- break;
159
- case 3: /* ID2 */
160
- val = 0xc0d1;
161
- break;
162
- case 4: /* Auto-neg advertisement */
163
- val = s->phy_advertise;
164
- break;
165
- case 5: /* Auto-neg Link Partner Ability */
166
- val = 0x0f71;
167
- break;
168
- case 6: /* Auto-neg Expansion */
169
- val = 1;
170
- break;
171
- case 29: /* Interrupt source. */
172
- val = s->phy_int;
173
- s->phy_int = 0;
174
- imx_phy_update_irq(s);
175
- break;
176
- case 30: /* Interrupt mask */
177
- val = s->phy_int_mask;
178
- break;
179
- case 17:
180
- case 18:
181
- case 27:
182
- case 31:
183
- qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n",
184
- TYPE_IMX_FEC, __func__, reg);
185
- val = 0;
186
- break;
187
- default:
188
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
189
- TYPE_IMX_FEC, __func__, reg);
190
- val = 0;
191
- break;
192
- }
193
-
194
- trace_imx_phy_read(val, phy, reg);
195
-
196
- return val;
197
+ return lan9118_phy_read(&s->mii, reg);
198
}
199
200
static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
201
@@ -XXX,XX +XXX,XX @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
202
203
reg %= 32;
204
205
- trace_imx_phy_write(val, phy, reg);
206
-
207
- switch (reg) {
208
- case 0: /* Basic Control */
209
- if (val & 0x8000) {
210
- imx_phy_reset(s);
211
- } else {
212
- s->phy_control = val & 0x7980;
213
- /* Complete autonegotiation immediately. */
214
- if (val & 0x1000) {
215
- s->phy_status |= 0x0020;
216
- }
217
- }
218
- break;
219
- case 4: /* Auto-neg advertisement */
220
- s->phy_advertise = (val & 0x2d7f) | 0x80;
221
- break;
222
- case 30: /* Interrupt mask */
223
- s->phy_int_mask = val & 0xff;
224
- imx_phy_update_irq(s);
225
- break;
226
- case 17:
227
- case 18:
228
- case 27:
229
- case 31:
230
- qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n",
231
- TYPE_IMX_FEC, __func__, reg);
232
- break;
233
- default:
234
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
235
- TYPE_IMX_FEC, __func__, reg);
236
- break;
237
- }
238
+ lan9118_phy_write(&s->mii, reg, val);
239
}
240
241
static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr)
242
@@ -XXX,XX +XXX,XX @@ static void imx_eth_reset(DeviceState *d)
243
244
s->rx_descriptor = 0;
245
memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor));
246
-
247
- /* We also reset the PHY */
248
- imx_phy_reset(s);
249
}
250
251
static uint32_t imx_default_read(IMXFECState *s, uint32_t index)
252
@@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
253
sysbus_init_irq(sbd, &s->irq[0]);
254
sysbus_init_irq(sbd, &s->irq[1]);
255
256
+ qemu_init_irq(&s->mii_irq, imx_phy_update_irq, s, 0);
257
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
258
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
259
+ return;
260
+ }
261
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
262
+
263
qemu_macaddr_default_if_unset(&s->conf.macaddr);
264
265
s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf,
266
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
267
index XXXXXXX..XXXXXXX 100644
268
--- a/hw/net/lan9118_phy.c
269
+++ b/hw/net/lan9118_phy.c
270
@@ -XXX,XX +XXX,XX @@
271
* Copyright (c) 2009 CodeSourcery, LLC.
272
* Written by Paul Brook
273
*
274
+ * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
275
+ *
276
* This code is licensed under the GNU GPL v2
277
*
278
* Contributions after 2012-01-13 are licensed under the terms of the
279
@@ -XXX,XX +XXX,XX @@
280
#include "hw/resettable.h"
281
#include "migration/vmstate.h"
282
#include "qemu/log.h"
283
+#include "trace.h"
284
285
#define PHY_INT_ENERGYON (1 << 7)
286
#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
287
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
288
289
switch (reg) {
290
case 0: /* Basic Control */
291
- return s->control;
292
+ val = s->control;
293
+ break;
294
case 1: /* Basic Status */
295
- return s->status;
296
+ val = s->status;
297
+ break;
298
case 2: /* ID1 */
299
- return 0x0007;
300
+ val = 0x0007;
301
+ break;
302
case 3: /* ID2 */
303
- return 0xc0d1;
304
+ val = 0xc0d1;
305
+ break;
306
case 4: /* Auto-neg advertisement */
307
- return s->advertise;
308
+ val = s->advertise;
309
+ break;
310
case 5: /* Auto-neg Link Partner Ability */
311
- return 0x0f71;
312
+ val = 0x0f71;
313
+ break;
314
case 6: /* Auto-neg Expansion */
315
- return 1;
316
- /* TODO 17, 18, 27, 29, 30, 31 */
317
+ val = 1;
318
+ break;
319
case 29: /* Interrupt source. */
320
val = s->ints;
321
s->ints = 0;
322
lan9118_phy_update_irq(s);
323
- return val;
324
+ break;
325
case 30: /* Interrupt mask */
326
- return s->int_mask;
327
+ val = s->int_mask;
328
+ break;
329
+ case 17:
330
+ case 18:
331
+ case 27:
332
+ case 31:
333
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
334
+ __func__, reg);
335
+ val = 0;
336
+ break;
337
default:
338
- qemu_log_mask(LOG_GUEST_ERROR,
339
- "lan9118_phy_read: PHY read reg %d\n", reg);
340
- return 0;
341
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
342
+ __func__, reg);
343
+ val = 0;
344
+ break;
345
}
346
+
347
+ trace_lan9118_phy_read(val, reg);
348
+
349
+ return val;
350
}
351
352
void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
353
{
354
+ trace_lan9118_phy_write(val, reg);
355
+
356
switch (reg) {
357
case 0: /* Basic Control */
358
if (val & 0x8000) {
359
lan9118_phy_reset(s);
360
- break;
361
- }
362
- s->control = val & 0x7980;
363
- /* Complete autonegotiation immediately. */
364
- if (val & 0x1000) {
365
- s->status |= 0x0020;
366
+ } else {
367
+ s->control = val & 0x7980;
368
+ /* Complete autonegotiation immediately. */
369
+ if (val & 0x1000) {
370
+ s->status |= 0x0020;
371
+ }
372
}
373
break;
374
case 4: /* Auto-neg advertisement */
375
s->advertise = (val & 0x2d7f) | 0x80;
376
break;
377
- /* TODO 17, 18, 27, 31 */
378
case 30: /* Interrupt mask */
379
s->int_mask = val & 0xff;
380
lan9118_phy_update_irq(s);
381
break;
382
+ case 17:
383
+ case 18:
384
+ case 27:
385
+ case 31:
386
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
387
+ __func__, reg);
388
+ break;
389
default:
390
- qemu_log_mask(LOG_GUEST_ERROR,
391
- "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
392
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
393
+ __func__, reg);
394
+ break;
395
}
396
}
397
398
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
399
400
/* Autonegotiation status mirrors link status. */
401
if (link_down) {
402
+ trace_lan9118_phy_update_link("down");
403
s->status &= ~0x0024;
404
s->ints |= PHY_INT_DOWN;
405
} else {
406
+ trace_lan9118_phy_update_link("up");
407
s->status |= 0x0024;
408
s->ints |= PHY_INT_ENERGYON;
409
s->ints |= PHY_INT_AUTONEG_COMPLETE;
410
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
411
412
void lan9118_phy_reset(Lan9118PhyState *s)
413
{
414
+ trace_lan9118_phy_reset();
415
+
416
s->control = 0x3000;
417
s->status = 0x7809;
418
s->advertise = 0x01e1;
419
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118_phy = {
420
.version_id = 1,
421
.minimum_version_id = 1,
422
.fields = (const VMStateField[]) {
423
- VMSTATE_UINT16(control, Lan9118PhyState),
424
VMSTATE_UINT16(status, Lan9118PhyState),
425
+ VMSTATE_UINT16(control, Lan9118PhyState),
426
VMSTATE_UINT16(advertise, Lan9118PhyState),
427
VMSTATE_UINT16(ints, Lan9118PhyState),
428
VMSTATE_UINT16(int_mask, Lan9118PhyState),
429
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
430
index XXXXXXX..XXXXXXX 100644
431
--- a/hw/net/Kconfig
432
+++ b/hw/net/Kconfig
433
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_SUN8I_EMAC
434
435
config IMX_FEC
436
bool
437
+ select LAN9118_PHY
438
439
config CADENCE
440
bool
441
diff --git a/hw/net/trace-events b/hw/net/trace-events
442
index XXXXXXX..XXXXXXX 100644
443
--- a/hw/net/trace-events
444
+++ b/hw/net/trace-events
445
@@ -XXX,XX +XXX,XX @@ allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u"
446
allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64
447
allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64
448
449
+# lan9118_phy.c
450
+lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16
451
+lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16
452
+lan9118_phy_update_link(const char *s) "%s"
453
+lan9118_phy_reset(void) ""
454
+
455
# lance.c
456
lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x"
457
lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x"
458
@@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries"
459
i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
460
461
# imx_fec.c
462
-imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]"
463
imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)"
464
-imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]"
465
imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)"
466
-imx_phy_update_link(const char *s) "%s"
467
-imx_phy_reset(void) ""
468
imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
469
imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x"
470
imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit"
471
--
472
2.34.1
diff view generated by jsdifflib
New patch
[PULL 03/72] hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
1
From: Bernhard Beschow <shentey@gmail.com>
1
2
3
Turns 0x70 into 0xe0 (== 0x70 << 1) which adds the missing MII_ANLPAR_TX and
4
fixes the MSB of selector field to be zero, as specified in the datasheet.
5
6
Fixes: 2a424990170b "LAN9118 emulation"
7
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
8
Tested-by: Guenter Roeck <linux@roeck-us.net>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20241102125724.532843-4-shentey@gmail.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/net/lan9118_phy.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/net/lan9118_phy.c
19
+++ b/hw/net/lan9118_phy.c
20
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
21
val = s->advertise;
22
break;
23
case 5: /* Auto-neg Link Partner Ability */
24
- val = 0x0f71;
25
+ val = 0x0fe1;
26
break;
27
case 6: /* Auto-neg Expansion */
28
val = 1;
29
--
30
2.34.1
diff view generated by jsdifflib
New patch
[PULL 04/72] hw/net/lan9118_phy: Reuse MII constants
1
From: Bernhard Beschow <shentey@gmail.com>
1
2
3
Prefer named constants over magic values for better readability.
4
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
7
Tested-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20241102125724.532843-5-shentey@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/net/mii.h | 6 +++++
12
hw/net/lan9118_phy.c | 63 ++++++++++++++++++++++++++++----------------
13
2 files changed, 46 insertions(+), 23 deletions(-)
14
15
diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/net/mii.h
18
+++ b/include/hw/net/mii.h
19
@@ -XXX,XX +XXX,XX @@
20
#define MII_BMSR_JABBER (1 << 1) /* Jabber detected */
21
#define MII_BMSR_EXTCAP (1 << 0) /* Ext-reg capability */
22
23
+#define MII_ANAR_RFAULT (1 << 13) /* Say we can detect faults */
24
#define MII_ANAR_PAUSE_ASYM (1 << 11) /* Try for asymmetric pause */
25
#define MII_ANAR_PAUSE (1 << 10) /* Try for pause */
26
#define MII_ANAR_TXFD (1 << 8)
27
@@ -XXX,XX +XXX,XX @@
28
#define MII_ANAR_10FD (1 << 6)
29
#define MII_ANAR_10 (1 << 5)
30
#define MII_ANAR_CSMACD (1 << 0)
31
+#define MII_ANAR_SELECT (0x001f) /* Selector bits */
32
33
#define MII_ANLPAR_ACK (1 << 14)
34
#define MII_ANLPAR_PAUSEASY (1 << 11) /* can pause asymmetrically */
35
@@ -XXX,XX +XXX,XX @@
36
#define RTL8201CP_PHYID1 0x0000
37
#define RTL8201CP_PHYID2 0x8201
38
39
+/* SMSC LAN9118 */
40
+#define SMSCLAN9118_PHYID1 0x0007
41
+#define SMSCLAN9118_PHYID2 0xc0d1
42
+
43
/* RealTek 8211E */
44
#define RTL8211E_PHYID1 0x001c
45
#define RTL8211E_PHYID2 0xc915
46
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/net/lan9118_phy.c
49
+++ b/hw/net/lan9118_phy.c
50
@@ -XXX,XX +XXX,XX @@
51
52
#include "qemu/osdep.h"
53
#include "hw/net/lan9118_phy.h"
54
+#include "hw/net/mii.h"
55
#include "hw/irq.h"
56
#include "hw/resettable.h"
57
#include "migration/vmstate.h"
58
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
59
uint16_t val;
60
61
switch (reg) {
62
- case 0: /* Basic Control */
63
+ case MII_BMCR:
64
val = s->control;
65
break;
66
- case 1: /* Basic Status */
67
+ case MII_BMSR:
68
val = s->status;
69
break;
70
- case 2: /* ID1 */
71
- val = 0x0007;
72
+ case MII_PHYID1:
73
+ val = SMSCLAN9118_PHYID1;
74
break;
75
- case 3: /* ID2 */
76
- val = 0xc0d1;
77
+ case MII_PHYID2:
78
+ val = SMSCLAN9118_PHYID2;
79
break;
80
- case 4: /* Auto-neg advertisement */
81
+ case MII_ANAR:
82
val = s->advertise;
83
break;
84
- case 5: /* Auto-neg Link Partner Ability */
85
- val = 0x0fe1;
86
+ case MII_ANLPAR:
87
+ val = MII_ANLPAR_PAUSEASY | MII_ANLPAR_PAUSE | MII_ANLPAR_T4 |
88
+ MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD |
89
+ MII_ANLPAR_10 | MII_ANLPAR_CSMACD;
90
break;
91
- case 6: /* Auto-neg Expansion */
92
- val = 1;
93
+ case MII_ANER:
94
+ val = MII_ANER_NWAY;
95
break;
96
case 29: /* Interrupt source. */
97
val = s->ints;
98
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
99
trace_lan9118_phy_write(val, reg);
100
101
switch (reg) {
102
- case 0: /* Basic Control */
103
- if (val & 0x8000) {
104
+ case MII_BMCR:
105
+ if (val & MII_BMCR_RESET) {
106
lan9118_phy_reset(s);
107
} else {
108
- s->control = val & 0x7980;
109
+ s->control = val & (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 |
110
+ MII_BMCR_AUTOEN | MII_BMCR_PDOWN | MII_BMCR_FD |
111
+ MII_BMCR_CTST);
112
/* Complete autonegotiation immediately. */
113
- if (val & 0x1000) {
114
- s->status |= 0x0020;
115
+ if (val & MII_BMCR_AUTOEN) {
116
+ s->status |= MII_BMSR_AN_COMP;
117
}
118
}
119
break;
120
- case 4: /* Auto-neg advertisement */
121
- s->advertise = (val & 0x2d7f) | 0x80;
122
+ case MII_ANAR:
123
+ s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
124
+ MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
125
+ MII_ANAR_SELECT))
126
+ | MII_ANAR_TX;
127
break;
128
case 30: /* Interrupt mask */
129
s->int_mask = val & 0xff;
130
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
131
/* Autonegotiation status mirrors link status. */
132
if (link_down) {
133
trace_lan9118_phy_update_link("down");
134
- s->status &= ~0x0024;
135
+ s->status &= ~(MII_BMSR_AN_COMP | MII_BMSR_LINK_ST);
136
s->ints |= PHY_INT_DOWN;
137
} else {
138
trace_lan9118_phy_update_link("up");
139
- s->status |= 0x0024;
140
+ s->status |= MII_BMSR_AN_COMP | MII_BMSR_LINK_ST;
141
s->ints |= PHY_INT_ENERGYON;
142
s->ints |= PHY_INT_AUTONEG_COMPLETE;
143
}
144
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_reset(Lan9118PhyState *s)
145
{
146
trace_lan9118_phy_reset();
147
148
- s->control = 0x3000;
149
- s->status = 0x7809;
150
- s->advertise = 0x01e1;
151
+ s->control = MII_BMCR_AUTOEN | MII_BMCR_SPEED100;
152
+ s->status = MII_BMSR_100TX_FD
153
+ | MII_BMSR_100TX_HD
154
+ | MII_BMSR_10T_FD
155
+ | MII_BMSR_10T_HD
156
+ | MII_BMSR_AUTONEG
157
+ | MII_BMSR_EXTCAP;
158
+ s->advertise = MII_ANAR_TXFD
159
+ | MII_ANAR_TX
160
+ | MII_ANAR_10FD
161
+ | MII_ANAR_10
162
+ | MII_ANAR_CSMACD;
163
s->int_mask = 0;
164
s->ints = 0;
165
lan9118_phy_update_link(s, s->link_down);
166
--
167
2.34.1
diff view generated by jsdifflib
New patch
[PULL 05/72] hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
1
From: Bernhard Beschow <shentey@gmail.com>
1
2
3
The real device advertises this mode and the device model already advertises
4
100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to
5
make the model more realistic.
6
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
9
Tested-by: Guenter Roeck <linux@roeck-us.net>
10
Message-id: 20241102125724.532843-6-shentey@gmail.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/net/lan9118_phy.c | 4 ++--
14
1 file changed, 2 insertions(+), 2 deletions(-)
15
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/net/lan9118_phy.c
19
+++ b/hw/net/lan9118_phy.c
20
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
21
break;
22
case MII_ANAR:
23
s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
24
- MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
25
- MII_ANAR_SELECT))
26
+ MII_ANAR_PAUSE | MII_ANAR_TXFD | MII_ANAR_10FD |
27
+ MII_ANAR_10 | MII_ANAR_SELECT))
28
| MII_ANAR_TX;
29
break;
30
case 30: /* Interrupt mask */
31
--
32
2.34.1
diff view generated by jsdifflib
New patch
[PULL 06/72] fpu: handle raising Invalid for infzero in pick_nan_muladd
1
For IEEE fused multiply-add, the (0 * inf) + NaN case should raise
2
Invalid for the multiplication of 0 by infinity. Currently we handle
3
this in the per-architecture ifdef ladder in pickNaNMulAdd().
4
However, since this isn't really architecture specific we can hoist
5
it up to the generic code.
1
6
7
For the cases where the infzero test in pickNaNMulAdd was
8
returning 2, we can delete the check entirely and allow the
9
code to fall into the normal pick-a-NaN handling, because this
10
will return 2 anyway (input 'c' being the only NaN in this case).
11
For the cases where infzero was returning 3 to indicate "return
12
the default NaN", we must retain that "return 3".
13
14
For Arm, this looks like it might be a behaviour change because we
15
used to set float_flag_invalid | float_flag_invalid_imz only if C is
16
a quiet NaN. However, it is not, because Arm target code never looks
17
at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we
18
already raised float_flag_invalid via the "abc_mask &
19
float_cmask_snan" check in pick_nan_muladd.
20
21
For any target architecture using the "default implementation" at the
22
bottom of the ifdef, this is a behaviour change but will be fixing a
23
bug (where we failed to raise the Invalid exception for (0 * inf +
24
QNaN). The architectures using the default case are:
25
* hppa
26
* i386
27
* sh4
28
* tricore
29
30
The x86, Tricore and SH4 CPU architecture manuals are clear that this
31
should have raised Invalid; HPPA is a bit vaguer but still seems
32
clear enough.
33
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
36
Message-id: 20241202131347.498124-2-peter.maydell@linaro.org
37
---
38
fpu/softfloat-parts.c.inc | 13 +++++++------
39
fpu/softfloat-specialize.c.inc | 29 +----------------------------
40
2 files changed, 8 insertions(+), 34 deletions(-)
41
42
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
43
index XXXXXXX..XXXXXXX 100644
44
--- a/fpu/softfloat-parts.c.inc
45
+++ b/fpu/softfloat-parts.c.inc
46
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
47
int ab_mask, int abc_mask)
48
{
49
int which;
50
+ bool infzero = (ab_mask == float_cmask_infzero);
51
52
if (unlikely(abc_mask & float_cmask_snan)) {
53
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
54
}
55
56
- which = pickNaNMulAdd(a->cls, b->cls, c->cls,
57
- ab_mask == float_cmask_infzero, s);
58
+ if (infzero) {
59
+ /* This is (0 * inf) + NaN or (inf * 0) + NaN */
60
+ float_raise(float_flag_invalid | float_flag_invalid_imz, s);
61
+ }
62
+
63
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
64
65
if (s->default_nan_mode || which == 3) {
66
- /*
67
- * Note that this check is after pickNaNMulAdd so that function
68
- * has an opportunity to set the Invalid flag for infzero.
69
- */
70
parts_default_nan(a, s);
71
return a;
72
}
73
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
74
index XXXXXXX..XXXXXXX 100644
75
--- a/fpu/softfloat-specialize.c.inc
76
+++ b/fpu/softfloat-specialize.c.inc
77
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
78
* the default NaN
79
*/
80
if (infzero && is_qnan(c_cls)) {
81
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
82
return 3;
83
}
84
85
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
86
* case sets InvalidOp and returns the default NaN
87
*/
88
if (infzero) {
89
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
90
return 3;
91
}
92
/* Prefer sNaN over qNaN, in the a, b, c order. */
93
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
94
* For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
95
* case sets InvalidOp and returns the input value 'c'
96
*/
97
- if (infzero) {
98
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
99
- return 2;
100
- }
101
/* Prefer sNaN over qNaN, in the c, a, b order. */
102
if (is_snan(c_cls)) {
103
return 2;
104
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
105
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
106
* case sets InvalidOp and returns the input value 'c'
107
*/
108
- if (infzero) {
109
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
110
- return 2;
111
- }
112
+
113
/* Prefer sNaN over qNaN, in the c, a, b order. */
114
if (is_snan(c_cls)) {
115
return 2;
116
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
117
* to return an input NaN if we have one (ie c) rather than generating
118
* a default NaN
119
*/
120
- if (infzero) {
121
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
122
- return 2;
123
- }
124
125
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
126
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
127
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
128
return 1;
129
}
130
#elif defined(TARGET_RISCV)
131
- /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
132
- if (infzero) {
133
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
134
- }
135
return 3; /* default NaN */
136
#elif defined(TARGET_S390X)
137
if (infzero) {
138
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
139
return 3;
140
}
141
142
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
143
return 2;
144
}
145
#elif defined(TARGET_SPARC)
146
- /* For (inf,0,nan) return c. */
147
- if (infzero) {
148
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
149
- return 2;
150
- }
151
/* Prefer SNaN over QNaN, order C, B, A. */
152
if (is_snan(c_cls)) {
153
return 2;
154
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
155
* For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
156
* an input NaN if we have one (ie c).
157
*/
158
- if (infzero) {
159
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
160
- return 2;
161
- }
162
if (status->use_first_nan) {
163
if (is_nan(a_cls)) {
164
return 0;
165
--
166
2.34.1
diff view generated by jsdifflib
New patch
[PULL 07/72] fpu: Check for default_nan_mode before calling pickNaNMulAdd
1
If the target sets default_nan_mode then we're always going to return
2
the default NaN, and pickNaNMulAdd() no longer has any side effects.
3
For consistency with pickNaN(), check for default_nan_mode before
4
calling pickNaNMulAdd().
1
5
6
When we convert pickNaNMulAdd() to allow runtime selection of the NaN
7
propagation rule, this means we won't have to make the targets which
8
use default_nan_mode also set a propagation rule.
9
10
Since RiscV always uses default_nan_mode, this allows us to remove
11
its ifdef case from pickNaNMulAdd().
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-3-peter.maydell@linaro.org
16
---
17
fpu/softfloat-parts.c.inc | 8 ++++++--
18
fpu/softfloat-specialize.c.inc | 9 +++++++--
19
2 files changed, 13 insertions(+), 4 deletions(-)
20
21
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
22
index XXXXXXX..XXXXXXX 100644
23
--- a/fpu/softfloat-parts.c.inc
24
+++ b/fpu/softfloat-parts.c.inc
25
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
26
float_raise(float_flag_invalid | float_flag_invalid_imz, s);
27
}
28
29
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
30
+ if (s->default_nan_mode) {
31
+ which = 3;
32
+ } else {
33
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
34
+ }
35
36
- if (s->default_nan_mode || which == 3) {
37
+ if (which == 3) {
38
parts_default_nan(a, s);
39
return a;
40
}
41
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
42
index XXXXXXX..XXXXXXX 100644
43
--- a/fpu/softfloat-specialize.c.inc
44
+++ b/fpu/softfloat-specialize.c.inc
45
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
46
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
47
bool infzero, float_status *status)
48
{
49
+ /*
50
+ * We guarantee not to require the target to tell us how to
51
+ * pick a NaN if we're always returning the default NaN.
52
+ * But if we're not in default-NaN mode then the target must
53
+ * specify.
54
+ */
55
+ assert(!status->default_nan_mode);
56
#if defined(TARGET_ARM)
57
/* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
58
* the default NaN
59
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
60
} else {
61
return 1;
62
}
63
-#elif defined(TARGET_RISCV)
64
- return 3; /* default NaN */
65
#elif defined(TARGET_S390X)
66
if (infzero) {
67
return 3;
68
--
69
2.34.1
diff view generated by jsdifflib
New patch
[PULL 08/72] softfloat: Allow runtime choice of inf * 0 + NaN result
1
1
IEEE 758 does not define a fixed rule for what NaN to return in
2
the case of a fused multiply-add of inf * 0 + NaN. Different
3
architectures thus do different things:
4
* some return the default NaN
5
* some return the input NaN
6
* Arm returns the default NaN if the input NaN is quiet,
7
and the input NaN if it is signalling
8
9
We want to make this logic be runtime selected rather than
10
hardcoded into the binary, because:
11
* this will let us have multiple targets in one QEMU binary
12
* the Arm FEAT_AFP architectural feature includes letting
13
the guest select a NaN propagation rule at runtime
14
15
In this commit we add an enum for the propagation rule, the field in
16
float_status, and the corresponding getters and setters. We change
17
pickNaNMulAdd to honour this, but because all targets still leave
18
this field at its default 0 value, the fallback logic will pick the
19
rule type with the old ifdef ladder.
20
21
Note that four architectures both use the muladd softfloat functions
22
and did not have a branch of the ifdef ladder to specify their
23
behaviour (and so were ending up with the "default" case, probably
24
wrongly): i386, HPPA, SH4 and Tricore. SH4 and Tricore both set
25
default_nan_mode, and so will never get into pickNaNMulAdd(). For
26
HPPA and i386 we retain the same behaviour as the old default-case,
27
which is to not ever return the default NaN. This might not be
28
correct but it is not a behaviour change.
29
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
32
Message-id: 20241202131347.498124-4-peter.maydell@linaro.org
33
---
34
include/fpu/softfloat-helpers.h | 11 ++++
35
include/fpu/softfloat-types.h | 23 +++++++++
36
fpu/softfloat-specialize.c.inc | 91 ++++++++++++++++++++++-----------
37
3 files changed, 95 insertions(+), 30 deletions(-)
38
39
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
40
index XXXXXXX..XXXXXXX 100644
41
--- a/include/fpu/softfloat-helpers.h
42
+++ b/include/fpu/softfloat-helpers.h
43
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
44
status->float_2nan_prop_rule = rule;
45
}
46
47
+static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
48
+ float_status *status)
49
+{
50
+ status->float_infzeronan_rule = rule;
51
+}
52
+
53
static inline void set_flush_to_zero(bool val, float_status *status)
54
{
55
status->flush_to_zero = val;
56
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
57
return status->float_2nan_prop_rule;
58
}
59
60
+static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
61
+{
62
+ return status->float_infzeronan_rule;
63
+}
64
+
65
static inline bool get_flush_to_zero(float_status *status)
66
{
67
return status->flush_to_zero;
68
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
69
index XXXXXXX..XXXXXXX 100644
70
--- a/include/fpu/softfloat-types.h
71
+++ b/include/fpu/softfloat-types.h
72
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
73
float_2nan_prop_x87,
74
} Float2NaNPropRule;
75
76
+/*
77
+ * Rule for result of fused multiply-add 0 * Inf + NaN.
78
+ * This must be a NaN, but implementations differ on whether this
79
+ * is the input NaN or the default NaN.
80
+ *
81
+ * You don't need to set this if default_nan_mode is enabled.
82
+ * When not in default-NaN mode, it is an error for the target
83
+ * not to set the rule in float_status if it uses muladd, and we
84
+ * will assert if we need to handle an input NaN and no rule was
85
+ * selected.
86
+ */
87
+typedef enum __attribute__((__packed__)) {
88
+ /* No propagation rule specified */
89
+ float_infzeronan_none = 0,
90
+ /* Result is never the default NaN (so always the input NaN) */
91
+ float_infzeronan_dnan_never,
92
+ /* Result is always the default NaN */
93
+ float_infzeronan_dnan_always,
94
+ /* Result is the default NaN if the input NaN is quiet */
95
+ float_infzeronan_dnan_if_qnan,
96
+} FloatInfZeroNaNRule;
97
+
98
/*
99
* Floating Point Status. Individual architectures may maintain
100
* several versions of float_status for different functions. The
101
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
102
FloatRoundMode float_rounding_mode;
103
FloatX80RoundPrec floatx80_rounding_precision;
104
Float2NaNPropRule float_2nan_prop_rule;
105
+ FloatInfZeroNaNRule float_infzeronan_rule;
106
bool tininess_before_rounding;
107
/* should denormalised results go to zero and set the inexact flag? */
108
bool flush_to_zero;
109
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
110
index XXXXXXX..XXXXXXX 100644
111
--- a/fpu/softfloat-specialize.c.inc
112
+++ b/fpu/softfloat-specialize.c.inc
113
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
114
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
115
bool infzero, float_status *status)
116
{
117
+ FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
118
+
119
/*
120
* We guarantee not to require the target to tell us how to
121
* pick a NaN if we're always returning the default NaN.
122
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
123
* specify.
124
*/
125
assert(!status->default_nan_mode);
126
+
127
+ if (rule == float_infzeronan_none) {
128
+ /*
129
+ * Temporarily fall back to ifdef ladder
130
+ */
131
#if defined(TARGET_ARM)
132
- /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
133
- * the default NaN
134
- */
135
- if (infzero && is_qnan(c_cls)) {
136
- return 3;
137
+ /*
138
+ * For ARM, the (inf,zero,qnan) case returns the default NaN,
139
+ * but (inf,zero,snan) returns the input NaN.
140
+ */
141
+ rule = float_infzeronan_dnan_if_qnan;
142
+#elif defined(TARGET_MIPS)
143
+ if (snan_bit_is_one(status)) {
144
+ /*
145
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
146
+ * case sets InvalidOp and returns the default NaN
147
+ */
148
+ rule = float_infzeronan_dnan_always;
149
+ } else {
150
+ /*
151
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
152
+ * case sets InvalidOp and returns the input value 'c'
153
+ */
154
+ rule = float_infzeronan_dnan_never;
155
+ }
156
+#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
157
+ defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
158
+ defined(TARGET_I386) || defined(TARGET_LOONGARCH)
159
+ /*
160
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
161
+ * case sets InvalidOp and returns the input value 'c'
162
+ */
163
+ /*
164
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
165
+ * to return an input NaN if we have one (ie c) rather than generating
166
+ * a default NaN
167
+ */
168
+ rule = float_infzeronan_dnan_never;
169
+#elif defined(TARGET_S390X)
170
+ rule = float_infzeronan_dnan_always;
171
+#endif
172
}
173
174
+ if (infzero) {
175
+ /*
176
+ * Inf * 0 + NaN -- some implementations return the default NaN here,
177
+ * and some return the input NaN.
178
+ */
179
+ switch (rule) {
180
+ case float_infzeronan_dnan_never:
181
+ return 2;
182
+ case float_infzeronan_dnan_always:
183
+ return 3;
184
+ case float_infzeronan_dnan_if_qnan:
185
+ return is_qnan(c_cls) ? 3 : 2;
186
+ default:
187
+ g_assert_not_reached();
188
+ }
189
+ }
190
+
191
+#if defined(TARGET_ARM)
192
+
193
/* This looks different from the ARM ARM pseudocode, because the ARM ARM
194
* puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
195
*/
196
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
197
}
198
#elif defined(TARGET_MIPS)
199
if (snan_bit_is_one(status)) {
200
- /*
201
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
202
- * case sets InvalidOp and returns the default NaN
203
- */
204
- if (infzero) {
205
- return 3;
206
- }
207
/* Prefer sNaN over qNaN, in the a, b, c order. */
208
if (is_snan(a_cls)) {
209
return 0;
210
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
211
return 2;
212
}
213
} else {
214
- /*
215
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
216
- * case sets InvalidOp and returns the input value 'c'
217
- */
218
/* Prefer sNaN over qNaN, in the c, a, b order. */
219
if (is_snan(c_cls)) {
220
return 2;
221
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
222
}
223
}
224
#elif defined(TARGET_LOONGARCH64)
225
- /*
226
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
227
- * case sets InvalidOp and returns the input value 'c'
228
- */
229
-
230
/* Prefer sNaN over qNaN, in the c, a, b order. */
231
if (is_snan(c_cls)) {
232
return 2;
233
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
234
return 1;
235
}
236
#elif defined(TARGET_PPC)
237
- /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
238
- * to return an input NaN if we have one (ie c) rather than generating
239
- * a default NaN
240
- */
241
-
242
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
243
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
244
*/
245
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
246
return 1;
247
}
248
#elif defined(TARGET_S390X)
249
- if (infzero) {
250
- return 3;
251
- }
252
-
253
if (is_snan(a_cls)) {
254
return 0;
255
} else if (is_snan(b_cls)) {
256
--
257
2.34.1
diff view generated by jsdifflib
New patch
[PULL 09/72] tests/fp: Explicitly set inf-zero-nan rule
1
Explicitly set a rule in the softfloat tests for the inf-zero-nan
2
muladd special case. In meson.build we put -DTARGET_ARM in fpcflags,
3
and so we should select here the Arm rule of
4
float_infzeronan_dnan_if_qnan.
1
5
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241202131347.498124-5-peter.maydell@linaro.org
9
---
10
tests/fp/fp-bench.c | 5 +++++
11
tests/fp/fp-test.c | 5 +++++
12
2 files changed, 10 insertions(+)
13
14
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/tests/fp/fp-bench.c
17
+++ b/tests/fp/fp-bench.c
18
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
19
{
20
bench_func_t f;
21
22
+ /*
23
+ * These implementation-defined choices for various things IEEE
24
+ * doesn't specify match those used by the Arm architecture.
25
+ */
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
28
29
f = bench_funcs[operation][precision];
30
g_assert(f);
31
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/tests/fp/fp-test.c
34
+++ b/tests/fp/fp-test.c
35
@@ -XXX,XX +XXX,XX @@ void run_test(void)
36
{
37
unsigned int i;
38
39
+ /*
40
+ * These implementation-defined choices for various things IEEE
41
+ * doesn't specify match those used by the Arm architecture.
42
+ */
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
44
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
45
46
genCases_setLevel(test_level);
47
verCases_maxErrorCount = n_max_errors;
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 10/72] target/arm: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the Arm target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-6-peter.maydell@linaro.org
7
---
8
target/arm/cpu.c | 3 +++
9
fpu/softfloat-specialize.c.inc | 8 +-------
10
2 files changed, 4 insertions(+), 7 deletions(-)
11
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
17
* * tininess-before-rounding
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
20
+ * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
21
+ * and the input NaN if it is signalling
22
*/
23
static void arm_set_default_fp_behaviours(float_status *s)
24
{
25
set_float_detect_tininess(float_tininess_before_rounding, s);
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
28
}
29
30
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
32
index XXXXXXX..XXXXXXX 100644
33
--- a/fpu/softfloat-specialize.c.inc
34
+++ b/fpu/softfloat-specialize.c.inc
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
36
/*
37
* Temporarily fall back to ifdef ladder
38
*/
39
-#if defined(TARGET_ARM)
40
- /*
41
- * For ARM, the (inf,zero,qnan) case returns the default NaN,
42
- * but (inf,zero,snan) returns the input NaN.
43
- */
44
- rule = float_infzeronan_dnan_if_qnan;
45
-#elif defined(TARGET_MIPS)
46
+#if defined(TARGET_MIPS)
47
if (snan_bit_is_one(status)) {
48
/*
49
* For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
50
--
51
2.34.1
diff view generated by jsdifflib
New patch
[PULL 11/72] target/s390: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for s390, so we
2
can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-7-peter.maydell@linaro.org
7
---
8
target/s390x/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
11
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/s390x/cpu.c
15
+++ b/target/s390x/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
17
set_float_detect_tininess(float_tininess_before_rounding,
18
&env->fpu_status);
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
20
+ set_float_infzeronan_rule(float_infzeronan_dnan_always,
21
+ &env->fpu_status);
22
/* fall through */
23
case RESET_TYPE_S390_CPU_NORMAL:
24
env->psw.mask &= ~PSW_MASK_RI;
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
* a default NaN
31
*/
32
rule = float_infzeronan_dnan_never;
33
-#elif defined(TARGET_S390X)
34
- rule = float_infzeronan_dnan_always;
35
#endif
36
}
37
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 12/72] target/ppc: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the PPC target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-8-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 7 +++++++
9
fpu/softfloat-specialize.c.inc | 7 +------
10
2 files changed, 8 insertions(+), 6 deletions(-)
11
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/ppc/cpu_init.c
15
+++ b/target/ppc/cpu_init.c
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
20
+ /*
21
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
22
+ * to return an input NaN if we have one (ie c) rather than generating
23
+ * a default NaN
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
26
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
27
28
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
29
ppc_spr_t *spr = &env->spr_cb[i];
30
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
31
index XXXXXXX..XXXXXXX 100644
32
--- a/fpu/softfloat-specialize.c.inc
33
+++ b/fpu/softfloat-specialize.c.inc
34
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
*/
36
rule = float_infzeronan_dnan_never;
37
}
38
-#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
39
+#elif defined(TARGET_SPARC) || \
40
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
41
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
42
/*
43
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
44
* case sets InvalidOp and returns the input value 'c'
45
*/
46
- /*
47
- * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
48
- * to return an input NaN if we have one (ie c) rather than generating
49
- * a default NaN
50
- */
51
rule = float_infzeronan_dnan_never;
52
#endif
53
}
54
--
55
2.34.1
diff view generated by jsdifflib
New patch
[PULL 13/72] target/mips: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the MIPS target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-9-peter.maydell@linaro.org
7
---
8
target/mips/fpu_helper.h | 9 +++++++++
9
target/mips/msa.c | 4 ++++
10
fpu/softfloat-specialize.c.inc | 16 +---------------
11
3 files changed, 14 insertions(+), 15 deletions(-)
12
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/mips/fpu_helper.h
16
+++ b/target/mips/fpu_helper.h
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_flush_mode(CPUMIPSState *env)
18
static inline void restore_snan_bit_mode(CPUMIPSState *env)
19
{
20
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
21
+ FloatInfZeroNaNRule izn_rule;
22
23
/*
24
* With nan2008, SNaNs are silenced in the usual way.
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
26
*/
27
set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status);
28
set_default_nan_mode(!nan2008, &env->active_fpu.fp_status);
29
+ /*
30
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
31
+ * case sets InvalidOp and returns the default NaN.
32
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
33
+ * case sets InvalidOp and returns the input value 'c'.
34
+ */
35
+ izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
36
+ set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
37
}
38
39
static inline void restore_fp_status(CPUMIPSState *env)
40
diff --git a/target/mips/msa.c b/target/mips/msa.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/mips/msa.c
43
+++ b/target/mips/msa.c
44
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
45
46
/* set proper signanling bit meaning ("1" means "quiet") */
47
set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
48
+
49
+ /* Inf * 0 + NaN returns the input NaN */
50
+ set_float_infzeronan_rule(float_infzeronan_dnan_never,
51
+ &env->active_tc.msa_fp_status);
52
}
53
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
54
index XXXXXXX..XXXXXXX 100644
55
--- a/fpu/softfloat-specialize.c.inc
56
+++ b/fpu/softfloat-specialize.c.inc
57
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
58
/*
59
* Temporarily fall back to ifdef ladder
60
*/
61
-#if defined(TARGET_MIPS)
62
- if (snan_bit_is_one(status)) {
63
- /*
64
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
65
- * case sets InvalidOp and returns the default NaN
66
- */
67
- rule = float_infzeronan_dnan_always;
68
- } else {
69
- /*
70
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
71
- * case sets InvalidOp and returns the input value 'c'
72
- */
73
- rule = float_infzeronan_dnan_never;
74
- }
75
-#elif defined(TARGET_SPARC) || \
76
+#if defined(TARGET_SPARC) || \
77
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
78
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
79
/*
80
--
81
2.34.1
diff view generated by jsdifflib
New patch
[PULL 14/72] target/sparc: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the SPARC target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-10-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
* the CPU state struct so it won't get zeroed on reset.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
20
+ /* For inf * 0 + NaN, return the input NaN */
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
23
cpu_exec_realizefn(cs, &local_err);
24
if (local_err != NULL) {
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
/*
31
* Temporarily fall back to ifdef ladder
32
*/
33
-#if defined(TARGET_SPARC) || \
34
- defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
35
+#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
36
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
37
/*
38
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 15/72] target/xtensa: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the xtensa target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-11-peter.maydell@linaro.org
7
---
8
target/xtensa/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 +-
10
2 files changed, 3 insertions(+), 1 deletion(-)
11
12
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/xtensa/cpu.c
15
+++ b/target/xtensa/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
17
reset_mmu(env);
18
cs->halted = env->runstall;
19
#endif
20
+ /* For inf * 0 + NaN, return the input NaN */
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
set_no_signaling_nans(!dfpu, &env->fp_status);
23
xtensa_use_first_nan(env, !dfpu);
24
}
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
/*
31
* Temporarily fall back to ifdef ladder
32
*/
33
-#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
34
+#if defined(TARGET_HPPA) || \
35
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
36
/*
37
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 16/72] target/x86: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the x86 target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-12-peter.maydell@linaro.org
6
---
7
target/i386/tcg/fpu_helper.c | 7 +++++++
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 8 insertions(+), 1 deletion(-)
10
11
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/i386/tcg/fpu_helper.c
14
+++ b/target/i386/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status);
18
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status);
19
+ /*
20
+ * Only SSE has multiply-add instructions. In the SDM Section 14.5.2
21
+ * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is
22
+ * specified -- for 0 * inf + NaN the input NaN is selected, and if
23
+ * there are multiple input NaNs they are selected in the order a, b, c.
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
26
}
27
28
static inline uint8_t save_exception_flags(CPUX86State *env)
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
31
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
34
* Temporarily fall back to ifdef ladder
35
*/
36
#if defined(TARGET_HPPA) || \
37
- defined(TARGET_I386) || defined(TARGET_LOONGARCH)
38
+ defined(TARGET_LOONGARCH)
39
/*
40
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
41
* case sets InvalidOp and returns the input value 'c'
42
--
43
2.34.1
diff view generated by jsdifflib
New patch
[PULL 17/72] target/loongarch: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the loongarch target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-13-peter.maydell@linaro.org
6
---
7
target/loongarch/tcg/fpu_helper.c | 5 +++++
8
fpu/softfloat-specialize.c.inc | 7 +------
9
2 files changed, 6 insertions(+), 6 deletions(-)
10
11
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/loongarch/tcg/fpu_helper.c
14
+++ b/target/loongarch/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
16
&env->fp_status);
17
set_flush_to_zero(0, &env->fp_status);
18
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
19
+ /*
20
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
21
+ * case sets InvalidOp and returns the input value 'c'
22
+ */
23
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
24
}
25
26
int ieee_ex_to_loongarch(int xcpt)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
29
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
32
/*
33
* Temporarily fall back to ifdef ladder
34
*/
35
-#if defined(TARGET_HPPA) || \
36
- defined(TARGET_LOONGARCH)
37
- /*
38
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
- * case sets InvalidOp and returns the input value 'c'
40
- */
41
+#if defined(TARGET_HPPA)
42
rule = float_infzeronan_dnan_never;
43
#endif
44
}
45
--
46
2.34.1
diff view generated by jsdifflib
New patch
[PULL 18/72] target/hppa: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the HPPA target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
As this is the last target to be converted to explicitly setting
5
the rule, we can remove the fallback code in pickNaNMulAdd()
6
entirely.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20241202131347.498124-14-peter.maydell@linaro.org
11
---
12
target/hppa/fpu_helper.c | 2 ++
13
fpu/softfloat-specialize.c.inc | 13 +------------
14
2 files changed, 3 insertions(+), 12 deletions(-)
15
16
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/hppa/fpu_helper.c
19
+++ b/target/hppa/fpu_helper.c
20
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
21
* HPPA does note implement a CPU reset method at all...
22
*/
23
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
24
+ /* For inf * 0 + NaN, return the input NaN */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
26
}
27
28
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
31
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
34
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
bool infzero, float_status *status)
36
{
37
- FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
38
-
39
/*
40
* We guarantee not to require the target to tell us how to
41
* pick a NaN if we're always returning the default NaN.
42
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
43
*/
44
assert(!status->default_nan_mode);
45
46
- if (rule == float_infzeronan_none) {
47
- /*
48
- * Temporarily fall back to ifdef ladder
49
- */
50
-#if defined(TARGET_HPPA)
51
- rule = float_infzeronan_dnan_never;
52
-#endif
53
- }
54
-
55
if (infzero) {
56
/*
57
* Inf * 0 + NaN -- some implementations return the default NaN here,
58
* and some return the input NaN.
59
*/
60
- switch (rule) {
61
+ switch (status->float_infzeronan_rule) {
62
case float_infzeronan_dnan_never:
63
return 2;
64
case float_infzeronan_dnan_always:
65
--
66
2.34.1
diff view generated by jsdifflib
New patch
[PULL 19/72] softfloat: Pass have_snan to pickNaNMulAdd
1
The new implementation of pickNaNMulAdd() will find it convenient
2
to know whether at least one of the three arguments to the muladd
3
was a signaling NaN. We already calculate that in the caller,
4
so pass it in as a new bool have_snan.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-15-peter.maydell@linaro.org
9
---
10
fpu/softfloat-parts.c.inc | 5 +++--
11
fpu/softfloat-specialize.c.inc | 2 +-
12
2 files changed, 4 insertions(+), 3 deletions(-)
13
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
16
--- a/fpu/softfloat-parts.c.inc
17
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
{
20
int which;
21
bool infzero = (ab_mask == float_cmask_infzero);
22
+ bool have_snan = (abc_mask & float_cmask_snan);
23
24
- if (unlikely(abc_mask & float_cmask_snan)) {
25
+ if (unlikely(have_snan)) {
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
27
}
28
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
30
if (s->default_nan_mode) {
31
which = 3;
32
} else {
33
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
34
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
35
}
36
37
if (which == 3) {
38
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
39
index XXXXXXX..XXXXXXX 100644
40
--- a/fpu/softfloat-specialize.c.inc
41
+++ b/fpu/softfloat-specialize.c.inc
42
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
43
| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
44
*----------------------------------------------------------------------------*/
45
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
46
- bool infzero, float_status *status)
47
+ bool infzero, bool have_snan, float_status *status)
48
{
49
/*
50
* We guarantee not to require the target to tell us how to
51
--
52
2.34.1
diff view generated by jsdifflib
[PULL 04/24] target/arm: Support migration when FPSR/FPCR won't fit in the FPSCR
[PULL 20/72] softfloat: Allow runtime choice of NaN propagation for muladd
1
To support FPSR and FPCR bits that don't exist in the AArch32 FPSCR
1
IEEE 758 does not define a fixed rule for which NaN to pick as the
2
view of floating point control and status (such as the FEAT_AFP ones),
2
result if both operands of a 3-operand fused multiply-add operation
3
we need to make sure those bits can be migrated. This commit allows
3
are NaNs. As a result different architectures have ended up with
4
that, whilst maintaining backwards and forwards migration compatibility
4
different rules for propagating NaNs.
5
for CPUs where there are no such bits:
5
6
6
QEMU currently hardcodes the NaN propagation logic into the binary
7
On sending:
7
because pickNaNMulAdd() has an ifdef ladder for different targets.
8
* If either the FPCR or the FPSR include set bits that are not
8
We want to make the propagation rule instead be selectable at
9
visible in the AArch32 FPSCR view of floating point control/status
9
runtime, because:
10
then we send the FPCR and FPSR as two separate fields in a new
10
* this will let us have multiple targets in one QEMU binary
11
cpu/vfp/fpcr_fpsr subsection, and we send a 0 for the old
11
* the Arm FEAT_AFP architectural feature includes letting
12
FPSCR field in cpu/vfp
12
the guest select a NaN propagation rule at runtime
13
* Otherwise, we don't send the fpcr_fpsr subsection, and we send
13
14
an FPSCR-format value in cpu/vfp as we did previously
14
In this commit we add an enum for the propagation rule, the field in
15
15
float_status, and the corresponding getters and setters. We change
16
On receiving:
16
pickNaNMulAdd to honour this, but because all targets still leave
17
* if we see a non-zero FPSCR field, that is the right information
17
this field at its default 0 value, the fallback logic will pick the
18
* if we see a fpcr_fpsr subsection then that has the information
18
rule type with the old ifdef ladder.
19
* if we see neither, then FPSCR/FPCR/FPSR are all zero on the source;
19
20
cpu_pre_load() ensures the CPU state defaults to that
20
It's valid not to set a propagation rule if default_nan_mode is
21
* if we see both, then the migration source is buggy or malicious;
21
enabled, because in that case there's no need to pick a NaN; all the
22
either the fpcr_fpsr or the FPSCR will "win" depending which
22
callers of pickNaNMulAdd() catch this case and skip calling it.
23
is first in the migration stream; we don't care which that is
24
25
We make the new FPCR and FPSR on-the-wire data be 64 bits, because
26
architecturally these registers are that wide, and this avoids the
27
need to engage in further migration-compatibility contortions in
28
future if some new architecture revision defines bits in the high
29
half of either register.
30
31
(We won't ever send the new migration subsection until we add support
32
for a CPU feature which enables setting overlapping FPCR bits, like
33
FEAT_AFP.)
34
23
35
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
36
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
37
Message-id: 20240628142347.1283015-5-peter.maydell@linaro.org
26
Message-id: 20241202131347.498124-16-peter.maydell@linaro.org
38
---
27
---
39
target/arm/machine.c | 134 ++++++++++++++++++++++++++++++++++++++++++-
28
include/fpu/softfloat-helpers.h | 11 +++
40
1 file changed, 132 insertions(+), 2 deletions(-)
29
include/fpu/softfloat-types.h | 55 +++++++++++
41
30
fpu/softfloat-specialize.c.inc | 167 ++++++++------------------------
42
diff --git a/target/arm/machine.c b/target/arm/machine.c
31
3 files changed, 107 insertions(+), 126 deletions(-)
32
33
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
43
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/machine.c
35
--- a/include/fpu/softfloat-helpers.h
45
+++ b/target/arm/machine.c
36
+++ b/include/fpu/softfloat-helpers.h
46
@@ -XXX,XX +XXX,XX @@ static bool vfp_needed(void *opaque)
37
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
47
: cpu_isar_feature(aa32_vfp_simd, cpu));
38
status->float_2nan_prop_rule = rule;
48
}
39
}
49
40
50
+static bool vfp_fpcr_fpsr_needed(void *opaque)
41
+static inline void set_float_3nan_prop_rule(Float3NaNPropRule rule,
42
+ float_status *status)
51
+{
43
+{
52
+ /*
44
+ status->float_3nan_prop_rule = rule;
53
+ * If either the FPCR or the FPSR include set bits that are not
54
+ * visible in the AArch32 FPSCR view of floating point control/status
55
+ * then we must send the FPCR and FPSR as two separate fields in the
56
+ * cpu/vfp/fpcr_fpsr subsection, and we will send a 0 for the old
57
+ * FPSCR field in cpu/vfp.
58
+ *
59
+ * If all the set bits are representable in an AArch32 FPSCR then we
60
+ * send that value as the cpu/vfp FPSCR field, and don't send the
61
+ * cpu/vfp/fpcr_fpsr subsection.
62
+ *
63
+ * On incoming migration, if the cpu/vfp FPSCR field is non-zero we
64
+ * use it, and if the fpcr_fpsr subsection is present we use that.
65
+ * (The subsection will never be present with a non-zero FPSCR field,
66
+ * and if FPSCR is zero and the subsection is not present that means
67
+ * that FPSCR/FPSR/FPCR are zero.)
68
+ *
69
+ * This preserves migration compatibility with older QEMU versions,
70
+ * in both directions.
71
+ */
72
+ ARMCPU *cpu = opaque;
73
+ CPUARMState *env = &cpu->env;
74
+
75
+ return (vfp_get_fpcr(env) & ~FPCR_MASK) || (vfp_get_fpsr(env) & ~FPSR_MASK);
76
+}
45
+}
77
+
46
+
78
static int get_fpscr(QEMUFile *f, void *opaque, size_t size,
47
static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
79
const VMStateField *field)
48
float_status *status)
80
{
49
{
81
@@ -XXX,XX +XXX,XX @@ static int get_fpscr(QEMUFile *f, void *opaque, size_t size,
50
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
82
CPUARMState *env = &cpu->env;
51
return status->float_2nan_prop_rule;
83
uint32_t val = qemu_get_be32(f);
52
}
84
53
85
- vfp_set_fpscr(env, val);
54
+static inline Float3NaNPropRule get_float_3nan_prop_rule(float_status *status)
86
+ if (val) {
55
+{
87
+ /* 0 means we might have the data in the fpcr_fpsr subsection */
56
+ return status->float_3nan_prop_rule;
88
+ vfp_set_fpscr(env, val);
57
+}
58
+
59
static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
60
{
61
return status->float_infzeronan_rule;
62
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
63
index XXXXXXX..XXXXXXX 100644
64
--- a/include/fpu/softfloat-types.h
65
+++ b/include/fpu/softfloat-types.h
66
@@ -XXX,XX +XXX,XX @@ this code that are retained.
67
#ifndef SOFTFLOAT_TYPES_H
68
#define SOFTFLOAT_TYPES_H
69
70
+#include "hw/registerfields.h"
71
+
72
/*
73
* Software IEC/IEEE floating-point types.
74
*/
75
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
76
float_2nan_prop_x87,
77
} Float2NaNPropRule;
78
79
+/*
80
+ * 3-input NaN propagation rule, for fused multiply-add. Individual
81
+ * architectures have different rules for which input NaN is
82
+ * propagated to the output when there is more than one NaN on the
83
+ * input.
84
+ *
85
+ * If default_nan_mode is enabled then it is valid not to set a NaN
86
+ * propagation rule, because the softfloat code guarantees not to try
87
+ * to pick a NaN to propagate in default NaN mode. When not in
88
+ * default-NaN mode, it is an error for the target not to set the rule
89
+ * in float_status if it uses a muladd, and we will assert if we need
90
+ * to handle an input NaN and no rule was selected.
91
+ *
92
+ * The naming scheme for Float3NaNPropRule values is:
93
+ * float_3nan_prop_s_abc:
94
+ * = "Prefer SNaN over QNaN, then operand A over B over C"
95
+ * float_3nan_prop_abc:
96
+ * = "Prefer A over B over C regardless of SNaN vs QNAN"
97
+ *
98
+ * For QEMU, the multiply-add operation is A * B + C.
99
+ */
100
+
101
+/*
102
+ * We set the Float3NaNPropRule enum values up so we can select the
103
+ * right value in pickNaNMulAdd in a data driven way.
104
+ */
105
+FIELD(3NAN, 1ST, 0, 2) /* which operand is most preferred ? */
106
+FIELD(3NAN, 2ND, 2, 2) /* which operand is next most preferred ? */
107
+FIELD(3NAN, 3RD, 4, 2) /* which operand is least preferred ? */
108
+FIELD(3NAN, SNAN, 6, 1) /* do we prefer SNaN over QNaN ? */
109
+
110
+#define PROPRULE(X, Y, Z) \
111
+ ((X << R_3NAN_1ST_SHIFT) | (Y << R_3NAN_2ND_SHIFT) | (Z << R_3NAN_3RD_SHIFT))
112
+
113
+typedef enum __attribute__((__packed__)) {
114
+ float_3nan_prop_none = 0, /* No propagation rule specified */
115
+ float_3nan_prop_abc = PROPRULE(0, 1, 2),
116
+ float_3nan_prop_acb = PROPRULE(0, 2, 1),
117
+ float_3nan_prop_bac = PROPRULE(1, 0, 2),
118
+ float_3nan_prop_bca = PROPRULE(1, 2, 0),
119
+ float_3nan_prop_cab = PROPRULE(2, 0, 1),
120
+ float_3nan_prop_cba = PROPRULE(2, 1, 0),
121
+ float_3nan_prop_s_abc = float_3nan_prop_abc | R_3NAN_SNAN_MASK,
122
+ float_3nan_prop_s_acb = float_3nan_prop_acb | R_3NAN_SNAN_MASK,
123
+ float_3nan_prop_s_bac = float_3nan_prop_bac | R_3NAN_SNAN_MASK,
124
+ float_3nan_prop_s_bca = float_3nan_prop_bca | R_3NAN_SNAN_MASK,
125
+ float_3nan_prop_s_cab = float_3nan_prop_cab | R_3NAN_SNAN_MASK,
126
+ float_3nan_prop_s_cba = float_3nan_prop_cba | R_3NAN_SNAN_MASK,
127
+} Float3NaNPropRule;
128
+
129
+#undef PROPRULE
130
+
131
/*
132
* Rule for result of fused multiply-add 0 * Inf + NaN.
133
* This must be a NaN, but implementations differ on whether this
134
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
135
FloatRoundMode float_rounding_mode;
136
FloatX80RoundPrec floatx80_rounding_precision;
137
Float2NaNPropRule float_2nan_prop_rule;
138
+ Float3NaNPropRule float_3nan_prop_rule;
139
FloatInfZeroNaNRule float_infzeronan_rule;
140
bool tininess_before_rounding;
141
/* should denormalised results go to zero and set the inexact flag? */
142
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
143
index XXXXXXX..XXXXXXX 100644
144
--- a/fpu/softfloat-specialize.c.inc
145
+++ b/fpu/softfloat-specialize.c.inc
146
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
147
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
148
bool infzero, bool have_snan, float_status *status)
149
{
150
+ FloatClass cls[3] = { a_cls, b_cls, c_cls };
151
+ Float3NaNPropRule rule = status->float_3nan_prop_rule;
152
+ int which;
153
+
154
/*
155
* We guarantee not to require the target to tell us how to
156
* pick a NaN if we're always returning the default NaN.
157
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
158
}
159
}
160
161
+ if (rule == float_3nan_prop_none) {
162
#if defined(TARGET_ARM)
163
-
164
- /* This looks different from the ARM ARM pseudocode, because the ARM ARM
165
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
166
- */
167
- if (is_snan(c_cls)) {
168
- return 2;
169
- } else if (is_snan(a_cls)) {
170
- return 0;
171
- } else if (is_snan(b_cls)) {
172
- return 1;
173
- } else if (is_qnan(c_cls)) {
174
- return 2;
175
- } else if (is_qnan(a_cls)) {
176
- return 0;
177
- } else {
178
- return 1;
179
- }
180
+ /*
181
+ * This looks different from the ARM ARM pseudocode, because the ARM ARM
182
+ * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
183
+ */
184
+ rule = float_3nan_prop_s_cab;
185
#elif defined(TARGET_MIPS)
186
- if (snan_bit_is_one(status)) {
187
- /* Prefer sNaN over qNaN, in the a, b, c order. */
188
- if (is_snan(a_cls)) {
189
- return 0;
190
- } else if (is_snan(b_cls)) {
191
- return 1;
192
- } else if (is_snan(c_cls)) {
193
- return 2;
194
- } else if (is_qnan(a_cls)) {
195
- return 0;
196
- } else if (is_qnan(b_cls)) {
197
- return 1;
198
+ if (snan_bit_is_one(status)) {
199
+ rule = float_3nan_prop_s_abc;
200
} else {
201
- return 2;
202
+ rule = float_3nan_prop_s_cab;
203
}
204
- } else {
205
- /* Prefer sNaN over qNaN, in the c, a, b order. */
206
- if (is_snan(c_cls)) {
207
- return 2;
208
- } else if (is_snan(a_cls)) {
209
- return 0;
210
- } else if (is_snan(b_cls)) {
211
- return 1;
212
- } else if (is_qnan(c_cls)) {
213
- return 2;
214
- } else if (is_qnan(a_cls)) {
215
- return 0;
216
- } else {
217
- return 1;
218
- }
219
- }
220
#elif defined(TARGET_LOONGARCH64)
221
- /* Prefer sNaN over qNaN, in the c, a, b order. */
222
- if (is_snan(c_cls)) {
223
- return 2;
224
- } else if (is_snan(a_cls)) {
225
- return 0;
226
- } else if (is_snan(b_cls)) {
227
- return 1;
228
- } else if (is_qnan(c_cls)) {
229
- return 2;
230
- } else if (is_qnan(a_cls)) {
231
- return 0;
232
- } else {
233
- return 1;
234
- }
235
+ rule = float_3nan_prop_s_cab;
236
#elif defined(TARGET_PPC)
237
- /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
238
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
239
- */
240
- if (is_nan(a_cls)) {
241
- return 0;
242
- } else if (is_nan(c_cls)) {
243
- return 2;
244
- } else {
245
- return 1;
246
- }
247
+ /*
248
+ * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
249
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
250
+ */
251
+ rule = float_3nan_prop_acb;
252
#elif defined(TARGET_S390X)
253
- if (is_snan(a_cls)) {
254
- return 0;
255
- } else if (is_snan(b_cls)) {
256
- return 1;
257
- } else if (is_snan(c_cls)) {
258
- return 2;
259
- } else if (is_qnan(a_cls)) {
260
- return 0;
261
- } else if (is_qnan(b_cls)) {
262
- return 1;
263
- } else {
264
- return 2;
265
- }
266
+ rule = float_3nan_prop_s_abc;
267
#elif defined(TARGET_SPARC)
268
- /* Prefer SNaN over QNaN, order C, B, A. */
269
- if (is_snan(c_cls)) {
270
- return 2;
271
- } else if (is_snan(b_cls)) {
272
- return 1;
273
- } else if (is_snan(a_cls)) {
274
- return 0;
275
- } else if (is_qnan(c_cls)) {
276
- return 2;
277
- } else if (is_qnan(b_cls)) {
278
- return 1;
279
- } else {
280
- return 0;
281
- }
282
+ rule = float_3nan_prop_s_cba;
283
#elif defined(TARGET_XTENSA)
284
- /*
285
- * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
286
- * an input NaN if we have one (ie c).
287
- */
288
- if (status->use_first_nan) {
289
- if (is_nan(a_cls)) {
290
- return 0;
291
- } else if (is_nan(b_cls)) {
292
- return 1;
293
+ if (status->use_first_nan) {
294
+ rule = float_3nan_prop_abc;
295
} else {
296
- return 2;
297
+ rule = float_3nan_prop_cba;
298
}
299
- } else {
300
- if (is_nan(c_cls)) {
301
- return 2;
302
- } else if (is_nan(b_cls)) {
303
- return 1;
304
- } else {
305
- return 0;
306
- }
307
- }
308
#else
309
- /* A default implementation: prefer a to b to c.
310
- * This is unlikely to actually match any real implementation.
311
- */
312
- if (is_nan(a_cls)) {
313
- return 0;
314
- } else if (is_nan(b_cls)) {
315
- return 1;
316
- } else {
317
- return 2;
318
- }
319
+ rule = float_3nan_prop_abc;
320
#endif
89
+ }
321
+ }
90
return 0;
322
+
323
+ assert(rule != float_3nan_prop_none);
324
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
325
+ /* We have at least one SNaN input and should prefer it */
326
+ do {
327
+ which = rule & R_3NAN_1ST_MASK;
328
+ rule >>= R_3NAN_1ST_LENGTH;
329
+ } while (!is_snan(cls[which]));
330
+ } else {
331
+ do {
332
+ which = rule & R_3NAN_1ST_MASK;
333
+ rule >>= R_3NAN_1ST_LENGTH;
334
+ } while (!is_nan(cls[which]));
335
+ }
336
+ return which;
91
}
337
}
92
338
93
@@ -XXX,XX +XXX,XX @@ static int put_fpscr(QEMUFile *f, void *opaque, size_t size,
339
/*----------------------------------------------------------------------------
94
{
95
ARMCPU *cpu = opaque;
96
CPUARMState *env = &cpu->env;
97
+ uint32_t fpscr = vfp_fpcr_fpsr_needed(opaque) ? 0 : vfp_get_fpscr(env);
98
99
- qemu_put_be32(f, vfp_get_fpscr(env));
100
+ qemu_put_be32(f, fpscr);
101
return 0;
102
}
103
104
@@ -XXX,XX +XXX,XX @@ static const VMStateInfo vmstate_fpscr = {
105
.put = put_fpscr,
106
};
107
108
+static int get_fpcr(QEMUFile *f, void *opaque, size_t size,
109
+ const VMStateField *field)
110
+{
111
+ ARMCPU *cpu = opaque;
112
+ CPUARMState *env = &cpu->env;
113
+ uint64_t val = qemu_get_be64(f);
114
+
115
+ vfp_set_fpcr(env, val);
116
+ return 0;
117
+}
118
+
119
+static int put_fpcr(QEMUFile *f, void *opaque, size_t size,
120
+ const VMStateField *field, JSONWriter *vmdesc)
121
+{
122
+ ARMCPU *cpu = opaque;
123
+ CPUARMState *env = &cpu->env;
124
+
125
+ qemu_put_be64(f, vfp_get_fpcr(env));
126
+ return 0;
127
+}
128
+
129
+static const VMStateInfo vmstate_fpcr = {
130
+ .name = "fpcr",
131
+ .get = get_fpcr,
132
+ .put = put_fpcr,
133
+};
134
+
135
+static int get_fpsr(QEMUFile *f, void *opaque, size_t size,
136
+ const VMStateField *field)
137
+{
138
+ ARMCPU *cpu = opaque;
139
+ CPUARMState *env = &cpu->env;
140
+ uint64_t val = qemu_get_be64(f);
141
+
142
+ vfp_set_fpsr(env, val);
143
+ return 0;
144
+}
145
+
146
+static int put_fpsr(QEMUFile *f, void *opaque, size_t size,
147
+ const VMStateField *field, JSONWriter *vmdesc)
148
+{
149
+ ARMCPU *cpu = opaque;
150
+ CPUARMState *env = &cpu->env;
151
+
152
+ qemu_put_be64(f, vfp_get_fpsr(env));
153
+ return 0;
154
+}
155
+
156
+static const VMStateInfo vmstate_fpsr = {
157
+ .name = "fpsr",
158
+ .get = get_fpsr,
159
+ .put = put_fpsr,
160
+};
161
+
162
+static const VMStateDescription vmstate_vfp_fpcr_fpsr = {
163
+ .name = "cpu/vfp/fpcr_fpsr",
164
+ .version_id = 1,
165
+ .minimum_version_id = 1,
166
+ .needed = vfp_fpcr_fpsr_needed,
167
+ .fields = (const VMStateField[]) {
168
+ {
169
+ .name = "fpcr",
170
+ .version_id = 0,
171
+ .size = sizeof(uint64_t),
172
+ .info = &vmstate_fpcr,
173
+ .flags = VMS_SINGLE,
174
+ .offset = 0,
175
+ },
176
+ {
177
+ .name = "fpsr",
178
+ .version_id = 0,
179
+ .size = sizeof(uint64_t),
180
+ .info = &vmstate_fpsr,
181
+ .flags = VMS_SINGLE,
182
+ .offset = 0,
183
+ },
184
+ VMSTATE_END_OF_LIST()
185
+ },
186
+};
187
+
188
static const VMStateDescription vmstate_vfp = {
189
.name = "cpu/vfp",
190
.version_id = 3,
191
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_vfp = {
192
.offset = 0,
193
},
194
VMSTATE_END_OF_LIST()
195
+ },
196
+ .subsections = (const VMStateDescription * const []) {
197
+ &vmstate_vfp_fpcr_fpsr,
198
+ NULL
199
}
200
};
201
202
@@ -XXX,XX +XXX,XX @@ static int cpu_pre_load(void *opaque)
203
ARMCPU *cpu = opaque;
204
CPUARMState *env = &cpu->env;
205
206
+ /*
207
+ * In an inbound migration where on the source FPSCR/FPSR/FPCR are 0,
208
+ * there will be no fpcr_fpsr subsection so we won't call vfp_set_fpcr()
209
+ * and vfp_set_fpsr() from get_fpcr() and get_fpsr(); also the get_fpscr()
210
+ * function will not call vfp_set_fpscr() because it will see a 0 in the
211
+ * inbound data. Ensure that in this case we have a correctly set up
212
+ * zero FPSCR/FPCR/FPSR.
213
+ *
214
+ * This is not strictly needed because FPSCR is zero out of reset, but
215
+ * it avoids the possibility of future confusing migration bugs if some
216
+ * future architecture change makes the reset value non-zero.
217
+ */
218
+ vfp_set_fpscr(env, 0);
219
+
220
/*
221
* Pre-initialize irq_line_state to a value that's never valid as
222
* real data, so cpu_post_load() can tell whether we've seen the
223
--
340
--
224
2.34.1
341
2.34.1
diff view generated by jsdifflib
New patch
[PULL 21/72] tests/fp: Explicitly set 3-NaN propagation rule
1
Explicitly set a rule in the softfloat tests for propagating NaNs in
2
the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and
3
so we should select here the Arm rule of float_3nan_prop_s_cab.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-17-peter.maydell@linaro.org
8
---
9
tests/fp/fp-bench.c | 1 +
10
tests/fp/fp-test.c | 1 +
11
2 files changed, 2 insertions(+)
12
13
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/tests/fp/fp-bench.c
16
+++ b/tests/fp/fp-bench.c
17
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
18
* doesn't specify match those used by the Arm architecture.
19
*/
20
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
22
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
23
24
f = bench_funcs[operation][precision];
25
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/tests/fp/fp-test.c
28
+++ b/tests/fp/fp-test.c
29
@@ -XXX,XX +XXX,XX @@ void run_test(void)
30
* doesn't specify match those used by the Arm architecture.
31
*/
32
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
33
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
34
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
35
36
genCases_setLevel(test_level);
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 22/72] target/arm: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-18-peter.maydell@linaro.org
7
---
8
target/arm/cpu.c | 5 +++++
9
fpu/softfloat-specialize.c.inc | 8 +-------
10
2 files changed, 6 insertions(+), 7 deletions(-)
11
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
17
* * tininess-before-rounding
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
20
+ * * 3-input NaN propagation prefers SNaN over QNaN, and then
21
+ * operand C over A over B (see FPProcessNaNs3() pseudocode,
22
+ * but note that for QEMU muladd is a * b + c, whereas for
23
+ * the pseudocode function the arguments are in the order c, a, b.
24
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
25
* and the input NaN if it is signalling
26
*/
27
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
28
{
29
set_float_detect_tininess(float_tininess_before_rounding, s);
30
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
31
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
32
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
33
}
34
35
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
36
index XXXXXXX..XXXXXXX 100644
37
--- a/fpu/softfloat-specialize.c.inc
38
+++ b/fpu/softfloat-specialize.c.inc
39
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
40
}
41
42
if (rule == float_3nan_prop_none) {
43
-#if defined(TARGET_ARM)
44
- /*
45
- * This looks different from the ARM ARM pseudocode, because the ARM ARM
46
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
47
- */
48
- rule = float_3nan_prop_s_cab;
49
-#elif defined(TARGET_MIPS)
50
+#if defined(TARGET_MIPS)
51
if (snan_bit_is_one(status)) {
52
rule = float_3nan_prop_s_abc;
53
} else {
54
--
55
2.34.1
diff view generated by jsdifflib
New patch
[PULL 23/72] target/loongarch: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for loongarch, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-19-peter.maydell@linaro.org
7
---
8
target/loongarch/tcg/fpu_helper.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
11
12
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/loongarch/tcg/fpu_helper.c
15
+++ b/target/loongarch/tcg/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
17
* case sets InvalidOp and returns the input value 'c'
18
*/
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
21
}
22
23
int ieee_ex_to_loongarch(int xcpt)
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
} else {
30
rule = float_3nan_prop_s_cab;
31
}
32
-#elif defined(TARGET_LOONGARCH64)
33
- rule = float_3nan_prop_s_cab;
34
#elif defined(TARGET_PPC)
35
/*
36
* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 24/72] target/ppc: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for PPC, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-20-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 8 ++++++++
9
fpu/softfloat-specialize.c.inc | 6 ------
10
2 files changed, 8 insertions(+), 6 deletions(-)
11
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/ppc/cpu_init.c
15
+++ b/target/ppc/cpu_init.c
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
20
+ /*
21
+ * NaN propagation for fused multiply-add:
22
+ * if fRA is a NaN return it; otherwise if fRB is a NaN return it;
23
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
24
+ * whereas QEMU labels the operands as (a * b) + c.
25
+ */
26
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status);
27
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status);
28
/*
29
* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
30
* to return an input NaN if we have one (ie c) rather than generating
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
32
index XXXXXXX..XXXXXXX 100644
33
--- a/fpu/softfloat-specialize.c.inc
34
+++ b/fpu/softfloat-specialize.c.inc
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
36
} else {
37
rule = float_3nan_prop_s_cab;
38
}
39
-#elif defined(TARGET_PPC)
40
- /*
41
- * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
42
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
43
- */
44
- rule = float_3nan_prop_acb;
45
#elif defined(TARGET_S390X)
46
rule = float_3nan_prop_s_abc;
47
#elif defined(TARGET_SPARC)
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 25/72] target/s390x: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for s390x, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-21-peter.maydell@linaro.org
7
---
8
target/s390x/cpu.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
11
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/s390x/cpu.c
15
+++ b/target/s390x/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
17
set_float_detect_tininess(float_tininess_before_rounding,
18
&env->fpu_status);
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
21
set_float_infzeronan_rule(float_infzeronan_dnan_always,
22
&env->fpu_status);
23
/* fall through */
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
} else {
30
rule = float_3nan_prop_s_cab;
31
}
32
-#elif defined(TARGET_S390X)
33
- rule = float_3nan_prop_s_abc;
34
#elif defined(TARGET_SPARC)
35
rule = float_3nan_prop_s_cba;
36
#elif defined(TARGET_XTENSA)
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 26/72] target/sparc: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for SPARC, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-22-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
* the CPU state struct so it won't get zeroed on reset.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
20
+ /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
22
/* For inf * 0 + NaN, return the input NaN */
23
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
24
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
} else {
31
rule = float_3nan_prop_s_cab;
32
}
33
-#elif defined(TARGET_SPARC)
34
- rule = float_3nan_prop_s_cba;
35
#elif defined(TARGET_XTENSA)
36
if (status->use_first_nan) {
37
rule = float_3nan_prop_abc;
38
--
39
2.34.1
diff view generated by jsdifflib
[PULL 01/24] target/arm: Correct comments about M-profile FPSCR
[PULL 27/72] target/mips: Set Float3NaNPropRule explicitly
1
The M-profile FPSCR LTPSIZE is bits [18:16]; this is the same
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
field as A-profile FPSCR Len, not Stride. Correct the comment
2
ifdef from pickNaNMulAdd().
3
in vfp_get_fpscr().
4
5
We also implemented M-profile FPSCR.QC, but forgot to delete
6
a TODO comment from vfp_set_fpscr(); remove it now.
7
3
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20240628142347.1283015-2-peter.maydell@linaro.org
6
Message-id: 20241202131347.498124-23-peter.maydell@linaro.org
11
---
7
---
12
target/arm/vfp_helper.c | 5 ++---
8
target/mips/fpu_helper.h | 4 ++++
13
1 file changed, 2 insertions(+), 3 deletions(-)
9
target/mips/msa.c | 3 +++
10
fpu/softfloat-specialize.c.inc | 8 +-------
11
3 files changed, 8 insertions(+), 7 deletions(-)
14
12
15
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
16
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/vfp_helper.c
15
--- a/target/mips/fpu_helper.h
18
+++ b/target/arm/vfp_helper.c
16
+++ b/target/mips/fpu_helper.h
19
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
20
| (env->vfp.vec_stride << 20);
18
{
19
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
20
FloatInfZeroNaNRule izn_rule;
21
+ Float3NaNPropRule nan3_rule;
21
22
22
/*
23
/*
23
- * M-profile LTPSIZE overlaps A-profile Stride; whichever of the
24
* With nan2008, SNaNs are silenced in the usual way.
24
- * two is not applicable to this CPU will always be zero.
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
25
+ * M-profile LTPSIZE is the same bits [18:16] as A-profile Len; whichever
26
+ * of the two is not applicable to this CPU will always be zero.
27
*/
26
*/
28
fpscr |= env->v7m.ltpsize << 16;
27
izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
29
28
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
30
@@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
29
+ nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
31
/*
30
+ set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
32
* The bit we set within fpscr_q is arbitrary; the register as a
31
+
33
* whole being zero/non-zero is what counts.
32
}
34
- * TODO: M-profile MVE also has a QC bit.
33
35
*/
34
static inline void restore_fp_status(CPUMIPSState *env)
36
env->vfp.qc[0] = val & FPCR_QC;
35
diff --git a/target/mips/msa.c b/target/mips/msa.c
37
env->vfp.qc[1] = 0;
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/mips/msa.c
38
+++ b/target/mips/msa.c
39
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
40
set_float_2nan_prop_rule(float_2nan_prop_s_ab,
41
&env->active_tc.msa_fp_status);
42
43
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab,
44
+ &env->active_tc.msa_fp_status);
45
+
46
/* clear float_status exception flags */
47
set_float_exception_flags(0, &env->active_tc.msa_fp_status);
48
49
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
50
index XXXXXXX..XXXXXXX 100644
51
--- a/fpu/softfloat-specialize.c.inc
52
+++ b/fpu/softfloat-specialize.c.inc
53
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
54
}
55
56
if (rule == float_3nan_prop_none) {
57
-#if defined(TARGET_MIPS)
58
- if (snan_bit_is_one(status)) {
59
- rule = float_3nan_prop_s_abc;
60
- } else {
61
- rule = float_3nan_prop_s_cab;
62
- }
63
-#elif defined(TARGET_XTENSA)
64
+#if defined(TARGET_XTENSA)
65
if (status->use_first_nan) {
66
rule = float_3nan_prop_abc;
67
} else {
38
--
68
--
39
2.34.1
69
2.34.1
diff view generated by jsdifflib
[PULL 09/24] target/arm: Allow FPCR bits that aren't in FPSCR
[PULL 28/72] target/xtensa: Set Float3NaNPropRule explicitly
1
In order to allow FPCR bits that aren't in the FPSCR (like the new
1
Set the Float3NaNPropRule explicitly for xtensa, and remove the
2
bits that are defined for FEAT_AFP), we need to make sure that writes
2
ifdef from pickNaNMulAdd().
3
to the FPSCR only write to the bits of FPCR that are architecturally
4
mapped, and not the others.
5
6
Implement this with a new function vfp_set_fpcr_masked() which
7
takes a mask of which bits to update.
8
9
(We could do the same for FPSR, but we leave that until we actually
10
are likely to need it.)
11
3
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20240628142347.1283015-10-peter.maydell@linaro.org
6
Message-id: 20241202131347.498124-24-peter.maydell@linaro.org
15
---
7
---
16
target/arm/vfp_helper.c | 54 ++++++++++++++++++++++++++---------------
8
target/xtensa/fpu_helper.c | 2 ++
17
1 file changed, 34 insertions(+), 20 deletions(-)
9
fpu/softfloat-specialize.c.inc | 8 --------
10
2 files changed, 2 insertions(+), 8 deletions(-)
18
11
19
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
12
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
20
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/vfp_helper.c
14
--- a/target/xtensa/fpu_helper.c
22
+++ b/target/arm/vfp_helper.c
15
+++ b/target/xtensa/fpu_helper.c
23
@@ -XXX,XX +XXX,XX @@ static void vfp_set_fpsr_to_host(CPUARMState *env, uint32_t val)
16
@@ -XXX,XX +XXX,XX @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
24
set_float_exception_flags(0, &env->vfp.standard_fp_status_f16);
17
set_use_first_nan(use_first, &env->fp_status);
18
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
19
&env->fp_status);
20
+ set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
21
+ &env->fp_status);
25
}
22
}
26
23
27
-static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val)
24
void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v)
28
+static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
29
{
26
index XXXXXXX..XXXXXXX 100644
30
uint64_t changed = env->vfp.fpcr;
27
--- a/fpu/softfloat-specialize.c.inc
31
28
+++ b/fpu/softfloat-specialize.c.inc
32
changed ^= val;
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
33
+ changed &= mask;
34
if (changed & (3 << 22)) {
35
int i = (val >> 22) & 3;
36
switch (i) {
37
@@ -XXX,XX +XXX,XX @@ static void vfp_set_fpsr_to_host(CPUARMState *env, uint32_t val)
38
{
39
}
40
41
-static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val)
42
+static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
43
{
44
}
45
46
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpsr(CPUARMState *env, uint32_t val)
47
env->vfp.fpsr = val;
48
}
49
50
-void vfp_set_fpcr(CPUARMState *env, uint32_t val)
51
+static void vfp_set_fpcr_masked(CPUARMState *env, uint32_t val, uint32_t mask)
52
{
53
+ /*
54
+ * We only set FPCR bits defined by mask, and leave the others alone.
55
+ * We assume the mask is sensible (e.g. doesn't try to set only
56
+ * part of a field)
57
+ */
58
ARMCPU *cpu = env_archcpu(env);
59
60
/* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
61
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpcr(CPUARMState *env, uint32_t val)
62
val &= ~FPCR_FZ16;
63
}
30
}
64
31
65
- vfp_set_fpcr_to_host(env, val);
32
if (rule == float_3nan_prop_none) {
66
+ vfp_set_fpcr_to_host(env, val, mask);
33
-#if defined(TARGET_XTENSA)
67
34
- if (status->use_first_nan) {
68
- if (!arm_feature(env, ARM_FEATURE_M)) {
35
- rule = float_3nan_prop_abc;
69
- /*
36
- } else {
70
- * Short-vector length and stride; on M-profile these bits
37
- rule = float_3nan_prop_cba;
71
- * are used for different purposes.
38
- }
72
- * We can't make this conditional be "if MVFR0.FPShVec != 0",
39
-#else
73
- * because in v7A no-short-vector-support cores still had to
40
rule = float_3nan_prop_abc;
74
- * allow Stride/Len to be written with the only effect that
41
-#endif
75
- * some insns are required to UNDEF if the guest sets them.
76
- */
77
- env->vfp.vec_len = extract32(val, 16, 3);
78
- env->vfp.vec_stride = extract32(val, 20, 2);
79
- } else if (cpu_isar_feature(aa32_mve, cpu)) {
80
- env->v7m.ltpsize = extract32(val, FPCR_LTPSIZE_SHIFT,
81
- FPCR_LTPSIZE_LENGTH);
82
+ if (mask & (FPCR_LEN_MASK | FPCR_STRIDE_MASK)) {
83
+ if (!arm_feature(env, ARM_FEATURE_M)) {
84
+ /*
85
+ * Short-vector length and stride; on M-profile these bits
86
+ * are used for different purposes.
87
+ * We can't make this conditional be "if MVFR0.FPShVec != 0",
88
+ * because in v7A no-short-vector-support cores still had to
89
+ * allow Stride/Len to be written with the only effect that
90
+ * some insns are required to UNDEF if the guest sets them.
91
+ */
92
+ env->vfp.vec_len = extract32(val, 16, 3);
93
+ env->vfp.vec_stride = extract32(val, 20, 2);
94
+ } else if (cpu_isar_feature(aa32_mve, cpu)) {
95
+ env->v7m.ltpsize = extract32(val, FPCR_LTPSIZE_SHIFT,
96
+ FPCR_LTPSIZE_LENGTH);
97
+ }
98
}
42
}
99
43
100
/*
44
assert(rule != float_3nan_prop_none);
101
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpcr(CPUARMState *env, uint32_t val)
102
* bits.
103
*/
104
val &= FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK | FPCR_FZ16;
105
- env->vfp.fpcr = val;
106
+ env->vfp.fpcr &= ~mask;
107
+ env->vfp.fpcr |= val;
108
+}
109
+
110
+void vfp_set_fpcr(CPUARMState *env, uint32_t val)
111
+{
112
+ vfp_set_fpcr_masked(env, val, MAKE_64BIT_MASK(0, 32));
113
}
114
115
void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
116
{
117
- vfp_set_fpcr(env, val & FPSCR_FPCR_MASK);
118
+ vfp_set_fpcr_masked(env, val, FPSCR_FPCR_MASK);
119
vfp_set_fpsr(env, val & FPSCR_FPSR_MASK);
120
}
121
122
--
45
--
123
2.34.1
46
2.34.1
diff view generated by jsdifflib
New patch
[PULL 29/72] target/i386: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for i386. We had no
2
i386-specific behaviour in the old ifdef ladder, so we were using the
3
default "prefer a then b then c" fallback; this is actually the
4
correct per-the-spec handling for i386.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-25-peter.maydell@linaro.org
9
---
10
target/i386/tcg/fpu_helper.c | 1 +
11
1 file changed, 1 insertion(+)
12
13
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/i386/tcg/fpu_helper.c
16
+++ b/target/i386/tcg/fpu_helper.c
17
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
18
* there are multiple input NaNs they are selected in the order a, b, c.
19
*/
20
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
21
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
22
}
23
24
static inline uint8_t save_exception_flags(CPUX86State *env)
25
--
26
2.34.1
diff view generated by jsdifflib
New patch
[PULL 30/72] target/hppa: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for HPPA, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
HPPA is the only target that was using the default branch of the
5
ifdef ladder (other targets either do not use muladd or set
6
default_nan_mode), so we can remove the ifdef fallback entirely now
7
(allowing the "rule not set" case to fall into the default of the
8
switch statement and assert).
9
10
We add a TODO note that the HPPA rule is probably wrong; this is
11
not a behavioural change for this refactoring.
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-26-peter.maydell@linaro.org
16
---
17
target/hppa/fpu_helper.c | 8 ++++++++
18
fpu/softfloat-specialize.c.inc | 4 ----
19
2 files changed, 8 insertions(+), 4 deletions(-)
20
21
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/hppa/fpu_helper.c
24
+++ b/target/hppa/fpu_helper.c
25
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
26
* HPPA does note implement a CPU reset method at all...
27
*/
28
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
29
+ /*
30
+ * TODO: The HPPA architecture reference only documents its NaN
31
+ * propagation rule for 2-operand operations. Testing on real hardware
32
+ * might be necessary to confirm whether this order for muladd is correct.
33
+ * Not preferring the SNaN is almost certainly incorrect as it diverges
34
+ * from the documented rules for 2-operand operations.
35
+ */
36
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
37
/* For inf * 0 + NaN, return the input NaN */
38
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
39
}
40
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
41
index XXXXXXX..XXXXXXX 100644
42
--- a/fpu/softfloat-specialize.c.inc
43
+++ b/fpu/softfloat-specialize.c.inc
44
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
45
}
46
}
47
48
- if (rule == float_3nan_prop_none) {
49
- rule = float_3nan_prop_abc;
50
- }
51
-
52
assert(rule != float_3nan_prop_none);
53
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
54
/* We have at least one SNaN input and should prefer it */
55
--
56
2.34.1
diff view generated by jsdifflib
New patch
[PULL 31/72] fpu: Remove use_first_nan field from float_status
1
The use_first_nan field in float_status was an xtensa-specific way to
2
select at runtime from two different NaN propagation rules. Now that
3
xtensa is using the target-agnostic NaN propagation rule selection
4
that we've just added, we can remove use_first_nan, because there is
5
no longer any code that reads it.
1
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20241202131347.498124-27-peter.maydell@linaro.org
10
---
11
include/fpu/softfloat-helpers.h | 5 -----
12
include/fpu/softfloat-types.h | 1 -
13
target/xtensa/fpu_helper.c | 1 -
14
3 files changed, 7 deletions(-)
15
16
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/fpu/softfloat-helpers.h
19
+++ b/include/fpu/softfloat-helpers.h
20
@@ -XXX,XX +XXX,XX @@ static inline void set_snan_bit_is_one(bool val, float_status *status)
21
status->snan_bit_is_one = val;
22
}
23
24
-static inline void set_use_first_nan(bool val, float_status *status)
25
-{
26
- status->use_first_nan = val;
27
-}
28
-
29
static inline void set_no_signaling_nans(bool val, float_status *status)
30
{
31
status->no_signaling_nans = val;
32
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/include/fpu/softfloat-types.h
35
+++ b/include/fpu/softfloat-types.h
36
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
37
* softfloat-specialize.inc.c)
38
*/
39
bool snan_bit_is_one;
40
- bool use_first_nan;
41
bool no_signaling_nans;
42
/* should overflowed results subtract re_bias to its exponent? */
43
bool rebias_overflow;
44
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/xtensa/fpu_helper.c
47
+++ b/target/xtensa/fpu_helper.c
48
@@ -XXX,XX +XXX,XX @@ static const struct {
49
50
void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
51
{
52
- set_use_first_nan(use_first, &env->fp_status);
53
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
54
&env->fp_status);
55
set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
56
--
57
2.34.1
diff view generated by jsdifflib
New patch
[PULL 32/72] target/m68k: Don't pass NULL float_status to floatx80_default_nan()
1
Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL)
2
to get the NaN bit pattern to reset the FPU registers. This
3
works because it happens that our implementation of
4
floatx80_default_nan() doesn't actually look at the float_status
5
pointer except for TARGET_MIPS. However, this isn't guaranteed,
6
and to be able to remove the ifdef in floatx80_default_nan()
7
we're going to need a real float_status here.
1
8
9
Rearrange m68k_cpu_reset_hold() so that we initialize env->fp_status
10
earlier, and thus can pass it to floatx80_default_nan().
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20241202131347.498124-28-peter.maydell@linaro.org
15
---
16
target/m68k/cpu.c | 12 +++++++-----
17
1 file changed, 7 insertions(+), 5 deletions(-)
18
19
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/m68k/cpu.c
22
+++ b/target/m68k/cpu.c
23
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
24
CPUState *cs = CPU(obj);
25
M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj);
26
CPUM68KState *env = cpu_env(cs);
27
- floatx80 nan = floatx80_default_nan(NULL);
28
+ floatx80 nan;
29
int i;
30
31
if (mcc->parent_phases.hold) {
32
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
33
#else
34
cpu_m68k_set_sr(env, SR_S | SR_I);
35
#endif
36
- for (i = 0; i < 8; i++) {
37
- env->fregs[i].d = nan;
38
- }
39
- cpu_m68k_set_fpcr(env, 0);
40
/*
41
* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
42
* 3.4 FLOATING-POINT INSTRUCTION DETAILS
43
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
44
* preceding paragraph for nonsignaling NaNs.
45
*/
46
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
47
+
48
+ nan = floatx80_default_nan(&env->fp_status);
49
+ for (i = 0; i < 8; i++) {
50
+ env->fregs[i].d = nan;
51
+ }
52
+ cpu_m68k_set_fpcr(env, 0);
53
env->fpsr = 0;
54
55
/* TODO: We should set PC from the interrupt vector. */
56
--
57
2.34.1
diff view generated by jsdifflib
New patch
[PULL 33/72] softfloat: Create floatx80 default NaN from parts64_default_nan
1
We create our 128-bit default NaN by calling parts64_default_nan()
2
and then adjusting the result. We can do the same trick for creating
3
the floatx80 default NaN, which lets us drop a target ifdef.
1
4
5
floatx80 is used only by:
6
i386
7
m68k
8
arm nwfpe old floating-point emulation emulation support
9
(which is essentially dead, especially the parts involving floatx80)
10
PPC (only in the xsrqpxp instruction, which just rounds an input
11
value by converting to floatx80 and back, so will never generate
12
the default NaN)
13
14
The floatx80 default NaN as currently implemented is:
15
m68k: sign = 0, exp = 1...1, int = 1, frac = 1....1
16
i386: sign = 1, exp = 1...1, int = 1, frac = 10...0
17
18
These are the same as the parts64_default_nan for these architectures.
19
20
This is technically a possible behaviour change for arm linux-user
21
nwfpe emulation emulation, because the default NaN will now have the
22
sign bit clear. But we were already generating a different floatx80
23
default NaN from the real kernel emulation we are supposedly
24
following, which appears to use an all-bits-1 value:
25
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L267
26
27
This won't affect the only "real" use of the nwfpe emulation, which
28
is ancient binaries that used it as part of the old floating point
29
calling convention; that only uses loads and stores of 32 and 64 bit
30
floats, not any of the floatx80 behaviour the original hardware had.
31
We also get the nwfpe float64 default NaN value wrong:
32
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L166
33
so if we ever cared about this obscure corner the right fix would be
34
to correct that so nwfpe used its own default-NaN setting rather
35
than the Arm VFP one.
36
37
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
38
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
39
Message-id: 20241202131347.498124-29-peter.maydell@linaro.org
40
---
41
fpu/softfloat-specialize.c.inc | 20 ++++++++++----------
42
1 file changed, 10 insertions(+), 10 deletions(-)
43
44
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
45
index XXXXXXX..XXXXXXX 100644
46
--- a/fpu/softfloat-specialize.c.inc
47
+++ b/fpu/softfloat-specialize.c.inc
48
@@ -XXX,XX +XXX,XX @@ static void parts128_silence_nan(FloatParts128 *p, float_status *status)
49
floatx80 floatx80_default_nan(float_status *status)
50
{
51
floatx80 r;
52
+ /*
53
+ * Extrapolate from the choices made by parts64_default_nan to fill
54
+ * in the floatx80 format. We assume that floatx80's explicit
55
+ * integer bit is always set (this is true for i386 and m68k,
56
+ * which are the only real users of this format).
57
+ */
58
+ FloatParts64 p64;
59
+ parts64_default_nan(&p64, status);
60
61
- /* None of the targets that have snan_bit_is_one use floatx80. */
62
- assert(!snan_bit_is_one(status));
63
-#if defined(TARGET_M68K)
64
- r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
65
- r.high = 0x7FFF;
66
-#else
67
- /* X86 */
68
- r.low = UINT64_C(0xC000000000000000);
69
- r.high = 0xFFFF;
70
-#endif
71
+ r.high = 0x7FFF | (p64.sign << 15);
72
+ r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac;
73
return r;
74
}
75
76
--
77
2.34.1
diff view generated by jsdifflib
New patch
[PULL 34/72] target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
1
In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass
2
a zero-initialized float_status struct to float32_is_quiet_nan() and
3
float64_is_quiet_nan(), with the cryptic comment "for
4
snan_bit_is_one".
1
5
6
This pattern appears to have been copied from target/riscv, where it
7
is used because the functions there do not have ready access to the
8
CPU state struct. The comment presumably refers to the fact that the
9
main reason the is_quiet_nan() functions want the float_state is
10
because they want to know about the snan_bit_is_one config.
11
12
In the loongarch helpers, though, we have the CPU state struct
13
to hand. Use the usual env->fp_status here. This avoids our needing
14
to track that we need to update the initializer of the local
15
float_status structs when the core softfloat code adds new
16
options for targets to configure their behaviour.
17
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20241202131347.498124-30-peter.maydell@linaro.org
21
---
22
target/loongarch/tcg/fpu_helper.c | 6 ++----
23
1 file changed, 2 insertions(+), 4 deletions(-)
24
25
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/loongarch/tcg/fpu_helper.c
28
+++ b/target/loongarch/tcg/fpu_helper.c
29
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_s(CPULoongArchState *env, uint64_t fj)
30
} else if (float32_is_zero_or_denormal(f)) {
31
return sign ? 1 << 4 : 1 << 8;
32
} else if (float32_is_any_nan(f)) {
33
- float_status s = { }; /* for snan_bit_is_one */
34
- return float32_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
35
+ return float32_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
36
} else {
37
return sign ? 1 << 3 : 1 << 7;
38
}
39
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_d(CPULoongArchState *env, uint64_t fj)
40
} else if (float64_is_zero_or_denormal(f)) {
41
return sign ? 1 << 4 : 1 << 8;
42
} else if (float64_is_any_nan(f)) {
43
- float_status s = { }; /* for snan_bit_is_one */
44
- return float64_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
45
+ return float64_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
46
} else {
47
return sign ? 1 << 3 : 1 << 7;
48
}
49
--
50
2.34.1
diff view generated by jsdifflib
New patch
[PULL 35/72] target/m68k: In frem helper, initialize local float_status from env->fp_status
1
In the frem helper, we have a local float_status because we want to
2
execute the floatx80_div() with a custom rounding mode. Instead of
3
zero-initializing the local float_status and then having to set it up
4
with the m68k standard behaviour (including the NaN propagation rule
5
and copying the rounding precision from env->fp_status), initialize
6
it as a complete copy of env->fp_status. This will avoid our having
7
to add new code in this function for every new config knob we add
8
to fp_status.
1
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-31-peter.maydell@linaro.org
13
---
14
target/m68k/fpu_helper.c | 6 ++----
15
1 file changed, 2 insertions(+), 4 deletions(-)
16
17
diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/m68k/fpu_helper.c
20
+++ b/target/m68k/fpu_helper.c
21
@@ -XXX,XX +XXX,XX @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1)
22
23
fp_rem = floatx80_rem(val1->d, val0->d, &env->fp_status);
24
if (!floatx80_is_any_nan(fp_rem)) {
25
- float_status fp_status = { };
26
+ /* Use local temporary fp_status to set different rounding mode */
27
+ float_status fp_status = env->fp_status;
28
uint32_t quotient;
29
int sign;
30
31
/* Calculate quotient directly using round to nearest mode */
32
- set_float_2nan_prop_rule(float_2nan_prop_ab, &fp_status);
33
set_float_rounding_mode(float_round_nearest_even, &fp_status);
34
- set_floatx80_rounding_precision(
35
- get_floatx80_rounding_precision(&env->fp_status), &fp_status);
36
fp_quot.d = floatx80_div(val1->d, val0->d, &fp_status);
37
38
sign = extractFloatx80Sign(fp_quot.d);
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 36/72] target/m68k: Init local float_status from env fp_status in gdb get/set reg
1
In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion
2
from float64 to floatx80 using a scratch float_status, because we
3
don't want the conversion to affect the CPU's floating point exception
4
status. Currently we use a zero-initialized float_status. This will
5
get steadily more awkward as we add config knobs to float_status
6
that the target must initialize. Avoid having to add any of that
7
configuration here by instead initializing our local float_status
8
from the env->fp_status.
1
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-32-peter.maydell@linaro.org
13
---
14
target/m68k/helper.c | 6 ++++--
15
1 file changed, 4 insertions(+), 2 deletions(-)
16
17
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/m68k/helper.c
20
+++ b/target/m68k/helper.c
21
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n)
22
CPUM68KState *env = &cpu->env;
23
24
if (n < 8) {
25
- float_status s = {};
26
+ /* Use scratch float_status so any exceptions don't change CPU state */
27
+ float_status s = env->fp_status;
28
return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s));
29
}
30
switch (n) {
31
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n)
32
CPUM68KState *env = &cpu->env;
33
34
if (n < 8) {
35
- float_status s = {};
36
+ /* Use scratch float_status so any exceptions don't change CPU state */
37
+ float_status s = env->fp_status;
38
env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s);
39
return 8;
40
}
41
--
42
2.34.1
diff view generated by jsdifflib
[PULL 07/24] target/arm: Rename FPCR_ QC, NZCV macros to FPSR_
[PULL 37/72] target/sparc: Initialize local scratch float_status from env->fp_status
1
The QC, N, Z, C, V bits live in the FPSR, not the FPCR. Rename the
1
In the helper functions flcmps and flcmpd we use a scratch float_status
2
macros that define these bits accordingly.
2
so that we don't change the CPU state if the comparison raises any
3
floating point exception flags. Instead of zero-initializing this
4
scratch float_status, initialize it as a copy of env->fp_status. This
5
avoids the need to explicitly initialize settings like the NaN
6
propagation rule or others we might add to softfloat in future.
7
8
To do this we need to pass the CPU env pointer in to the helper.
3
9
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20240628142347.1283015-8-peter.maydell@linaro.org
12
Message-id: 20241202131347.498124-33-peter.maydell@linaro.org
7
---
13
---
8
target/arm/cpu.h | 17 ++++++++++-------
14
target/sparc/helper.h | 4 ++--
9
target/arm/tcg/mve_helper.c | 8 ++++----
15
target/sparc/fop_helper.c | 8 ++++----
10
target/arm/tcg/translate-m-nocp.c | 16 ++++++++--------
16
target/sparc/translate.c | 4 ++--
11
target/arm/tcg/translate-vfp.c | 2 +-
17
3 files changed, 8 insertions(+), 8 deletions(-)
12
target/arm/vfp_helper.c | 8 ++++----
13
5 files changed, 27 insertions(+), 24 deletions(-)
14
18
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
16
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.h
21
--- a/target/sparc/helper.h
18
+++ b/target/arm/cpu.h
22
+++ b/target/sparc/helper.h
19
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
23
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64)
20
#define FPSR_MASK 0xf800009f
24
DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64)
21
#define FPCR_MASK 0x07ff9f00
25
DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128)
22
26
DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128)
23
+/* FPCR bits */
27
-DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32)
24
#define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */
28
-DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64)
25
#define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */
29
+DEF_HELPER_FLAGS_3(flcmps, TCG_CALL_NO_RWG_SE, i32, env, f32, f32)
26
#define FPCR_OFE (1 << 10) /* Overflow exception trap enable */
30
+DEF_HELPER_FLAGS_3(flcmpd, TCG_CALL_NO_RWG_SE, i32, env, f64, f64)
27
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
31
DEF_HELPER_2(raise_exception, noreturn, env, int)
28
#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
32
29
#define FPCR_DN (1 << 25) /* Default NaN enable bit */
33
DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64)
30
#define FPCR_AHP (1 << 26) /* Alternative half-precision */
34
diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c
31
-#define FPCR_QC (1 << 27) /* Cumulative saturation bit */
32
-#define FPCR_V (1 << 28) /* FP overflow flag */
33
-#define FPCR_C (1 << 29) /* FP carry flag */
34
-#define FPCR_Z (1 << 30) /* FP zero flag */
35
-#define FPCR_N (1 << 31) /* FP negative flag */
36
37
#define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */
38
#define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT)
39
#define FPCR_LTPSIZE_LENGTH 3
40
41
-#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
42
-#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
43
+/* FPSR bits */
44
+#define FPSR_QC (1 << 27) /* Cumulative saturation bit */
45
+#define FPSR_V (1 << 28) /* FP overflow flag */
46
+#define FPSR_C (1 << 29) /* FP carry flag */
47
+#define FPSR_Z (1 << 30) /* FP zero flag */
48
+#define FPSR_N (1 << 31) /* FP negative flag */
49
+
50
+#define FPSR_NZCV_MASK (FPSR_N | FPSR_Z | FPSR_C | FPSR_V)
51
+#define FPSR_NZCVQC_MASK (FPSR_NZCV_MASK | FPSR_QC)
52
53
/**
54
* vfp_get_fpsr: read the AArch64 FPSR
55
diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c
56
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
57
--- a/target/arm/tcg/mve_helper.c
36
--- a/target/sparc/fop_helper.c
58
+++ b/target/arm/tcg/mve_helper.c
37
+++ b/target/sparc/fop_helper.c
59
@@ -XXX,XX +XXX,XX @@ static void do_vadc(CPUARMState *env, uint32_t *d, uint32_t *n, uint32_t *m,
38
@@ -XXX,XX +XXX,XX @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2)
60
39
return finish_fcmp(env, r, GETPC());
61
if (update_flags) {
62
/* Store C, clear NZV. */
63
- env->vfp.fpsr &= ~FPCR_NZCV_MASK;
64
- env->vfp.fpsr |= carry_in * FPCR_C;
65
+ env->vfp.fpsr &= ~FPSR_NZCV_MASK;
66
+ env->vfp.fpsr |= carry_in * FPSR_C;
67
}
68
mve_advance_vpt(env);
69
}
40
}
70
41
71
void HELPER(mve_vadc)(CPUARMState *env, void *vd, void *vn, void *vm)
42
-uint32_t helper_flcmps(float32 src1, float32 src2)
43
+uint32_t helper_flcmps(CPUSPARCState *env, float32 src1, float32 src2)
72
{
44
{
73
- bool carry_in = env->vfp.fpsr & FPCR_C;
45
/*
74
+ bool carry_in = env->vfp.fpsr & FPSR_C;
46
* FLCMP never raises an exception nor modifies any FSR fields.
75
do_vadc(env, vd, vn, vm, 0, carry_in, false);
47
* Perform the comparison with a dummy fp environment.
48
*/
49
- float_status discard = { };
50
+ float_status discard = env->fp_status;
51
FloatRelation r;
52
53
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
54
@@ -XXX,XX +XXX,XX @@ uint32_t helper_flcmps(float32 src1, float32 src2)
55
g_assert_not_reached();
76
}
56
}
77
57
78
void HELPER(mve_vsbc)(CPUARMState *env, void *vd, void *vn, void *vm)
58
-uint32_t helper_flcmpd(float64 src1, float64 src2)
59
+uint32_t helper_flcmpd(CPUSPARCState *env, float64 src1, float64 src2)
79
{
60
{
80
- bool carry_in = env->vfp.fpsr & FPCR_C;
61
- float_status discard = { };
81
+ bool carry_in = env->vfp.fpsr & FPSR_C;
62
+ float_status discard = env->fp_status;
82
do_vadc(env, vd, vn, vm, -1, carry_in, false);
63
FloatRelation r;
64
65
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
66
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/sparc/translate.c
69
+++ b/target/sparc/translate.c
70
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a)
71
72
src1 = gen_load_fpr_F(dc, a->rs1);
73
src2 = gen_load_fpr_F(dc, a->rs2);
74
- gen_helper_flcmps(cpu_fcc[a->cc], src1, src2);
75
+ gen_helper_flcmps(cpu_fcc[a->cc], tcg_env, src1, src2);
76
return advance_pc(dc);
83
}
77
}
84
78
85
diff --git a/target/arm/tcg/translate-m-nocp.c b/target/arm/tcg/translate-m-nocp.c
79
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a)
86
index XXXXXXX..XXXXXXX 100644
80
87
--- a/target/arm/tcg/translate-m-nocp.c
81
src1 = gen_load_fpr_D(dc, a->rs1);
88
+++ b/target/arm/tcg/translate-m-nocp.c
82
src2 = gen_load_fpr_D(dc, a->rs2);
89
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
83
- gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2);
90
if (dc_isar_feature(aa32_mve, s)) {
84
+ gen_helper_flcmpd(cpu_fcc[a->cc], tcg_env, src1, src2);
91
/* QC is only present for MVE; otherwise RES0 */
85
return advance_pc(dc);
92
TCGv_i32 qc = tcg_temp_new_i32();
93
- tcg_gen_andi_i32(qc, tmp, FPCR_QC);
94
+ tcg_gen_andi_i32(qc, tmp, FPSR_QC);
95
/*
96
* The 4 vfp.qc[] fields need only be "zero" vs "non-zero";
97
* here writing the same value into all elements is simplest.
98
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
99
tcg_gen_gvec_dup_i32(MO_32, offsetof(CPUARMState, vfp.qc),
100
16, 16, qc);
101
}
102
- tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
103
+ tcg_gen_andi_i32(tmp, tmp, FPSR_NZCV_MASK);
104
fpscr = load_cpu_field_low32(vfp.fpsr);
105
- tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK);
106
+ tcg_gen_andi_i32(fpscr, fpscr, ~FPSR_NZCV_MASK);
107
tcg_gen_or_i32(fpscr, fpscr, tmp);
108
store_cpu_field_low32(fpscr, vfp.fpsr);
109
break;
110
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
111
tcg_gen_deposit_i32(control, control, sfpa,
112
R_V7M_CONTROL_SFPA_SHIFT, 1);
113
store_cpu_field(control, v7m.control[M_REG_S]);
114
- tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
115
+ tcg_gen_andi_i32(tmp, tmp, ~FPSR_NZCV_MASK);
116
gen_helper_vfp_set_fpscr(tcg_env, tmp);
117
s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
118
break;
119
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
120
case ARM_VFP_FPSCR_NZCVQC:
121
tmp = tcg_temp_new_i32();
122
gen_helper_vfp_get_fpscr(tmp, tcg_env);
123
- tcg_gen_andi_i32(tmp, tmp, FPCR_NZCVQC_MASK);
124
+ tcg_gen_andi_i32(tmp, tmp, FPSR_NZCVQC_MASK);
125
storefn(s, opaque, tmp, true);
126
break;
127
case QEMU_VFP_FPSCR_NZCV:
128
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
129
* helper call for the "VMRS to CPSR.NZCV" insn.
130
*/
131
tmp = load_cpu_field_low32(vfp.fpsr);
132
- tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
133
+ tcg_gen_andi_i32(tmp, tmp, FPSR_NZCV_MASK);
134
storefn(s, opaque, tmp, true);
135
break;
136
case ARM_VFP_FPCXT_S:
137
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
138
tmp = tcg_temp_new_i32();
139
sfpa = tcg_temp_new_i32();
140
gen_helper_vfp_get_fpscr(tmp, tcg_env);
141
- tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
142
+ tcg_gen_andi_i32(tmp, tmp, ~FPSR_NZCV_MASK);
143
control = load_cpu_field(v7m.control[M_REG_S]);
144
tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
145
tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT);
146
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
147
sfpa = tcg_temp_new_i32();
148
fpscr = tcg_temp_new_i32();
149
gen_helper_vfp_get_fpscr(fpscr, tcg_env);
150
- tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK);
151
+ tcg_gen_andi_i32(tmp, fpscr, ~FPSR_NZCV_MASK);
152
control = load_cpu_field(v7m.control[M_REG_S]);
153
tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
154
tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT);
155
diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c
156
index XXXXXXX..XXXXXXX 100644
157
--- a/target/arm/tcg/translate-vfp.c
158
+++ b/target/arm/tcg/translate-vfp.c
159
@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
160
case ARM_VFP_FPSCR:
161
if (a->rt == 15) {
162
tmp = load_cpu_field_low32(vfp.fpsr);
163
- tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
164
+ tcg_gen_andi_i32(tmp, tmp, FPSR_NZCV_MASK);
165
} else {
166
tmp = tcg_temp_new_i32();
167
gen_helper_vfp_get_fpscr(tmp, tcg_env);
168
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
169
index XXXXXXX..XXXXXXX 100644
170
--- a/target/arm/vfp_helper.c
171
+++ b/target/arm/vfp_helper.c
172
@@ -XXX,XX +XXX,XX @@ uint32_t vfp_get_fpsr(CPUARMState *env)
173
fpsr |= vfp_get_fpsr_from_host(env);
174
175
i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
176
- fpsr |= i ? FPCR_QC : 0;
177
+ fpsr |= i ? FPSR_QC : 0;
178
return fpsr;
179
}
86
}
180
87
181
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpsr(CPUARMState *env, uint32_t val)
182
* The bit we set within vfp.qc[] is arbitrary; the array as a
183
* whole being zero/non-zero is what counts.
184
*/
185
- env->vfp.qc[0] = val & FPCR_QC;
186
+ env->vfp.qc[0] = val & FPSR_QC;
187
env->vfp.qc[1] = 0;
188
env->vfp.qc[2] = 0;
189
env->vfp.qc[3] = 0;
190
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpsr(CPUARMState *env, uint32_t val)
191
* fp_status, and QC is in vfp.qc[]. Store the NZCV bits there,
192
* and zero any of the other FPSR bits.
193
*/
194
- val &= FPCR_NZCV_MASK;
195
+ val &= FPSR_NZCV_MASK;
196
env->vfp.fpsr = val;
197
}
198
199
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env)
200
uint32_t z = (pair >> 32) == 0;
201
202
/* Store Z, clear NCV, in FPSCR.NZCV. */
203
- env->vfp.fpsr = (env->vfp.fpsr & ~FPCR_NZCV_MASK) | (z * FPCR_Z);
204
+ env->vfp.fpsr = (env->vfp.fpsr & ~FPSR_NZCV_MASK) | (z * FPSR_Z);
205
206
return result;
207
}
208
--
88
--
209
2.34.1
89
2.34.1
diff view generated by jsdifflib
New patch
[PULL 38/72] target/ppc: Use env->fp_status in helper_compute_fprf functions
1
In the helper_compute_fprf functions, we pass a dummy float_status
2
in to the is_signaling_nan() function. This is unnecessary, because
3
we have convenient access to the CPU env pointer here and that
4
is already set up with the correct values for the snan_bit_is_one
5
and no_signaling_nans config settings. is_signaling_nan() doesn't
6
ever update the fp_status with any exception flags, so there is
7
no reason not to use env->fp_status here.
1
8
9
Use env->fp_status instead of the dummy fp_status.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20241202131347.498124-34-peter.maydell@linaro.org
14
---
15
target/ppc/fpu_helper.c | 3 +--
16
1 file changed, 1 insertion(+), 2 deletions(-)
17
18
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/ppc/fpu_helper.c
21
+++ b/target/ppc/fpu_helper.c
22
@@ -XXX,XX +XXX,XX @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
23
} else if (tp##_is_infinity(arg)) { \
24
fprf = neg ? 0x09 << FPSCR_FPRF : 0x05 << FPSCR_FPRF; \
25
} else { \
26
- float_status dummy = { }; /* snan_bit_is_one = 0 */ \
27
- if (tp##_is_signaling_nan(arg, &dummy)) { \
28
+ if (tp##_is_signaling_nan(arg, &env->fp_status)) { \
29
fprf = 0x00 << FPSCR_FPRF; \
30
} else { \
31
fprf = 0x11 << FPSCR_FPRF; \
32
--
33
2.34.1
diff view generated by jsdifflib
[PULL 17/24] hw/misc: In STM32L4x5 EXTI, handle direct interrupts
[PULL 39/72] target/arm: Copy entire float_status in is_ebf
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The previous implementation for EXTI interrupts only handled
3
Now that float_status has a bunch of fp parameters,
4
"configurable" interrupts, like those originating from STM32L4x5 SYSCFG
4
it is easier to copy an existing structure than create
5
(the only device currently connected to the EXTI up until now).
5
one from scratch. Begin by copying the structure that
6
corresponds to the FPSR and make only the adjustments
7
required for BFloat16 semantics.
6
8
7
In order to connect STM32L4x5 USART to the EXTI, this commit adds
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
handling for direct interrupts (interrupts without configurable edge).
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
10
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
11
Message-id: 20240707085927.122867-3-ines.varhol@telecom-paris.fr
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20241203203949.483774-2-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
14
---
15
hw/misc/stm32l4x5_exti.c | 7 +++++++
15
target/arm/tcg/vec_helper.c | 20 +++++++-------------
16
1 file changed, 7 insertions(+)
16
1 file changed, 7 insertions(+), 13 deletions(-)
17
17
18
diff --git a/hw/misc/stm32l4x5_exti.c b/hw/misc/stm32l4x5_exti.c
18
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
19
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/misc/stm32l4x5_exti.c
20
--- a/target/arm/tcg/vec_helper.c
21
+++ b/hw/misc/stm32l4x5_exti.c
21
+++ b/target/arm/tcg/vec_helper.c
22
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_exti_set_irq(void *opaque, int irq, int level)
22
@@ -XXX,XX +XXX,XX @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp)
23
return;
23
* no effect on AArch32 instructions.
24
*/
25
bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF;
26
- *statusp = (float_status){
27
- .tininess_before_rounding = float_tininess_before_rounding,
28
- .float_rounding_mode = float_round_to_odd_inf,
29
- .flush_to_zero = true,
30
- .flush_inputs_to_zero = true,
31
- .default_nan_mode = true,
32
- };
33
+
34
+ *statusp = env->vfp.fp_status;
35
+ set_default_nan_mode(true, statusp);
36
37
if (ebf) {
38
- float_status *fpst = &env->vfp.fp_status;
39
- set_flush_to_zero(get_flush_to_zero(fpst), statusp);
40
- set_flush_inputs_to_zero(get_flush_inputs_to_zero(fpst), statusp);
41
- set_float_rounding_mode(get_float_rounding_mode(fpst), statusp);
42
-
43
/* EBF=1 needs to do a step with round-to-odd semantics */
44
*oddstatusp = *statusp;
45
set_float_rounding_mode(float_round_to_odd, oddstatusp);
46
+ } else {
47
+ set_flush_to_zero(true, statusp);
48
+ set_flush_inputs_to_zero(true, statusp);
49
+ set_float_rounding_mode(float_round_to_odd_inf, statusp);
24
}
50
}
25
51
-
26
+ /* In case of a direct line interrupt */
52
return ebf;
27
+ if (extract32(exti_romask[bank], irq, 1)) {
53
}
28
+ qemu_set_irq(s->irq[oirq], level);
29
+ return;
30
+ }
31
+
32
+ /* In case of a configurable interrupt */
33
if ((level && extract32(s->rtsr[bank], irq, 1)) ||
34
(!level && extract32(s->ftsr[bank], irq, 1))) {
35
54
36
--
55
--
37
2.34.1
56
2.34.1
38
57
39
58
diff view generated by jsdifflib
[PULL 03/24] target/arm: Make vfp_set_fpscr() call vfp_set_{fpcr, fpsr}
[PULL 40/72] fpu: Allow runtime choice of default NaN value
1
Make vfp_set_fpscr() call vfp_set_fpsr() and vfp_set_fpcr()
1
Currently we hardcode the default NaN value in parts64_default_nan()
2
instead of the other way around.
2
using a compile-time ifdef ladder. This is awkward for two cases:
3
* for single-QEMU-binary we can't hard-code target-specifics like this
4
* for Arm FEAT_AFP the default NaN value depends on FPCR.AH
5
(specifically the sign bit is different)
3
6
4
The masking we do when getting and setting vfp.xregs[ARM_VFP_FPSCR]
7
Add a field to float_status to specify the default NaN value; fall
5
is a little awkward, but we are going to change where we store the
8
back to the old ifdef behaviour if these are not set.
6
underlying FPSR and FPCR information in a later commit, so it will
9
7
go away then.
10
The default NaN value is specified by setting a uint8_t to a
11
pattern corresponding to the sign and upper fraction parts of
12
the NaN; the lower bits of the fraction are set from bit 0 of
13
the pattern.
8
14
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20240628142347.1283015-4-peter.maydell@linaro.org
17
Message-id: 20241202131347.498124-35-peter.maydell@linaro.org
12
---
18
---
13
target/arm/cpu.h | 22 +++++----
19
include/fpu/softfloat-helpers.h | 11 +++++++
14
target/arm/vfp_helper.c | 100 ++++++++++++++++++++++++++--------------
20
include/fpu/softfloat-types.h | 10 ++++++
15
2 files changed, 78 insertions(+), 44 deletions(-)
21
fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++-------------
22
3 files changed, 54 insertions(+), 22 deletions(-)
16
23
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
24
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
18
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
26
--- a/include/fpu/softfloat-helpers.h
20
+++ b/target/arm/cpu.h
27
+++ b/include/fpu/softfloat-helpers.h
21
@@ -XXX,XX +XXX,XX @@ uint32_t vfp_get_fpsr(CPUARMState *env);
28
@@ -XXX,XX +XXX,XX @@ static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
22
*/
29
status->float_infzeronan_rule = rule;
23
uint32_t vfp_get_fpcr(CPUARMState *env);
24
25
-static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
26
-{
27
- uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
28
- vfp_set_fpscr(env, new_fpscr);
29
-}
30
+/**
31
+ * vfp_set_fpsr: write the AArch64 FPSR
32
+ * @env: CPU context
33
+ * @value: new value
34
+ */
35
+void vfp_set_fpsr(CPUARMState *env, uint32_t value);
36
37
-static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
38
-{
39
- uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
40
- vfp_set_fpscr(env, new_fpscr);
41
-}
42
+/**
43
+ * vfp_set_fpcr: write the AArch64 FPCR
44
+ * @env: CPU context
45
+ * @value: new value
46
+ */
47
+void vfp_set_fpcr(CPUARMState *env, uint32_t value);
48
49
enum arm_cpu_mode {
50
ARM_CPU_MODE_USR = 0x10,
51
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/target/arm/vfp_helper.c
54
+++ b/target/arm/vfp_helper.c
55
@@ -XXX,XX +XXX,XX @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
56
return vfp_exceptbits_from_host(i);
57
}
30
}
58
31
59
-static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
32
+static inline void set_float_default_nan_pattern(uint8_t dnan_pattern,
60
+static void vfp_set_fpsr_to_host(CPUARMState *env, uint32_t val)
33
+ float_status *status)
61
+{
34
+{
62
+ /*
35
+ status->default_nan_pattern = dnan_pattern;
63
+ * The exception flags are ORed together when we read fpscr so we
64
+ * only need to preserve the current state in one of our
65
+ * float_status values.
66
+ */
67
+ int i = vfp_exceptbits_to_host(val);
68
+ set_float_exception_flags(i, &env->vfp.fp_status);
69
+ set_float_exception_flags(0, &env->vfp.fp_status_f16);
70
+ set_float_exception_flags(0, &env->vfp.standard_fp_status);
71
+ set_float_exception_flags(0, &env->vfp.standard_fp_status_f16);
72
+}
36
+}
73
+
37
+
74
+static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val)
38
static inline void set_flush_to_zero(bool val, float_status *status)
75
{
39
{
76
- int i;
40
status->flush_to_zero = val;
77
uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR];
41
@@ -XXX,XX +XXX,XX @@ static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status
78
42
return status->float_infzeronan_rule;
79
changed ^= val;
80
if (changed & (3 << 22)) {
81
- i = (val >> 22) & 3;
82
+ int i = (val >> 22) & 3;
83
switch (i) {
84
case FPROUNDING_TIEEVEN:
85
i = float_round_nearest_even;
86
@@ -XXX,XX +XXX,XX @@ static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
87
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
88
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
89
}
90
-
91
- /*
92
- * The exception flags are ORed together when we read fpscr so we
93
- * only need to preserve the current state in one of our
94
- * float_status values.
95
- */
96
- i = vfp_exceptbits_to_host(val);
97
- set_float_exception_flags(i, &env->vfp.fp_status);
98
- set_float_exception_flags(0, &env->vfp.fp_status_f16);
99
- set_float_exception_flags(0, &env->vfp.standard_fp_status);
100
- set_float_exception_flags(0, &env->vfp.standard_fp_status_f16);
101
}
43
}
102
44
103
#else
45
+static inline uint8_t get_float_default_nan_pattern(float_status *status)
104
@@ -XXX,XX +XXX,XX @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
105
return 0;
106
}
107
108
-static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
109
+static void vfp_set_fpsr_to_host(CPUARMState *env, uint32_t val)
110
+{
46
+{
47
+ return status->default_nan_pattern;
111
+}
48
+}
112
+
49
+
113
+static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val)
50
static inline bool get_flush_to_zero(float_status *status)
114
{
51
{
115
}
52
return status->flush_to_zero;
116
53
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
117
@@ -XXX,XX +XXX,XX @@ uint32_t vfp_get_fpscr(CPUARMState *env)
54
index XXXXXXX..XXXXXXX 100644
118
return HELPER(vfp_get_fpscr)(env);
55
--- a/include/fpu/softfloat-types.h
119
}
56
+++ b/include/fpu/softfloat-types.h
120
57
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
121
-void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
58
/* should denormalised inputs go to zero and set the input_denormal flag? */
122
+void vfp_set_fpsr(CPUARMState *env, uint32_t val)
59
bool flush_inputs_to_zero;
123
+{
60
bool default_nan_mode;
124
+ ARMCPU *cpu = env_archcpu(env);
61
+ /*
62
+ * The pattern to use for the default NaN. Here the high bit specifies
63
+ * the default NaN's sign bit, and bits 6..0 specify the high bits of the
64
+ * fractional part. The low bits of the fractional part are copies of bit 0.
65
+ * The exponent of the default NaN is (as for any NaN) always all 1s.
66
+ * Note that a value of 0 here is not a valid NaN. The target must set
67
+ * this to the correct non-zero value, or we will assert when trying to
68
+ * create a default NaN.
69
+ */
70
+ uint8_t default_nan_pattern;
71
/*
72
* The flags below are not used on all specializations and may
73
* constant fold away (see snan_bit_is_one()/no_signalling_nans() in
74
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
75
index XXXXXXX..XXXXXXX 100644
76
--- a/fpu/softfloat-specialize.c.inc
77
+++ b/fpu/softfloat-specialize.c.inc
78
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
79
{
80
bool sign = 0;
81
uint64_t frac;
82
+ uint8_t dnan_pattern = status->default_nan_pattern;
83
84
+ if (dnan_pattern == 0) {
85
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
86
- /* !snan_bit_is_one, set all bits */
87
- frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
88
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
89
+ /* Sign bit clear, all frac bits set */
90
+ dnan_pattern = 0b01111111;
91
+#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
92
|| defined(TARGET_MICROBLAZE)
93
- /* !snan_bit_is_one, set sign and msb */
94
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
95
- sign = 1;
96
+ /* Sign bit set, most significant frac bit set */
97
+ dnan_pattern = 0b11000000;
98
#elif defined(TARGET_HPPA)
99
- /* snan_bit_is_one, set msb-1. */
100
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
101
+ /* Sign bit clear, msb-1 frac bit set */
102
+ dnan_pattern = 0b00100000;
103
#elif defined(TARGET_HEXAGON)
104
- sign = 1;
105
- frac = ~0ULL;
106
+ /* Sign bit set, all frac bits set. */
107
+ dnan_pattern = 0b11111111;
108
#else
109
- /*
110
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
111
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
112
- * do not have floating-point.
113
- */
114
- if (snan_bit_is_one(status)) {
115
- /* set all bits other than msb */
116
- frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
117
- } else {
118
- /* set msb */
119
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
120
- }
121
+ /*
122
+ * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
123
+ * S390, SH4, TriCore, and Xtensa. Our other supported targets
124
+ * do not have floating-point.
125
+ */
126
+ if (snan_bit_is_one(status)) {
127
+ /* sign bit clear, set all frac bits other than msb */
128
+ dnan_pattern = 0b00111111;
129
+ } else {
130
+ /* sign bit clear, set frac msb */
131
+ dnan_pattern = 0b01000000;
132
+ }
133
#endif
134
+ }
135
+ assert(dnan_pattern != 0);
125
+
136
+
126
+ vfp_set_fpsr_to_host(env, val);
137
+ sign = dnan_pattern >> 7;
127
+
128
+ if (arm_feature(env, ARM_FEATURE_NEON) ||
129
+ cpu_isar_feature(aa32_mve, cpu)) {
130
+ /*
131
+ * The bit we set within vfp.qc[] is arbitrary; the array as a
132
+ * whole being zero/non-zero is what counts.
133
+ */
134
+ env->vfp.qc[0] = val & FPCR_QC;
135
+ env->vfp.qc[1] = 0;
136
+ env->vfp.qc[2] = 0;
137
+ env->vfp.qc[3] = 0;
138
+ }
139
+
140
+ /*
138
+ /*
141
+ * The only FPSR bits we keep in vfp.xregs[FPSCR] are NZCV:
139
+ * Place default_nan_pattern [6:0] into bits [62:56],
142
+ * the exception flags IOC|DZC|OFC|UFC|IXC|IDC are stored in
140
+ * and replecate bit [0] down into [55:0]
143
+ * fp_status, and QC is in vfp.qc[]. Store the NZCV bits there,
144
+ * and zero any of the other FPSR bits (but preserve the FPCR
145
+ * bits).
146
+ */
141
+ */
147
+ val &= FPCR_NZCV_MASK;
142
+ frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern);
148
+ env->vfp.xregs[ARM_VFP_FPSCR] &= ~FPSR_MASK;
143
+ frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1));
149
+ env->vfp.xregs[ARM_VFP_FPSCR] |= val;
144
150
+}
145
*p = (FloatParts64) {
151
+
146
.cls = float_class_qnan,
152
+void vfp_set_fpcr(CPUARMState *env, uint32_t val)
153
{
154
ARMCPU *cpu = env_archcpu(env);
155
156
@@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
157
val &= ~FPCR_FZ16;
158
}
159
160
- vfp_set_fpscr_to_host(env, val);
161
+ vfp_set_fpcr_to_host(env, val);
162
163
if (!arm_feature(env, ARM_FEATURE_M)) {
164
/*
165
@@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
166
FPCR_LTPSIZE_LENGTH);
167
}
168
169
- if (arm_feature(env, ARM_FEATURE_NEON) ||
170
- cpu_isar_feature(aa32_mve, cpu)) {
171
- /*
172
- * The bit we set within fpscr_q is arbitrary; the register as a
173
- * whole being zero/non-zero is what counts.
174
- */
175
- env->vfp.qc[0] = val & FPCR_QC;
176
- env->vfp.qc[1] = 0;
177
- env->vfp.qc[2] = 0;
178
- env->vfp.qc[3] = 0;
179
- }
180
-
181
/*
182
* We don't implement trapped exception handling, so the
183
* trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
184
*
185
- * The exception flags IOC|DZC|OFC|UFC|IXC|IDC are stored in
186
- * fp_status; QC, Len and Stride are stored separately earlier.
187
- * Clear out all of those and the RES0 bits: only NZCV, AHP, DN,
188
- * FZ, RMode and FZ16 are kept in vfp.xregs[FPSCR].
189
+ * The FPCR bits we keep in vfp.xregs[FPSCR] are AHP, DN, FZ, RMode
190
+ * and FZ16. Len, Stride and LTPSIZE we just handled. Store those bits
191
+ * there, and zero any of the other FPCR bits and the RES0 and RAZ/WI
192
+ * bits.
193
*/
194
- env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000;
195
+ val &= FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK | FPCR_FZ16;
196
+ env->vfp.xregs[ARM_VFP_FPSCR] &= ~FPCR_MASK;
197
+ env->vfp.xregs[ARM_VFP_FPSCR] |= val;
198
+}
199
+
200
+void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
201
+{
202
+ vfp_set_fpcr(env, val & FPCR_MASK);
203
+ vfp_set_fpsr(env, val & FPSR_MASK);
204
}
205
206
void vfp_set_fpscr(CPUARMState *env, uint32_t val)
207
--
147
--
208
2.34.1
148
2.34.1
diff view generated by jsdifflib
New patch
[PULL 41/72] tests/fp: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for the tests/fp code.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-36-peter.maydell@linaro.org
6
---
7
tests/fp/fp-bench.c | 1 +
8
tests/fp/fp-test-log2.c | 1 +
9
tests/fp/fp-test.c | 1 +
10
3 files changed, 3 insertions(+)
11
12
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/tests/fp/fp-bench.c
15
+++ b/tests/fp/fp-bench.c
16
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
17
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
18
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
19
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
20
+ set_float_default_nan_pattern(0b01000000, &soft_status);
21
22
f = bench_funcs[operation][precision];
23
g_assert(f);
24
diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/tests/fp/fp-test-log2.c
27
+++ b/tests/fp/fp-test-log2.c
28
@@ -XXX,XX +XXX,XX @@ int main(int ac, char **av)
29
int i;
30
31
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
32
+ set_float_default_nan_pattern(0b01000000, &qsf);
33
set_float_rounding_mode(float_round_nearest_even, &qsf);
34
35
test.d = 0.0;
36
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/tests/fp/fp-test.c
39
+++ b/tests/fp/fp-test.c
40
@@ -XXX,XX +XXX,XX @@ void run_test(void)
41
*/
42
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
43
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
44
+ set_float_default_nan_pattern(0b01000000, &qsf);
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
46
47
genCases_setLevel(test_level);
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 42/72] target/microblaze: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-37-peter.maydell@linaro.org
7
---
8
target/microblaze/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
11
12
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/microblaze/cpu.c
15
+++ b/target/microblaze/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_reset_hold(Object *obj, ResetType type)
17
* this architecture.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
20
+ /* Default NaN: sign bit set, most significant frac bit set */
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
22
23
#if defined(CONFIG_USER_ONLY)
24
/* start in user mode with interrupts enabled. */
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
31
/* Sign bit clear, all frac bits set */
32
dnan_pattern = 0b01111111;
33
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
34
- || defined(TARGET_MICROBLAZE)
35
+#elif defined(TARGET_I386) || defined(TARGET_X86_64)
36
/* Sign bit set, most significant frac bit set */
37
dnan_pattern = 0b11000000;
38
#elif defined(TARGET_HPPA)
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 43/72] target/i386: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-38-peter.maydell@linaro.org
7
---
8
target/i386/tcg/fpu_helper.c | 4 ++++
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 4 insertions(+), 3 deletions(-)
11
12
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/i386/tcg/fpu_helper.c
15
+++ b/target/i386/tcg/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
17
*/
18
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
19
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
20
+ /* Default NaN: sign bit set, most significant frac bit set */
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
22
+ set_float_default_nan_pattern(0b11000000, &env->mmx_status);
23
+ set_float_default_nan_pattern(0b11000000, &env->sse_status);
24
}
25
26
static inline uint8_t save_exception_flags(CPUX86State *env)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
29
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
32
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
33
/* Sign bit clear, all frac bits set */
34
dnan_pattern = 0b01111111;
35
-#elif defined(TARGET_I386) || defined(TARGET_X86_64)
36
- /* Sign bit set, most significant frac bit set */
37
- dnan_pattern = 0b11000000;
38
#elif defined(TARGET_HPPA)
39
/* Sign bit clear, msb-1 frac bit set */
40
dnan_pattern = 0b00100000;
41
--
42
2.34.1
diff view generated by jsdifflib
New patch
[PULL 44/72] target/hppa: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-39-peter.maydell@linaro.org
7
---
8
target/hppa/fpu_helper.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 2 insertions(+), 3 deletions(-)
11
12
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/hppa/fpu_helper.c
15
+++ b/target/hppa/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
17
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
18
/* For inf * 0 + NaN, return the input NaN */
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ /* Default NaN: sign bit clear, msb-1 frac bit set */
21
+ set_float_default_nan_pattern(0b00100000, &env->fp_status);
22
}
23
24
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
31
/* Sign bit clear, all frac bits set */
32
dnan_pattern = 0b01111111;
33
-#elif defined(TARGET_HPPA)
34
- /* Sign bit clear, msb-1 frac bit set */
35
- dnan_pattern = 0b00100000;
36
#elif defined(TARGET_HEXAGON)
37
/* Sign bit set, all frac bits set. */
38
dnan_pattern = 0b11111111;
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 45/72] target/alpha: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for the alpha target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-40-peter.maydell@linaro.org
6
---
7
target/alpha/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/alpha/cpu.c
13
+++ b/target/alpha/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void alpha_cpu_initfn(Object *obj)
15
* operand in Fa. That is float_2nan_prop_ba.
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
18
+ /* Default NaN: sign bit clear, msb frac bit set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
#if defined(CONFIG_USER_ONLY)
21
env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN;
22
cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD
23
--
24
2.34.1
diff view generated by jsdifflib
[PULL 13/24] target/arm: Set arm_v7m_tcg_ops cpu_exec_halt to arm_cpu_exec_halt()
[PULL 46/72] target/arm: Set default NaN pattern explicitly
1
In commit a96edb687e76 we set the cpu_exec_halt field of the
1
Set the default NaN pattern explicitly for the arm target.
2
TCGCPUOps arm_tcg_ops to arm_cpu_exec_halt(), but we left the
2
This includes setting it for the old linux-user nwfpe emulation.
3
arm_v7m_tcg_ops struct unchanged. That isn't wrong, because for
3
For nwfpe, our default doesn't match the real kernel, but we
4
M-profile FEAT_WFxT doesn't exist and the default handling for "no
4
avoid making a behaviour change in this commit.
5
cpu_exec_halt method" is correct, but it's perhaps a little
6
confusing. We would also like to make setting the cpu_exec_halt
7
method mandatory.
8
9
Initialize arm_v7m_tcg_ops cpu_exec_halt to the same function we use
10
for A-profile. (On M-profile we never set up the wfxt timer so there
11
is no change in behaviour here.)
12
5
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-41-peter.maydell@linaro.org
15
---
9
---
16
target/arm/internals.h | 3 +++
10
linux-user/arm/nwfpe/fpa11.c | 5 +++++
17
target/arm/cpu.c | 2 +-
11
target/arm/cpu.c | 2 ++
18
target/arm/tcg/cpu-v7m.c | 1 +
12
2 files changed, 7 insertions(+)
19
3 files changed, 5 insertions(+), 1 deletion(-)
20
13
21
diff --git a/target/arm/internals.h b/target/arm/internals.h
14
diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c
22
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/internals.h
16
--- a/linux-user/arm/nwfpe/fpa11.c
24
+++ b/target/arm/internals.h
17
+++ b/linux-user/arm/nwfpe/fpa11.c
25
@@ -XXX,XX +XXX,XX @@ void arm_restore_state_to_opc(CPUState *cs,
18
@@ -XXX,XX +XXX,XX @@ void resetFPA11(void)
26
19
* this late date.
27
#ifdef CONFIG_TCG
20
*/
28
void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
21
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status);
29
+
22
+ /*
30
+/* Our implementation of TCGCPUOps::cpu_exec_halt */
23
+ * Use the same default NaN value as Arm VFP. This doesn't match
31
+bool arm_cpu_exec_halt(CPUState *cs);
24
+ * the Linux kernel's nwfpe emulation, which uses an all-1s value.
32
#endif /* CONFIG_TCG */
25
+ */
33
26
+ set_float_default_nan_pattern(0b01000000, &fpa11->fp_status);
34
typedef enum ARMFPRounding {
27
}
28
29
void SetRoundingMode(const unsigned int opcode)
35
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
30
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
36
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/cpu.c
32
--- a/target/arm/cpu.c
38
+++ b/target/arm/cpu.c
33
+++ b/target/arm/cpu.c
39
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
34
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
35
* the pseudocode function the arguments are in the order c, a, b.
36
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
37
* and the input NaN if it is signalling
38
+ * * Default NaN has sign bit clear, msb frac bit set
39
*/
40
static void arm_set_default_fp_behaviours(float_status *s)
41
{
42
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
44
set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
46
+ set_float_default_nan_pattern(0b01000000, s);
40
}
47
}
41
48
42
#ifdef CONFIG_TCG
49
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
43
-static bool arm_cpu_exec_halt(CPUState *cs)
44
+bool arm_cpu_exec_halt(CPUState *cs)
45
{
46
bool leave_halt = cpu_has_work(cs);
47
48
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/tcg/cpu-v7m.c
51
+++ b/target/arm/tcg/cpu-v7m.c
52
@@ -XXX,XX +XXX,XX @@ static const TCGCPUOps arm_v7m_tcg_ops = {
53
#else
54
.tlb_fill = arm_cpu_tlb_fill,
55
.cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
56
+ .cpu_exec_halt = arm_cpu_exec_halt,
57
.do_interrupt = arm_v7m_cpu_do_interrupt,
58
.do_transaction_failed = arm_cpu_do_transaction_failed,
59
.do_unaligned_access = arm_cpu_do_unaligned_access,
60
--
50
--
61
2.34.1
51
2.34.1
62
63
diff view generated by jsdifflib
New patch
[PULL 47/72] target/loongarch: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for loongarch.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-42-peter.maydell@linaro.org
6
---
7
target/loongarch/tcg/fpu_helper.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/loongarch/tcg/fpu_helper.c
13
+++ b/target/loongarch/tcg/fpu_helper.c
14
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
15
*/
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
17
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
18
+ /* Default NaN: sign bit clear, msb frac bit set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
}
21
22
int ieee_ex_to_loongarch(int xcpt)
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 48/72] target/m68k: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for m68k.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-43-peter.maydell@linaro.org
6
---
7
target/m68k/cpu.c | 2 ++
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 3 insertions(+), 1 deletion(-)
10
11
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/m68k/cpu.c
14
+++ b/target/m68k/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
16
* preceding paragraph for nonsignaling NaNs.
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
+ /* Default NaN: sign bit clear, all frac bits set */
20
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
21
22
nan = floatx80_default_nan(&env->fp_status);
23
for (i = 0; i < 8; i++) {
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
29
uint8_t dnan_pattern = status->default_nan_pattern;
30
31
if (dnan_pattern == 0) {
32
-#if defined(TARGET_SPARC) || defined(TARGET_M68K)
33
+#if defined(TARGET_SPARC)
34
/* Sign bit clear, all frac bits set */
35
dnan_pattern = 0b01111111;
36
#elif defined(TARGET_HEXAGON)
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 49/72] target/mips: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for MIPS. Note that this
2
is our only target which currently changes the default NaN
3
at runtime (which it was previously doing indirectly when it
4
changed the snan_bit_is_one setting).
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-44-peter.maydell@linaro.org
9
---
10
target/mips/fpu_helper.h | 7 +++++++
11
target/mips/msa.c | 3 +++
12
2 files changed, 10 insertions(+)
13
14
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/mips/fpu_helper.h
17
+++ b/target/mips/fpu_helper.h
18
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
19
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
20
nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
21
set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
22
+ /*
23
+ * With nan2008, the default NaN value has the sign bit clear and the
24
+ * frac msb set; with the older mode, the sign bit is clear, and all
25
+ * frac bits except the msb are set.
26
+ */
27
+ set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111,
28
+ &env->active_fpu.fp_status);
29
30
}
31
32
diff --git a/target/mips/msa.c b/target/mips/msa.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/mips/msa.c
35
+++ b/target/mips/msa.c
36
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
37
/* Inf * 0 + NaN returns the input NaN */
38
set_float_infzeronan_rule(float_infzeronan_dnan_never,
39
&env->active_tc.msa_fp_status);
40
+ /* Default NaN: sign bit clear, frac msb set */
41
+ set_float_default_nan_pattern(0b01000000,
42
+ &env->active_tc.msa_fp_status);
43
}
44
--
45
2.34.1
diff view generated by jsdifflib
New patch
[PULL 50/72] target/openrisc: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for openrisc.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-45-peter.maydell@linaro.org
6
---
7
target/openrisc/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/openrisc/cpu.c
13
+++ b/target/openrisc/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type)
15
*/
16
set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status);
17
18
+ /* Default NaN: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status);
20
21
#ifndef CONFIG_USER_ONLY
22
cpu->env.picmr = 0x00000000;
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 51/72] target/ppc: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for ppc.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-46-peter.maydell@linaro.org
6
---
7
target/ppc/cpu_init.c | 4 ++++
8
1 file changed, 4 insertions(+)
9
10
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/ppc/cpu_init.c
13
+++ b/target/ppc/cpu_init.c
14
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
15
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
17
18
+ /* Default NaN: sign bit clear, set frac msb */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
+ set_float_default_nan_pattern(0b01000000, &env->vec_status);
21
+
22
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
23
ppc_spr_t *spr = &env->spr_cb[i];
24
25
--
26
2.34.1
diff view generated by jsdifflib
New patch
[PULL 52/72] target/sh4: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for sh4. Note that sh4
2
is one of the only three targets (the others being HPPA and
3
sometimes MIPS) that has snan_bit_is_one set.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-47-peter.maydell@linaro.org
8
---
9
target/sh4/cpu.c | 2 ++
10
1 file changed, 2 insertions(+)
11
12
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sh4/cpu.c
15
+++ b/target/sh4/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_reset_hold(Object *obj, ResetType type)
17
set_flush_to_zero(1, &env->fp_status);
18
#endif
19
set_default_nan_mode(1, &env->fp_status);
20
+ /* sign bit clear, set all frac bits other than msb */
21
+ set_float_default_nan_pattern(0b00111111, &env->fp_status);
22
}
23
24
static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
25
--
26
2.34.1
diff view generated by jsdifflib
[PULL 08/24] target/arm: Rename FPSR_MASK and FPCR_MASK and define them symbolically
[PULL 53/72] target/rx: Set default NaN pattern explicitly
1
Now that we store FPSR and FPCR separately, the FPSR_MASK and
1
Set the default NaN pattern explicitly for rx.
2
FPCR_MASK macros are slightly confusingly named and the comment
3
describing them is out of date. Rename them to FPSCR_FPSR_MASK and
4
FPSCR_FPCR_MASK, document that they are the mask of which FPSCR bits
5
are architecturally mapped to which AArch64 register, and define them
6
symbolically rather than as hex values. (This latter requires
7
defining some extra macros for bits which we haven't previously
8
defined.)
9
2
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20240628142347.1283015-9-peter.maydell@linaro.org
5
Message-id: 20241202131347.498124-48-peter.maydell@linaro.org
13
---
6
---
14
target/arm/cpu.h | 41 ++++++++++++++++++++++++++++++++++-------
7
target/rx/cpu.c | 2 ++
15
target/arm/machine.c | 3 ++-
8
1 file changed, 2 insertions(+)
16
target/arm/vfp_helper.c | 7 ++++---
17
3 files changed, 40 insertions(+), 11 deletions(-)
18
9
19
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
10
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
20
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/cpu.h
12
--- a/target/rx/cpu.c
22
+++ b/target/arm/cpu.h
13
+++ b/target/rx/cpu.c
23
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
14
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_reset_hold(Object *obj, ResetType type)
24
uint32_t vfp_get_fpscr(CPUARMState *env);
15
* then prefer dest over source", which is float_2nan_prop_s_ab.
25
void vfp_set_fpscr(CPUARMState *env, uint32_t val);
16
*/
26
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
27
-/* FPCR, Floating Point Control Register
18
+ /* Default NaN value: sign bit clear, set frac msb */
28
- * FPSR, Floating Poiht Status Register
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
29
+/*
30
+ * FPCR, Floating Point Control Register
31
+ * FPSR, Floating Point Status Register
32
*
33
- * For A64 the FPSCR is split into two logically distinct registers,
34
- * FPCR and FPSR. However since they still use non-overlapping bits
35
- * we store the underlying state in fpscr and just mask on read/write.
36
+ * For A64 floating point control and status bits are stored in
37
+ * two logically distinct registers, FPCR and FPSR. We store these
38
+ * in QEMU in vfp.fpcr and vfp.fpsr.
39
+ * For A32 there was only one register, FPSCR. The bits are arranged
40
+ * such that FPSCR bits map to FPCR or FPSR bits in the same bit positions,
41
+ * so we can use appropriate masking to handle FPSCR reads and writes.
42
+ * Note that the FPCR has some bits which are not visible in the
43
+ * AArch32 view (for FEAT_AFP). Writing the FPSCR leaves these unchanged.
44
*/
45
-#define FPSR_MASK 0xf800009f
46
-#define FPCR_MASK 0x07ff9f00
47
48
/* FPCR bits */
49
#define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */
50
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
51
#define FPCR_UFE (1 << 11) /* Underflow exception trap enable */
52
#define FPCR_IXE (1 << 12) /* Inexact exception trap enable */
53
#define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */
54
+#define FPCR_LEN_MASK (7 << 16) /* LEN, A-profile only */
55
#define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
56
+#define FPCR_STRIDE_MASK (3 << 20) /* Stride */
57
#define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */
58
#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
59
#define FPCR_DN (1 << 25) /* Default NaN enable bit */
60
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
61
#define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT)
62
#define FPCR_LTPSIZE_LENGTH 3
63
64
+/* Cumulative exception trap enable bits */
65
+#define FPCR_EEXC_MASK (FPCR_IOE | FPCR_DZE | FPCR_OFE | FPCR_UFE | FPCR_IXE | FPCR_IDE)
66
+
67
/* FPSR bits */
68
+#define FPSR_IOC (1 << 0) /* Invalid Operation cumulative exception */
69
+#define FPSR_DZC (1 << 1) /* Divide by Zero cumulative exception */
70
+#define FPSR_OFC (1 << 2) /* Overflow cumulative exception */
71
+#define FPSR_UFC (1 << 3) /* Underflow cumulative exception */
72
+#define FPSR_IXC (1 << 4) /* Inexact cumulative exception */
73
+#define FPSR_IDC (1 << 7) /* Input Denormal cumulative exception */
74
#define FPSR_QC (1 << 27) /* Cumulative saturation bit */
75
#define FPSR_V (1 << 28) /* FP overflow flag */
76
#define FPSR_C (1 << 29) /* FP carry flag */
77
#define FPSR_Z (1 << 30) /* FP zero flag */
78
#define FPSR_N (1 << 31) /* FP negative flag */
79
80
+/* Cumulative exception status bits */
81
+#define FPSR_CEXC_MASK (FPSR_IOC | FPSR_DZC | FPSR_OFC | FPSR_UFC | FPSR_IXC | FPSR_IDC)
82
+
83
#define FPSR_NZCV_MASK (FPSR_N | FPSR_Z | FPSR_C | FPSR_V)
84
#define FPSR_NZCVQC_MASK (FPSR_NZCV_MASK | FPSR_QC)
85
86
+/* A32 FPSCR bits which architecturally map to FPSR bits */
87
+#define FPSCR_FPSR_MASK (FPSR_NZCVQC_MASK | FPSR_CEXC_MASK)
88
+/* A32 FPSCR bits which architecturally map to FPCR bits */
89
+#define FPSCR_FPCR_MASK (FPCR_EEXC_MASK | FPCR_LEN_MASK | FPCR_FZ16 | \
90
+ FPCR_STRIDE_MASK | FPCR_RMODE_MASK | \
91
+ FPCR_FZ | FPCR_DN | FPCR_AHP)
92
+/* These masks don't overlap: each bit lives in only one place */
93
+QEMU_BUILD_BUG_ON(FPSCR_FPSR_MASK & FPSCR_FPCR_MASK);
94
+
95
/**
96
* vfp_get_fpsr: read the AArch64 FPSR
97
* @env: CPU context
98
diff --git a/target/arm/machine.c b/target/arm/machine.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/machine.c
101
+++ b/target/arm/machine.c
102
@@ -XXX,XX +XXX,XX @@ static bool vfp_fpcr_fpsr_needed(void *opaque)
103
ARMCPU *cpu = opaque;
104
CPUARMState *env = &cpu->env;
105
106
- return (vfp_get_fpcr(env) & ~FPCR_MASK) || (vfp_get_fpsr(env) & ~FPSR_MASK);
107
+ return (vfp_get_fpcr(env) & ~FPSCR_FPCR_MASK) ||
108
+ (vfp_get_fpsr(env) & ~FPSCR_FPSR_MASK);
109
}
20
}
110
21
111
static int get_fpscr(QEMUFile *f, void *opaque, size_t size,
22
static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
112
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
113
index XXXXXXX..XXXXXXX 100644
114
--- a/target/arm/vfp_helper.c
115
+++ b/target/arm/vfp_helper.c
116
@@ -XXX,XX +XXX,XX @@ uint32_t vfp_get_fpsr(CPUARMState *env)
117
118
uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
119
{
120
- return (vfp_get_fpcr(env) & FPCR_MASK) | (vfp_get_fpsr(env) & FPSR_MASK);
121
+ return (vfp_get_fpcr(env) & FPSCR_FPCR_MASK) |
122
+ (vfp_get_fpsr(env) & FPSCR_FPSR_MASK);
123
}
124
125
uint32_t vfp_get_fpscr(CPUARMState *env)
126
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpcr(CPUARMState *env, uint32_t val)
127
128
void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
129
{
130
- vfp_set_fpcr(env, val & FPCR_MASK);
131
- vfp_set_fpsr(env, val & FPSR_MASK);
132
+ vfp_set_fpcr(env, val & FPSCR_FPCR_MASK);
133
+ vfp_set_fpsr(env, val & FPSCR_FPSR_MASK);
134
}
135
136
void vfp_set_fpscr(CPUARMState *env, uint32_t val)
137
--
23
--
138
2.34.1
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 54/72] target/s390x: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for s390x.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-49-peter.maydell@linaro.org
6
---
7
target/s390x/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/s390x/cpu.c
13
+++ b/target/s390x/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
15
set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
16
set_float_infzeronan_rule(float_infzeronan_dnan_always,
17
&env->fpu_status);
18
+ /* Default NaN value: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fpu_status);
20
/* fall through */
21
case RESET_TYPE_S390_CPU_NORMAL:
22
env->psw.mask &= ~PSW_MASK_RI;
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 55/72] target/sparc: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for SPARC, and remove
2
the ifdef from parts64_default_nan.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-50-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 5 +----
10
2 files changed, 3 insertions(+), 4 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
18
/* For inf * 0 + NaN, return the input NaN */
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ /* Default NaN value: sign bit clear, all frac bits set */
21
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
22
23
cpu_exec_realizefn(cs, &local_err);
24
if (local_err != NULL) {
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
uint8_t dnan_pattern = status->default_nan_pattern;
31
32
if (dnan_pattern == 0) {
33
-#if defined(TARGET_SPARC)
34
- /* Sign bit clear, all frac bits set */
35
- dnan_pattern = 0b01111111;
36
-#elif defined(TARGET_HEXAGON)
37
+#if defined(TARGET_HEXAGON)
38
/* Sign bit set, all frac bits set. */
39
dnan_pattern = 0b11111111;
40
#else
41
--
42
2.34.1
diff view generated by jsdifflib
[PULL 05/24] target/arm: Implement store_cpu_field_low32() macro
[PULL 56/72] target/xtensa: Set default NaN pattern explicitly
1
We already have a load_cpu_field_low32() to load the low half of a
1
Set the default NaN pattern explicitly for xtensa.
2
64-bit CPU struct field to a TCGv_i32; however we haven't yet needed
3
the store equivalent. We'll want that in the next patch, so
4
implement it.
5
2
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20240628142347.1283015-6-peter.maydell@linaro.org
5
Message-id: 20241202131347.498124-51-peter.maydell@linaro.org
9
---
6
---
10
target/arm/tcg/translate-a32.h | 7 +++++++
7
target/xtensa/cpu.c | 2 ++
11
1 file changed, 7 insertions(+)
8
1 file changed, 2 insertions(+)
12
9
13
diff --git a/target/arm/tcg/translate-a32.h b/target/arm/tcg/translate-a32.h
10
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
14
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/tcg/translate-a32.h
12
--- a/target/xtensa/cpu.c
16
+++ b/target/arm/tcg/translate-a32.h
13
+++ b/target/xtensa/cpu.c
17
@@ -XXX,XX +XXX,XX @@ void store_cpu_offset(TCGv_i32 var, int offset, int size);
14
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
18
sizeof_field(CPUARMState, name)); \
15
/* For inf * 0 + NaN, return the input NaN */
19
})
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
17
set_no_signaling_nans(!dfpu, &env->fp_status);
21
+/* Store to the low half of a 64-bit field from a TCGv_i32 */
18
+ /* Default NaN value: sign bit clear, set frac msb */
22
+#define store_cpu_field_low32(val, name) \
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
23
+ ({ \
20
xtensa_use_first_nan(env, !dfpu);
24
+ QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, name) != 8); \
21
}
25
+ store_cpu_offset(val, offsetoflow32(CPUARMState, name), 4); \
26
+ })
27
+
28
#define store_cpu_field_constant(val, name) \
29
store_cpu_field(tcg_constant_i32(val), name)
30
22
31
--
23
--
32
2.34.1
24
2.34.1
diff view generated by jsdifflib
[PULL 02/24] target/arm: Make vfp_get_fpscr() call vfp_get_{fpcr, fpsr}
[PULL 57/72] target/hexagon: Set default NaN pattern explicitly
1
In AArch32, the floating point control and status bits are all in a
1
Set the default NaN pattern explicitly for hexagon.
2
single register, FPSCR. In AArch64, these were split into separate
2
Remove the ifdef from parts64_default_nan(); the only
3
FPCR and FPSR registers, but the bit layouts remained the same, with
3
remaining unconverted targets all use the default case.
4
no overlaps, so that you could construct an FPSCR value by ORing FPCR
5
and FPSR, or equivalently could produce FPSR and FPCR by masking an
6
FPSCR value. For QEMU's implementation, we opted to use masking to
7
produce FPSR and FPCR, because we started with an AArch32
8
implementation of FPSCR.
9
10
The addition of the (AArch64-only) FEAT_AFP adds new bits to the FPCR
11
which overlap with some bits in the FPSR. This means we'll no longer
12
be able to consider the FPSCR-encoded value as the primary one, but
13
instead need to treat FPSR/FPCR as the primary encoding and construct
14
the FPSCR from those. (This remains possible because the FEAT_AFP
15
bits in FPCR don't appear in the FPSCR.)
16
17
As the first step in this refactoring, make vfp_get_fpscr() call
18
vfp_get_fpcr() and vfp_get_fpsr(), instead of the other way around.
19
20
Note that vfp_get_fpcsr_from_host() returns only bits in the FPSR
21
(for the cumulative fp exception bits), so we can simply rename
22
it without needing to add a new function for getting FPCR bits.
23
4
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-id: 20240628142347.1283015-3-peter.maydell@linaro.org
7
Message-id: 20241202131347.498124-52-peter.maydell@linaro.org
27
---
8
---
28
target/arm/cpu.h | 24 +++++++++++++++---------
9
target/hexagon/cpu.c | 2 ++
29
target/arm/vfp_helper.c | 34 ++++++++++++++++++++++------------
10
fpu/softfloat-specialize.c.inc | 5 -----
30
2 files changed, 37 insertions(+), 21 deletions(-)
11
2 files changed, 2 insertions(+), 5 deletions(-)
31
12
32
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
13
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
33
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/cpu.h
15
--- a/target/hexagon/cpu.c
35
+++ b/target/arm/cpu.h
16
+++ b/target/hexagon/cpu.c
36
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
17
@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
37
#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
18
38
#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
19
set_default_nan_mode(1, &env->fp_status);
39
20
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
40
-static inline uint32_t vfp_get_fpsr(CPUARMState *env)
21
+ /* Default NaN value: sign bit set, all frac bits set */
41
-{
22
+ set_float_default_nan_pattern(0b11111111, &env->fp_status);
42
- return vfp_get_fpscr(env) & FPSR_MASK;
43
-}
44
+/**
45
+ * vfp_get_fpsr: read the AArch64 FPSR
46
+ * @env: CPU context
47
+ *
48
+ * Return the current AArch64 FPSR value
49
+ */
50
+uint32_t vfp_get_fpsr(CPUARMState *env);
51
+
52
+/**
53
+ * vfp_get_fpcr: read the AArch64 FPCR
54
+ * @env: CPU context
55
+ *
56
+ * Return the current AArch64 FPCR value
57
+ */
58
+uint32_t vfp_get_fpcr(CPUARMState *env);
59
60
static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
61
{
62
@@ -XXX,XX +XXX,XX @@ static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
63
vfp_set_fpscr(env, new_fpscr);
64
}
23
}
65
24
66
-static inline uint32_t vfp_get_fpcr(CPUARMState *env)
25
static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
67
-{
26
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
68
- return vfp_get_fpscr(env) & FPCR_MASK;
69
-}
70
-
71
static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
72
{
73
uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
74
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
75
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
76
--- a/target/arm/vfp_helper.c
28
--- a/fpu/softfloat-specialize.c.inc
77
+++ b/target/arm/vfp_helper.c
29
+++ b/fpu/softfloat-specialize.c.inc
78
@@ -XXX,XX +XXX,XX @@ static inline int vfp_exceptbits_to_host(int target_bits)
30
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
79
return host_bits;
31
uint8_t dnan_pattern = status->default_nan_pattern;
80
}
32
81
33
if (dnan_pattern == 0) {
82
-static uint32_t vfp_get_fpscr_from_host(CPUARMState *env)
34
-#if defined(TARGET_HEXAGON)
83
+static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
35
- /* Sign bit set, all frac bits set. */
84
{
36
- dnan_pattern = 0b11111111;
85
uint32_t i;
37
-#else
86
38
/*
87
@@ -XXX,XX +XXX,XX @@ static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
39
* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
88
40
* S390, SH4, TriCore, and Xtensa. Our other supported targets
89
#else
41
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
90
42
/* sign bit clear, set frac msb */
91
-static uint32_t vfp_get_fpscr_from_host(CPUARMState *env)
43
dnan_pattern = 0b01000000;
92
+static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
44
}
93
{
45
-#endif
94
return 0;
46
}
95
}
47
assert(dnan_pattern != 0);
96
@@ -XXX,XX +XXX,XX @@ static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
48
97
98
#endif
99
100
-uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
101
+uint32_t vfp_get_fpcr(CPUARMState *env)
102
{
103
- uint32_t i, fpscr;
104
-
105
- fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
106
- | (env->vfp.vec_len << 16)
107
- | (env->vfp.vec_stride << 20);
108
+ uint32_t fpcr = (env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_MASK)
109
+ | (env->vfp.vec_len << 16)
110
+ | (env->vfp.vec_stride << 20);
111
112
/*
113
* M-profile LTPSIZE is the same bits [18:16] as A-profile Len; whichever
114
* of the two is not applicable to this CPU will always be zero.
115
*/
116
- fpscr |= env->v7m.ltpsize << 16;
117
+ fpcr |= env->v7m.ltpsize << 16;
118
119
- fpscr |= vfp_get_fpscr_from_host(env);
120
+ return fpcr;
121
+}
122
+
123
+uint32_t vfp_get_fpsr(CPUARMState *env)
124
+{
125
+ uint32_t fpsr = env->vfp.xregs[ARM_VFP_FPSCR] & FPSR_MASK;
126
+ uint32_t i;
127
+
128
+ fpsr |= vfp_get_fpsr_from_host(env);
129
130
i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
131
- fpscr |= i ? FPCR_QC : 0;
132
+ fpsr |= i ? FPCR_QC : 0;
133
+ return fpsr;
134
+}
135
136
- return fpscr;
137
+uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
138
+{
139
+ return (vfp_get_fpcr(env) & FPCR_MASK) | (vfp_get_fpsr(env) & FPSR_MASK);
140
}
141
142
uint32_t vfp_get_fpscr(CPUARMState *env)
143
--
49
--
144
2.34.1
50
2.34.1
diff view generated by jsdifflib
[PULL 14/24] target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation
[PULL 58/72] target/riscv: Set default NaN pattern explicitly
1
Currently the TCGCPUOps::cpu_exec_halt method is optional, and if it
1
Set the default NaN pattern explicitly for riscv.
2
is not set then the default is to call the CPUClass::has_work
3
method (which has an identical function signature).
4
5
We would like to make the cpu_exec_halt method mandatory so we can
6
remove the runtime check and fallback handling. In preparation for
7
that, make all the targets which don't need special handling in their
8
cpu_exec_halt set it to their cpu_has_work implementation instead of
9
leaving it unset. (This is every target except for arm and i386.)
10
11
In the riscv case this requires us to make the function not
12
be local to the source file it's defined in.
13
2
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-53-peter.maydell@linaro.org
16
---
6
---
17
target/riscv/internals.h | 3 +++
7
target/riscv/cpu.c | 2 ++
18
target/alpha/cpu.c | 1 +
8
1 file changed, 2 insertions(+)
19
target/avr/cpu.c | 1 +
20
target/cris/cpu.c | 2 ++
21
target/hppa/cpu.c | 1 +
22
target/loongarch/cpu.c | 1 +
23
target/m68k/cpu.c | 1 +
24
target/microblaze/cpu.c | 1 +
25
target/mips/cpu.c | 1 +
26
target/openrisc/cpu.c | 1 +
27
target/ppc/cpu_init.c | 2 ++
28
target/riscv/cpu.c | 2 +-
29
target/riscv/tcg/tcg-cpu.c | 2 ++
30
target/rx/cpu.c | 1 +
31
target/s390x/cpu.c | 1 +
32
target/sh4/cpu.c | 1 +
33
target/sparc/cpu.c | 1 +
34
target/tricore/cpu.c | 1 +
35
target/xtensa/cpu.c | 1 +
36
19 files changed, 24 insertions(+), 1 deletion(-)
37
9
38
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/riscv/internals.h
41
+++ b/target/riscv/internals.h
42
@@ -XXX,XX +XXX,XX @@ static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f)
43
}
44
}
45
46
+/* Our implementation of CPUClass::has_work */
47
+bool riscv_cpu_has_work(CPUState *cs);
48
+
49
#endif
50
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/target/alpha/cpu.c
53
+++ b/target/alpha/cpu.c
54
@@ -XXX,XX +XXX,XX @@ static const TCGCPUOps alpha_tcg_ops = {
55
#else
56
.tlb_fill = alpha_cpu_tlb_fill,
57
.cpu_exec_interrupt = alpha_cpu_exec_interrupt,
58
+ .cpu_exec_halt = alpha_cpu_has_work,
59
.do_interrupt = alpha_cpu_do_interrupt,
60
.do_transaction_failed = alpha_cpu_do_transaction_failed,
61
.do_unaligned_access = alpha_cpu_do_unaligned_access,
62
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
63
index XXXXXXX..XXXXXXX 100644
64
--- a/target/avr/cpu.c
65
+++ b/target/avr/cpu.c
66
@@ -XXX,XX +XXX,XX @@ static const TCGCPUOps avr_tcg_ops = {
67
.synchronize_from_tb = avr_cpu_synchronize_from_tb,
68
.restore_state_to_opc = avr_restore_state_to_opc,
69
.cpu_exec_interrupt = avr_cpu_exec_interrupt,
70
+ .cpu_exec_halt = avr_cpu_has_work,
71
.tlb_fill = avr_cpu_tlb_fill,
72
.do_interrupt = avr_cpu_do_interrupt,
73
};
74
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/target/cris/cpu.c
77
+++ b/target/cris/cpu.c
78
@@ -XXX,XX +XXX,XX @@ static const TCGCPUOps crisv10_tcg_ops = {
79
#ifndef CONFIG_USER_ONLY
80
.tlb_fill = cris_cpu_tlb_fill,
81
.cpu_exec_interrupt = cris_cpu_exec_interrupt,
82
+ .cpu_exec_halt = cris_cpu_has_work,
83
.do_interrupt = crisv10_cpu_do_interrupt,
84
#endif /* !CONFIG_USER_ONLY */
85
};
86
@@ -XXX,XX +XXX,XX @@ static const TCGCPUOps crisv32_tcg_ops = {
87
#ifndef CONFIG_USER_ONLY
88
.tlb_fill = cris_cpu_tlb_fill,
89
.cpu_exec_interrupt = cris_cpu_exec_interrupt,
90
+ .cpu_exec_halt = cris_cpu_has_work,
91
.do_interrupt = cris_cpu_do_interrupt,
92
#endif /* !CONFIG_USER_ONLY */
93
};
94
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
95
index XXXXXXX..XXXXXXX 100644
96
--- a/target/hppa/cpu.c
97
+++ b/target/hppa/cpu.c
98
@@ -XXX,XX +XXX,XX @@ static const TCGCPUOps hppa_tcg_ops = {
99
#ifndef CONFIG_USER_ONLY
100
.tlb_fill = hppa_cpu_tlb_fill,
101
.cpu_exec_interrupt = hppa_cpu_exec_interrupt,
102
+ .cpu_exec_halt = hppa_cpu_has_work,
103
.do_interrupt = hppa_cpu_do_interrupt,
104
.do_unaligned_access = hppa_cpu_do_unaligned_access,
105
.do_transaction_failed = hppa_cpu_do_transaction_failed,
106
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/loongarch/cpu.c
109
+++ b/target/loongarch/cpu.c
110
@@ -XXX,XX +XXX,XX @@ static const TCGCPUOps loongarch_tcg_ops = {
111
#ifndef CONFIG_USER_ONLY
112
.tlb_fill = loongarch_cpu_tlb_fill,
113
.cpu_exec_interrupt = loongarch_cpu_exec_interrupt,
114
+ .cpu_exec_halt = loongarch_cpu_has_work,
115
.do_interrupt = loongarch_cpu_do_interrupt,
116
.do_transaction_failed = loongarch_cpu_do_transaction_failed,
117
#endif
118
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
119
index XXXXXXX..XXXXXXX 100644
120
--- a/target/m68k/cpu.c
121
+++ b/target/m68k/cpu.c
122
@@ -XXX,XX +XXX,XX @@ static const TCGCPUOps m68k_tcg_ops = {
123
#ifndef CONFIG_USER_ONLY
124
.tlb_fill = m68k_cpu_tlb_fill,
125
.cpu_exec_interrupt = m68k_cpu_exec_interrupt,
126
+ .cpu_exec_halt = m68k_cpu_has_work,
127
.do_interrupt = m68k_cpu_do_interrupt,
128
.do_transaction_failed = m68k_cpu_transaction_failed,
129
#endif /* !CONFIG_USER_ONLY */
130
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
131
index XXXXXXX..XXXXXXX 100644
132
--- a/target/microblaze/cpu.c
133
+++ b/target/microblaze/cpu.c
134
@@ -XXX,XX +XXX,XX @@ static const TCGCPUOps mb_tcg_ops = {
135
#ifndef CONFIG_USER_ONLY
136
.tlb_fill = mb_cpu_tlb_fill,
137
.cpu_exec_interrupt = mb_cpu_exec_interrupt,
138
+ .cpu_exec_halt = mb_cpu_has_work,
139
.do_interrupt = mb_cpu_do_interrupt,
140
.do_transaction_failed = mb_cpu_transaction_failed,
141
.do_unaligned_access = mb_cpu_do_unaligned_access,
142
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
143
index XXXXXXX..XXXXXXX 100644
144
--- a/target/mips/cpu.c
145
+++ b/target/mips/cpu.c
146
@@ -XXX,XX +XXX,XX @@ static const TCGCPUOps mips_tcg_ops = {
147
#if !defined(CONFIG_USER_ONLY)
148
.tlb_fill = mips_cpu_tlb_fill,
149
.cpu_exec_interrupt = mips_cpu_exec_interrupt,
150
+ .cpu_exec_halt = mips_cpu_has_work,
151
.do_interrupt = mips_cpu_do_interrupt,
152
.do_transaction_failed = mips_cpu_do_transaction_failed,
153
.do_unaligned_access = mips_cpu_do_unaligned_access,
154
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
155
index XXXXXXX..XXXXXXX 100644
156
--- a/target/openrisc/cpu.c
157
+++ b/target/openrisc/cpu.c
158
@@ -XXX,XX +XXX,XX @@ static const TCGCPUOps openrisc_tcg_ops = {
159
#ifndef CONFIG_USER_ONLY
160
.tlb_fill = openrisc_cpu_tlb_fill,
161
.cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
162
+ .cpu_exec_halt = openrisc_cpu_has_work,
163
.do_interrupt = openrisc_cpu_do_interrupt,
164
#endif /* !CONFIG_USER_ONLY */
165
};
166
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
167
index XXXXXXX..XXXXXXX 100644
168
--- a/target/ppc/cpu_init.c
169
+++ b/target/ppc/cpu_init.c
170
@@ -XXX,XX +XXX,XX @@
171
+
172
/*
173
* PowerPC CPU initialization for qemu.
174
*
175
@@ -XXX,XX +XXX,XX @@ static const TCGCPUOps ppc_tcg_ops = {
176
#else
177
.tlb_fill = ppc_cpu_tlb_fill,
178
.cpu_exec_interrupt = ppc_cpu_exec_interrupt,
179
+ .cpu_exec_halt = ppc_cpu_has_work,
180
.do_interrupt = ppc_cpu_do_interrupt,
181
.cpu_exec_enter = ppc_cpu_exec_enter,
182
.cpu_exec_exit = ppc_cpu_exec_exit,
183
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
10
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
184
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
185
--- a/target/riscv/cpu.c
12
--- a/target/riscv/cpu.c
186
+++ b/target/riscv/cpu.c
13
+++ b/target/riscv/cpu.c
187
@@ -XXX,XX +XXX,XX @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
14
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
188
return env->pc;
15
cs->exception_index = RISCV_EXCP_NONE;
189
}
16
env->load_res = -1;
190
17
set_default_nan_mode(1, &env->fp_status);
191
-static bool riscv_cpu_has_work(CPUState *cs)
18
+ /* Default NaN value: sign bit clear, frac msb set */
192
+bool riscv_cpu_has_work(CPUState *cs)
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
193
{
20
env->vill = true;
21
194
#ifndef CONFIG_USER_ONLY
22
#ifndef CONFIG_USER_ONLY
195
RISCVCPU *cpu = RISCV_CPU(cs);
196
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
197
index XXXXXXX..XXXXXXX 100644
198
--- a/target/riscv/tcg/tcg-cpu.c
199
+++ b/target/riscv/tcg/tcg-cpu.c
200
@@ -XXX,XX +XXX,XX @@
201
#include "exec/exec-all.h"
202
#include "tcg-cpu.h"
203
#include "cpu.h"
204
+#include "internals.h"
205
#include "pmu.h"
206
#include "time_helper.h"
207
#include "qapi/error.h"
208
@@ -XXX,XX +XXX,XX @@ static const TCGCPUOps riscv_tcg_ops = {
209
#ifndef CONFIG_USER_ONLY
210
.tlb_fill = riscv_cpu_tlb_fill,
211
.cpu_exec_interrupt = riscv_cpu_exec_interrupt,
212
+ .cpu_exec_halt = riscv_cpu_has_work,
213
.do_interrupt = riscv_cpu_do_interrupt,
214
.do_transaction_failed = riscv_cpu_do_transaction_failed,
215
.do_unaligned_access = riscv_cpu_do_unaligned_access,
216
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
217
index XXXXXXX..XXXXXXX 100644
218
--- a/target/rx/cpu.c
219
+++ b/target/rx/cpu.c
220
@@ -XXX,XX +XXX,XX @@ static const TCGCPUOps rx_tcg_ops = {
221
222
#ifndef CONFIG_USER_ONLY
223
.cpu_exec_interrupt = rx_cpu_exec_interrupt,
224
+ .cpu_exec_halt = rx_cpu_has_work,
225
.do_interrupt = rx_cpu_do_interrupt,
226
#endif /* !CONFIG_USER_ONLY */
227
};
228
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
229
index XXXXXXX..XXXXXXX 100644
230
--- a/target/s390x/cpu.c
231
+++ b/target/s390x/cpu.c
232
@@ -XXX,XX +XXX,XX @@ static const TCGCPUOps s390_tcg_ops = {
233
#else
234
.tlb_fill = s390_cpu_tlb_fill,
235
.cpu_exec_interrupt = s390_cpu_exec_interrupt,
236
+ .cpu_exec_halt = s390_cpu_has_work,
237
.do_interrupt = s390_cpu_do_interrupt,
238
.debug_excp_handler = s390x_cpu_debug_excp_handler,
239
.do_unaligned_access = s390x_cpu_do_unaligned_access,
240
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
241
index XXXXXXX..XXXXXXX 100644
242
--- a/target/sh4/cpu.c
243
+++ b/target/sh4/cpu.c
244
@@ -XXX,XX +XXX,XX @@ static const TCGCPUOps superh_tcg_ops = {
245
#ifndef CONFIG_USER_ONLY
246
.tlb_fill = superh_cpu_tlb_fill,
247
.cpu_exec_interrupt = superh_cpu_exec_interrupt,
248
+ .cpu_exec_halt = superh_cpu_has_work,
249
.do_interrupt = superh_cpu_do_interrupt,
250
.do_unaligned_access = superh_cpu_do_unaligned_access,
251
.io_recompile_replay_branch = superh_io_recompile_replay_branch,
252
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
253
index XXXXXXX..XXXXXXX 100644
254
--- a/target/sparc/cpu.c
255
+++ b/target/sparc/cpu.c
256
@@ -XXX,XX +XXX,XX @@ static const TCGCPUOps sparc_tcg_ops = {
257
#ifndef CONFIG_USER_ONLY
258
.tlb_fill = sparc_cpu_tlb_fill,
259
.cpu_exec_interrupt = sparc_cpu_exec_interrupt,
260
+ .cpu_exec_halt = sparc_cpu_has_work,
261
.do_interrupt = sparc_cpu_do_interrupt,
262
.do_transaction_failed = sparc_cpu_do_transaction_failed,
263
.do_unaligned_access = sparc_cpu_do_unaligned_access,
264
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
265
index XXXXXXX..XXXXXXX 100644
266
--- a/target/tricore/cpu.c
267
+++ b/target/tricore/cpu.c
268
@@ -XXX,XX +XXX,XX @@ static const TCGCPUOps tricore_tcg_ops = {
269
.synchronize_from_tb = tricore_cpu_synchronize_from_tb,
270
.restore_state_to_opc = tricore_restore_state_to_opc,
271
.tlb_fill = tricore_cpu_tlb_fill,
272
+ .cpu_exec_halt = tricore_cpu_has_work,
273
};
274
275
static void tricore_cpu_class_init(ObjectClass *c, void *data)
276
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
277
index XXXXXXX..XXXXXXX 100644
278
--- a/target/xtensa/cpu.c
279
+++ b/target/xtensa/cpu.c
280
@@ -XXX,XX +XXX,XX @@ static const TCGCPUOps xtensa_tcg_ops = {
281
#ifndef CONFIG_USER_ONLY
282
.tlb_fill = xtensa_cpu_tlb_fill,
283
.cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
284
+ .cpu_exec_halt = xtensa_cpu_has_work,
285
.do_interrupt = xtensa_cpu_do_interrupt,
286
.do_transaction_failed = xtensa_cpu_do_transaction_failed,
287
.do_unaligned_access = xtensa_cpu_do_unaligned_access,
288
--
23
--
289
2.34.1
24
2.34.1
290
291
diff view generated by jsdifflib
[PULL 06/24] target/arm: Store FPSR and FPCR in separate CPU state fields
[PULL 59/72] target/tricore: Set default NaN pattern explicitly
1
Now that we have refactored the set/get functions so that the FPSCR
1
Set the default NaN pattern explicitly for tricore.
2
format is no longer the authoritative one, we can keep FPSR and FPCR
3
in separate CPU state fields.
4
5
As well as the get and set functions, we also have a scattering of
6
places in the code which directly access vfp.xregs[ARM_VFP_FPSCR] to
7
extract single fields which are stored there. These all change to
8
directly access either vfp.fpsr or vfp.fpcr, depending on the
9
location of the field. (Most commonly, this is the NZCV flags.)
10
11
We make the field in the CPU state struct 64 bits, because
12
architecturally FPSR and FPCR are 64 bits. However we leave the
13
types of the arguments and return values of the get/set functions as
14
32 bits, since we don't need to make that change with the current
15
architecture and various callsites would be unable to handle
16
set bits in the high half (for instance the gdbstub protocol
17
assumes they're only 32 bit registers).
18
2
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Message-id: 20240628142347.1283015-7-peter.maydell@linaro.org
5
Message-id: 20241202131347.498124-54-peter.maydell@linaro.org
22
---
6
---
23
target/arm/cpu.h | 7 +++++++
7
target/tricore/helper.c | 2 ++
24
target/arm/tcg/translate.h | 3 +--
8
1 file changed, 2 insertions(+)
25
target/arm/tcg/mve_helper.c | 12 ++++++------
26
target/arm/tcg/translate-m-nocp.c | 6 +++---
27
target/arm/tcg/translate-vfp.c | 2 +-
28
target/arm/vfp_helper.c | 25 ++++++++++---------------
29
6 files changed, 28 insertions(+), 27 deletions(-)
30
9
31
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
10
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
32
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/cpu.h
12
--- a/target/tricore/helper.c
34
+++ b/target/arm/cpu.h
13
+++ b/target/tricore/helper.c
35
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
14
@@ -XXX,XX +XXX,XX @@ void fpu_set_state(CPUTriCoreState *env)
36
int vec_len;
15
set_flush_to_zero(1, &env->fp_status);
37
int vec_stride;
16
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
38
17
set_default_nan_mode(1, &env->fp_status);
39
+ /*
18
+ /* Default NaN pattern: sign bit clear, frac msb set */
40
+ * Floating point status and control registers. Some bits are
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
41
+ * stored separately in other fields or in the float_status below.
42
+ */
43
+ uint64_t fpsr;
44
+ uint64_t fpcr;
45
+
46
uint32_t xregs[16];
47
48
/* Scratch space for aa32 neon expansion. */
49
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
50
index XXXXXXX..XXXXXXX 100644
51
--- a/target/arm/tcg/translate.h
52
+++ b/target/arm/tcg/translate.h
53
@@ -XXX,XX +XXX,XX @@ static inline TCGv_i32 get_ahp_flag(void)
54
{
55
TCGv_i32 ret = tcg_temp_new_i32();
56
57
- tcg_gen_ld_i32(ret, tcg_env,
58
- offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
59
+ tcg_gen_ld_i32(ret, tcg_env, offsetoflow32(CPUARMState, vfp.fpcr));
60
tcg_gen_extract_i32(ret, ret, 26, 1);
61
62
return ret;
63
diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/arm/tcg/mve_helper.c
66
+++ b/target/arm/tcg/mve_helper.c
67
@@ -XXX,XX +XXX,XX @@ static void do_vadc(CPUARMState *env, uint32_t *d, uint32_t *n, uint32_t *m,
68
69
if (update_flags) {
70
/* Store C, clear NZV. */
71
- env->vfp.xregs[ARM_VFP_FPSCR] &= ~FPCR_NZCV_MASK;
72
- env->vfp.xregs[ARM_VFP_FPSCR] |= carry_in * FPCR_C;
73
+ env->vfp.fpsr &= ~FPCR_NZCV_MASK;
74
+ env->vfp.fpsr |= carry_in * FPCR_C;
75
}
76
mve_advance_vpt(env);
77
}
20
}
78
21
79
void HELPER(mve_vadc)(CPUARMState *env, void *vd, void *vn, void *vm)
22
uint32_t psw_read(CPUTriCoreState *env)
80
{
81
- bool carry_in = env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_C;
82
+ bool carry_in = env->vfp.fpsr & FPCR_C;
83
do_vadc(env, vd, vn, vm, 0, carry_in, false);
84
}
85
86
void HELPER(mve_vsbc)(CPUARMState *env, void *vd, void *vn, void *vm)
87
{
88
- bool carry_in = env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_C;
89
+ bool carry_in = env->vfp.fpsr & FPCR_C;
90
do_vadc(env, vd, vn, vm, -1, carry_in, false);
91
}
92
93
@@ -XXX,XX +XXX,XX @@ static void do_vcvt_sh(CPUARMState *env, void *vd, void *vm, int top)
94
uint32_t *m = vm;
95
uint16_t r;
96
uint16_t mask = mve_element_mask(env);
97
- bool ieee = !(env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_AHP);
98
+ bool ieee = !(env->vfp.fpcr & FPCR_AHP);
99
unsigned e;
100
float_status *fpst;
101
float_status scratch_fpst;
102
@@ -XXX,XX +XXX,XX @@ static void do_vcvt_hs(CPUARMState *env, void *vd, void *vm, int top)
103
uint16_t *m = vm;
104
uint32_t r;
105
uint16_t mask = mve_element_mask(env);
106
- bool ieee = !(env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_AHP);
107
+ bool ieee = !(env->vfp.fpcr & FPCR_AHP);
108
unsigned e;
109
float_status *fpst;
110
float_status scratch_fpst;
111
diff --git a/target/arm/tcg/translate-m-nocp.c b/target/arm/tcg/translate-m-nocp.c
112
index XXXXXXX..XXXXXXX 100644
113
--- a/target/arm/tcg/translate-m-nocp.c
114
+++ b/target/arm/tcg/translate-m-nocp.c
115
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
116
16, 16, qc);
117
}
118
tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
119
- fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
120
+ fpscr = load_cpu_field_low32(vfp.fpsr);
121
tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK);
122
tcg_gen_or_i32(fpscr, fpscr, tmp);
123
- store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]);
124
+ store_cpu_field_low32(fpscr, vfp.fpsr);
125
break;
126
}
127
case ARM_VFP_FPCXT_NS:
128
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
129
* Read just NZCV; this is a special case to avoid the
130
* helper call for the "VMRS to CPSR.NZCV" insn.
131
*/
132
- tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
133
+ tmp = load_cpu_field_low32(vfp.fpsr);
134
tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
135
storefn(s, opaque, tmp, true);
136
break;
137
diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c
138
index XXXXXXX..XXXXXXX 100644
139
--- a/target/arm/tcg/translate-vfp.c
140
+++ b/target/arm/tcg/translate-vfp.c
141
@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
142
break;
143
case ARM_VFP_FPSCR:
144
if (a->rt == 15) {
145
- tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
146
+ tmp = load_cpu_field_low32(vfp.fpsr);
147
tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
148
} else {
149
tmp = tcg_temp_new_i32();
150
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
151
index XXXXXXX..XXXXXXX 100644
152
--- a/target/arm/vfp_helper.c
153
+++ b/target/arm/vfp_helper.c
154
@@ -XXX,XX +XXX,XX @@ static void vfp_set_fpsr_to_host(CPUARMState *env, uint32_t val)
155
156
static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val)
157
{
158
- uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR];
159
+ uint64_t changed = env->vfp.fpcr;
160
161
changed ^= val;
162
if (changed & (3 << 22)) {
163
@@ -XXX,XX +XXX,XX @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val)
164
165
uint32_t vfp_get_fpcr(CPUARMState *env)
166
{
167
- uint32_t fpcr = (env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_MASK)
168
+ uint32_t fpcr = env->vfp.fpcr
169
| (env->vfp.vec_len << 16)
170
| (env->vfp.vec_stride << 20);
171
172
@@ -XXX,XX +XXX,XX @@ uint32_t vfp_get_fpcr(CPUARMState *env)
173
174
uint32_t vfp_get_fpsr(CPUARMState *env)
175
{
176
- uint32_t fpsr = env->vfp.xregs[ARM_VFP_FPSCR] & FPSR_MASK;
177
+ uint32_t fpsr = env->vfp.fpsr;
178
uint32_t i;
179
180
fpsr |= vfp_get_fpsr_from_host(env);
181
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpsr(CPUARMState *env, uint32_t val)
182
}
183
184
/*
185
- * The only FPSR bits we keep in vfp.xregs[FPSCR] are NZCV:
186
+ * The only FPSR bits we keep in vfp.fpsr are NZCV:
187
* the exception flags IOC|DZC|OFC|UFC|IXC|IDC are stored in
188
* fp_status, and QC is in vfp.qc[]. Store the NZCV bits there,
189
- * and zero any of the other FPSR bits (but preserve the FPCR
190
- * bits).
191
+ * and zero any of the other FPSR bits.
192
*/
193
val &= FPCR_NZCV_MASK;
194
- env->vfp.xregs[ARM_VFP_FPSCR] &= ~FPSR_MASK;
195
- env->vfp.xregs[ARM_VFP_FPSCR] |= val;
196
+ env->vfp.fpsr = val;
197
}
198
199
void vfp_set_fpcr(CPUARMState *env, uint32_t val)
200
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpcr(CPUARMState *env, uint32_t val)
201
* We don't implement trapped exception handling, so the
202
* trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
203
*
204
- * The FPCR bits we keep in vfp.xregs[FPSCR] are AHP, DN, FZ, RMode
205
+ * The FPCR bits we keep in vfp.fpcr are AHP, DN, FZ, RMode
206
* and FZ16. Len, Stride and LTPSIZE we just handled. Store those bits
207
* there, and zero any of the other FPCR bits and the RES0 and RAZ/WI
208
* bits.
209
*/
210
val &= FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK | FPCR_FZ16;
211
- env->vfp.xregs[ARM_VFP_FPSCR] &= ~FPCR_MASK;
212
- env->vfp.xregs[ARM_VFP_FPSCR] |= val;
213
+ env->vfp.fpcr = val;
214
}
215
216
void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
217
@@ -XXX,XX +XXX,XX @@ static void softfloat_to_vfp_compare(CPUARMState *env, FloatRelation cmp)
218
default:
219
g_assert_not_reached();
220
}
221
- env->vfp.xregs[ARM_VFP_FPSCR] =
222
- deposit32(env->vfp.xregs[ARM_VFP_FPSCR], 28, 4, flags);
223
+ env->vfp.fpsr = deposit64(env->vfp.fpsr, 28, 4, flags); /* NZCV */
224
}
225
226
/* XXX: check quiet/signaling case */
227
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env)
228
uint32_t z = (pair >> 32) == 0;
229
230
/* Store Z, clear NCV, in FPSCR.NZCV. */
231
- env->vfp.xregs[ARM_VFP_FPSCR]
232
- = (env->vfp.xregs[ARM_VFP_FPSCR] & ~CPSR_NZCV) | (z * CPSR_Z);
233
+ env->vfp.fpsr = (env->vfp.fpsr & ~FPCR_NZCV_MASK) | (z * FPCR_Z);
234
235
return result;
236
}
237
--
23
--
238
2.34.1
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 60/72] fpu: Remove default handling for dnan_pattern
1
Now that all our targets have bene converted to explicitly specify
2
their pattern for the default NaN value we can remove the remaining
3
fallback code in parts64_default_nan().
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-55-peter.maydell@linaro.org
8
---
9
fpu/softfloat-specialize.c.inc | 14 --------------
10
1 file changed, 14 deletions(-)
11
12
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
13
index XXXXXXX..XXXXXXX 100644
14
--- a/fpu/softfloat-specialize.c.inc
15
+++ b/fpu/softfloat-specialize.c.inc
16
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
17
uint64_t frac;
18
uint8_t dnan_pattern = status->default_nan_pattern;
19
20
- if (dnan_pattern == 0) {
21
- /*
22
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
23
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
24
- * do not have floating-point.
25
- */
26
- if (snan_bit_is_one(status)) {
27
- /* sign bit clear, set all frac bits other than msb */
28
- dnan_pattern = 0b00111111;
29
- } else {
30
- /* sign bit clear, set frac msb */
31
- dnan_pattern = 0b01000000;
32
- }
33
- }
34
assert(dnan_pattern != 0);
35
36
sign = dnan_pattern >> 7;
37
--
38
2.34.1
diff view generated by jsdifflib
[PULL 21/24] target/arm: Convert SQDMULL, SQDMLAL, SQDMLSL to decodetree
[PULL 61/72] softfloat: Inline pickNaNMulAdd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Inline pickNaNMulAdd into its only caller. This makes
4
one assert redundant with the immediately preceding IF.
5
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Message-id: 20240709000610.382391-4-richard.henderson@linaro.org
8
Message-id: 20241203203949.483774-3-richard.henderson@linaro.org
9
[PMM: keep comment from old code in new location]
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
11
---
8
target/arm/tcg/a64.decode | 33 ++
12
fpu/softfloat-parts.c.inc | 41 +++++++++++++++++++++++++-
9
target/arm/tcg/translate-a64.c | 604 ++++++---------------------------
13
fpu/softfloat-specialize.c.inc | 54 ----------------------------------
10
2 files changed, 138 insertions(+), 499 deletions(-)
14
2 files changed, 40 insertions(+), 55 deletions(-)
11
15
12
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
13
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/tcg/a64.decode
18
--- a/fpu/softfloat-parts.c.inc
15
+++ b/target/arm/tcg/a64.decode
19
+++ b/fpu/softfloat-parts.c.inc
16
@@ -XXX,XX +XXX,XX @@ SQRDMULH_s 0111 1110 ..1 ..... 10110 1 ..... ..... @rrr_e
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
17
SQRDMLAH_s 0111 1110 ..0 ..... 10000 1 ..... ..... @rrr_e
21
}
18
SQRDMLSH_s 0111 1110 ..0 ..... 10001 1 ..... ..... @rrr_e
22
19
23
if (s->default_nan_mode) {
20
+# Decode scalar x scalar as scalar x indexed, with index 0.
24
+ /*
21
+SQDMULL_si 0101 1110 011 rm:5 11010 0 rn:5 rd:5 &rrx_e idx=0 esz=1
25
+ * We guarantee not to require the target to tell us how to
22
+SQDMULL_si 0101 1110 101 rm:5 11010 0 rn:5 rd:5 &rrx_e idx=0 esz=2
26
+ * pick a NaN if we're always returning the default NaN.
23
+SQDMLAL_si 0101 1110 011 rm:5 10010 0 rn:5 rd:5 &rrx_e idx=0 esz=1
27
+ * But if we're not in default-NaN mode then the target must
24
+SQDMLAL_si 0101 1110 101 rm:5 10010 0 rn:5 rd:5 &rrx_e idx=0 esz=2
28
+ * specify.
25
+SQDMLSL_si 0101 1110 011 rm:5 10110 0 rn:5 rd:5 &rrx_e idx=0 esz=1
29
+ */
26
+SQDMLSL_si 0101 1110 101 rm:5 10110 0 rn:5 rd:5 &rrx_e idx=0 esz=2
30
which = 3;
31
+ } else if (infzero) {
32
+ /*
33
+ * Inf * 0 + NaN -- some implementations return the
34
+ * default NaN here, and some return the input NaN.
35
+ */
36
+ switch (s->float_infzeronan_rule) {
37
+ case float_infzeronan_dnan_never:
38
+ which = 2;
39
+ break;
40
+ case float_infzeronan_dnan_always:
41
+ which = 3;
42
+ break;
43
+ case float_infzeronan_dnan_if_qnan:
44
+ which = is_qnan(c->cls) ? 3 : 2;
45
+ break;
46
+ default:
47
+ g_assert_not_reached();
48
+ }
49
} else {
50
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
51
+ FloatClass cls[3] = { a->cls, b->cls, c->cls };
52
+ Float3NaNPropRule rule = s->float_3nan_prop_rule;
27
+
53
+
28
### Advanced SIMD scalar pairwise
54
+ assert(rule != float_3nan_prop_none);
29
55
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
30
FADDP_s 0101 1110 0011 0000 1101 10 ..... ..... @rr_h
56
+ /* We have at least one SNaN input and should prefer it */
31
@@ -XXX,XX +XXX,XX @@ UABAL_v 0.10 1110 ..1 ..... 01010 0 ..... ..... @qrrr_e
57
+ do {
32
SABDL_v 0.00 1110 ..1 ..... 01110 0 ..... ..... @qrrr_e
58
+ which = rule & R_3NAN_1ST_MASK;
33
UABDL_v 0.10 1110 ..1 ..... 01110 0 ..... ..... @qrrr_e
59
+ rule >>= R_3NAN_1ST_LENGTH;
34
60
+ } while (!is_snan(cls[which]));
35
+SQDMULL_v 0.00 1110 011 ..... 11010 0 ..... ..... @qrrr_h
61
+ } else {
36
+SQDMULL_v 0.00 1110 101 ..... 11010 0 ..... ..... @qrrr_s
62
+ do {
37
+SQDMLAL_v 0.00 1110 011 ..... 10010 0 ..... ..... @qrrr_h
63
+ which = rule & R_3NAN_1ST_MASK;
38
+SQDMLAL_v 0.00 1110 101 ..... 10010 0 ..... ..... @qrrr_s
64
+ rule >>= R_3NAN_1ST_LENGTH;
39
+SQDMLSL_v 0.00 1110 011 ..... 10110 0 ..... ..... @qrrr_h
65
+ } while (!is_nan(cls[which]));
40
+SQDMLSL_v 0.00 1110 101 ..... 10110 0 ..... ..... @qrrr_s
66
+ }
41
+
67
}
42
### Advanced SIMD scalar x indexed element
68
43
69
if (which == 3) {
44
FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h
70
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
45
@@ -XXX,XX +XXX,XX @@ SQRDMLAH_si 0111 1111 10 .. .... 1101 . 0 ..... ..... @rrx_s
46
SQRDMLSH_si 0111 1111 01 .. .... 1111 . 0 ..... ..... @rrx_h
47
SQRDMLSH_si 0111 1111 10 .. .... 1111 . 0 ..... ..... @rrx_s
48
49
+SQDMULL_si 0101 1111 01 .. .... 1011 . 0 ..... ..... @rrx_h
50
+SQDMULL_si 0101 1111 10 . ..... 1011 . 0 ..... ..... @rrx_s
51
+
52
+SQDMLAL_si 0101 1111 01 .. .... 0011 . 0 ..... ..... @rrx_h
53
+SQDMLAL_si 0101 1111 10 . ..... 0011 . 0 ..... ..... @rrx_s
54
+
55
+SQDMLSL_si 0101 1111 01 .. .... 0111 . 0 ..... ..... @rrx_h
56
+SQDMLSL_si 0101 1111 10 . ..... 0111 . 0 ..... ..... @rrx_s
57
+
58
### Advanced SIMD vector x indexed element
59
60
FMUL_vi 0.00 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h
61
@@ -XXX,XX +XXX,XX @@ SMLSL_vi 0.00 1111 10 . ..... 0110 . 0 ..... ..... @qrrx_s
62
UMLSL_vi 0.10 1111 01 .. .... 0110 . 0 ..... ..... @qrrx_h
63
UMLSL_vi 0.10 1111 10 . ..... 0110 . 0 ..... ..... @qrrx_s
64
65
+SQDMULL_vi 0.00 1111 01 .. .... 1011 . 0 ..... ..... @qrrx_h
66
+SQDMULL_vi 0.00 1111 10 . ..... 1011 . 0 ..... ..... @qrrx_s
67
+
68
+SQDMLAL_vi 0.00 1111 01 .. .... 0011 . 0 ..... ..... @qrrx_h
69
+SQDMLAL_vi 0.00 1111 10 . ..... 0011 . 0 ..... ..... @qrrx_s
70
+
71
+SQDMLSL_vi 0.00 1111 01 .. .... 0111 . 0 ..... ..... @qrrx_h
72
+SQDMLSL_vi 0.00 1111 10 . ..... 0111 . 0 ..... ..... @qrrx_s
73
+
74
# Floating-point conditional select
75
76
FCSEL 0001 1110 .. 1 rm:5 cond:4 11 rn:5 rd:5 esz=%esz_hsd
77
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
78
index XXXXXXX..XXXXXXX 100644
71
index XXXXXXX..XXXXXXX 100644
79
--- a/target/arm/tcg/translate-a64.c
72
--- a/fpu/softfloat-specialize.c.inc
80
+++ b/target/arm/tcg/translate-a64.c
73
+++ b/fpu/softfloat-specialize.c.inc
81
@@ -XXX,XX +XXX,XX @@ TRANS(UABAL_v, do_3op_widening,
74
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
82
a->esz, a->q, a->rd, a->rn, a->rm, -1,
83
gen_uaba_i64, true)
84
85
+static void gen_sqdmull_h(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m)
86
+{
87
+ tcg_gen_mul_i64(d, n, m);
88
+ gen_helper_neon_addl_saturate_s32(d, tcg_env, d, d);
89
+}
90
+
91
+static void gen_sqdmull_s(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m)
92
+{
93
+ tcg_gen_mul_i64(d, n, m);
94
+ gen_helper_neon_addl_saturate_s64(d, tcg_env, d, d);
95
+}
96
+
97
+static void gen_sqdmlal_h(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m)
98
+{
99
+ TCGv_i64 t = tcg_temp_new_i64();
100
+
101
+ tcg_gen_mul_i64(t, n, m);
102
+ gen_helper_neon_addl_saturate_s32(t, tcg_env, t, t);
103
+ gen_helper_neon_addl_saturate_s32(d, tcg_env, d, t);
104
+}
105
+
106
+static void gen_sqdmlal_s(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m)
107
+{
108
+ TCGv_i64 t = tcg_temp_new_i64();
109
+
110
+ tcg_gen_mul_i64(t, n, m);
111
+ gen_helper_neon_addl_saturate_s64(t, tcg_env, t, t);
112
+ gen_helper_neon_addl_saturate_s64(d, tcg_env, d, t);
113
+}
114
+
115
+static void gen_sqdmlsl_h(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m)
116
+{
117
+ TCGv_i64 t = tcg_temp_new_i64();
118
+
119
+ tcg_gen_mul_i64(t, n, m);
120
+ gen_helper_neon_addl_saturate_s32(t, tcg_env, t, t);
121
+ tcg_gen_neg_i64(t, t);
122
+ gen_helper_neon_addl_saturate_s32(d, tcg_env, d, t);
123
+}
124
+
125
+static void gen_sqdmlsl_s(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m)
126
+{
127
+ TCGv_i64 t = tcg_temp_new_i64();
128
+
129
+ tcg_gen_mul_i64(t, n, m);
130
+ gen_helper_neon_addl_saturate_s64(t, tcg_env, t, t);
131
+ tcg_gen_neg_i64(t, t);
132
+ gen_helper_neon_addl_saturate_s64(d, tcg_env, d, t);
133
+}
134
+
135
+TRANS(SQDMULL_v, do_3op_widening,
136
+ a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, -1,
137
+ a->esz == MO_16 ? gen_sqdmull_h : gen_sqdmull_s, false)
138
+TRANS(SQDMLAL_v, do_3op_widening,
139
+ a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, -1,
140
+ a->esz == MO_16 ? gen_sqdmlal_h : gen_sqdmlal_s, true)
141
+TRANS(SQDMLSL_v, do_3op_widening,
142
+ a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, -1,
143
+ a->esz == MO_16 ? gen_sqdmlsl_h : gen_sqdmlsl_s, true)
144
+
145
+TRANS(SQDMULL_vi, do_3op_widening,
146
+ a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, a->idx,
147
+ a->esz == MO_16 ? gen_sqdmull_h : gen_sqdmull_s, false)
148
+TRANS(SQDMLAL_vi, do_3op_widening,
149
+ a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, a->idx,
150
+ a->esz == MO_16 ? gen_sqdmlal_h : gen_sqdmlal_s, true)
151
+TRANS(SQDMLSL_vi, do_3op_widening,
152
+ a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, a->idx,
153
+ a->esz == MO_16 ? gen_sqdmlsl_h : gen_sqdmlsl_s, true)
154
+
155
/*
156
* Advanced SIMD scalar/vector x indexed element
157
*/
158
@@ -XXX,XX +XXX,XX @@ static bool do_env_scalar3_idx_hs(DisasContext *s, arg_rrx_e *a,
159
TRANS_FEAT(SQRDMLAH_si, aa64_rdm, do_env_scalar3_idx_hs, a, &f_scalar_sqrdmlah)
160
TRANS_FEAT(SQRDMLSH_si, aa64_rdm, do_env_scalar3_idx_hs, a, &f_scalar_sqrdmlsh)
161
162
+static bool do_scalar_muladd_widening_idx(DisasContext *s, arg_rrx_e *a,
163
+ NeonGenTwo64OpFn *fn, bool acc)
164
+{
165
+ if (fp_access_check(s)) {
166
+ TCGv_i64 t0 = tcg_temp_new_i64();
167
+ TCGv_i64 t1 = tcg_temp_new_i64();
168
+ TCGv_i64 t2 = tcg_temp_new_i64();
169
+ unsigned vsz, dofs;
170
+
171
+ if (acc) {
172
+ read_vec_element(s, t0, a->rd, 0, a->esz + 1);
173
+ }
174
+ read_vec_element(s, t1, a->rn, 0, a->esz | MO_SIGN);
175
+ read_vec_element(s, t2, a->rm, a->idx, a->esz | MO_SIGN);
176
+ fn(t0, t1, t2);
177
+
178
+ /* Clear the whole register first, then store scalar. */
179
+ vsz = vec_full_reg_size(s);
180
+ dofs = vec_full_reg_offset(s, a->rd);
181
+ tcg_gen_gvec_dup_imm(MO_64, dofs, vsz, vsz, 0);
182
+ write_vec_element(s, t0, a->rd, 0, a->esz + 1);
183
+ }
184
+ return true;
185
+}
186
+
187
+TRANS(SQDMULL_si, do_scalar_muladd_widening_idx, a,
188
+ a->esz == MO_16 ? gen_sqdmull_h : gen_sqdmull_s, false)
189
+TRANS(SQDMLAL_si, do_scalar_muladd_widening_idx, a,
190
+ a->esz == MO_16 ? gen_sqdmlal_h : gen_sqdmlal_s, true)
191
+TRANS(SQDMLSL_si, do_scalar_muladd_widening_idx, a,
192
+ a->esz == MO_16 ? gen_sqdmlsl_h : gen_sqdmlsl_s, true)
193
+
194
static bool do_fp3_vector_idx(DisasContext *s, arg_qrrx_e *a,
195
gen_helper_gvec_3_ptr * const fns[3])
196
{
197
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
198
}
75
}
199
}
76
}
200
77
201
-/* AdvSIMD scalar three different
78
-/*----------------------------------------------------------------------------
202
- * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
79
-| Select which NaN to propagate for a three-input operation.
203
- * +-----+---+-----------+------+---+------+--------+-----+------+------+
80
-| For the moment we assume that no CPU needs the 'larger significand'
204
- * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
81
-| information.
205
- * +-----+---+-----------+------+---+------+--------+-----+------+------+
82
-| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
206
- */
83
-*----------------------------------------------------------------------------*/
207
-static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
84
-static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
85
- bool infzero, bool have_snan, float_status *status)
208
-{
86
-{
209
- bool is_u = extract32(insn, 29, 1);
87
- FloatClass cls[3] = { a_cls, b_cls, c_cls };
210
- int size = extract32(insn, 22, 2);
88
- Float3NaNPropRule rule = status->float_3nan_prop_rule;
211
- int opcode = extract32(insn, 12, 4);
89
- int which;
212
- int rm = extract32(insn, 16, 5);
213
- int rn = extract32(insn, 5, 5);
214
- int rd = extract32(insn, 0, 5);
215
-
90
-
216
- if (is_u) {
91
- /*
217
- unallocated_encoding(s);
92
- * We guarantee not to require the target to tell us how to
218
- return;
93
- * pick a NaN if we're always returning the default NaN.
219
- }
94
- * But if we're not in default-NaN mode then the target must
95
- * specify.
96
- */
97
- assert(!status->default_nan_mode);
220
-
98
-
221
- switch (opcode) {
99
- if (infzero) {
222
- case 0x9: /* SQDMLAL, SQDMLAL2 */
100
- /*
223
- case 0xb: /* SQDMLSL, SQDMLSL2 */
101
- * Inf * 0 + NaN -- some implementations return the default NaN here,
224
- case 0xd: /* SQDMULL, SQDMULL2 */
102
- * and some return the input NaN.
225
- if (size == 0 || size == 3) {
103
- */
226
- unallocated_encoding(s);
104
- switch (status->float_infzeronan_rule) {
227
- return;
105
- case float_infzeronan_dnan_never:
228
- }
106
- return 2;
229
- break;
107
- case float_infzeronan_dnan_always:
230
- default:
108
- return 3;
231
- unallocated_encoding(s);
109
- case float_infzeronan_dnan_if_qnan:
232
- return;
110
- return is_qnan(c_cls) ? 3 : 2;
233
- }
234
-
235
- if (!fp_access_check(s)) {
236
- return;
237
- }
238
-
239
- if (size == 2) {
240
- TCGv_i64 tcg_op1 = tcg_temp_new_i64();
241
- TCGv_i64 tcg_op2 = tcg_temp_new_i64();
242
- TCGv_i64 tcg_res = tcg_temp_new_i64();
243
-
244
- read_vec_element(s, tcg_op1, rn, 0, MO_32 | MO_SIGN);
245
- read_vec_element(s, tcg_op2, rm, 0, MO_32 | MO_SIGN);
246
-
247
- tcg_gen_mul_i64(tcg_res, tcg_op1, tcg_op2);
248
- gen_helper_neon_addl_saturate_s64(tcg_res, tcg_env, tcg_res, tcg_res);
249
-
250
- switch (opcode) {
251
- case 0xd: /* SQDMULL, SQDMULL2 */
252
- break;
253
- case 0xb: /* SQDMLSL, SQDMLSL2 */
254
- tcg_gen_neg_i64(tcg_res, tcg_res);
255
- /* fall through */
256
- case 0x9: /* SQDMLAL, SQDMLAL2 */
257
- read_vec_element(s, tcg_op1, rd, 0, MO_64);
258
- gen_helper_neon_addl_saturate_s64(tcg_res, tcg_env,
259
- tcg_res, tcg_op1);
260
- break;
261
- default:
111
- default:
262
- g_assert_not_reached();
112
- g_assert_not_reached();
263
- }
113
- }
114
- }
264
-
115
-
265
- write_fp_dreg(s, rd, tcg_res);
116
- assert(rule != float_3nan_prop_none);
117
- if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
118
- /* We have at least one SNaN input and should prefer it */
119
- do {
120
- which = rule & R_3NAN_1ST_MASK;
121
- rule >>= R_3NAN_1ST_LENGTH;
122
- } while (!is_snan(cls[which]));
266
- } else {
123
- } else {
267
- TCGv_i32 tcg_op1 = read_fp_hreg(s, rn);
124
- do {
268
- TCGv_i32 tcg_op2 = read_fp_hreg(s, rm);
125
- which = rule & R_3NAN_1ST_MASK;
269
- TCGv_i64 tcg_res = tcg_temp_new_i64();
126
- rule >>= R_3NAN_1ST_LENGTH;
270
-
127
- } while (!is_nan(cls[which]));
271
- gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
272
- gen_helper_neon_addl_saturate_s32(tcg_res, tcg_env, tcg_res, tcg_res);
273
-
274
- switch (opcode) {
275
- case 0xd: /* SQDMULL, SQDMULL2 */
276
- break;
277
- case 0xb: /* SQDMLSL, SQDMLSL2 */
278
- gen_helper_neon_negl_u32(tcg_res, tcg_res);
279
- /* fall through */
280
- case 0x9: /* SQDMLAL, SQDMLAL2 */
281
- {
282
- TCGv_i64 tcg_op3 = tcg_temp_new_i64();
283
- read_vec_element(s, tcg_op3, rd, 0, MO_32);
284
- gen_helper_neon_addl_saturate_s32(tcg_res, tcg_env,
285
- tcg_res, tcg_op3);
286
- break;
287
- }
288
- default:
289
- g_assert_not_reached();
290
- }
291
-
292
- tcg_gen_ext32u_i64(tcg_res, tcg_res);
293
- write_fp_dreg(s, rd, tcg_res);
294
- }
128
- }
129
- return which;
295
-}
130
-}
296
-
131
-
297
static void handle_2misc_64(DisasContext *s, int opcode, bool u,
132
/*----------------------------------------------------------------------------
298
TCGv_i64 tcg_rd, TCGv_i64 tcg_rn,
133
| Returns 1 if the double-precision floating-point value `a' is a quiet
299
TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus)
134
| NaN; otherwise returns 0.
300
@@ -XXX,XX +XXX,XX @@ static void gen_neon_addl(int size, bool is_sub, TCGv_i64 tcg_res,
301
genfn(tcg_res, tcg_op1, tcg_op2);
302
}
303
304
-static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
305
- int opcode, int rd, int rn, int rm)
306
-{
307
- /* 3-reg-different widening insns: 64 x 64 -> 128 */
308
- TCGv_i64 tcg_res[2];
309
- int pass, accop;
310
-
311
- tcg_res[0] = tcg_temp_new_i64();
312
- tcg_res[1] = tcg_temp_new_i64();
313
-
314
- /* Does this op do an adding accumulate, a subtracting accumulate,
315
- * or no accumulate at all?
316
- */
317
- switch (opcode) {
318
- case 5:
319
- case 8:
320
- case 9:
321
- accop = 1;
322
- break;
323
- case 10:
324
- case 11:
325
- accop = -1;
326
- break;
327
- default:
328
- accop = 0;
329
- break;
330
- }
331
-
332
- if (accop != 0) {
333
- read_vec_element(s, tcg_res[0], rd, 0, MO_64);
334
- read_vec_element(s, tcg_res[1], rd, 1, MO_64);
335
- }
336
-
337
- /* size == 2 means two 32x32->64 operations; this is worth special
338
- * casing because we can generally handle it inline.
339
- */
340
- if (size == 2) {
341
- for (pass = 0; pass < 2; pass++) {
342
- TCGv_i64 tcg_op1 = tcg_temp_new_i64();
343
- TCGv_i64 tcg_op2 = tcg_temp_new_i64();
344
- TCGv_i64 tcg_passres;
345
- MemOp memop = MO_32 | (is_u ? 0 : MO_SIGN);
346
-
347
- int elt = pass + is_q * 2;
348
-
349
- read_vec_element(s, tcg_op1, rn, elt, memop);
350
- read_vec_element(s, tcg_op2, rm, elt, memop);
351
-
352
- if (accop == 0) {
353
- tcg_passres = tcg_res[pass];
354
- } else {
355
- tcg_passres = tcg_temp_new_i64();
356
- }
357
-
358
- switch (opcode) {
359
- case 9: /* SQDMLAL, SQDMLAL2 */
360
- case 11: /* SQDMLSL, SQDMLSL2 */
361
- case 13: /* SQDMULL, SQDMULL2 */
362
- tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2);
363
- gen_helper_neon_addl_saturate_s64(tcg_passres, tcg_env,
364
- tcg_passres, tcg_passres);
365
- break;
366
- default:
367
- case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
368
- case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
369
- case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
370
- case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
371
- case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
372
- case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
373
- case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
374
- g_assert_not_reached();
375
- }
376
-
377
- if (accop != 0) {
378
- /* saturating accumulate ops */
379
- if (accop < 0) {
380
- tcg_gen_neg_i64(tcg_passres, tcg_passres);
381
- }
382
- gen_helper_neon_addl_saturate_s64(tcg_res[pass], tcg_env,
383
- tcg_res[pass], tcg_passres);
384
- }
385
- }
386
- } else {
387
- /* size 0 or 1, generally helper functions */
388
- for (pass = 0; pass < 2; pass++) {
389
- TCGv_i32 tcg_op1 = tcg_temp_new_i32();
390
- TCGv_i32 tcg_op2 = tcg_temp_new_i32();
391
- TCGv_i64 tcg_passres;
392
- int elt = pass + is_q * 2;
393
-
394
- read_vec_element_i32(s, tcg_op1, rn, elt, MO_32);
395
- read_vec_element_i32(s, tcg_op2, rm, elt, MO_32);
396
-
397
- if (accop == 0) {
398
- tcg_passres = tcg_res[pass];
399
- } else {
400
- tcg_passres = tcg_temp_new_i64();
401
- }
402
-
403
- switch (opcode) {
404
- case 9: /* SQDMLAL, SQDMLAL2 */
405
- case 11: /* SQDMLSL, SQDMLSL2 */
406
- case 13: /* SQDMULL, SQDMULL2 */
407
- assert(size == 1);
408
- gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2);
409
- gen_helper_neon_addl_saturate_s32(tcg_passres, tcg_env,
410
- tcg_passres, tcg_passres);
411
- break;
412
- default:
413
- case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
414
- case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
415
- case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
416
- case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
417
- case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
418
- case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
419
- case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
420
- g_assert_not_reached();
421
- }
422
-
423
- if (accop != 0) {
424
- /* saturating accumulate ops */
425
- if (accop < 0) {
426
- gen_helper_neon_negl_u32(tcg_passres, tcg_passres);
427
- }
428
- gen_helper_neon_addl_saturate_s32(tcg_res[pass], tcg_env,
429
- tcg_res[pass],
430
- tcg_passres);
431
- }
432
- }
433
- }
434
-
435
- write_vec_element(s, tcg_res[0], rd, 0, MO_64);
436
- write_vec_element(s, tcg_res[1], rd, 1, MO_64);
437
-}
438
-
439
static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size,
440
int opcode, int rd, int rn, int rm)
441
{
442
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
443
break;
444
}
445
return;
446
- case 9: /* SQDMLAL, SQDMLAL2 */
447
- case 11: /* SQDMLSL, SQDMLSL2 */
448
- case 13: /* SQDMULL, SQDMULL2 */
449
- if (is_u || size == 0) {
450
- unallocated_encoding(s);
451
- return;
452
- }
453
- /* 64 x 64 -> 128 */
454
- if (size == 3) {
455
- unallocated_encoding(s);
456
- return;
457
- }
458
- if (!fp_access_check(s)) {
459
- return;
460
- }
461
-
462
- handle_3rd_widening(s, is_q, is_u, size, opcode, rd, rn, rm);
463
- break;
464
default:
465
case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
466
case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
467
case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
468
case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
469
case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
470
+ case 9: /* SQDMLAL, SQDMLAL2 */
471
case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
472
+ case 11: /* SQDMLSL, SQDMLSL2 */
473
case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
474
+ case 13: /* SQDMULL, SQDMULL2 */
475
/* opcode 15 not allocated */
476
unallocated_encoding(s);
477
break;
478
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
479
}
480
}
481
482
-/* AdvSIMD scalar x indexed element
483
- * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
484
- * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
485
- * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
486
- * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
487
- * AdvSIMD vector x indexed element
488
- * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
489
- * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
490
- * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
491
- * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
492
- */
493
-static void disas_simd_indexed(DisasContext *s, uint32_t insn)
494
-{
495
- /* This encoding has two kinds of instruction:
496
- * normal, where we perform elt x idxelt => elt for each
497
- * element in the vector
498
- * long, where we perform elt x idxelt and generate a result of
499
- * double the width of the input element
500
- * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
501
- */
502
- bool is_scalar = extract32(insn, 28, 1);
503
- bool is_q = extract32(insn, 30, 1);
504
- bool u = extract32(insn, 29, 1);
505
- int size = extract32(insn, 22, 2);
506
- int l = extract32(insn, 21, 1);
507
- int m = extract32(insn, 20, 1);
508
- /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
509
- int rm = extract32(insn, 16, 4);
510
- int opcode = extract32(insn, 12, 4);
511
- int h = extract32(insn, 11, 1);
512
- int rn = extract32(insn, 5, 5);
513
- int rd = extract32(insn, 0, 5);
514
- int index;
515
-
516
- switch (16 * u + opcode) {
517
- case 0x03: /* SQDMLAL, SQDMLAL2 */
518
- case 0x07: /* SQDMLSL, SQDMLSL2 */
519
- case 0x0b: /* SQDMULL, SQDMULL2 */
520
- break;
521
- default:
522
- case 0x00: /* FMLAL */
523
- case 0x01: /* FMLA */
524
- case 0x02: /* SMLAL, SMLAL2 */
525
- case 0x04: /* FMLSL */
526
- case 0x05: /* FMLS */
527
- case 0x06: /* SMLSL, SMLSL2 */
528
- case 0x08: /* MUL */
529
- case 0x09: /* FMUL */
530
- case 0x0a: /* SMULL, SMULL2 */
531
- case 0x0c: /* SQDMULH */
532
- case 0x0d: /* SQRDMULH */
533
- case 0x0e: /* SDOT */
534
- case 0x0f: /* SUDOT / BFDOT / USDOT / BFMLAL */
535
- case 0x10: /* MLA */
536
- case 0x11: /* FCMLA #0 */
537
- case 0x12: /* UMLAL, UMLAL2 */
538
- case 0x13: /* FCMLA #90 */
539
- case 0x14: /* MLS */
540
- case 0x15: /* FCMLA #180 */
541
- case 0x16: /* UMLSL, UMLSL2 */
542
- case 0x17: /* FCMLA #270 */
543
- case 0x18: /* FMLAL2 */
544
- case 0x19: /* FMULX */
545
- case 0x1a: /* UMULL, UMULL2 */
546
- case 0x1c: /* FMLSL2 */
547
- case 0x1d: /* SQRDMLAH */
548
- case 0x1e: /* UDOT */
549
- case 0x1f: /* SQRDMLSH */
550
- unallocated_encoding(s);
551
- return;
552
- }
553
-
554
- /* Given MemOp size, adjust register and indexing. */
555
- switch (size) {
556
- case MO_8:
557
- case MO_64:
558
- unallocated_encoding(s);
559
- return;
560
- case MO_16:
561
- index = h << 2 | l << 1 | m;
562
- break;
563
- case MO_32:
564
- index = h << 1 | l;
565
- rm |= m << 4;
566
- break;
567
- default:
568
- g_assert_not_reached();
569
- }
570
-
571
- if (!fp_access_check(s)) {
572
- return;
573
- }
574
-
575
- if (size == 3) {
576
- g_assert_not_reached();
577
- } else {
578
- /* long ops: 16x16->32 or 32x32->64 */
579
- TCGv_i64 tcg_res[2];
580
- int pass;
581
- bool satop = extract32(opcode, 0, 1);
582
- MemOp memop = MO_32;
583
-
584
- if (satop || !u) {
585
- memop |= MO_SIGN;
586
- }
587
-
588
- if (size == 2) {
589
- TCGv_i64 tcg_idx = tcg_temp_new_i64();
590
-
591
- read_vec_element(s, tcg_idx, rm, index, memop);
592
-
593
- for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
594
- TCGv_i64 tcg_op = tcg_temp_new_i64();
595
- TCGv_i64 tcg_passres;
596
- int passelt;
597
-
598
- if (is_scalar) {
599
- passelt = 0;
600
- } else {
601
- passelt = pass + (is_q * 2);
602
- }
603
-
604
- read_vec_element(s, tcg_op, rn, passelt, memop);
605
-
606
- tcg_res[pass] = tcg_temp_new_i64();
607
-
608
- if (opcode == 0xa || opcode == 0xb) {
609
- /* Non-accumulating ops */
610
- tcg_passres = tcg_res[pass];
611
- } else {
612
- tcg_passres = tcg_temp_new_i64();
613
- }
614
-
615
- tcg_gen_mul_i64(tcg_passres, tcg_op, tcg_idx);
616
-
617
- if (satop) {
618
- /* saturating, doubling */
619
- gen_helper_neon_addl_saturate_s64(tcg_passres, tcg_env,
620
- tcg_passres, tcg_passres);
621
- }
622
-
623
- if (opcode == 0xa || opcode == 0xb) {
624
- continue;
625
- }
626
-
627
- /* Accumulating op: handle accumulate step */
628
- read_vec_element(s, tcg_res[pass], rd, pass, MO_64);
629
-
630
- switch (opcode) {
631
- case 0x7: /* SQDMLSL, SQDMLSL2 */
632
- tcg_gen_neg_i64(tcg_passres, tcg_passres);
633
- /* fall through */
634
- case 0x3: /* SQDMLAL, SQDMLAL2 */
635
- gen_helper_neon_addl_saturate_s64(tcg_res[pass], tcg_env,
636
- tcg_res[pass],
637
- tcg_passres);
638
- break;
639
- default:
640
- case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
641
- case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
642
- g_assert_not_reached();
643
- }
644
- }
645
-
646
- clear_vec_high(s, !is_scalar, rd);
647
- } else {
648
- TCGv_i32 tcg_idx = tcg_temp_new_i32();
649
-
650
- assert(size == 1);
651
- read_vec_element_i32(s, tcg_idx, rm, index, size);
652
-
653
- if (!is_scalar) {
654
- /* The simplest way to handle the 16x16 indexed ops is to
655
- * duplicate the index into both halves of the 32 bit tcg_idx
656
- * and then use the usual Neon helpers.
657
- */
658
- tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16);
659
- }
660
-
661
- for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
662
- TCGv_i32 tcg_op = tcg_temp_new_i32();
663
- TCGv_i64 tcg_passres;
664
-
665
- if (is_scalar) {
666
- read_vec_element_i32(s, tcg_op, rn, pass, size);
667
- } else {
668
- read_vec_element_i32(s, tcg_op, rn,
669
- pass + (is_q * 2), MO_32);
670
- }
671
-
672
- tcg_res[pass] = tcg_temp_new_i64();
673
-
674
- if (opcode == 0xa || opcode == 0xb) {
675
- /* Non-accumulating ops */
676
- tcg_passres = tcg_res[pass];
677
- } else {
678
- tcg_passres = tcg_temp_new_i64();
679
- }
680
-
681
- if (memop & MO_SIGN) {
682
- gen_helper_neon_mull_s16(tcg_passres, tcg_op, tcg_idx);
683
- } else {
684
- gen_helper_neon_mull_u16(tcg_passres, tcg_op, tcg_idx);
685
- }
686
- if (satop) {
687
- gen_helper_neon_addl_saturate_s32(tcg_passres, tcg_env,
688
- tcg_passres, tcg_passres);
689
- }
690
-
691
- if (opcode == 0xa || opcode == 0xb) {
692
- continue;
693
- }
694
-
695
- /* Accumulating op: handle accumulate step */
696
- read_vec_element(s, tcg_res[pass], rd, pass, MO_64);
697
-
698
- switch (opcode) {
699
- case 0x7: /* SQDMLSL, SQDMLSL2 */
700
- gen_helper_neon_negl_u32(tcg_passres, tcg_passres);
701
- /* fall through */
702
- case 0x3: /* SQDMLAL, SQDMLAL2 */
703
- gen_helper_neon_addl_saturate_s32(tcg_res[pass], tcg_env,
704
- tcg_res[pass],
705
- tcg_passres);
706
- break;
707
- default:
708
- case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
709
- case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
710
- g_assert_not_reached();
711
- }
712
- }
713
-
714
- if (is_scalar) {
715
- tcg_gen_ext32u_i64(tcg_res[0], tcg_res[0]);
716
- }
717
- }
718
-
719
- if (is_scalar) {
720
- tcg_res[1] = tcg_constant_i64(0);
721
- }
722
-
723
- for (pass = 0; pass < 2; pass++) {
724
- write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
725
- }
726
- }
727
-}
728
-
729
/* C3.6 Data processing - SIMD, inc Crypto
730
*
731
* As the decode gets a little complex we are using a table based
732
@@ -XXX,XX +XXX,XX @@ static const AArch64DecodeTable data_proc_simd[] = {
733
{ 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff },
734
{ 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc },
735
{ 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes },
736
- { 0x0f000000, 0x9f000400, disas_simd_indexed }, /* vector indexed */
737
/* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
738
{ 0x0f000400, 0x9ff80400, disas_simd_mod_imm },
739
{ 0x0f000400, 0x9f800400, disas_simd_shift_imm },
740
{ 0x0e000000, 0xbf208c00, disas_simd_tb },
741
{ 0x0e000800, 0xbf208c00, disas_simd_zip_trn },
742
{ 0x2e000000, 0xbf208400, disas_simd_ext },
743
- { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff },
744
{ 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc },
745
- { 0x5f000000, 0xdf000400, disas_simd_indexed }, /* scalar indexed */
746
{ 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm },
747
{ 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 },
748
{ 0x00000000, 0x00000000, NULL }
749
--
135
--
750
2.34.1
136
2.34.1
137
138
diff view generated by jsdifflib
[PULL 16/24] hw/misc: In STM32L4x5 EXTI, consolidate 2 constants
[PULL 62/72] softfloat: Use goto for default nan case in pick_nan_muladd
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Up until now, the EXTI implementation had 16 inbound GPIOs connected to
3
Remove "3" as a special case for which and simply
4
the 16 outbound GPIOs of STM32L4x5 SYSCFG.
4
branch to return the desired value.
5
The EXTI actually handles 40 lines (namely 5 from STM32L4x5 USART
6
devices which are already implemented in QEMU).
7
In order to connect USART devices to EXTI, this commit consolidates
8
constants `EXTI_NUM_INTERRUPT_OUT_LINES` (40) and
9
`EXTI_NUM_GPIO_EVENT_IN_LINES` (16) into `EXTI_NUM_LINES` (40).
10
5
11
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
Message-id: 20240707085927.122867-2-ines.varhol@telecom-paris.fr
8
Message-id: 20241203203949.483774-4-richard.henderson@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
10
---
16
include/hw/misc/stm32l4x5_exti.h | 4 ++--
11
fpu/softfloat-parts.c.inc | 20 ++++++++++----------
17
hw/misc/stm32l4x5_exti.c | 6 ++----
12
1 file changed, 10 insertions(+), 10 deletions(-)
18
2 files changed, 4 insertions(+), 6 deletions(-)
19
13
20
diff --git a/include/hw/misc/stm32l4x5_exti.h b/include/hw/misc/stm32l4x5_exti.h
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
21
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/misc/stm32l4x5_exti.h
16
--- a/fpu/softfloat-parts.c.inc
23
+++ b/include/hw/misc/stm32l4x5_exti.h
17
+++ b/fpu/softfloat-parts.c.inc
24
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
25
#define TYPE_STM32L4X5_EXTI "stm32l4x5-exti"
19
* But if we're not in default-NaN mode then the target must
26
OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5ExtiState, STM32L4X5_EXTI)
20
* specify.
27
21
*/
28
-#define EXTI_NUM_INTERRUPT_OUT_LINES 40
22
- which = 3;
29
+#define EXTI_NUM_LINES 40
23
+ goto default_nan;
30
#define EXTI_NUM_REGISTER 2
24
} else if (infzero) {
31
25
/*
32
struct Stm32l4x5ExtiState {
26
* Inf * 0 + NaN -- some implementations return the
33
@@ -XXX,XX +XXX,XX @@ struct Stm32l4x5ExtiState {
27
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
34
28
*/
35
/* used for edge detection */
29
switch (s->float_infzeronan_rule) {
36
uint32_t irq_levels[EXTI_NUM_REGISTER];
30
case float_infzeronan_dnan_never:
37
- qemu_irq irq[EXTI_NUM_INTERRUPT_OUT_LINES];
31
- which = 2;
38
+ qemu_irq irq[EXTI_NUM_LINES];
32
break;
39
};
33
case float_infzeronan_dnan_always:
40
34
- which = 3;
41
#endif
35
- break;
42
diff --git a/hw/misc/stm32l4x5_exti.c b/hw/misc/stm32l4x5_exti.c
36
+ goto default_nan;
43
index XXXXXXX..XXXXXXX 100644
37
case float_infzeronan_dnan_if_qnan:
44
--- a/hw/misc/stm32l4x5_exti.c
38
- which = is_qnan(c->cls) ? 3 : 2;
45
+++ b/hw/misc/stm32l4x5_exti.c
39
+ if (is_qnan(c->cls)) {
46
@@ -XXX,XX +XXX,XX @@
40
+ goto default_nan;
47
#define EXTI_SWIER2 0x30
41
+ }
48
#define EXTI_PR2 0x34
42
break;
49
43
default:
50
-#define EXTI_NUM_GPIO_EVENT_IN_LINES 16
44
g_assert_not_reached();
51
#define EXTI_MAX_IRQ_PER_BANK 32
45
}
52
#define EXTI_IRQS_BANK0 32
46
+ which = 2;
53
#define EXTI_IRQS_BANK1 8
47
} else {
54
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_exti_init(Object *obj)
48
FloatClass cls[3] = { a->cls, b->cls, c->cls };
55
{
49
Float3NaNPropRule rule = s->float_3nan_prop_rule;
56
Stm32l4x5ExtiState *s = STM32L4X5_EXTI(obj);
50
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
57
51
}
58
- for (size_t i = 0; i < EXTI_NUM_INTERRUPT_OUT_LINES; i++) {
59
+ for (size_t i = 0; i < EXTI_NUM_LINES; i++) {
60
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);
61
}
52
}
62
53
63
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_exti_init(Object *obj)
54
- if (which == 3) {
64
TYPE_STM32L4X5_EXTI, 0x400);
55
- parts_default_nan(a, s);
65
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
56
- return a;
66
57
- }
67
- qdev_init_gpio_in(DEVICE(obj), stm32l4x5_exti_set_irq,
58
-
68
- EXTI_NUM_GPIO_EVENT_IN_LINES);
59
switch (which) {
69
+ qdev_init_gpio_in(DEVICE(obj), stm32l4x5_exti_set_irq, EXTI_NUM_LINES);
60
case 0:
61
break;
62
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
63
parts_silence_nan(a, s);
64
}
65
return a;
66
+
67
+ default_nan:
68
+ parts_default_nan(a, s);
69
+ return a;
70
}
70
}
71
71
72
static const VMStateDescription vmstate_stm32l4x5_exti = {
72
/*
73
--
73
--
74
2.34.1
74
2.34.1
75
75
76
76
diff view generated by jsdifflib
[PULL 18/24] hw/arm: In STM32L4x5 SOC, connect USART devices to EXTI
[PULL 63/72] softfloat: Remove which from parts_pick_nan_muladd
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The USART devices were previously connecting their outbound IRQs
3
Assign the pointer return value to 'a' directly,
4
directly to the CPU because the EXTI wasn't handling direct lines
4
rather than going through an intermediary index.
5
interrupts.
6
Now the USART connects to the EXTI inbound GPIOs, and the EXTI connects
7
its IRQs to the CPU.
8
The existing QTest for the USART (tests/qtest/stm32l4x5_usart-test.c)
9
checks that USART1_IRQ in the CPU is pending when expected so it
10
confirms that the connection through the EXTI still works.
11
5
12
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Message-id: 20240707085927.122867-4-ines.varhol@telecom-paris.fr
8
Message-id: 20241203203949.483774-5-richard.henderson@linaro.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
10
---
17
hw/arm/stm32l4x5_soc.c | 24 +++++++++++-------------
11
fpu/softfloat-parts.c.inc | 32 ++++++++++----------------------
18
1 file changed, 11 insertions(+), 13 deletions(-)
12
1 file changed, 10 insertions(+), 22 deletions(-)
19
13
20
diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
21
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/stm32l4x5_soc.c
16
--- a/fpu/softfloat-parts.c.inc
23
+++ b/hw/arm/stm32l4x5_soc.c
17
+++ b/fpu/softfloat-parts.c.inc
24
@@ -XXX,XX +XXX,XX @@ static const int exti_irq[NUM_EXTI_IRQ] = {
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
25
#define RCC_BASE_ADDRESS 0x40021000
19
FloatPartsN *c, float_status *s,
26
#define RCC_IRQ 5
20
int ab_mask, int abc_mask)
27
28
+#define EXTI_USART1_IRQ 26
29
+#define EXTI_UART4_IRQ 29
30
+#define EXTI_LPUART1_IRQ 31
31
+
32
static const int exti_or_gates_out[NUM_EXTI_OR_GATES] = {
33
23, 40, 63, 1,
34
};
35
@@ -XXX,XX +XXX,XX @@ static const hwaddr uart_addr[] = {
36
37
#define LPUART_BASE_ADDRESS 0x40008000
38
39
-static const int usart_irq[] = { 37, 38, 39 };
40
-static const int uart_irq[] = { 52, 53 };
41
-#define LPUART_IRQ 70
42
-
43
static void stm32l4x5_soc_initfn(Object *obj)
44
{
21
{
45
Stm32l4x5SocState *s = STM32L4X5_SOC(obj);
22
- int which;
46
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
23
bool infzero = (ab_mask == float_cmask_infzero);
24
bool have_snan = (abc_mask & float_cmask_snan);
25
+ FloatPartsN *ret;
26
27
if (unlikely(have_snan)) {
28
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
30
default:
31
g_assert_not_reached();
32
}
33
- which = 2;
34
+ ret = c;
35
} else {
36
- FloatClass cls[3] = { a->cls, b->cls, c->cls };
37
+ FloatPartsN *val[3] = { a, b, c };
38
Float3NaNPropRule rule = s->float_3nan_prop_rule;
39
40
assert(rule != float_3nan_prop_none);
41
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
42
/* We have at least one SNaN input and should prefer it */
43
do {
44
- which = rule & R_3NAN_1ST_MASK;
45
+ ret = val[rule & R_3NAN_1ST_MASK];
46
rule >>= R_3NAN_1ST_LENGTH;
47
- } while (!is_snan(cls[which]));
48
+ } while (!is_snan(ret->cls));
49
} else {
50
do {
51
- which = rule & R_3NAN_1ST_MASK;
52
+ ret = val[rule & R_3NAN_1ST_MASK];
53
rule >>= R_3NAN_1ST_LENGTH;
54
- } while (!is_nan(cls[which]));
55
+ } while (!is_nan(ret->cls));
47
}
56
}
48
}
57
}
49
58
50
+ /* Connect SYSCFG to EXTI */
59
- switch (which) {
51
for (unsigned i = 0; i < GPIO_NUM_PINS; i++) {
60
- case 0:
52
qdev_connect_gpio_out(DEVICE(&s->syscfg), i,
61
- break;
53
qdev_get_gpio_in(DEVICE(&s->exti), i));
62
- case 1:
54
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
63
- a = b;
55
return;
64
- break;
56
}
65
- case 2:
57
sysbus_mmio_map(busdev, 0, usart_addr[i]);
66
- a = c;
58
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
67
- break;
59
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->exti),
68
- default:
60
+ EXTI_USART1_IRQ + i));
69
- g_assert_not_reached();
70
+ if (is_snan(ret->cls)) {
71
+ parts_silence_nan(ret, s);
61
}
72
}
62
73
- if (is_snan(a->cls)) {
63
- /*
74
- parts_silence_nan(a, s);
64
- * TODO: Connect the USARTs, UARTs and LPUART to the EXTI once the EXTI
75
- }
65
- * can handle other gpio-in than the gpios. (e.g. Direct Lines for the
76
- return a;
66
- * usarts)
77
+ return ret;
67
- */
78
68
-
79
default_nan:
69
/* UART devices */
80
parts_default_nan(a, s);
70
for (int i = 0; i < STM_NUM_UARTS; i++) {
71
g_autofree char *name = g_strdup_printf("uart%d-out", STM_NUM_USARTS + i + 1);
72
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
73
return;
74
}
75
sysbus_mmio_map(busdev, 0, uart_addr[i]);
76
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, uart_irq[i]));
77
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->exti),
78
+ EXTI_UART4_IRQ + i));
79
}
80
81
/* LPUART device*/
82
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
83
return;
84
}
85
sysbus_mmio_map(busdev, 0, LPUART_BASE_ADDRESS);
86
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, LPUART_IRQ));
87
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->exti),
88
+ EXTI_LPUART1_IRQ));
89
90
/* APB1 BUS */
91
create_unimplemented_device("TIM2", 0x40000000, 0x400);
92
--
81
--
93
2.34.1
82
2.34.1
94
83
95
84
diff view generated by jsdifflib
[PULL 12/24] target/arm: Use cpu_env in cpu_untagged_addr
[PULL 64/72] softfloat: Pad array size in pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
In a completely artifical memset benchmark object_dynamic_cast_assert
3
While all indices into val[] should be in [0-2], the mask
4
dominates the profile, even above guest address resolution and
4
applied is two bits. To help static analysis see there is
5
the underlying host memset.
5
no possibility of read beyond the end of the array, pad the
6
array to 4 entries, with the final being (implicitly) NULL.
6
7
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: 20240702154911.1667418-1-richard.henderson@linaro.org
10
Message-id: 20241203203949.483774-6-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
---
12
target/arm/cpu.h | 4 ++--
13
fpu/softfloat-parts.c.inc | 2 +-
13
1 file changed, 2 insertions(+), 2 deletions(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
14
15
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.h
18
--- a/fpu/softfloat-parts.c.inc
18
+++ b/target/arm/cpu.h
19
+++ b/fpu/softfloat-parts.c.inc
19
@@ -XXX,XX +XXX,XX @@ extern const uint64_t pred_esz_masks[5];
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
20
*/
21
}
21
static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x)
22
ret = c;
22
{
23
} else {
23
- ARMCPU *cpu = ARM_CPU(cs);
24
- FloatPartsN *val[3] = { a, b, c };
24
- if (cpu->env.tagged_addr_enable) {
25
+ FloatPartsN *val[R_3NAN_1ST_MASK + 1] = { a, b, c };
25
+ CPUARMState *env = cpu_env(cs);
26
Float3NaNPropRule rule = s->float_3nan_prop_rule;
26
+ if (env->tagged_addr_enable) {
27
27
/*
28
assert(rule != float_3nan_prop_none);
28
* TBI is enabled for userspace but not kernelspace addresses.
29
* Only clear the tag if bit 55 is clear.
30
--
29
--
31
2.34.1
30
2.34.1
32
31
33
32
diff view generated by jsdifflib
[PULL 22/24] target/arm: Convert SADDW, SSUBW, UADDW, USUBW to decodetree
[PULL 65/72] softfloat: Move propagateFloatx80NaN to softfloat.c
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
This function is part of the public interface and
4
is not "specialized" to any target in any way.
2
5
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20240709000610.382391-5-richard.henderson@linaro.org
8
Message-id: 20241203203949.483774-7-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
target/arm/tcg/a64.decode | 5 ++
11
fpu/softfloat.c | 52 ++++++++++++++++++++++++++++++++++
9
target/arm/tcg/translate-a64.c | 86 +++++++++++++++++-----------------
12
fpu/softfloat-specialize.c.inc | 52 ----------------------------------
10
2 files changed, 48 insertions(+), 43 deletions(-)
13
2 files changed, 52 insertions(+), 52 deletions(-)
11
14
12
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
13
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/tcg/a64.decode
17
--- a/fpu/softfloat.c
15
+++ b/target/arm/tcg/a64.decode
18
+++ b/fpu/softfloat.c
16
@@ -XXX,XX +XXX,XX @@ SQDMLAL_v 0.00 1110 101 ..... 10010 0 ..... ..... @qrrr_s
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
17
SQDMLSL_v 0.00 1110 011 ..... 10110 0 ..... ..... @qrrr_h
20
*zExpPtr = 1 - shiftCount;
18
SQDMLSL_v 0.00 1110 101 ..... 10110 0 ..... ..... @qrrr_s
21
}
19
22
20
+SADDW 0.00 1110 ..1 ..... 00010 0 ..... ..... @qrrr_e
23
+/*----------------------------------------------------------------------------
21
+UADDW 0.10 1110 ..1 ..... 00010 0 ..... ..... @qrrr_e
24
+| Takes two extended double-precision floating-point values `a' and `b', one
22
+SSUBW 0.00 1110 ..1 ..... 00110 0 ..... ..... @qrrr_e
25
+| of which is a NaN, and returns the appropriate NaN result. If either `a' or
23
+USUBW 0.10 1110 ..1 ..... 00110 0 ..... ..... @qrrr_e
26
+| `b' is a signaling NaN, the invalid exception is raised.
27
+*----------------------------------------------------------------------------*/
24
+
28
+
25
### Advanced SIMD scalar x indexed element
29
+floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
26
27
FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h
28
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/tcg/translate-a64.c
31
+++ b/target/arm/tcg/translate-a64.c
32
@@ -XXX,XX +XXX,XX @@ TRANS(SQDMLSL_vi, do_3op_widening,
33
a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, a->idx,
34
a->esz == MO_16 ? gen_sqdmlsl_h : gen_sqdmlsl_s, true)
35
36
+static bool do_addsub_wide(DisasContext *s, arg_qrrr_e *a,
37
+ MemOp sign, bool sub)
38
+{
30
+{
39
+ TCGv_i64 tcg_op0, tcg_op1;
31
+ bool aIsLargerSignificand;
40
+ MemOp esz = a->esz;
32
+ FloatClass a_cls, b_cls;
41
+ int half = 8 >> esz;
42
+ bool top = a->q;
43
+ int top_swap = top ? 0 : half - 1;
44
+ int top_half = top ? half : 0;
45
+
33
+
46
+ /* There are no 64x64->128 bit operations. */
34
+ /* This is not complete, but is good enough for pickNaN. */
47
+ if (esz >= MO_64) {
35
+ a_cls = (!floatx80_is_any_nan(a)
48
+ return false;
36
+ ? float_class_normal
37
+ : floatx80_is_signaling_nan(a, status)
38
+ ? float_class_snan
39
+ : float_class_qnan);
40
+ b_cls = (!floatx80_is_any_nan(b)
41
+ ? float_class_normal
42
+ : floatx80_is_signaling_nan(b, status)
43
+ ? float_class_snan
44
+ : float_class_qnan);
45
+
46
+ if (is_snan(a_cls) || is_snan(b_cls)) {
47
+ float_raise(float_flag_invalid, status);
49
+ }
48
+ }
50
+ if (!fp_access_check(s)) {
49
+
51
+ return true;
50
+ if (status->default_nan_mode) {
51
+ return floatx80_default_nan(status);
52
+ }
52
+ }
53
+ tcg_op0 = tcg_temp_new_i64();
54
+ tcg_op1 = tcg_temp_new_i64();
55
+
53
+
56
+ for (int elt_fwd = 0; elt_fwd < half; ++elt_fwd) {
54
+ if (a.low < b.low) {
57
+ int elt = elt_fwd ^ top_swap;
55
+ aIsLargerSignificand = 0;
56
+ } else if (b.low < a.low) {
57
+ aIsLargerSignificand = 1;
58
+ } else {
59
+ aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
60
+ }
58
+
61
+
59
+ read_vec_element(s, tcg_op1, a->rm, elt + top_half, esz | sign);
62
+ if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
60
+ read_vec_element(s, tcg_op0, a->rn, elt, esz + 1);
63
+ if (is_snan(b_cls)) {
61
+ if (sub) {
64
+ return floatx80_silence_nan(b, status);
62
+ tcg_gen_sub_i64(tcg_op0, tcg_op0, tcg_op1);
63
+ } else {
64
+ tcg_gen_add_i64(tcg_op0, tcg_op0, tcg_op1);
65
+ }
65
+ }
66
+ write_vec_element(s, tcg_op0, a->rd, elt, esz + 1);
66
+ return b;
67
+ } else {
68
+ if (is_snan(a_cls)) {
69
+ return floatx80_silence_nan(a, status);
70
+ }
71
+ return a;
67
+ }
72
+ }
68
+ clear_vec_high(s, 1, a->rd);
69
+ return true;
70
+}
73
+}
71
+
74
+
72
+TRANS(SADDW, do_addsub_wide, a, MO_SIGN, false)
75
/*----------------------------------------------------------------------------
73
+TRANS(UADDW, do_addsub_wide, a, 0, false)
76
| Takes an abstract floating-point value having sign `zSign', exponent `zExp',
74
+TRANS(SSUBW, do_addsub_wide, a, MO_SIGN, true)
77
| and extended significand formed by the concatenation of `zSig0' and `zSig1',
75
+TRANS(USUBW, do_addsub_wide, a, 0, true)
78
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
76
+
79
index XXXXXXX..XXXXXXX 100644
77
/*
80
--- a/fpu/softfloat-specialize.c.inc
78
* Advanced SIMD scalar/vector x indexed element
81
+++ b/fpu/softfloat-specialize.c.inc
79
*/
82
@@ -XXX,XX +XXX,XX @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
80
@@ -XXX,XX +XXX,XX @@ static void gen_neon_addl(int size, bool is_sub, TCGv_i64 tcg_res,
83
return a;
81
genfn(tcg_res, tcg_op1, tcg_op2);
82
}
84
}
83
85
84
-static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size,
86
-/*----------------------------------------------------------------------------
85
- int opcode, int rd, int rn, int rm)
87
-| Takes two extended double-precision floating-point values `a' and `b', one
88
-| of which is a NaN, and returns the appropriate NaN result. If either `a' or
89
-| `b' is a signaling NaN, the invalid exception is raised.
90
-*----------------------------------------------------------------------------*/
91
-
92
-floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
86
-{
93
-{
87
- TCGv_i64 tcg_res[2];
94
- bool aIsLargerSignificand;
88
- int part = is_q ? 2 : 0;
95
- FloatClass a_cls, b_cls;
89
- int pass;
90
-
96
-
91
- for (pass = 0; pass < 2; pass++) {
97
- /* This is not complete, but is good enough for pickNaN. */
92
- TCGv_i64 tcg_op1 = tcg_temp_new_i64();
98
- a_cls = (!floatx80_is_any_nan(a)
93
- TCGv_i32 tcg_op2 = tcg_temp_new_i32();
99
- ? float_class_normal
94
- TCGv_i64 tcg_op2_wide = tcg_temp_new_i64();
100
- : floatx80_is_signaling_nan(a, status)
95
- static NeonGenWidenFn * const widenfns[3][2] = {
101
- ? float_class_snan
96
- { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 },
102
- : float_class_qnan);
97
- { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 },
103
- b_cls = (!floatx80_is_any_nan(b)
98
- { tcg_gen_ext_i32_i64, tcg_gen_extu_i32_i64 },
104
- ? float_class_normal
99
- };
105
- : floatx80_is_signaling_nan(b, status)
100
- NeonGenWidenFn *widenfn = widenfns[size][is_u];
106
- ? float_class_snan
107
- : float_class_qnan);
101
-
108
-
102
- read_vec_element(s, tcg_op1, rn, pass, MO_64);
109
- if (is_snan(a_cls) || is_snan(b_cls)) {
103
- read_vec_element_i32(s, tcg_op2, rm, part + pass, MO_32);
110
- float_raise(float_flag_invalid, status);
104
- widenfn(tcg_op2_wide, tcg_op2);
105
- tcg_res[pass] = tcg_temp_new_i64();
106
- gen_neon_addl(size, (opcode == 3),
107
- tcg_res[pass], tcg_op1, tcg_op2_wide);
108
- }
111
- }
109
-
112
-
110
- for (pass = 0; pass < 2; pass++) {
113
- if (status->default_nan_mode) {
111
- write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
114
- return floatx80_default_nan(status);
115
- }
116
-
117
- if (a.low < b.low) {
118
- aIsLargerSignificand = 0;
119
- } else if (b.low < a.low) {
120
- aIsLargerSignificand = 1;
121
- } else {
122
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
123
- }
124
-
125
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
126
- if (is_snan(b_cls)) {
127
- return floatx80_silence_nan(b, status);
128
- }
129
- return b;
130
- } else {
131
- if (is_snan(a_cls)) {
132
- return floatx80_silence_nan(a, status);
133
- }
134
- return a;
112
- }
135
- }
113
-}
136
-}
114
-
137
-
115
static void do_narrow_round_high_u32(TCGv_i32 res, TCGv_i64 in)
138
/*----------------------------------------------------------------------------
116
{
139
| Returns 1 if the quadruple-precision floating-point value `a' is a quiet
117
tcg_gen_addi_i64(in, in, 1U << 31);
140
| NaN; otherwise returns 0.
118
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
119
int rd = extract32(insn, 0, 5);
120
121
switch (opcode) {
122
- case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
123
- case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
124
- /* 64 x 128 -> 128 */
125
- if (size == 3) {
126
- unallocated_encoding(s);
127
- return;
128
- }
129
- if (!fp_access_check(s)) {
130
- return;
131
- }
132
- handle_3rd_wide(s, is_q, is_u, size, opcode, rd, rn, rm);
133
- break;
134
case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
135
case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
136
/* 128 x 128 -> 64 */
137
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
138
return;
139
default:
140
case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
141
+ case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
142
case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
143
+ case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
144
case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
145
case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
146
case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
147
--
141
--
148
2.34.1
142
2.34.1
diff view generated by jsdifflib
New patch
[PULL 66/72] softfloat: Use parts_pick_nan in propagateFloatx80NaN
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Unpacking and repacking the parts may be slightly more work
4
than we did before, but we get to reuse more code. For a
5
code path handling exceptional values, this is an improvement.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241203203949.483774-8-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
fpu/softfloat.c | 43 +++++--------------------------------------
13
1 file changed, 5 insertions(+), 38 deletions(-)
14
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/fpu/softfloat.c
18
+++ b/fpu/softfloat.c
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
20
21
floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
22
{
23
- bool aIsLargerSignificand;
24
- FloatClass a_cls, b_cls;
25
+ FloatParts128 pa, pb, *pr;
26
27
- /* This is not complete, but is good enough for pickNaN. */
28
- a_cls = (!floatx80_is_any_nan(a)
29
- ? float_class_normal
30
- : floatx80_is_signaling_nan(a, status)
31
- ? float_class_snan
32
- : float_class_qnan);
33
- b_cls = (!floatx80_is_any_nan(b)
34
- ? float_class_normal
35
- : floatx80_is_signaling_nan(b, status)
36
- ? float_class_snan
37
- : float_class_qnan);
38
-
39
- if (is_snan(a_cls) || is_snan(b_cls)) {
40
- float_raise(float_flag_invalid, status);
41
- }
42
-
43
- if (status->default_nan_mode) {
44
+ if (!floatx80_unpack_canonical(&pa, a, status) ||
45
+ !floatx80_unpack_canonical(&pb, b, status)) {
46
return floatx80_default_nan(status);
47
}
48
49
- if (a.low < b.low) {
50
- aIsLargerSignificand = 0;
51
- } else if (b.low < a.low) {
52
- aIsLargerSignificand = 1;
53
- } else {
54
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
55
- }
56
-
57
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
58
- if (is_snan(b_cls)) {
59
- return floatx80_silence_nan(b, status);
60
- }
61
- return b;
62
- } else {
63
- if (is_snan(a_cls)) {
64
- return floatx80_silence_nan(a, status);
65
- }
66
- return a;
67
- }
68
+ pr = parts_pick_nan(&pa, &pb, status);
69
+ return floatx80_round_pack_canonical(pr, status);
70
}
71
72
/*----------------------------------------------------------------------------
73
--
74
2.34.1
diff view generated by jsdifflib
[PULL 24/24] target/arm: Convert PMULL to decodetree
[PULL 67/72] softfloat: Inline pickNaN
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
Inline pickNaN into its only caller. This makes one assert
4
redundant with the immediately preceding IF.
2
5
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241203203949.483774-9-richard.henderson@linaro.org
6
Message-id: 20240709000610.382391-7-richard.henderson@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
10
---
9
target/arm/tcg/a64.decode | 3 ++
11
fpu/softfloat-parts.c.inc | 82 +++++++++++++++++++++++++----
10
target/arm/tcg/translate-a64.c | 94 +++++-----------------------------
12
fpu/softfloat-specialize.c.inc | 96 ----------------------------------
11
2 files changed, 15 insertions(+), 82 deletions(-)
13
2 files changed, 73 insertions(+), 105 deletions(-)
12
14
13
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
15
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/tcg/a64.decode
17
--- a/fpu/softfloat-parts.c.inc
16
+++ b/target/arm/tcg/a64.decode
18
+++ b/fpu/softfloat-parts.c.inc
17
@@ -XXX,XX +XXX,XX @@ RADDHN 0.10 1110 ..1 ..... 01000 0 ..... ..... @qrrr_e
19
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
18
SUBHN 0.00 1110 ..1 ..... 01100 0 ..... ..... @qrrr_e
20
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
19
RSUBHN 0.10 1110 ..1 ..... 01100 0 ..... ..... @qrrr_e
21
float_status *s)
20
22
{
21
+PMULL_p8 0.00 1110 001 ..... 11100 0 ..... ..... @qrrr_b
23
+ int cmp, which;
22
+PMULL_p64 0.00 1110 111 ..... 11100 0 ..... ..... @qrrr_b
23
+
24
+
24
### Advanced SIMD scalar x indexed element
25
if (is_snan(a->cls) || is_snan(b->cls)) {
25
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
26
FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h
27
}
27
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
28
29
if (s->default_nan_mode) {
30
parts_default_nan(a, s);
31
- } else {
32
- int cmp = frac_cmp(a, b);
33
- if (cmp == 0) {
34
- cmp = a->sign < b->sign;
35
- }
36
+ return a;
37
+ }
38
39
- if (pickNaN(a->cls, b->cls, cmp > 0, s)) {
40
- a = b;
41
- }
42
+ cmp = frac_cmp(a, b);
43
+ if (cmp == 0) {
44
+ cmp = a->sign < b->sign;
45
+ }
46
+
47
+ switch (s->float_2nan_prop_rule) {
48
+ case float_2nan_prop_s_ab:
49
if (is_snan(a->cls)) {
50
- parts_silence_nan(a, s);
51
+ which = 0;
52
+ } else if (is_snan(b->cls)) {
53
+ which = 1;
54
+ } else if (is_qnan(a->cls)) {
55
+ which = 0;
56
+ } else {
57
+ which = 1;
58
}
59
+ break;
60
+ case float_2nan_prop_s_ba:
61
+ if (is_snan(b->cls)) {
62
+ which = 1;
63
+ } else if (is_snan(a->cls)) {
64
+ which = 0;
65
+ } else if (is_qnan(b->cls)) {
66
+ which = 1;
67
+ } else {
68
+ which = 0;
69
+ }
70
+ break;
71
+ case float_2nan_prop_ab:
72
+ which = is_nan(a->cls) ? 0 : 1;
73
+ break;
74
+ case float_2nan_prop_ba:
75
+ which = is_nan(b->cls) ? 1 : 0;
76
+ break;
77
+ case float_2nan_prop_x87:
78
+ /*
79
+ * This implements x87 NaN propagation rules:
80
+ * SNaN + QNaN => return the QNaN
81
+ * two SNaNs => return the one with the larger significand, silenced
82
+ * two QNaNs => return the one with the larger significand
83
+ * SNaN and a non-NaN => return the SNaN, silenced
84
+ * QNaN and a non-NaN => return the QNaN
85
+ *
86
+ * If we get down to comparing significands and they are the same,
87
+ * return the NaN with the positive sign bit (if any).
88
+ */
89
+ if (is_snan(a->cls)) {
90
+ if (is_snan(b->cls)) {
91
+ which = cmp > 0 ? 0 : 1;
92
+ } else {
93
+ which = is_qnan(b->cls) ? 1 : 0;
94
+ }
95
+ } else if (is_qnan(a->cls)) {
96
+ if (is_snan(b->cls) || !is_qnan(b->cls)) {
97
+ which = 0;
98
+ } else {
99
+ which = cmp > 0 ? 0 : 1;
100
+ }
101
+ } else {
102
+ which = 1;
103
+ }
104
+ break;
105
+ default:
106
+ g_assert_not_reached();
107
+ }
108
+
109
+ if (which) {
110
+ a = b;
111
+ }
112
+ if (is_snan(a->cls)) {
113
+ parts_silence_nan(a, s);
114
}
115
return a;
116
}
117
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
118
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/tcg/translate-a64.c
119
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/target/arm/tcg/translate-a64.c
120
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ TRANS(SUBHN, do_addsub_highnarrow, a, true, false)
121
@@ -XXX,XX +XXX,XX @@ bool float32_is_signaling_nan(float32 a_, float_status *status)
32
TRANS(RADDHN, do_addsub_highnarrow, a, false, true)
33
TRANS(RSUBHN, do_addsub_highnarrow, a, true, true)
34
35
+static bool do_pmull(DisasContext *s, arg_qrrr_e *a, gen_helper_gvec_3 *fn)
36
+{
37
+ if (fp_access_check(s)) {
38
+ /* The Q field specifies lo/hi half input for these insns. */
39
+ gen_gvec_op3_ool(s, true, a->rd, a->rn, a->rm, a->q, fn);
40
+ }
41
+ return true;
42
+}
43
+
44
+TRANS(PMULL_p8, do_pmull, a, gen_helper_neon_pmull_h)
45
+TRANS_FEAT(PMULL_p64, aa64_pmull, do_pmull, a, gen_helper_gvec_pmull_q)
46
+
47
/*
48
* Advanced SIMD scalar/vector x indexed element
49
*/
50
@@ -XXX,XX +XXX,XX @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn)
51
}
122
}
52
}
123
}
53
124
54
-/* AdvSIMD three different
125
-/*----------------------------------------------------------------------------
55
- * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
126
-| Select which NaN to propagate for a two-input operation.
56
- * +---+---+---+-----------+------+---+------+--------+-----+------+------+
127
-| IEEE754 doesn't specify all the details of this, so the
57
- * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
128
-| algorithm is target-specific.
58
- * +---+---+---+-----------+------+---+------+--------+-----+------+------+
129
-| The routine is passed various bits of information about the
59
- */
130
-| two NaNs and should return 0 to select NaN a and 1 for NaN b.
60
-static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
131
-| Note that signalling NaNs are always squashed to quiet NaNs
132
-| by the caller, by calling floatXX_silence_nan() before
133
-| returning them.
134
-|
135
-| aIsLargerSignificand is only valid if both a and b are NaNs
136
-| of some kind, and is true if a has the larger significand,
137
-| or if both a and b have the same significand but a is
138
-| positive but b is negative. It is only needed for the x87
139
-| tie-break rule.
140
-*----------------------------------------------------------------------------*/
141
-
142
-static int pickNaN(FloatClass a_cls, FloatClass b_cls,
143
- bool aIsLargerSignificand, float_status *status)
61
-{
144
-{
62
- /* Instructions in this group fall into three basic classes
145
- /*
63
- * (in each case with the operation working on each element in
146
- * We guarantee not to require the target to tell us how to
64
- * the input vectors):
147
- * pick a NaN if we're always returning the default NaN.
65
- * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
148
- * But if we're not in default-NaN mode then the target must
66
- * 128 bit input)
149
- * specify via set_float_2nan_prop_rule().
67
- * (2) wide 64 x 128 -> 128
68
- * (3) narrowing 128 x 128 -> 64
69
- * Here we do initial decode, catch unallocated cases and
70
- * dispatch to separate functions for each class.
71
- */
150
- */
72
- int is_q = extract32(insn, 30, 1);
151
- assert(!status->default_nan_mode);
73
- int is_u = extract32(insn, 29, 1);
74
- int size = extract32(insn, 22, 2);
75
- int opcode = extract32(insn, 12, 4);
76
- int rm = extract32(insn, 16, 5);
77
- int rn = extract32(insn, 5, 5);
78
- int rd = extract32(insn, 0, 5);
79
-
152
-
80
- switch (opcode) {
153
- switch (status->float_2nan_prop_rule) {
81
- case 14: /* PMULL, PMULL2 */
154
- case float_2nan_prop_s_ab:
82
- if (is_u) {
155
- if (is_snan(a_cls)) {
83
- unallocated_encoding(s);
156
- return 0;
84
- return;
157
- } else if (is_snan(b_cls)) {
85
- }
158
- return 1;
86
- switch (size) {
159
- } else if (is_qnan(a_cls)) {
87
- case 0: /* PMULL.P8 */
160
- return 0;
88
- if (!fp_access_check(s)) {
161
- } else {
89
- return;
162
- return 1;
163
- }
164
- break;
165
- case float_2nan_prop_s_ba:
166
- if (is_snan(b_cls)) {
167
- return 1;
168
- } else if (is_snan(a_cls)) {
169
- return 0;
170
- } else if (is_qnan(b_cls)) {
171
- return 1;
172
- } else {
173
- return 0;
174
- }
175
- break;
176
- case float_2nan_prop_ab:
177
- if (is_nan(a_cls)) {
178
- return 0;
179
- } else {
180
- return 1;
181
- }
182
- break;
183
- case float_2nan_prop_ba:
184
- if (is_nan(b_cls)) {
185
- return 1;
186
- } else {
187
- return 0;
188
- }
189
- break;
190
- case float_2nan_prop_x87:
191
- /*
192
- * This implements x87 NaN propagation rules:
193
- * SNaN + QNaN => return the QNaN
194
- * two SNaNs => return the one with the larger significand, silenced
195
- * two QNaNs => return the one with the larger significand
196
- * SNaN and a non-NaN => return the SNaN, silenced
197
- * QNaN and a non-NaN => return the QNaN
198
- *
199
- * If we get down to comparing significands and they are the same,
200
- * return the NaN with the positive sign bit (if any).
201
- */
202
- if (is_snan(a_cls)) {
203
- if (is_snan(b_cls)) {
204
- return aIsLargerSignificand ? 0 : 1;
90
- }
205
- }
91
- /* The Q field specifies lo/hi half input for this insn. */
206
- return is_qnan(b_cls) ? 1 : 0;
92
- gen_gvec_op3_ool(s, true, rd, rn, rm, is_q,
207
- } else if (is_qnan(a_cls)) {
93
- gen_helper_neon_pmull_h);
208
- if (is_snan(b_cls) || !is_qnan(b_cls)) {
94
- break;
209
- return 0;
95
-
210
- } else {
96
- case 3: /* PMULL.P64 */
211
- return aIsLargerSignificand ? 0 : 1;
97
- if (!dc_isar_feature(aa64_pmull, s)) {
98
- unallocated_encoding(s);
99
- return;
100
- }
212
- }
101
- if (!fp_access_check(s)) {
213
- } else {
102
- return;
214
- return 1;
103
- }
215
- }
104
- /* The Q field specifies lo/hi half input for this insn. */
105
- gen_gvec_op3_ool(s, true, rd, rn, rm, is_q,
106
- gen_helper_gvec_pmull_q);
107
- break;
108
-
109
- default:
110
- unallocated_encoding(s);
111
- break;
112
- }
113
- return;
114
- default:
216
- default:
115
- case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
217
- g_assert_not_reached();
116
- case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
117
- case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
118
- case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
119
- case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
120
- case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
121
- case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
122
- case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
123
- case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
124
- case 9: /* SQDMLAL, SQDMLAL2 */
125
- case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
126
- case 11: /* SQDMLSL, SQDMLSL2 */
127
- case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
128
- case 13: /* SQDMULL, SQDMULL2 */
129
- /* opcode 15 not allocated */
130
- unallocated_encoding(s);
131
- break;
132
- }
218
- }
133
-}
219
-}
134
-
220
-
135
static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
221
/*----------------------------------------------------------------------------
136
int size, int rn, int rd)
222
| Returns 1 if the double-precision floating-point value `a' is a quiet
137
{
223
| NaN; otherwise returns 0.
138
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
139
*/
140
static const AArch64DecodeTable data_proc_simd[] = {
141
/* pattern , mask , fn */
142
- { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff },
143
{ 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc },
144
{ 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes },
145
/* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
146
--
224
--
147
2.34.1
225
2.34.1
148
226
149
227
diff view generated by jsdifflib
[PULL 19/24] target/arm: Convert SMULL, UMULL, SMLAL, UMLAL, SMLSL, UMLSL to decodetree
[PULL 68/72] softfloat: Share code between parts_pick_nan cases
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
Remember if there was an SNaN, and use that to simplify
4
float_2nan_prop_s_{ab,ba} to only the snan component.
5
Then, fall through to the corresponding
6
float_2nan_prop_{ab,ba} case to handle any remaining
7
nans, which must be quiet.
2
8
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20240709000610.382391-2-richard.henderson@linaro.org
11
Message-id: 20241203203949.483774-10-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
13
---
8
target/arm/tcg/a64.decode | 22 ++++
14
fpu/softfloat-parts.c.inc | 32 ++++++++++++--------------------
9
target/arm/tcg/translate-a64.c | 184 ++++++++++++++++++++++++---------
15
1 file changed, 12 insertions(+), 20 deletions(-)
10
2 files changed, 156 insertions(+), 50 deletions(-)
11
16
12
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
13
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/tcg/a64.decode
19
--- a/fpu/softfloat-parts.c.inc
15
+++ b/target/arm/tcg/a64.decode
20
+++ b/fpu/softfloat-parts.c.inc
16
@@ -XXX,XX +XXX,XX @@ FCADD_270 0.10 1110 ..0 ..... 11110 1 ..... ..... @qrrr_e
21
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
17
22
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
18
FCMLA_v 0 q:1 10 1110 esz:2 0 rm:5 110 rot:2 1 rn:5 rd:5
23
float_status *s)
19
24
{
20
+SMULL_v 0.00 1110 ..1 ..... 11000 0 ..... ..... @qrrr_e
25
+ bool have_snan = false;
21
+UMULL_v 0.10 1110 ..1 ..... 11000 0 ..... ..... @qrrr_e
26
int cmp, which;
22
+SMLAL_v 0.00 1110 ..1 ..... 10000 0 ..... ..... @qrrr_e
27
23
+UMLAL_v 0.10 1110 ..1 ..... 10000 0 ..... ..... @qrrr_e
28
if (is_snan(a->cls) || is_snan(b->cls)) {
24
+SMLSL_v 0.00 1110 ..1 ..... 10100 0 ..... ..... @qrrr_e
29
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
25
+UMLSL_v 0.10 1110 ..1 ..... 10100 0 ..... ..... @qrrr_e
30
+ have_snan = true;
26
+
31
}
27
### Advanced SIMD scalar x indexed element
32
28
33
if (s->default_nan_mode) {
29
FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h
34
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
30
@@ -XXX,XX +XXX,XX @@ FCMLA_vi 0 0 10 1111 01 idx:1 rm:5 0 rot:2 1 0 0 rn:5 rd:5 esz=1 q=0
35
31
FCMLA_vi 0 1 10 1111 01 . rm:5 0 rot:2 1 . 0 rn:5 rd:5 esz=1 idx=%hl q=1
36
switch (s->float_2nan_prop_rule) {
32
FCMLA_vi 0 1 10 1111 10 0 rm:5 0 rot:2 1 idx:1 0 rn:5 rd:5 esz=2 q=1
37
case float_2nan_prop_s_ab:
33
38
- if (is_snan(a->cls)) {
34
+SMULL_vi 0.00 1111 01 .. .... 1010 . 0 ..... ..... @qrrx_h
39
- which = 0;
35
+SMULL_vi 0.00 1111 10 . ..... 1010 . 0 ..... ..... @qrrx_s
40
- } else if (is_snan(b->cls)) {
36
+UMULL_vi 0.10 1111 01 .. .... 1010 . 0 ..... ..... @qrrx_h
41
- which = 1;
37
+UMULL_vi 0.10 1111 10 . ..... 1010 . 0 ..... ..... @qrrx_s
42
- } else if (is_qnan(a->cls)) {
38
+
43
- which = 0;
39
+SMLAL_vi 0.00 1111 01 .. .... 0010 . 0 ..... ..... @qrrx_h
44
- } else {
40
+SMLAL_vi 0.00 1111 10 . ..... 0010 . 0 ..... ..... @qrrx_s
45
- which = 1;
41
+UMLAL_vi 0.10 1111 01 .. .... 0010 . 0 ..... ..... @qrrx_h
46
+ if (have_snan) {
42
+UMLAL_vi 0.10 1111 10 . ..... 0010 . 0 ..... ..... @qrrx_s
47
+ which = is_snan(a->cls) ? 0 : 1;
43
+
48
+ break;
44
+SMLSL_vi 0.00 1111 01 .. .... 0110 . 0 ..... ..... @qrrx_h
49
}
45
+SMLSL_vi 0.00 1111 10 . ..... 0110 . 0 ..... ..... @qrrx_s
50
- break;
46
+UMLSL_vi 0.10 1111 01 .. .... 0110 . 0 ..... ..... @qrrx_h
51
- case float_2nan_prop_s_ba:
47
+UMLSL_vi 0.10 1111 10 . ..... 0110 . 0 ..... ..... @qrrx_s
52
- if (is_snan(b->cls)) {
48
+
53
- which = 1;
49
# Floating-point conditional select
54
- } else if (is_snan(a->cls)) {
50
55
- which = 0;
51
FCSEL 0001 1110 .. 1 rm:5 cond:4 11 rn:5 rd:5 esz=%esz_hsd
56
- } else if (is_qnan(b->cls)) {
52
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
57
- which = 1;
53
index XXXXXXX..XXXXXXX 100644
58
- } else {
54
--- a/target/arm/tcg/translate-a64.c
59
- which = 0;
55
+++ b/target/arm/tcg/translate-a64.c
56
@@ -XXX,XX +XXX,XX @@ static bool trans_FCMLA_v(DisasContext *s, arg_FCMLA_v *a)
57
return true;
58
}
59
60
+/*
61
+ * Widening vector x vector/indexed.
62
+ *
63
+ * These read from the top or bottom half of a 128-bit vector.
64
+ * After widening, optionally accumulate with a 128-bit vector.
65
+ * Implement these inline, as the number of elements are limited
66
+ * and the related SVE and SME operations on larger vectors use
67
+ * even/odd elements instead of top/bottom half.
68
+ *
69
+ * If idx >= 0, operand 2 is indexed, otherwise vector.
70
+ * If acc, operand 0 is loaded with rd.
71
+ */
72
+
73
+/* For low half, iterating up. */
74
+static bool do_3op_widening(DisasContext *s, MemOp memop, int top,
75
+ int rd, int rn, int rm, int idx,
76
+ NeonGenTwo64OpFn *fn, bool acc)
77
+{
78
+ TCGv_i64 tcg_op0 = tcg_temp_new_i64();
79
+ TCGv_i64 tcg_op1 = tcg_temp_new_i64();
80
+ TCGv_i64 tcg_op2 = tcg_temp_new_i64();
81
+ MemOp esz = memop & MO_SIZE;
82
+ int half = 8 >> esz;
83
+ int top_swap, top_half;
84
+
85
+ /* There are no 64x64->128 bit operations. */
86
+ if (esz >= MO_64) {
87
+ return false;
88
+ }
89
+ if (!fp_access_check(s)) {
90
+ return true;
91
+ }
92
+
93
+ if (idx >= 0) {
94
+ read_vec_element(s, tcg_op2, rm, idx, memop);
95
+ }
96
+
97
+ /*
98
+ * For top half inputs, iterate forward; backward for bottom half.
99
+ * This means the store to the destination will not occur until
100
+ * overlapping input inputs are consumed.
101
+ * Use top_swap to conditionally invert the forward iteration index.
102
+ */
103
+ top_swap = top ? 0 : half - 1;
104
+ top_half = top ? half : 0;
105
+
106
+ for (int elt_fwd = 0; elt_fwd < half; ++elt_fwd) {
107
+ int elt = elt_fwd ^ top_swap;
108
+
109
+ read_vec_element(s, tcg_op1, rn, elt + top_half, memop);
110
+ if (idx < 0) {
111
+ read_vec_element(s, tcg_op2, rm, elt + top_half, memop);
112
+ }
113
+ if (acc) {
114
+ read_vec_element(s, tcg_op0, rd, elt, memop + 1);
115
+ }
116
+ fn(tcg_op0, tcg_op1, tcg_op2);
117
+ write_vec_element(s, tcg_op0, rd, elt, esz + 1);
118
+ }
119
+ clear_vec_high(s, 1, rd);
120
+ return true;
121
+}
122
+
123
+static void gen_muladd_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m)
124
+{
125
+ TCGv_i64 t = tcg_temp_new_i64();
126
+ tcg_gen_mul_i64(t, n, m);
127
+ tcg_gen_add_i64(d, d, t);
128
+}
129
+
130
+static void gen_mulsub_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m)
131
+{
132
+ TCGv_i64 t = tcg_temp_new_i64();
133
+ tcg_gen_mul_i64(t, n, m);
134
+ tcg_gen_sub_i64(d, d, t);
135
+}
136
+
137
+TRANS(SMULL_v, do_3op_widening,
138
+ a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, -1,
139
+ tcg_gen_mul_i64, false)
140
+TRANS(UMULL_v, do_3op_widening,
141
+ a->esz, a->q, a->rd, a->rn, a->rm, -1,
142
+ tcg_gen_mul_i64, false)
143
+TRANS(SMLAL_v, do_3op_widening,
144
+ a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, -1,
145
+ gen_muladd_i64, true)
146
+TRANS(UMLAL_v, do_3op_widening,
147
+ a->esz, a->q, a->rd, a->rn, a->rm, -1,
148
+ gen_muladd_i64, true)
149
+TRANS(SMLSL_v, do_3op_widening,
150
+ a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, -1,
151
+ gen_mulsub_i64, true)
152
+TRANS(UMLSL_v, do_3op_widening,
153
+ a->esz, a->q, a->rd, a->rn, a->rm, -1,
154
+ gen_mulsub_i64, true)
155
+
156
+TRANS(SMULL_vi, do_3op_widening,
157
+ a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, a->idx,
158
+ tcg_gen_mul_i64, false)
159
+TRANS(UMULL_vi, do_3op_widening,
160
+ a->esz, a->q, a->rd, a->rn, a->rm, a->idx,
161
+ tcg_gen_mul_i64, false)
162
+TRANS(SMLAL_vi, do_3op_widening,
163
+ a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, a->idx,
164
+ gen_muladd_i64, true)
165
+TRANS(UMLAL_vi, do_3op_widening,
166
+ a->esz, a->q, a->rd, a->rn, a->rm, a->idx,
167
+ gen_muladd_i64, true)
168
+TRANS(SMLSL_vi, do_3op_widening,
169
+ a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, a->idx,
170
+ gen_mulsub_i64, true)
171
+TRANS(UMLSL_vi, do_3op_widening,
172
+ a->esz, a->q, a->rd, a->rn, a->rm, a->idx,
173
+ gen_mulsub_i64, true)
174
+
175
/*
176
* Advanced SIMD scalar/vector x indexed element
177
*/
178
@@ -XXX,XX +XXX,XX @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
179
tcg_op1, tcg_op2, tcg_tmp1, tcg_tmp2);
180
break;
181
}
182
- case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
183
- case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
184
- case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
185
- tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2);
186
- break;
187
case 9: /* SQDMLAL, SQDMLAL2 */
188
case 11: /* SQDMLSL, SQDMLSL2 */
189
case 13: /* SQDMULL, SQDMULL2 */
190
@@ -XXX,XX +XXX,XX @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
191
tcg_passres, tcg_passres);
192
break;
193
default:
194
+ case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
195
+ case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
196
+ case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
197
g_assert_not_reached();
198
}
199
200
@@ -XXX,XX +XXX,XX @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
201
}
202
}
203
break;
204
- case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
205
- case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
206
- case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
207
- if (size == 0) {
208
- if (is_u) {
209
- gen_helper_neon_mull_u8(tcg_passres, tcg_op1, tcg_op2);
210
- } else {
211
- gen_helper_neon_mull_s8(tcg_passres, tcg_op1, tcg_op2);
212
- }
213
- } else {
214
- if (is_u) {
215
- gen_helper_neon_mull_u16(tcg_passres, tcg_op1, tcg_op2);
216
- } else {
217
- gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2);
218
- }
219
- }
220
- break;
221
case 9: /* SQDMLAL, SQDMLAL2 */
222
case 11: /* SQDMLSL, SQDMLSL2 */
223
case 13: /* SQDMULL, SQDMULL2 */
224
@@ -XXX,XX +XXX,XX @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
225
tcg_passres, tcg_passres);
226
break;
227
default:
228
+ case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
229
+ case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
230
+ case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
231
g_assert_not_reached();
232
}
233
234
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
235
case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
236
case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
237
case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
238
- case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
239
- case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
240
- case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
241
/* 64 x 64 -> 128 */
242
if (size == 3) {
243
unallocated_encoding(s);
244
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
245
handle_3rd_widening(s, is_q, is_u, size, opcode, rd, rn, rm);
246
break;
247
default:
248
+ case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
249
+ case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
250
+ case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
251
/* opcode 15 not allocated */
252
unallocated_encoding(s);
253
break;
254
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
255
int index;
256
257
switch (16 * u + opcode) {
258
- case 0x02: /* SMLAL, SMLAL2 */
259
- case 0x12: /* UMLAL, UMLAL2 */
260
- case 0x06: /* SMLSL, SMLSL2 */
261
- case 0x16: /* UMLSL, UMLSL2 */
262
- case 0x0a: /* SMULL, SMULL2 */
263
- case 0x1a: /* UMULL, UMULL2 */
264
- if (is_scalar) {
265
- unallocated_encoding(s);
266
- return;
267
- }
60
- }
268
- break;
61
- break;
269
case 0x03: /* SQDMLAL, SQDMLAL2 */
62
+ /* fall through */
270
case 0x07: /* SQDMLSL, SQDMLSL2 */
63
case float_2nan_prop_ab:
271
case 0x0b: /* SQDMULL, SQDMULL2 */
64
which = is_nan(a->cls) ? 0 : 1;
272
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
65
break;
273
default:
66
+ case float_2nan_prop_s_ba:
274
case 0x00: /* FMLAL */
67
+ if (have_snan) {
275
case 0x01: /* FMLA */
68
+ which = is_snan(b->cls) ? 1 : 0;
276
+ case 0x02: /* SMLAL, SMLAL2 */
69
+ break;
277
case 0x04: /* FMLSL */
70
+ }
278
case 0x05: /* FMLS */
71
+ /* fall through */
279
+ case 0x06: /* SMLSL, SMLSL2 */
72
case float_2nan_prop_ba:
280
case 0x08: /* MUL */
73
which = is_nan(b->cls) ? 1 : 0;
281
case 0x09: /* FMUL */
74
break;
282
+ case 0x0a: /* SMULL, SMULL2 */
283
case 0x0c: /* SQDMULH */
284
case 0x0d: /* SQRDMULH */
285
case 0x0e: /* SDOT */
286
case 0x0f: /* SUDOT / BFDOT / USDOT / BFMLAL */
287
case 0x10: /* MLA */
288
case 0x11: /* FCMLA #0 */
289
+ case 0x12: /* UMLAL, UMLAL2 */
290
case 0x13: /* FCMLA #90 */
291
case 0x14: /* MLS */
292
case 0x15: /* FCMLA #180 */
293
+ case 0x16: /* UMLSL, UMLSL2 */
294
case 0x17: /* FCMLA #270 */
295
case 0x18: /* FMLAL2 */
296
case 0x19: /* FMULX */
297
+ case 0x1a: /* UMULL, UMULL2 */
298
case 0x1c: /* FMLSL2 */
299
case 0x1d: /* SQRDMLAH */
300
case 0x1e: /* UDOT */
301
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
302
read_vec_element(s, tcg_res[pass], rd, pass, MO_64);
303
304
switch (opcode) {
305
- case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
306
- tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
307
- break;
308
- case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
309
- tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
310
- break;
311
case 0x7: /* SQDMLSL, SQDMLSL2 */
312
tcg_gen_neg_i64(tcg_passres, tcg_passres);
313
/* fall through */
314
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
315
tcg_passres);
316
break;
317
default:
318
+ case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
319
+ case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
320
g_assert_not_reached();
321
}
322
}
323
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
324
read_vec_element(s, tcg_res[pass], rd, pass, MO_64);
325
326
switch (opcode) {
327
- case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
328
- gen_helper_neon_addl_u32(tcg_res[pass], tcg_res[pass],
329
- tcg_passres);
330
- break;
331
- case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
332
- gen_helper_neon_subl_u32(tcg_res[pass], tcg_res[pass],
333
- tcg_passres);
334
- break;
335
case 0x7: /* SQDMLSL, SQDMLSL2 */
336
gen_helper_neon_negl_u32(tcg_passres, tcg_passres);
337
/* fall through */
338
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
339
tcg_passres);
340
break;
341
default:
342
+ case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
343
+ case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
344
g_assert_not_reached();
345
}
346
}
347
--
75
--
348
2.34.1
76
2.34.1
diff view generated by jsdifflib
[PULL 20/24] target/arm: Convert SADDL, SSUBL, SABDL, SABAL, and unsigned to decodetree
[PULL 69/72] softfloat: Sink frac_cmp in parts_pick_nan until needed
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
Move the fractional comparison to the end of the
4
float_2nan_prop_x87 case. This is not required for
5
any other 2nan propagation rule. Reorganize the
6
x87 case itself to break out of the switch when the
7
fractional comparison is not required.
2
8
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20240709000610.382391-3-richard.henderson@linaro.org
11
Message-id: 20241203203949.483774-11-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
13
---
8
target/arm/tcg/a64.decode | 9 ++
14
fpu/softfloat-parts.c.inc | 19 +++++++++----------
9
target/arm/tcg/translate-a64.c | 150 +++++++++++++++++----------------
15
1 file changed, 9 insertions(+), 10 deletions(-)
10
2 files changed, 87 insertions(+), 72 deletions(-)
11
16
12
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
13
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/tcg/a64.decode
19
--- a/fpu/softfloat-parts.c.inc
15
+++ b/target/arm/tcg/a64.decode
20
+++ b/fpu/softfloat-parts.c.inc
16
@@ -XXX,XX +XXX,XX @@ UMLAL_v 0.10 1110 ..1 ..... 10000 0 ..... ..... @qrrr_e
21
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
17
SMLSL_v 0.00 1110 ..1 ..... 10100 0 ..... ..... @qrrr_e
22
return a;
18
UMLSL_v 0.10 1110 ..1 ..... 10100 0 ..... ..... @qrrr_e
23
}
19
24
20
+SADDL_v 0.00 1110 ..1 ..... 00000 0 ..... ..... @qrrr_e
25
- cmp = frac_cmp(a, b);
21
+UADDL_v 0.10 1110 ..1 ..... 00000 0 ..... ..... @qrrr_e
26
- if (cmp == 0) {
22
+SSUBL_v 0.00 1110 ..1 ..... 00100 0 ..... ..... @qrrr_e
27
- cmp = a->sign < b->sign;
23
+USUBL_v 0.10 1110 ..1 ..... 00100 0 ..... ..... @qrrr_e
28
- }
24
+SABAL_v 0.00 1110 ..1 ..... 01010 0 ..... ..... @qrrr_e
29
-
25
+UABAL_v 0.10 1110 ..1 ..... 01010 0 ..... ..... @qrrr_e
30
switch (s->float_2nan_prop_rule) {
26
+SABDL_v 0.00 1110 ..1 ..... 01110 0 ..... ..... @qrrr_e
31
case float_2nan_prop_s_ab:
27
+UABDL_v 0.10 1110 ..1 ..... 01110 0 ..... ..... @qrrr_e
32
if (have_snan) {
28
+
33
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
29
### Advanced SIMD scalar x indexed element
34
* return the NaN with the positive sign bit (if any).
30
35
*/
31
FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h
36
if (is_snan(a->cls)) {
32
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
37
- if (is_snan(b->cls)) {
33
index XXXXXXX..XXXXXXX 100644
38
- which = cmp > 0 ? 0 : 1;
34
--- a/target/arm/tcg/translate-a64.c
39
- } else {
35
+++ b/target/arm/tcg/translate-a64.c
40
+ if (!is_snan(b->cls)) {
36
@@ -XXX,XX +XXX,XX @@ TRANS(UMLSL_vi, do_3op_widening,
41
which = is_qnan(b->cls) ? 1 : 0;
37
a->esz, a->q, a->rd, a->rn, a->rm, a->idx,
42
+ break;
38
gen_mulsub_i64, true)
39
40
+static void gen_sabd_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m)
41
+{
42
+ TCGv_i64 t1 = tcg_temp_new_i64();
43
+ TCGv_i64 t2 = tcg_temp_new_i64();
44
+
45
+ tcg_gen_sub_i64(t1, n, m);
46
+ tcg_gen_sub_i64(t2, m, n);
47
+ tcg_gen_movcond_i64(TCG_COND_GE, d, n, m, t1, t2);
48
+}
49
+
50
+static void gen_uabd_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m)
51
+{
52
+ TCGv_i64 t1 = tcg_temp_new_i64();
53
+ TCGv_i64 t2 = tcg_temp_new_i64();
54
+
55
+ tcg_gen_sub_i64(t1, n, m);
56
+ tcg_gen_sub_i64(t2, m, n);
57
+ tcg_gen_movcond_i64(TCG_COND_GEU, d, n, m, t1, t2);
58
+}
59
+
60
+static void gen_saba_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m)
61
+{
62
+ TCGv_i64 t = tcg_temp_new_i64();
63
+ gen_sabd_i64(t, n, m);
64
+ tcg_gen_add_i64(d, d, t);
65
+}
66
+
67
+static void gen_uaba_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m)
68
+{
69
+ TCGv_i64 t = tcg_temp_new_i64();
70
+ gen_uabd_i64(t, n, m);
71
+ tcg_gen_add_i64(d, d, t);
72
+}
73
+
74
+TRANS(SADDL_v, do_3op_widening,
75
+ a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, -1,
76
+ tcg_gen_add_i64, false)
77
+TRANS(UADDL_v, do_3op_widening,
78
+ a->esz, a->q, a->rd, a->rn, a->rm, -1,
79
+ tcg_gen_add_i64, false)
80
+TRANS(SSUBL_v, do_3op_widening,
81
+ a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, -1,
82
+ tcg_gen_sub_i64, false)
83
+TRANS(USUBL_v, do_3op_widening,
84
+ a->esz, a->q, a->rd, a->rn, a->rm, -1,
85
+ tcg_gen_sub_i64, false)
86
+TRANS(SABDL_v, do_3op_widening,
87
+ a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, -1,
88
+ gen_sabd_i64, false)
89
+TRANS(UABDL_v, do_3op_widening,
90
+ a->esz, a->q, a->rd, a->rn, a->rm, -1,
91
+ gen_uabd_i64, false)
92
+TRANS(SABAL_v, do_3op_widening,
93
+ a->esz | MO_SIGN, a->q, a->rd, a->rn, a->rm, -1,
94
+ gen_saba_i64, true)
95
+TRANS(UABAL_v, do_3op_widening,
96
+ a->esz, a->q, a->rd, a->rn, a->rm, -1,
97
+ gen_uaba_i64, true)
98
+
99
/*
100
* Advanced SIMD scalar/vector x indexed element
101
*/
102
@@ -XXX,XX +XXX,XX @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
103
}
43
}
104
44
} else if (is_qnan(a->cls)) {
105
switch (opcode) {
45
if (is_snan(b->cls) || !is_qnan(b->cls)) {
106
- case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
46
which = 0;
107
- tcg_gen_add_i64(tcg_passres, tcg_op1, tcg_op2);
47
- } else {
108
- break;
48
- which = cmp > 0 ? 0 : 1;
109
- case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
49
+ break;
110
- tcg_gen_sub_i64(tcg_passres, tcg_op1, tcg_op2);
111
- break;
112
- case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
113
- case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
114
- {
115
- TCGv_i64 tcg_tmp1 = tcg_temp_new_i64();
116
- TCGv_i64 tcg_tmp2 = tcg_temp_new_i64();
117
-
118
- tcg_gen_sub_i64(tcg_tmp1, tcg_op1, tcg_op2);
119
- tcg_gen_sub_i64(tcg_tmp2, tcg_op2, tcg_op1);
120
- tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE,
121
- tcg_passres,
122
- tcg_op1, tcg_op2, tcg_tmp1, tcg_tmp2);
123
- break;
124
- }
125
case 9: /* SQDMLAL, SQDMLAL2 */
126
case 11: /* SQDMLSL, SQDMLSL2 */
127
case 13: /* SQDMULL, SQDMULL2 */
128
@@ -XXX,XX +XXX,XX @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
129
case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
130
case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
131
case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
132
+ case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
133
+ case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
134
+ case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
135
+ case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
136
g_assert_not_reached();
137
}
50
}
138
51
} else {
139
- if (opcode == 9 || opcode == 11) {
52
which = 1;
140
+ if (accop != 0) {
53
+ break;
141
/* saturating accumulate ops */
142
if (accop < 0) {
143
tcg_gen_neg_i64(tcg_passres, tcg_passres);
144
}
145
gen_helper_neon_addl_saturate_s64(tcg_res[pass], tcg_env,
146
tcg_res[pass], tcg_passres);
147
- } else if (accop > 0) {
148
- tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
149
- } else if (accop < 0) {
150
- tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
151
}
152
}
54
}
153
} else {
55
+ cmp = frac_cmp(a, b);
154
@@ -XXX,XX +XXX,XX @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
56
+ if (cmp == 0) {
155
}
57
+ cmp = a->sign < b->sign;
156
58
+ }
157
switch (opcode) {
59
+ which = cmp > 0 ? 0 : 1;
158
- case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
159
- case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
160
- {
161
- TCGv_i64 tcg_op2_64 = tcg_temp_new_i64();
162
- static NeonGenWidenFn * const widenfns[2][2] = {
163
- { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 },
164
- { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 },
165
- };
166
- NeonGenWidenFn *widenfn = widenfns[size][is_u];
167
-
168
- widenfn(tcg_op2_64, tcg_op2);
169
- widenfn(tcg_passres, tcg_op1);
170
- gen_neon_addl(size, (opcode == 2), tcg_passres,
171
- tcg_passres, tcg_op2_64);
172
- break;
173
- }
174
- case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
175
- case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
176
- if (size == 0) {
177
- if (is_u) {
178
- gen_helper_neon_abdl_u16(tcg_passres, tcg_op1, tcg_op2);
179
- } else {
180
- gen_helper_neon_abdl_s16(tcg_passres, tcg_op1, tcg_op2);
181
- }
182
- } else {
183
- if (is_u) {
184
- gen_helper_neon_abdl_u32(tcg_passres, tcg_op1, tcg_op2);
185
- } else {
186
- gen_helper_neon_abdl_s32(tcg_passres, tcg_op1, tcg_op2);
187
- }
188
- }
189
- break;
190
case 9: /* SQDMLAL, SQDMLAL2 */
191
case 11: /* SQDMLSL, SQDMLSL2 */
192
case 13: /* SQDMULL, SQDMULL2 */
193
@@ -XXX,XX +XXX,XX @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
194
case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
195
case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
196
case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
197
+ case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
198
+ case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
199
+ case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
200
+ case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
201
g_assert_not_reached();
202
}
203
204
if (accop != 0) {
205
- if (opcode == 9 || opcode == 11) {
206
- /* saturating accumulate ops */
207
- if (accop < 0) {
208
- gen_helper_neon_negl_u32(tcg_passres, tcg_passres);
209
- }
210
- gen_helper_neon_addl_saturate_s32(tcg_res[pass], tcg_env,
211
- tcg_res[pass],
212
- tcg_passres);
213
- } else {
214
- gen_neon_addl(size, (accop < 0), tcg_res[pass],
215
- tcg_res[pass], tcg_passres);
216
+ /* saturating accumulate ops */
217
+ if (accop < 0) {
218
+ gen_helper_neon_negl_u32(tcg_passres, tcg_passres);
219
}
220
+ gen_helper_neon_addl_saturate_s32(tcg_res[pass], tcg_env,
221
+ tcg_res[pass],
222
+ tcg_passres);
223
}
224
}
225
}
226
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
227
unallocated_encoding(s);
228
return;
229
}
230
- /* fall through */
231
- case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
232
- case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
233
- case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
234
- case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
235
/* 64 x 64 -> 128 */
236
if (size == 3) {
237
unallocated_encoding(s);
238
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
239
handle_3rd_widening(s, is_q, is_u, size, opcode, rd, rn, rm);
240
break;
60
break;
241
default:
61
default:
242
+ case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
62
g_assert_not_reached();
243
+ case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
244
+ case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
245
+ case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
246
case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
247
case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
248
case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
249
--
63
--
250
2.34.1
64
2.34.1
diff view generated by jsdifflib
[PULL 10/24] hw/char/pl011: Avoid division-by-zero in pl011_get_baudrate()
[PULL 70/72] softfloat: Replace WHICH with RET in parts_pick_nan
1
From: Zheyu Ma <zheyuma97@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
In pl011_get_baudrate(), when we calculate the baudrate we can
3
Replace the "index" selecting between A and B with a result variable
4
accidentally divide by zero. This happens because although (as the
4
of the proper type. This improves clarity within the function.
5
specification requires) we treat UARTIBRD = 0 as invalid, we aren't
6
correctly limiting UARTIBRD and UARTFBRD values to the 16-bit and 6-bit
7
ranges the hardware allows, and so some non-zero values of UARTIBRD can
8
result in a zero divisor.
9
5
10
Enforce the correct register field widths on guest writes and on inbound
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
migration to avoid the division by zero.
12
13
ASAN log:
14
==2973125==ERROR: AddressSanitizer: FPE on unknown address 0x55f72629b348
15
(pc 0x55f72629b348 bp 0x7fffa24d0e00 sp 0x7fffa24d0d60 T0)
16
#0 0x55f72629b348 in pl011_get_baudrate hw/char/pl011.c:255:17
17
#1 0x55f726298d94 in pl011_trace_baudrate_change hw/char/pl011.c:260:33
18
#2 0x55f726296fc8 in pl011_write hw/char/pl011.c:378:9
19
20
Reproducer:
21
cat << EOF | qemu-system-aarch64 -display \
22
none -machine accel=qtest, -m 512M -machine realview-pb-a8 -qtest stdio
23
writeq 0x1000b024 0xf8000000
24
EOF
25
26
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Zheyu Ma <zheyuma97@gmail.com>
28
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
29
Message-id: 20240702155752.3022007-1-zheyuma97@gmail.com
8
Message-id: 20241203203949.483774-12-richard.henderson@linaro.org
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
---
10
---
32
hw/char/pl011.c | 13 +++++++++++--
11
fpu/softfloat-parts.c.inc | 28 +++++++++++++---------------
33
1 file changed, 11 insertions(+), 2 deletions(-)
12
1 file changed, 13 insertions(+), 15 deletions(-)
34
13
35
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
36
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/char/pl011.c
16
--- a/fpu/softfloat-parts.c.inc
38
+++ b/hw/char/pl011.c
17
+++ b/fpu/softfloat-parts.c.inc
39
@@ -XXX,XX +XXX,XX @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr)
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
40
#define CR_DTR (1 << 10)
19
float_status *s)
41
#define CR_LBE (1 << 7)
20
{
42
21
bool have_snan = false;
43
+/* Integer Baud Rate Divider, UARTIBRD */
22
- int cmp, which;
44
+#define IBRD_MASK 0x3f
23
+ FloatPartsN *ret;
45
+
24
+ int cmp;
46
+/* Fractional Baud Rate Divider, UARTFBRD */
25
47
+#define FBRD_MASK 0xffff
26
if (is_snan(a->cls) || is_snan(b->cls)) {
48
+
27
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
49
static const unsigned char pl011_id_arm[8] =
28
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
50
{ 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
29
switch (s->float_2nan_prop_rule) {
51
static const unsigned char pl011_id_luminary[8] =
30
case float_2nan_prop_s_ab:
52
@@ -XXX,XX +XXX,XX @@ static void pl011_write(void *opaque, hwaddr offset,
31
if (have_snan) {
53
s->ilpr = value;
32
- which = is_snan(a->cls) ? 0 : 1;
33
+ ret = is_snan(a->cls) ? a : b;
34
break;
35
}
36
/* fall through */
37
case float_2nan_prop_ab:
38
- which = is_nan(a->cls) ? 0 : 1;
39
+ ret = is_nan(a->cls) ? a : b;
54
break;
40
break;
55
case 9: /* UARTIBRD */
41
case float_2nan_prop_s_ba:
56
- s->ibrd = value;
42
if (have_snan) {
57
+ s->ibrd = value & IBRD_MASK;
43
- which = is_snan(b->cls) ? 1 : 0;
58
pl011_trace_baudrate_change(s);
44
+ ret = is_snan(b->cls) ? b : a;
45
break;
46
}
47
/* fall through */
48
case float_2nan_prop_ba:
49
- which = is_nan(b->cls) ? 1 : 0;
50
+ ret = is_nan(b->cls) ? b : a;
59
break;
51
break;
60
case 10: /* UARTFBRD */
52
case float_2nan_prop_x87:
61
- s->fbrd = value;
53
/*
62
+ s->fbrd = value & FBRD_MASK;
54
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
63
pl011_trace_baudrate_change(s);
55
*/
56
if (is_snan(a->cls)) {
57
if (!is_snan(b->cls)) {
58
- which = is_qnan(b->cls) ? 1 : 0;
59
+ ret = is_qnan(b->cls) ? b : a;
60
break;
61
}
62
} else if (is_qnan(a->cls)) {
63
if (is_snan(b->cls) || !is_qnan(b->cls)) {
64
- which = 0;
65
+ ret = a;
66
break;
67
}
68
} else {
69
- which = 1;
70
+ ret = b;
71
break;
72
}
73
cmp = frac_cmp(a, b);
74
if (cmp == 0) {
75
cmp = a->sign < b->sign;
76
}
77
- which = cmp > 0 ? 0 : 1;
78
+ ret = cmp > 0 ? a : b;
64
break;
79
break;
65
case 11: /* UARTLCR_H */
80
default:
66
@@ -XXX,XX +XXX,XX @@ static int pl011_post_load(void *opaque, int version_id)
81
g_assert_not_reached();
67
s->read_pos = 0;
68
}
82
}
69
83
70
+ s->ibrd &= IBRD_MASK;
84
- if (which) {
71
+ s->fbrd &= FBRD_MASK;
85
- a = b;
72
+
86
+ if (is_snan(ret->cls)) {
73
return 0;
87
+ parts_silence_nan(ret, s);
88
}
89
- if (is_snan(a->cls)) {
90
- parts_silence_nan(a, s);
91
- }
92
- return a;
93
+ return ret;
74
}
94
}
75
95
96
static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
76
--
97
--
77
2.34.1
98
2.34.1
78
99
79
100
diff view generated by jsdifflib
[PULL 15/24] accel/tcg: Make TCGCPUOps::cpu_exec_halt mandatory
[PULL 71/72] MAINTAINERS: update email address for Leif Lindholm
1
Now that all targets set TCGCPUOps::cpu_exec_halt, we can make it
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
2
mandatory and remove the fallback handling that calls cpu_has_work.
3
2
3
I'm migrating to Qualcomm's new open source email infrastructure, so
4
update my email address, and update the mailmap to match.
5
6
Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
7
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
8
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-id: 20241205114047.1125842-1-leif.lindholm@oss.qualcomm.com
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
---
13
---
7
include/hw/core/tcg-cpu-ops.h | 9 ++++++---
14
MAINTAINERS | 2 +-
8
accel/tcg/cpu-exec.c | 11 +++++------
15
.mailmap | 5 +++--
9
2 files changed, 11 insertions(+), 9 deletions(-)
16
2 files changed, 4 insertions(+), 3 deletions(-)
10
17
11
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
18
diff --git a/MAINTAINERS b/MAINTAINERS
12
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/core/tcg-cpu-ops.h
20
--- a/MAINTAINERS
14
+++ b/include/hw/core/tcg-cpu-ops.h
21
+++ b/MAINTAINERS
15
@@ -XXX,XX +XXX,XX @@ struct TCGCPUOps {
22
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
16
* to do when the CPU is in the halted state.
23
SBSA-REF
17
*
24
M: Radoslaw Biernacki <rad@semihalf.com>
18
* Return true to indicate that the CPU should now leave halt, false
25
M: Peter Maydell <peter.maydell@linaro.org>
19
- * if it should remain in the halted state.
26
-R: Leif Lindholm <quic_llindhol@quicinc.com>
20
+ * if it should remain in the halted state. (This should generally
27
+R: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
21
+ * be the same value that cpu_has_work() would return.)
28
R: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
22
*
29
L: qemu-arm@nongnu.org
23
- * If this method is not provided, the default is to do nothing, and
30
S: Maintained
24
- * to leave halt if cpu_has_work() returns true.
31
diff --git a/.mailmap b/.mailmap
25
+ * This method must be provided. If the target does not need to
26
+ * do anything special for halt, the same function used for its
27
+ * CPUClass::has_work method can be used here, as they have the
28
+ * same function signature.
29
*/
30
bool (*cpu_exec_halt)(CPUState *cpu);
31
/**
32
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
33
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
34
--- a/accel/tcg/cpu-exec.c
33
--- a/.mailmap
35
+++ b/accel/tcg/cpu-exec.c
34
+++ b/.mailmap
36
@@ -XXX,XX +XXX,XX @@ static inline bool cpu_handle_halt(CPUState *cpu)
35
@@ -XXX,XX +XXX,XX @@ Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
37
#ifndef CONFIG_USER_ONLY
36
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
38
if (cpu->halted) {
37
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
39
const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
38
Juan Quintela <quintela@trasno.org> <quintela@redhat.com>
40
- bool leave_halt;
39
-Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
41
+ bool leave_halt = tcg_ops->cpu_exec_halt(cpu);
40
-Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
42
41
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <quic_llindhol@quicinc.com>
43
- if (tcg_ops->cpu_exec_halt) {
42
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif.lindholm@linaro.org>
44
- leave_halt = tcg_ops->cpu_exec_halt(cpu);
43
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif@nuviainc.com>
45
- } else {
44
Luc Michel <luc@lmichel.fr> <luc.michel@git.antfield.fr>
46
- leave_halt = cpu_has_work(cpu);
45
Luc Michel <luc@lmichel.fr> <luc.michel@greensocs.com>
47
- }
46
Luc Michel <luc@lmichel.fr> <lmichel@kalray.eu>
48
if (!leave_halt) {
49
return true;
50
}
51
@@ -XXX,XX +XXX,XX @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp)
52
static bool tcg_target_initialized;
53
54
if (!tcg_target_initialized) {
55
+ /* Check mandatory TCGCPUOps handlers */
56
+#ifndef CONFIG_USER_ONLY
57
+ assert(cpu->cc->tcg_ops->cpu_exec_halt);
58
+#endif /* !CONFIG_USER_ONLY */
59
cpu->cc->tcg_ops->initialize();
60
tcg_target_initialized = true;
61
}
62
--
47
--
63
2.34.1
48
2.34.1
64
49
65
50
diff view generated by jsdifflib
[PULL 11/24] hw/misc/bcm2835_thermal: Fix access size handling in bcm2835_thermal_ops
[PULL 72/72] MAINTAINERS: Add correct email address for Vikram Garhwal
1
From: Zheyu Ma <zheyuma97@gmail.com>
1
From: Vikram Garhwal <vikram.garhwal@bytedance.com>
2
2
3
The current implementation of bcm2835_thermal_ops sets
3
Previously, maintainer role was paused due to inactive email id. Commit id:
4
impl.max_access_size and valid.min_access_size to 4, but leaves
4
c009d715721861984c4987bcc78b7ee183e86d75.
5
impl.min_access_size and valid.max_access_size unset, defaulting to 1.
6
This causes issues when the memory system is presented with an access
7
of size 2 at an offset of 3, leading to an attempt to synthesize it as
8
a pair of byte accesses at offsets 3 and 4, which trips an assert.
9
5
10
Additionally, the lack of valid.max_access_size setting causes another
6
Signed-off-by: Vikram Garhwal <vikram.garhwal@bytedance.com>
11
issue: the memory system tries to synthesize a read using a 4-byte
7
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
12
access at offset 3 even though the device doesn't allow unaligned
8
Message-id: 20241204184205.12952-1-vikram.garhwal@bytedance.com
13
accesses.
14
15
This patch addresses these issues by explicitly setting both
16
impl.min_access_size and valid.max_access_size to 4, ensuring proper
17
handling of access sizes.
18
19
Error log:
20
ERROR:hw/misc/bcm2835_thermal.c:55:bcm2835_thermal_read: code should not be reached
21
Bail out! ERROR:hw/misc/bcm2835_thermal.c:55:bcm2835_thermal_read: code should not be reached
22
Aborted
23
24
Reproducer:
25
cat << EOF | qemu-system-aarch64 -display \
26
none -machine accel=qtest, -m 512M -machine raspi3b -m 1G -qtest stdio
27
readw 0x3f212003
28
EOF
29
30
Signed-off-by: Zheyu Ma <zheyuma97@gmail.com>
31
Message-id: 20240702154042.3018932-1-zheyuma97@gmail.com
32
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
33
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
34
---
10
---
35
hw/misc/bcm2835_thermal.c | 2 ++
11
MAINTAINERS | 2 ++
36
1 file changed, 2 insertions(+)
12
1 file changed, 2 insertions(+)
37
13
38
diff --git a/hw/misc/bcm2835_thermal.c b/hw/misc/bcm2835_thermal.c
14
diff --git a/MAINTAINERS b/MAINTAINERS
39
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/misc/bcm2835_thermal.c
16
--- a/MAINTAINERS
41
+++ b/hw/misc/bcm2835_thermal.c
17
+++ b/MAINTAINERS
42
@@ -XXX,XX +XXX,XX @@ static void bcm2835_thermal_write(void *opaque, hwaddr addr,
18
@@ -XXX,XX +XXX,XX @@ F: tests/qtest/fuzz-sb16-test.c
43
static const MemoryRegionOps bcm2835_thermal_ops = {
19
44
.read = bcm2835_thermal_read,
20
Xilinx CAN
45
.write = bcm2835_thermal_write,
21
M: Francisco Iglesias <francisco.iglesias@amd.com>
46
+ .impl.min_access_size = 4,
22
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
47
.impl.max_access_size = 4,
23
S: Maintained
48
.valid.min_access_size = 4,
24
F: hw/net/can/xlnx-*
49
+ .valid.max_access_size = 4,
25
F: include/hw/net/xlnx-*
50
.endianness = DEVICE_NATIVE_ENDIAN,
26
@@ -XXX,XX +XXX,XX @@ F: include/hw/rx/
51
};
27
CAN bus subsystem and hardware
52
28
M: Pavel Pisa <pisa@cmp.felk.cvut.cz>
29
M: Francisco Iglesias <francisco.iglesias@amd.com>
30
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
31
S: Maintained
32
W: https://canbus.pages.fel.cvut.cz/
33
F: net/can/*
53
--
34
--
54
2.34.1
35
2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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