[v2] RISC-V: Add preliminary textra trigger CSR functions

[PATCH v2 0/2] RISC-V: Add preliminary textra trigger CSR functions

Alvin Chang via posted 2 patches 4 months, 2 weeks ago

Diff against v1 v4
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git fetch https://github.com/patchew-project/qemu tags/patchew/20240710100010.814934-1-alvinga@andestech.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

There is a newer version of this series

target/riscv/cpu_bits.h |  10 +++
target/riscv/debug.c    | 138 ++++++++++++++++++++++++++++++++++++++--
target/riscv/debug.h    |   3 +
3 files changed, 144 insertions(+), 7 deletions(-)

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[PATCH v2 0/2] RISC-V: Add preliminary textra trigger CSR functions

Posted by Alvin Chang via 4 months, 2 weeks ago

According to RISC-V Debug specification, the optional textra32 and textra64
trigger CSRs can be used to configure additional matching conditions for the
triggers.

This series support to write MHVALUE and MHSELECT fields into textra32 and
textra64 trigger CSRs. Besides, the additional matching condition between
textra.MHVALUE and mcontext CSR is also implemented.

Changes from v1:
- Log that mhselect only supports 0 or 4 for now
- Simplify writing of tdata3

Alvin Chang (2):
  target/riscv: Preliminary textra trigger CSR writting support
  target/riscv: Add textra matching condition for the triggers

 target/riscv/cpu_bits.h |  10 +++
 target/riscv/debug.c    | 138 ++++++++++++++++++++++++++++++++++++++--
 target/riscv/debug.h    |   3 +
 3 files changed, 144 insertions(+), 7 deletions(-)

-- 
2.34.1