[v1] target/arm: AdvSIMD decodetree conversion, part 3

[PATCH 0/6] target/arm: AdvSIMD decodetree conversion, part 3

Richard Henderson posted 6 patches 4 months, 2 weeks ago

Diff against v1
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20240708235936.382058-1-richard.henderson@linaro.org

Maintainers: Peter Maydell <peter.maydell@linaro.org>

There is a newer version of this series

target/arm/tcg/translate-a64.c | 1155 +++++++++++---------------------
target/arm/tcg/a64.decode      |   77 +++
2 files changed, 460 insertions(+), 772 deletions(-)

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[PATCH 0/6] target/arm: AdvSIMD decodetree conversion, part 3

Posted by Richard Henderson 4 months, 2 weeks ago

A small set, but better than waiting for a larger set.
It's a good stopping point, finishing the convertion of

  disas_simd_three_reg_diff
  disas_simd_scalar_three_reg_diff
  disas_simd_indexed


r~


Richard Henderson (6):
  target/arm: Convert SMULL, UMULL, SMLAL, UMLAL, SMLSL, UMLSL to
    decodetree
  target/arm: Convert SADDL, SSUBL, SABDL, SABAL, and unsigned to
    decodetree
  target/arm: Convert SQDMULL, SQDMLAL, SQDMLSL to decodetree
  target/arm: Convert SADDW, SSUBW, UADDW, USUBW to decodetree
  target/arm: Convert ADDHN, SUBHN, RADDHN, RSUBHN to decodetree
  target/arm: Convert PMULL to decodetree

 target/arm/tcg/translate-a64.c | 1155 +++++++++++---------------------
 target/arm/tcg/a64.decode      |   77 +++
 2 files changed, 460 insertions(+), 772 deletions(-)

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2.43.0