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[PATCH] intel-iommu: fix Read DMAR IQA REG DW

YeeLi posted 1 patch 1 year, 7 months ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20240704035302.306244-1-seven.yi.lee@gmail.com
Maintainers: "Michael S. Tsirkin" <mst@redhat.com>, Jason Wang <jasowang@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>, Richard Henderson <richard.henderson@linaro.org>, Eduardo Habkost <eduardo@habkost.net>, Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
hw/i386/intel_iommu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
[PATCH] intel-iommu: fix Read DMAR IQA REG DW
Posted by YeeLi 1 year, 7 months ago 
From: yeeli <seven.yi.lee@gmail.com>

When dmar_readq or devmem2 read the DW of IQA always 0UL because
"& VTD_IQA_QS". So, try to fix it.

case:
after vtd_mem_write
IQA val: 0x100206801

after vtd_mem_read
IQA val: 0x100206001

Signed-off-by: yeeli <seven.yi.lee@gmail.com>
---
 hw/i386/intel_iommu.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 37c21a0aec..e230a45940 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2938,7 +2938,8 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)
 
     /* Invalidation Queue Address Register, 64-bit */
     case DMAR_IQA_REG:
-        val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS);
+        val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS
+                | VTD_IQA_DW_MASK);
         if (size == 4) {
             val = val & ((1ULL << 32) - 1);
         }
-- 
2.34.1
Re: [PATCH] intel-iommu: fix Read DMAR IQA REG DW
Posted by Michael S. Tsirkin 1 year, 6 months ago 
On Thu, Jul 04, 2024 at 11:53:02AM +0800, YeeLi wrote:
> From: yeeli <seven.yi.lee@gmail.com>
> 
> When dmar_readq or devmem2 read the DW of IQA always 0UL because
> "& VTD_IQA_QS". So, try to fix it.
> 
> case:
> after vtd_mem_write
> IQA val: 0x100206801
> 
> after vtd_mem_read
> IQA val: 0x100206001
> 
> Signed-off-by: yeeli <seven.yi.lee@gmail.com>


how was this tested?

> ---
>  hw/i386/intel_iommu.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 37c21a0aec..e230a45940 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -2938,7 +2938,8 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)
>  
>      /* Invalidation Queue Address Register, 64-bit */
>      case DMAR_IQA_REG:
> -        val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS);
> +        val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS
> +                | VTD_IQA_DW_MASK);
>          if (size == 4) {
>              val = val & ((1ULL << 32) - 1);
>          }
> -- 
> 2.34.1
Re: [PATCH] intel-iommu: fix Read DMAR IQA REG DW
Posted by Yee Li 1 year, 7 months ago 
Sorry, the patch missing "((  ))"
Replace "& VTD_IQA_QS" with "& (VTD_IQA_QS | VTD_IQA_DW_MASK))" is correct.
Revised patch as follows,

Signed-off-by: yeeli <seven.yi.lee@gmail.com>
---
 hw/i386/intel_iommu.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 37c21a0aec..23562ba26b 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2938,7 +2938,8 @@ static uint64_t vtd_mem_read(void *opaque,
hwaddr addr, unsigned size)

     /* Invalidation Queue Address Register, 64-bit */
     case DMAR_IQA_REG:
-        val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS);
+        val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & (VTD_IQA_QS
+                    | VTD_IQA_DW_MASK));
         if (size == 4) {
             val = val & ((1ULL << 32) - 1);
         }
-- 
2.34.1

YeeLi <seven.yi.lee@gmail.com> 于2024年7月4日周四 11:53写道：
>
> From: yeeli <seven.yi.lee@gmail.com>
>
> When dmar_readq or devmem2 read the DW of IQA always 0UL because
> "& VTD_IQA_QS". So, try to fix it.
>
> case:
> after vtd_mem_write
> IQA val: 0x100206801
>
> after vtd_mem_read
> IQA val: 0x100206001
>
> Signed-off-by: yeeli <seven.yi.lee@gmail.com>
> ---
>  hw/i386/intel_iommu.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 37c21a0aec..e230a45940 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -2938,7 +2938,8 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)
>
>      /* Invalidation Queue Address Register, 64-bit */
>      case DMAR_IQA_REG:
> -        val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS);
> +        val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS
> +                | VTD_IQA_DW_MASK);
>          if (size == 4) {
>              val = val & ((1ULL << 32) - 1);
>          }
> --
> 2.34.1
>
Re: [PATCH] intel-iommu: fix Read DMAR IQA REG DW
Posted by Michael S. Tsirkin 1 year, 6 months ago 
On Thu, Jul 04, 2024 at 02:54:00PM +0800, Yee Li wrote:
> Sorry, the patch missing "((  ))"
> Replace "& VTD_IQA_QS" with "& (VTD_IQA_QS | VTD_IQA_DW_MASK))" is correct.
> Revised patch as follows,
> 

So submit it properly.
Also, how did you test the patch?

> Signed-off-by: yeeli <seven.yi.lee@gmail.com>




> ---
>  hw/i386/intel_iommu.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 37c21a0aec..23562ba26b 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -2938,7 +2938,8 @@ static uint64_t vtd_mem_read(void *opaque,
> hwaddr addr, unsigned size)
> 
>      /* Invalidation Queue Address Register, 64-bit */
>      case DMAR_IQA_REG:
> -        val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS);
> +        val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & (VTD_IQA_QS
> +                    | VTD_IQA_DW_MASK));


This is a very messy way to write this.
Align things properly pls.

>          if (size == 4) {
>              val = val & ((1ULL << 32) - 1);
>          }
> -- 
> 2.34.1
> 
> YeeLi <seven.yi.lee@gmail.com> 于2024年7月4日周四 11:53写道：
> >
> > From: yeeli <seven.yi.lee@gmail.com>
> >
> > When dmar_readq or devmem2 read the DW of IQA always 0UL because
> > "& VTD_IQA_QS". So, try to fix it.
> >
> > case:
> > after vtd_mem_write
> > IQA val: 0x100206801
> >
> > after vtd_mem_read
> > IQA val: 0x100206001
> >
> > Signed-off-by: yeeli <seven.yi.lee@gmail.com>
> > ---
> >  hw/i386/intel_iommu.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> > index 37c21a0aec..e230a45940 100644
> > --- a/hw/i386/intel_iommu.c
> > +++ b/hw/i386/intel_iommu.c
> > @@ -2938,7 +2938,8 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)
> >
> >      /* Invalidation Queue Address Register, 64-bit */
> >      case DMAR_IQA_REG:
> > -        val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS);
> > +        val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS
> > +                | VTD_IQA_DW_MASK);
> >          if (size == 4) {
> >              val = val & ((1ULL << 32) - 1);
> >          }
> > --
> > 2.34.1
> >

Patchew 2.1-devel-b67e4c2

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