[PULL 0/7] tcg patch queue
[PULL v2.5 00/27] tcg patch queue
1
The following changes since commit 6746482d12da3b6e4d3cdf06481a0027a797f719:
1
v2: Fix target/loongarch printf formats for vaddr
2
Include two more reviewed patches.
2
3
3
Merge tag 'sdmmc-20240702' of https://github.com/philmd/qemu into staging (2024-07-02 09:52:10 -0700)
4
This time with actual pull urls. :-/
5
6
r~
7
8
9
The following changes since commit db7aa99ef894e88fc5eedf02ca2579b8c344b2ec:
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11
Merge tag 'hw-misc-20250216' of https://github.com/philmd/qemu into staging (2025-02-16 20:48:06 -0500)
4
12
5
are available in the Git repository at:
13
are available in the Git repository at:
6
14
7
https://gitlab.com/rth7680/qemu tags/pull-tcg-20240703
15
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250215-2
8
16
9
for you to fetch changes up to a71d9dfbf63db42d6e6ae87fc112d1f5502183bd:
17
for you to fetch changes up to a39bdd0f4ba96fcbb6b5bcb6e89591d2b24f52eb:
10
18
11
tcg/optimize: Fix TCG_COND_TST* simplification of setcond2 (2024-07-03 10:24:12 -0700)
19
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 (2025-02-17 09:52:07 -0800)
12
20
13
----------------------------------------------------------------
21
----------------------------------------------------------------
14
util: cpuinfo portability fixes for FreeBSD and OpenBSD
22
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
15
util: cpuinfo for riscv host
23
tcg: Cleanups after disallowing 64-on-32
16
tcg/optimize: Fix TCG_COND_TST* simplification of setcond2
24
tcg: Introduce constraint for zero register
25
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
26
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
27
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
28
linux-user: Fix alignment when unmapping excess reservation
29
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
30
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
31
target/sparc: fake UltraSPARC T1 PCR and PIC registers
17
32
18
----------------------------------------------------------------
33
----------------------------------------------------------------
19
Brad Smith (3):
34
Andreas Schwab (1):
20
util/cpuinfo-ppc: Fix building on OpenBSD
35
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
21
util/cpuinfo-ppc: Add FreeBSD support
22
util/cpuinfo-aarch64: Add OpenBSD support
23
36
24
Richard Henderson (4):
37
Artyom Tarasenko (1):
25
util/cpuinfo-riscv: Support host/cpuinfo.h for riscv
38
target/sparc: fake UltraSPARC T1 PCR and PIC registers
26
util/cpuinfo-riscv: Support OpenBSD signal frame
27
util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall
28
tcg/optimize: Fix TCG_COND_TST* simplification of setcond2
29
39
30
meson.build | 6 ++
40
Fabiano Rosas (1):
31
host/include/riscv/host/cpuinfo.h | 23 ++++++++
41
elfload: Fix alignment when unmapping excess reservation
32
tcg/riscv/tcg-target.h | 46 +++++++--------
42
33
tcg/optimize.c | 2 +-
43
Mikael Szreder (2):
34
tests/tcg/x86_64/test-2413.c | 30 ++++++++++
44
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
35
util/cpuinfo-aarch64.c | 36 ++++++++++++
45
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
36
util/cpuinfo-ppc.c | 27 ++++++---
46
37
util/cpuinfo-riscv.c | 118 ++++++++++++++++++++++++++++++++++++++
47
Richard Henderson (22):
38
tcg/riscv/tcg-target.c.inc | 84 +++------------------------
48
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
39
tests/tcg/x86_64/Makefile.target | 2 +
49
tcg: Remove TCG_OVERSIZED_GUEST
40
util/meson.build | 2 +
50
tcg: Drop support for two address registers in gen_ldst
41
11 files changed, 266 insertions(+), 110 deletions(-)
51
tcg: Merge INDEX_op_qemu_*_{a32,a64}_*
42
create mode 100644 host/include/riscv/host/cpuinfo.h
52
tcg/arm: Drop addrhi from prepare_host_addr
43
create mode 100644 tests/tcg/x86_64/test-2413.c
53
tcg/i386: Drop addrhi from prepare_host_addr
44
create mode 100644 util/cpuinfo-riscv.c
54
tcg/mips: Drop addrhi from prepare_host_addr
55
tcg/ppc: Drop addrhi from prepare_host_addr
56
tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst
57
plugins: Fix qemu_plugin_read_memory_vaddr parameters
58
accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
59
target/loongarch: Use VADDR_PRIx for logging pc_next
60
include/exec: Change vaddr to uintptr_t
61
include/exec: Use uintptr_t in CPUTLBEntry
62
tcg: Introduce the 'z' constraint for a hardware zero register
63
tcg/aarch64: Use 'z' constraint
64
tcg/loongarch64: Use 'z' constraint
65
tcg/mips: Use 'z' constraint
66
tcg/riscv: Use 'z' constraint
67
tcg/sparc64: Use 'z' constraint
68
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
69
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
70
71
include/exec/tlb-common.h | 10 +-
72
include/exec/vaddr.h | 16 +-
73
include/qemu/atomic.h | 18 +-
74
include/tcg/oversized-guest.h | 23 ---
75
include/tcg/tcg-opc.h | 28 +--
76
include/tcg/tcg.h | 3 +-
77
linux-user/aarch64/target_signal.h | 2 +
78
linux-user/arm/target_signal.h | 2 +
79
linux-user/generic/signal.h | 1 -
80
linux-user/i386/target_signal.h | 2 +
81
linux-user/m68k/target_signal.h | 1 +
82
linux-user/microblaze/target_signal.h | 2 +
83
linux-user/ppc/target_signal.h | 2 +
84
linux-user/s390x/target_signal.h | 2 +
85
linux-user/sh4/target_signal.h | 2 +
86
linux-user/x86_64/target_signal.h | 2 +
87
linux-user/xtensa/target_signal.h | 2 +
88
tcg/aarch64/tcg-target-con-set.h | 12 +-
89
tcg/aarch64/tcg-target.h | 2 +
90
tcg/loongarch64/tcg-target-con-set.h | 15 +-
91
tcg/loongarch64/tcg-target-con-str.h | 1 -
92
tcg/loongarch64/tcg-target-has.h | 2 -
93
tcg/loongarch64/tcg-target.h | 2 +
94
tcg/mips/tcg-target-con-set.h | 26 +--
95
tcg/mips/tcg-target-con-str.h | 1 -
96
tcg/mips/tcg-target.h | 2 +
97
tcg/riscv/tcg-target-con-set.h | 10 +-
98
tcg/riscv/tcg-target-con-str.h | 1 -
99
tcg/riscv/tcg-target-has.h | 2 -
100
tcg/riscv/tcg-target.h | 2 +
101
tcg/sparc64/tcg-target-con-set.h | 12 +-
102
tcg/sparc64/tcg-target-con-str.h | 1 -
103
tcg/sparc64/tcg-target.h | 3 +-
104
tcg/tci/tcg-target.h | 1 -
105
accel/tcg/cputlb.c | 32 +---
106
accel/tcg/tcg-all.c | 9 +-
107
linux-user/elfload.c | 4 +-
108
plugins/api.c | 2 +-
109
target/arm/ptw.c | 34 ----
110
target/loongarch/tcg/translate.c | 2 +-
111
target/riscv/cpu_helper.c | 13 +-
112
target/sparc/gdbstub.c | 18 +-
113
target/sparc/translate.c | 19 +++
114
tcg/optimize.c | 21 +--
115
tcg/tcg-op-ldst.c | 103 +++--------
116
tcg/tcg.c | 97 +++++------
117
tcg/tci.c | 119 +++----------
118
docs/devel/multi-thread-tcg.rst | 1 -
119
docs/devel/tcg-ops.rst | 4 +-
120
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
121
target/sparc/insns.decode | 19 ++-
122
tcg/aarch64/tcg-target.c.inc | 86 ++++------
123
tcg/arm/tcg-target.c.inc | 114 ++++---------
124
tcg/i386/tcg-target.c.inc | 190 +++++----------------
125
tcg/loongarch64/tcg-target.c.inc | 72 +++-----
126
tcg/mips/tcg-target.c.inc | 169 ++++++------------
127
tcg/ppc/tcg-target.c.inc | 164 +++++-------------
128
tcg/riscv/tcg-target.c.inc | 56 +++---
129
tcg/s390x/tcg-target.c.inc | 40 ++---
130
tcg/sparc64/tcg-target.c.inc | 45 ++---
131
tcg/tci/tcg-target.c.inc | 60 ++-----
132
61 files changed, 548 insertions(+), 1160 deletions(-)
133
delete mode 100644 include/tcg/oversized-guest.h
diff view generated by jsdifflib
[PULL 1/7] util/cpuinfo-ppc: Fix building on OpenBSD
Deleted patch
1
From: Brad Smith <brad@comstyle.com>
2
1
3
OpenBSD does not support AT_HWCAP.
4
5
Signed-off-by: Brad Smith <brad@comstyle.com>
6
Message-Id: <ZnzM1T6Vo1Q0yAH-@humpty.home.comstyle.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
util/cpuinfo-ppc.c | 20 ++++++++++++--------
10
1 file changed, 12 insertions(+), 8 deletions(-)
11
12
diff --git a/util/cpuinfo-ppc.c b/util/cpuinfo-ppc.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/util/cpuinfo-ppc.c
15
+++ b/util/cpuinfo-ppc.c
16
@@ -XXX,XX +XXX,XX @@
17
#include "qemu/osdep.h"
18
#include "host/cpuinfo.h"
19
20
-#include <asm/cputable.h>
21
-#ifdef CONFIG_GETAUXVAL
22
-# include <sys/auxv.h>
23
-#else
24
-# include "elf.h"
25
+#ifdef CONFIG_LINUX
26
+# include <asm/cputable.h>
27
+# ifdef CONFIG_GETAUXVAL
28
+# include <sys/auxv.h>
29
+# else
30
+# include "elf.h"
31
+# endif
32
#endif
33
34
unsigned cpuinfo;
35
@@ -XXX,XX +XXX,XX @@ unsigned cpuinfo;
36
unsigned __attribute__((constructor)) cpuinfo_init(void)
37
{
38
unsigned info = cpuinfo;
39
- unsigned long hwcap, hwcap2;
40
41
if (info) {
42
return info;
43
}
44
45
- hwcap = qemu_getauxval(AT_HWCAP);
46
- hwcap2 = qemu_getauxval(AT_HWCAP2);
47
info = CPUINFO_ALWAYS;
48
49
+#ifdef CONFIG_LINUX
50
+ unsigned long hwcap = qemu_getauxval(AT_HWCAP);
51
+ unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2);
52
+
53
/* Version numbers are monotonic, and so imply all lower versions. */
54
if (hwcap2 & PPC_FEATURE2_ARCH_3_1) {
55
info |= CPUINFO_V3_1 | CPUINFO_V3_0 | CPUINFO_V2_07 | CPUINFO_V2_06;
56
@@ -XXX,XX +XXX,XX @@ unsigned __attribute__((constructor)) cpuinfo_init(void)
57
}
58
}
59
}
60
+#endif
61
62
cpuinfo = info;
63
return info;
64
--
65
2.34.1
diff view generated by jsdifflib
[PULL 2/7] util/cpuinfo-ppc: Add FreeBSD support
Deleted patch
1
From: Brad Smith <brad@comstyle.com>
2
1
3
Signed-off-by: Brad Smith <brad@comstyle.com>
4
Message-Id: <Zn9cJ3puWr5lIgsg@humpty.home.comstyle.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
util/cpuinfo-ppc.c | 9 ++++++++-
8
1 file changed, 8 insertions(+), 1 deletion(-)
9
10
diff --git a/util/cpuinfo-ppc.c b/util/cpuinfo-ppc.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/util/cpuinfo-ppc.c
13
+++ b/util/cpuinfo-ppc.c
14
@@ -XXX,XX +XXX,XX @@
15
# include "elf.h"
16
# endif
17
#endif
18
+#ifdef __FreeBSD__
19
+# include <machine/cpu.h>
20
+# ifndef PPC_FEATURE2_ARCH_3_1
21
+# define PPC_FEATURE2_ARCH_3_1 0
22
+# endif
23
+# define PPC_FEATURE2_VEC_CRYPTO PPC_FEATURE2_HAS_VEC_CRYPTO
24
+#endif
25
26
unsigned cpuinfo;
27
28
@@ -XXX,XX +XXX,XX @@ unsigned __attribute__((constructor)) cpuinfo_init(void)
29
30
info = CPUINFO_ALWAYS;
31
32
-#ifdef CONFIG_LINUX
33
+#if defined(CONFIG_LINUX) || defined(__FreeBSD__)
34
unsigned long hwcap = qemu_getauxval(AT_HWCAP);
35
unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2);
36
37
--
38
2.34.1
diff view generated by jsdifflib
[PULL 3/7] util/cpuinfo-aarch64: Add OpenBSD support
Deleted patch
1
From: Brad Smith <brad@comstyle.com>
2
1
3
Signed-off-by: Brad Smith <brad@comstyle.com>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-Id: <ZneEh51XKhxgZKpp@humpty.home.comstyle.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
util/cpuinfo-aarch64.c | 36 ++++++++++++++++++++++++++++++++++++
9
1 file changed, 36 insertions(+)
10
11
diff --git a/util/cpuinfo-aarch64.c b/util/cpuinfo-aarch64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/util/cpuinfo-aarch64.c
14
+++ b/util/cpuinfo-aarch64.c
15
@@ -XXX,XX +XXX,XX @@
16
#ifdef CONFIG_DARWIN
17
# include <sys/sysctl.h>
18
#endif
19
+#ifdef __OpenBSD__
20
+# include <machine/armreg.h>
21
+# include <machine/cpu.h>
22
+# include <sys/types.h>
23
+# include <sys/sysctl.h>
24
+#endif
25
26
unsigned cpuinfo;
27
28
@@ -XXX,XX +XXX,XX @@ unsigned __attribute__((constructor)) cpuinfo_init(void)
29
info |= sysctl_for_bool("hw.optional.arm.FEAT_PMULL") * CPUINFO_PMULL;
30
info |= sysctl_for_bool("hw.optional.arm.FEAT_BTI") * CPUINFO_BTI;
31
#endif
32
+#ifdef __OpenBSD__
33
+ int mib[2];
34
+ uint64_t isar0;
35
+ uint64_t pfr1;
36
+ size_t len;
37
+
38
+ mib[0] = CTL_MACHDEP;
39
+ mib[1] = CPU_ID_AA64ISAR0;
40
+ len = sizeof(isar0);
41
+ if (sysctl(mib, 2, &isar0, &len, NULL, 0) != -1) {
42
+ if (ID_AA64ISAR0_ATOMIC(isar0) >= ID_AA64ISAR0_ATOMIC_IMPL) {
43
+ info |= CPUINFO_LSE;
44
+ }
45
+ if (ID_AA64ISAR0_AES(isar0) >= ID_AA64ISAR0_AES_BASE) {
46
+ info |= CPUINFO_AES;
47
+ }
48
+ if (ID_AA64ISAR0_AES(isar0) >= ID_AA64ISAR0_AES_PMULL) {
49
+ info |= CPUINFO_PMULL;
50
+ }
51
+ }
52
+
53
+ mib[0] = CTL_MACHDEP;
54
+ mib[1] = CPU_ID_AA64PFR1;
55
+ len = sizeof(pfr1);
56
+ if (sysctl(mib, 2, &pfr1, &len, NULL, 0) != -1) {
57
+ if (ID_AA64PFR1_BT(pfr1) >= ID_AA64PFR1_BT_IMPL) {
58
+ info |= CPUINFO_BTI;
59
+ }
60
+ }
61
+#endif
62
63
cpuinfo = info;
64
return info;
65
--
66
2.34.1
diff view generated by jsdifflib
[PULL 4/7] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv
Deleted patch
1
Move detection code out of tcg, similar to other hosts.
2
1
3
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
host/include/riscv/host/cpuinfo.h | 23 +++++++++
10
tcg/riscv/tcg-target.h | 46 ++++++++---------
11
util/cpuinfo-riscv.c | 85 +++++++++++++++++++++++++++++++
12
tcg/riscv/tcg-target.c.inc | 84 +++---------------------------
13
util/meson.build | 2 +
14
5 files changed, 139 insertions(+), 101 deletions(-)
15
create mode 100644 host/include/riscv/host/cpuinfo.h
16
create mode 100644 util/cpuinfo-riscv.c
17
18
diff --git a/host/include/riscv/host/cpuinfo.h b/host/include/riscv/host/cpuinfo.h
19
new file mode 100644
20
index XXXXXXX..XXXXXXX
21
--- /dev/null
22
+++ b/host/include/riscv/host/cpuinfo.h
23
@@ -XXX,XX +XXX,XX @@
24
+/*
25
+ * SPDX-License-Identifier: GPL-2.0-or-later
26
+ * Host specific cpu identification for RISC-V.
27
+ */
28
+
29
+#ifndef HOST_CPUINFO_H
30
+#define HOST_CPUINFO_H
31
+
32
+#define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */
33
+#define CPUINFO_ZBA (1u << 1)
34
+#define CPUINFO_ZBB (1u << 2)
35
+#define CPUINFO_ZICOND (1u << 3)
36
+
37
+/* Initialized with a constructor. */
38
+extern unsigned cpuinfo;
39
+
40
+/*
41
+ * We cannot rely on constructor ordering, so other constructors must
42
+ * use the function interface rather than the variable above.
43
+ */
44
+unsigned cpuinfo_init(void);
45
+
46
+#endif /* HOST_CPUINFO_H */
47
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
48
index XXXXXXX..XXXXXXX 100644
49
--- a/tcg/riscv/tcg-target.h
50
+++ b/tcg/riscv/tcg-target.h
51
@@ -XXX,XX +XXX,XX @@
52
#ifndef RISCV_TCG_TARGET_H
53
#define RISCV_TCG_TARGET_H
54
55
+#include "host/cpuinfo.h"
56
+
57
#define TCG_TARGET_INSN_UNIT_SIZE 4
58
#define TCG_TARGET_NB_REGS 32
59
#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
60
@@ -XXX,XX +XXX,XX @@ typedef enum {
61
#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL
62
#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
63
64
-#if defined(__riscv_arch_test) && defined(__riscv_zbb)
65
-# define have_zbb true
66
-#else
67
-extern bool have_zbb;
68
-#endif
69
-
70
/* optional instructions */
71
#define TCG_TARGET_HAS_negsetcond_i32 1
72
#define TCG_TARGET_HAS_div_i32 1
73
#define TCG_TARGET_HAS_rem_i32 1
74
#define TCG_TARGET_HAS_div2_i32 0
75
-#define TCG_TARGET_HAS_rot_i32 have_zbb
76
+#define TCG_TARGET_HAS_rot_i32 (cpuinfo & CPUINFO_ZBB)
77
#define TCG_TARGET_HAS_deposit_i32 0
78
#define TCG_TARGET_HAS_extract_i32 0
79
#define TCG_TARGET_HAS_sextract_i32 0
80
@@ -XXX,XX +XXX,XX @@ extern bool have_zbb;
81
#define TCG_TARGET_HAS_ext16s_i32 1
82
#define TCG_TARGET_HAS_ext8u_i32 1
83
#define TCG_TARGET_HAS_ext16u_i32 1
84
-#define TCG_TARGET_HAS_bswap16_i32 have_zbb
85
-#define TCG_TARGET_HAS_bswap32_i32 have_zbb
86
+#define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB)
87
+#define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB)
88
#define TCG_TARGET_HAS_not_i32 1
89
-#define TCG_TARGET_HAS_andc_i32 have_zbb
90
-#define TCG_TARGET_HAS_orc_i32 have_zbb
91
-#define TCG_TARGET_HAS_eqv_i32 have_zbb
92
+#define TCG_TARGET_HAS_andc_i32 (cpuinfo & CPUINFO_ZBB)
93
+#define TCG_TARGET_HAS_orc_i32 (cpuinfo & CPUINFO_ZBB)
94
+#define TCG_TARGET_HAS_eqv_i32 (cpuinfo & CPUINFO_ZBB)
95
#define TCG_TARGET_HAS_nand_i32 0
96
#define TCG_TARGET_HAS_nor_i32 0
97
-#define TCG_TARGET_HAS_clz_i32 have_zbb
98
-#define TCG_TARGET_HAS_ctz_i32 have_zbb
99
-#define TCG_TARGET_HAS_ctpop_i32 have_zbb
100
+#define TCG_TARGET_HAS_clz_i32 (cpuinfo & CPUINFO_ZBB)
101
+#define TCG_TARGET_HAS_ctz_i32 (cpuinfo & CPUINFO_ZBB)
102
+#define TCG_TARGET_HAS_ctpop_i32 (cpuinfo & CPUINFO_ZBB)
103
#define TCG_TARGET_HAS_brcond2 1
104
#define TCG_TARGET_HAS_setcond2 1
105
#define TCG_TARGET_HAS_qemu_st8_i32 0
106
@@ -XXX,XX +XXX,XX @@ extern bool have_zbb;
107
#define TCG_TARGET_HAS_div_i64 1
108
#define TCG_TARGET_HAS_rem_i64 1
109
#define TCG_TARGET_HAS_div2_i64 0
110
-#define TCG_TARGET_HAS_rot_i64 have_zbb
111
+#define TCG_TARGET_HAS_rot_i64 (cpuinfo & CPUINFO_ZBB)
112
#define TCG_TARGET_HAS_deposit_i64 0
113
#define TCG_TARGET_HAS_extract_i64 0
114
#define TCG_TARGET_HAS_sextract_i64 0
115
@@ -XXX,XX +XXX,XX @@ extern bool have_zbb;
116
#define TCG_TARGET_HAS_ext8u_i64 1
117
#define TCG_TARGET_HAS_ext16u_i64 1
118
#define TCG_TARGET_HAS_ext32u_i64 1
119
-#define TCG_TARGET_HAS_bswap16_i64 have_zbb
120
-#define TCG_TARGET_HAS_bswap32_i64 have_zbb
121
-#define TCG_TARGET_HAS_bswap64_i64 have_zbb
122
+#define TCG_TARGET_HAS_bswap16_i64 (cpuinfo & CPUINFO_ZBB)
123
+#define TCG_TARGET_HAS_bswap32_i64 (cpuinfo & CPUINFO_ZBB)
124
+#define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB)
125
#define TCG_TARGET_HAS_not_i64 1
126
-#define TCG_TARGET_HAS_andc_i64 have_zbb
127
-#define TCG_TARGET_HAS_orc_i64 have_zbb
128
-#define TCG_TARGET_HAS_eqv_i64 have_zbb
129
+#define TCG_TARGET_HAS_andc_i64 (cpuinfo & CPUINFO_ZBB)
130
+#define TCG_TARGET_HAS_orc_i64 (cpuinfo & CPUINFO_ZBB)
131
+#define TCG_TARGET_HAS_eqv_i64 (cpuinfo & CPUINFO_ZBB)
132
#define TCG_TARGET_HAS_nand_i64 0
133
#define TCG_TARGET_HAS_nor_i64 0
134
-#define TCG_TARGET_HAS_clz_i64 have_zbb
135
-#define TCG_TARGET_HAS_ctz_i64 have_zbb
136
-#define TCG_TARGET_HAS_ctpop_i64 have_zbb
137
+#define TCG_TARGET_HAS_clz_i64 (cpuinfo & CPUINFO_ZBB)
138
+#define TCG_TARGET_HAS_ctz_i64 (cpuinfo & CPUINFO_ZBB)
139
+#define TCG_TARGET_HAS_ctpop_i64 (cpuinfo & CPUINFO_ZBB)
140
#define TCG_TARGET_HAS_add2_i64 1
141
#define TCG_TARGET_HAS_sub2_i64 1
142
#define TCG_TARGET_HAS_mulu2_i64 0
143
diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c
144
new file mode 100644
145
index XXXXXXX..XXXXXXX
146
--- /dev/null
147
+++ b/util/cpuinfo-riscv.c
148
@@ -XXX,XX +XXX,XX @@
149
+/*
150
+ * SPDX-License-Identifier: GPL-2.0-or-later
151
+ * Host specific cpu identification for RISC-V.
152
+ */
153
+
154
+#include "qemu/osdep.h"
155
+#include "host/cpuinfo.h"
156
+
157
+unsigned cpuinfo;
158
+static volatile sig_atomic_t got_sigill;
159
+
160
+static void sigill_handler(int signo, siginfo_t *si, void *data)
161
+{
162
+ /* Skip the faulty instruction */
163
+ ucontext_t *uc = (ucontext_t *)data;
164
+ uc->uc_mcontext.__gregs[REG_PC] += 4;
165
+
166
+ got_sigill = 1;
167
+}
168
+
169
+/* Called both as constructor and (possibly) via other constructors. */
170
+unsigned __attribute__((constructor)) cpuinfo_init(void)
171
+{
172
+ unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND;
173
+ unsigned info = cpuinfo;
174
+
175
+ if (info) {
176
+ return info;
177
+ }
178
+
179
+ /* Test for compile-time settings. */
180
+#if defined(__riscv_arch_test) && defined(__riscv_zba)
181
+ info |= CPUINFO_ZBA;
182
+#endif
183
+#if defined(__riscv_arch_test) && defined(__riscv_zbb)
184
+ info |= CPUINFO_ZBB;
185
+#endif
186
+#if defined(__riscv_arch_test) && defined(__riscv_zicond)
187
+ info |= CPUINFO_ZICOND;
188
+#endif
189
+ left &= ~info;
190
+
191
+ if (left) {
192
+ struct sigaction sa_old, sa_new;
193
+
194
+ memset(&sa_new, 0, sizeof(sa_new));
195
+ sa_new.sa_flags = SA_SIGINFO;
196
+ sa_new.sa_sigaction = sigill_handler;
197
+ sigaction(SIGILL, &sa_new, &sa_old);
198
+
199
+ if (left & CPUINFO_ZBA) {
200
+ /* Probe for Zba: add.uw zero,zero,zero. */
201
+ got_sigill = 0;
202
+ asm volatile(".insn r 0x3b, 0, 0x04, zero, zero, zero"
203
+ : : : "memory");
204
+ info |= got_sigill ? 0 : CPUINFO_ZBA;
205
+ left &= ~CPUINFO_ZBA;
206
+ }
207
+
208
+ if (left & CPUINFO_ZBB) {
209
+ /* Probe for Zbb: andn zero,zero,zero. */
210
+ got_sigill = 0;
211
+ asm volatile(".insn r 0x33, 7, 0x20, zero, zero, zero"
212
+ : : : "memory");
213
+ info |= got_sigill ? 0 : CPUINFO_ZBB;
214
+ left &= ~CPUINFO_ZBB;
215
+ }
216
+
217
+ if (left & CPUINFO_ZICOND) {
218
+ /* Probe for Zicond: czero.eqz zero,zero,zero. */
219
+ got_sigill = 0;
220
+ asm volatile(".insn r 0x33, 5, 0x07, zero, zero, zero"
221
+ : : : "memory");
222
+ info |= got_sigill ? 0 : CPUINFO_ZICOND;
223
+ left &= ~CPUINFO_ZICOND;
224
+ }
225
+
226
+ sigaction(SIGILL, &sa_old, NULL);
227
+ assert(left == 0);
228
+ }
229
+
230
+ info |= CPUINFO_ALWAYS;
231
+ cpuinfo = info;
232
+ return info;
233
+}
234
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
235
index XXXXXXX..XXXXXXX 100644
236
--- a/tcg/riscv/tcg-target.c.inc
237
+++ b/tcg/riscv/tcg-target.c.inc
238
@@ -XXX,XX +XXX,XX @@ static const int tcg_target_call_iarg_regs[] = {
239
TCG_REG_A7,
240
};
241
242
-#ifndef have_zbb
243
-bool have_zbb;
244
-#endif
245
-#if defined(__riscv_arch_test) && defined(__riscv_zba)
246
-# define have_zba true
247
-#else
248
-static bool have_zba;
249
-#endif
250
-#if defined(__riscv_arch_test) && defined(__riscv_zicond)
251
-# define have_zicond true
252
-#else
253
-static bool have_zicond;
254
-#endif
255
-
256
static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
257
{
258
tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
259
@@ -XXX,XX +XXX,XX @@ static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg)
260
261
static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
262
{
263
- if (have_zbb) {
264
+ if (cpuinfo & CPUINFO_ZBB) {
265
tcg_out_opc_reg(s, OPC_ZEXT_H, ret, arg, TCG_REG_ZERO);
266
} else {
267
tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
268
@@ -XXX,XX +XXX,XX @@ static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
269
270
static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
271
{
272
- if (have_zba) {
273
+ if (cpuinfo & CPUINFO_ZBA) {
274
tcg_out_opc_reg(s, OPC_ADD_UW, ret, arg, TCG_REG_ZERO);
275
} else {
276
tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
277
@@ -XXX,XX +XXX,XX @@ static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
278
279
static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
280
{
281
- if (have_zbb) {
282
+ if (cpuinfo & CPUINFO_ZBB) {
283
tcg_out_opc_imm(s, OPC_SEXT_B, ret, arg, 0);
284
} else {
285
tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24);
286
@@ -XXX,XX +XXX,XX @@ static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
287
288
static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
289
{
290
- if (have_zbb) {
291
+ if (cpuinfo & CPUINFO_ZBB) {
292
tcg_out_opc_imm(s, OPC_SEXT_H, ret, arg, 0);
293
} else {
294
tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
295
@@ -XXX,XX +XXX,XX @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
296
int tmpflags;
297
TCGReg t;
298
299
- if (!have_zicond && (!c_cmp2 || cmp2 == 0)) {
300
+ if (!(cpuinfo & CPUINFO_ZICOND) && (!c_cmp2 || cmp2 == 0)) {
301
tcg_out_movcond_br2(s, cond, ret, cmp1, cmp2,
302
val1, c_val1, val2, c_val2);
303
return;
304
@@ -XXX,XX +XXX,XX @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
305
tmpflags = tcg_out_setcond_int(s, cond, TCG_REG_TMP0, cmp1, cmp2, c_cmp2);
306
t = tmpflags & ~SETCOND_FLAGS;
307
308
- if (have_zicond) {
309
+ if (cpuinfo & CPUINFO_ZICOND) {
310
if (tmpflags & SETCOND_INV) {
311
tcg_out_movcond_zicond(s, ret, t, val2, c_val2, val1, c_val1);
312
} else {
313
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
314
/* TLB Hit - translate address using addend. */
315
if (addr_type != TCG_TYPE_I32) {
316
tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2);
317
- } else if (have_zba) {
318
+ } else if (cpuinfo & CPUINFO_ZBA) {
319
tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0,
320
addr_reg, TCG_REG_TMP2);
321
} else {
322
@@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
323
if (addr_type != TCG_TYPE_I32) {
324
tcg_out_opc_reg(s, OPC_ADD, base, addr_reg,
325
TCG_GUEST_BASE_REG);
326
- } else if (have_zba) {
327
+ } else if (cpuinfo & CPUINFO_ZBA) {
328
tcg_out_opc_reg(s, OPC_ADD_UW, base, addr_reg,
329
TCG_GUEST_BASE_REG);
330
} else {
331
@@ -XXX,XX +XXX,XX @@ static void tcg_out_tb_start(TCGContext *s)
332
/* nothing to do */
333
}
334
335
-static volatile sig_atomic_t got_sigill;
336
-
337
-static void sigill_handler(int signo, siginfo_t *si, void *data)
338
-{
339
- /* Skip the faulty instruction */
340
- ucontext_t *uc = (ucontext_t *)data;
341
- uc->uc_mcontext.__gregs[REG_PC] += 4;
342
-
343
- got_sigill = 1;
344
-}
345
-
346
-static void tcg_target_detect_isa(void)
347
-{
348
-#if !defined(have_zba) || !defined(have_zbb) || !defined(have_zicond)
349
- /*
350
- * TODO: It is expected that this will be determinable via
351
- * linux riscv_hwprobe syscall, not yet merged.
352
- * In the meantime, test via sigill.
353
- */
354
-
355
- struct sigaction sa_old, sa_new;
356
-
357
- memset(&sa_new, 0, sizeof(sa_new));
358
- sa_new.sa_flags = SA_SIGINFO;
359
- sa_new.sa_sigaction = sigill_handler;
360
- sigaction(SIGILL, &sa_new, &sa_old);
361
-
362
-#ifndef have_zba
363
- /* Probe for Zba: add.uw zero,zero,zero. */
364
- got_sigill = 0;
365
- asm volatile(".insn r 0x3b, 0, 0x04, zero, zero, zero" : : : "memory");
366
- have_zba = !got_sigill;
367
-#endif
368
-
369
-#ifndef have_zbb
370
- /* Probe for Zba: andn zero,zero,zero. */
371
- got_sigill = 0;
372
- asm volatile(".insn r 0x33, 7, 0x20, zero, zero, zero" : : : "memory");
373
- have_zbb = !got_sigill;
374
-#endif
375
-
376
-#ifndef have_zicond
377
- /* Probe for Zicond: czero.eqz zero,zero,zero. */
378
- got_sigill = 0;
379
- asm volatile(".insn r 0x33, 5, 0x07, zero, zero, zero" : : : "memory");
380
- have_zicond = !got_sigill;
381
-#endif
382
-
383
- sigaction(SIGILL, &sa_old, NULL);
384
-#endif
385
-}
386
-
387
static void tcg_target_init(TCGContext *s)
388
{
389
- tcg_target_detect_isa();
390
-
391
tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
392
tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
393
394
diff --git a/util/meson.build b/util/meson.build
395
index XXXXXXX..XXXXXXX 100644
396
--- a/util/meson.build
397
+++ b/util/meson.build
398
@@ -XXX,XX +XXX,XX @@ elif cpu == 'loongarch64'
399
util_ss.add(files('cpuinfo-loongarch.c'))
400
elif cpu in ['ppc', 'ppc64']
401
util_ss.add(files('cpuinfo-ppc.c'))
402
+elif cpu in ['riscv32', 'riscv64']
403
+ util_ss.add(files('cpuinfo-riscv.c'))
404
endif
405
--
406
2.34.1
407
408
diff view generated by jsdifflib
[PULL 5/7] util/cpuinfo-riscv: Support OpenBSD signal frame
Deleted patch
1
Reported-by: Brad Smith <brad@comstyle.com>
2
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
3
Acked-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
4
Acked-by: Alistair Francis <alistair.francis@wdc.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
util/cpuinfo-riscv.c | 7 +++++++
8
1 file changed, 7 insertions(+)
9
1
10
diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/util/cpuinfo-riscv.c
13
+++ b/util/cpuinfo-riscv.c
14
@@ -XXX,XX +XXX,XX @@ static void sigill_handler(int signo, siginfo_t *si, void *data)
15
{
16
/* Skip the faulty instruction */
17
ucontext_t *uc = (ucontext_t *)data;
18
+
19
+#ifdef __linux__
20
uc->uc_mcontext.__gregs[REG_PC] += 4;
21
+#elif defined(__OpenBSD__)
22
+ uc->sc_sepc += 4;
23
+#else
24
+# error Unsupported OS
25
+#endif
26
27
got_sigill = 1;
28
}
29
--
30
2.34.1
31
32
diff view generated by jsdifflib
[PULL 6/7] util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall
Deleted patch
1
With recent linux kernels, there is a syscall to probe for various
2
ISA extensions. These bits were phased in over several kernel
3
releases, so we still require checks for symbol availability.
4
1
5
Acked-by: Alistair Francis <alistair.francis@wdc.com>
6
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
meson.build | 6 ++++++
10
util/cpuinfo-riscv.c | 26 ++++++++++++++++++++++++++
11
2 files changed, 32 insertions(+)
12
13
diff --git a/meson.build b/meson.build
14
index XXXXXXX..XXXXXXX 100644
15
--- a/meson.build
16
+++ b/meson.build
17
@@ -XXX,XX +XXX,XX @@ have_cpuid_h = cc.links('''
18
}''')
19
config_host_data.set('CONFIG_CPUID_H', have_cpuid_h)
20
21
+# Don't bother to advertise asm/hwprobe.h for old versions that do
22
+# not contain RISCV_HWPROBE_EXT_ZBA.
23
+config_host_data.set('CONFIG_ASM_HWPROBE_H',
24
+ cc.has_header_symbol('asm/hwprobe.h',
25
+ 'RISCV_HWPROBE_EXT_ZBA'))
26
+
27
config_host_data.set('CONFIG_AVX2_OPT', get_option('avx2') \
28
.require(have_cpuid_h, error_message: 'cpuid.h not available, cannot enable AVX2') \
29
.require(cc.links('''
30
diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/util/cpuinfo-riscv.c
33
+++ b/util/cpuinfo-riscv.c
34
@@ -XXX,XX +XXX,XX @@
35
#include "qemu/osdep.h"
36
#include "host/cpuinfo.h"
37
38
+#ifdef CONFIG_ASM_HWPROBE_H
39
+#include <asm/hwprobe.h>
40
+#include <sys/syscall.h>
41
+#endif
42
+
43
unsigned cpuinfo;
44
static volatile sig_atomic_t got_sigill;
45
46
@@ -XXX,XX +XXX,XX @@ unsigned __attribute__((constructor)) cpuinfo_init(void)
47
#endif
48
left &= ~info;
49
50
+#ifdef CONFIG_ASM_HWPROBE_H
51
+ if (left) {
52
+ /*
53
+ * TODO: glibc 2.40 will introduce <sys/hwprobe.h>, which
54
+ * provides __riscv_hwprobe and __riscv_hwprobe_one,
55
+ * which is a slightly cleaner interface.
56
+ */
57
+ struct riscv_hwprobe pair = { .key = RISCV_HWPROBE_KEY_IMA_EXT_0 };
58
+ if (syscall(__NR_riscv_hwprobe, &pair, 1, 0, NULL, 0) == 0
59
+ && pair.key >= 0) {
60
+ info |= pair.value & RISCV_HWPROBE_EXT_ZBA ? CPUINFO_ZBA : 0;
61
+ info |= pair.value & RISCV_HWPROBE_EXT_ZBB ? CPUINFO_ZBB : 0;
62
+ left &= ~(CPUINFO_ZBA | CPUINFO_ZBB);
63
+#ifdef RISCV_HWPROBE_EXT_ZICOND
64
+ info |= pair.value & RISCV_HWPROBE_EXT_ZICOND ? CPUINFO_ZICOND : 0;
65
+ left &= ~CPUINFO_ZICOND;
66
+#endif
67
+ }
68
+ }
69
+#endif /* CONFIG_ASM_HWPROBE_H */
70
+
71
if (left) {
72
struct sigaction sa_old, sa_new;
73
74
--
75
2.34.1
diff view generated by jsdifflib
[PULL 7/7] tcg/optimize: Fix TCG_COND_TST* simplification of setcond2
Deleted patch
1
Argument ordering for setcond2 is:
2
1
3
output, a_low, a_high, b_low, b_high, cond
4
5
The test is supposed to be against b_low, not a_high.
6
7
Cc: qemu-stable@nongnu.org
8
Fixes: ceb9ee06b71 ("tcg/optimize: Handle TCG_COND_TST{EQ,NE}")
9
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2413
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Tested-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-Id: <20240701024623.1265028-1-richard.henderson@linaro.org>
13
---
14
tcg/optimize.c | 2 +-
15
tests/tcg/x86_64/test-2413.c | 30 ++++++++++++++++++++++++++++++
16
tests/tcg/x86_64/Makefile.target | 2 ++
17
3 files changed, 33 insertions(+), 1 deletion(-)
18
create mode 100644 tests/tcg/x86_64/test-2413.c
19
20
diff --git a/tcg/optimize.c b/tcg/optimize.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/tcg/optimize.c
23
+++ b/tcg/optimize.c
24
@@ -XXX,XX +XXX,XX @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op)
25
26
case TCG_COND_TSTEQ:
27
case TCG_COND_TSTNE:
28
- if (arg_is_const_val(op->args[2], 0)) {
29
+ if (arg_is_const_val(op->args[3], 0)) {
30
goto do_setcond_high;
31
}
32
if (arg_is_const_val(op->args[4], 0)) {
33
diff --git a/tests/tcg/x86_64/test-2413.c b/tests/tcg/x86_64/test-2413.c
34
new file mode 100644
35
index XXXXXXX..XXXXXXX
36
--- /dev/null
37
+++ b/tests/tcg/x86_64/test-2413.c
38
@@ -XXX,XX +XXX,XX @@
39
+/* SPDX-License-Identifier: GPL-2.0-or-later */
40
+/* Copyright 2024 Linaro, Ltd. */
41
+/* See https://gitlab.com/qemu-project/qemu/-/issues/2413 */
42
+
43
+#include <assert.h>
44
+
45
+void test(unsigned long *a, unsigned long *d, unsigned long c)
46
+{
47
+ asm("xorl %%eax, %%eax\n\t"
48
+ "xorl %%edx, %%edx\n\t"
49
+ "testb $0x20, %%cl\n\t"
50
+ "sete %%al\n\t"
51
+ "setne %%dl\n\t"
52
+ "shll %%cl, %%eax\n\t"
53
+ "shll %%cl, %%edx\n\t"
54
+ : "=a"(*a), "=d"(*d)
55
+ : "c"(c));
56
+}
57
+
58
+int main(void)
59
+{
60
+ unsigned long a, c, d;
61
+
62
+ for (c = 0; c < 64; c++) {
63
+ test(&a, &d, c);
64
+ assert(a == (c & 0x20 ? 0 : 1u << (c & 0x1f)));
65
+ assert(d == (c & 0x20 ? 1u << (c & 0x1f) : 0));
66
+ }
67
+ return 0;
68
+}
69
diff --git a/tests/tcg/x86_64/Makefile.target b/tests/tcg/x86_64/Makefile.target
70
index XXXXXXX..XXXXXXX 100644
71
--- a/tests/tcg/x86_64/Makefile.target
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+++ b/tests/tcg/x86_64/Makefile.target
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@@ -XXX,XX +XXX,XX @@
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include $(SRC_PATH)/tests/tcg/i386/Makefile.target
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+X86_64_TESTS += test-2413
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+
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ifeq ($(filter %-linux-user, $(TARGET)),$(TARGET))
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X86_64_TESTS += vsyscall
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X86_64_TESTS += noexec
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--
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2.34.1
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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