1 | The following changes since commit 6746482d12da3b6e4d3cdf06481a0027a797f719: | 1 | Pretty small still, but there are two patches that ought |
---|---|---|---|
2 | to get backported to stable, so no point in delaying. | ||
2 | 3 | ||
3 | Merge tag 'sdmmc-20240702' of https://github.com/philmd/qemu into staging (2024-07-02 09:52:10 -0700) | 4 | r~ |
5 | |||
6 | The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307: | ||
7 | |||
8 | Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000) | ||
4 | 9 | ||
5 | are available in the Git repository at: | 10 | are available in the Git repository at: |
6 | 11 | ||
7 | https://gitlab.com/rth7680/qemu tags/pull-tcg-20240703 | 12 | https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241212 |
8 | 13 | ||
9 | for you to fetch changes up to a71d9dfbf63db42d6e6ae87fc112d1f5502183bd: | 14 | for you to fetch changes up to 7ac87b14a92234b6a89b701b4043ad6cf8bdcccf: |
10 | 15 | ||
11 | tcg/optimize: Fix TCG_COND_TST* simplification of setcond2 (2024-07-03 10:24:12 -0700) | 16 | target/sparc: Use memcpy() and remove memcpy32() (2024-12-12 14:28:38 -0600) |
12 | 17 | ||
13 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
14 | util: cpuinfo portability fixes for FreeBSD and OpenBSD | 19 | tcg: Reset free_temps before tcg_optimize |
15 | util: cpuinfo for riscv host | 20 | tcg/riscv: Fix StoreStore barrier generation |
16 | tcg/optimize: Fix TCG_COND_TST* simplification of setcond2 | 21 | include/exec: Introduce fpst alias in helper-head.h.inc |
22 | target/sparc: Use memcpy() and remove memcpy32() | ||
17 | 23 | ||
18 | ---------------------------------------------------------------- | 24 | ---------------------------------------------------------------- |
19 | Brad Smith (3): | 25 | Philippe Mathieu-Daudé (1): |
20 | util/cpuinfo-ppc: Fix building on OpenBSD | 26 | target/sparc: Use memcpy() and remove memcpy32() |
21 | util/cpuinfo-ppc: Add FreeBSD support | ||
22 | util/cpuinfo-aarch64: Add OpenBSD support | ||
23 | 27 | ||
24 | Richard Henderson (4): | 28 | Richard Henderson (2): |
25 | util/cpuinfo-riscv: Support host/cpuinfo.h for riscv | 29 | tcg: Reset free_temps before tcg_optimize |
26 | util/cpuinfo-riscv: Support OpenBSD signal frame | 30 | include/exec: Introduce fpst alias in helper-head.h.inc |
27 | util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall | ||
28 | tcg/optimize: Fix TCG_COND_TST* simplification of setcond2 | ||
29 | 31 | ||
30 | meson.build | 6 ++ | 32 | Roman Artemev (1): |
31 | host/include/riscv/host/cpuinfo.h | 23 ++++++++ | 33 | tcg/riscv: Fix StoreStore barrier generation |
32 | tcg/riscv/tcg-target.h | 46 +++++++-------- | 34 | |
33 | tcg/optimize.c | 2 +- | 35 | include/tcg/tcg-temp-internal.h | 6 ++++++ |
34 | tests/tcg/x86_64/test-2413.c | 30 ++++++++++ | 36 | accel/tcg/plugin-gen.c | 2 +- |
35 | util/cpuinfo-aarch64.c | 36 ++++++++++++ | 37 | target/sparc/win_helper.c | 26 ++++++++------------------ |
36 | util/cpuinfo-ppc.c | 27 ++++++--- | 38 | tcg/tcg.c | 5 ++++- |
37 | util/cpuinfo-riscv.c | 118 ++++++++++++++++++++++++++++++++++++++ | 39 | include/exec/helper-head.h.inc | 3 +++ |
38 | tcg/riscv/tcg-target.c.inc | 84 +++------------------------ | 40 | tcg/riscv/tcg-target.c.inc | 2 +- |
39 | tests/tcg/x86_64/Makefile.target | 2 + | 41 | 6 files changed, 23 insertions(+), 21 deletions(-) |
40 | util/meson.build | 2 + | 42 | |
41 | 11 files changed, 266 insertions(+), 110 deletions(-) | ||
42 | create mode 100644 host/include/riscv/host/cpuinfo.h | ||
43 | create mode 100644 tests/tcg/x86_64/test-2413.c | ||
44 | create mode 100644 util/cpuinfo-riscv.c | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Brad Smith <brad@comstyle.com> | ||
2 | 1 | ||
3 | OpenBSD does not support AT_HWCAP. | ||
4 | |||
5 | Signed-off-by: Brad Smith <brad@comstyle.com> | ||
6 | Message-Id: <ZnzM1T6Vo1Q0yAH-@humpty.home.comstyle.com> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | --- | ||
9 | util/cpuinfo-ppc.c | 20 ++++++++++++-------- | ||
10 | 1 file changed, 12 insertions(+), 8 deletions(-) | ||
11 | |||
12 | diff --git a/util/cpuinfo-ppc.c b/util/cpuinfo-ppc.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/util/cpuinfo-ppc.c | ||
15 | +++ b/util/cpuinfo-ppc.c | ||
16 | @@ -XXX,XX +XXX,XX @@ | ||
17 | #include "qemu/osdep.h" | ||
18 | #include "host/cpuinfo.h" | ||
19 | |||
20 | -#include <asm/cputable.h> | ||
21 | -#ifdef CONFIG_GETAUXVAL | ||
22 | -# include <sys/auxv.h> | ||
23 | -#else | ||
24 | -# include "elf.h" | ||
25 | +#ifdef CONFIG_LINUX | ||
26 | +# include <asm/cputable.h> | ||
27 | +# ifdef CONFIG_GETAUXVAL | ||
28 | +# include <sys/auxv.h> | ||
29 | +# else | ||
30 | +# include "elf.h" | ||
31 | +# endif | ||
32 | #endif | ||
33 | |||
34 | unsigned cpuinfo; | ||
35 | @@ -XXX,XX +XXX,XX @@ unsigned cpuinfo; | ||
36 | unsigned __attribute__((constructor)) cpuinfo_init(void) | ||
37 | { | ||
38 | unsigned info = cpuinfo; | ||
39 | - unsigned long hwcap, hwcap2; | ||
40 | |||
41 | if (info) { | ||
42 | return info; | ||
43 | } | ||
44 | |||
45 | - hwcap = qemu_getauxval(AT_HWCAP); | ||
46 | - hwcap2 = qemu_getauxval(AT_HWCAP2); | ||
47 | info = CPUINFO_ALWAYS; | ||
48 | |||
49 | +#ifdef CONFIG_LINUX | ||
50 | + unsigned long hwcap = qemu_getauxval(AT_HWCAP); | ||
51 | + unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2); | ||
52 | + | ||
53 | /* Version numbers are monotonic, and so imply all lower versions. */ | ||
54 | if (hwcap2 & PPC_FEATURE2_ARCH_3_1) { | ||
55 | info |= CPUINFO_V3_1 | CPUINFO_V3_0 | CPUINFO_V2_07 | CPUINFO_V2_06; | ||
56 | @@ -XXX,XX +XXX,XX @@ unsigned __attribute__((constructor)) cpuinfo_init(void) | ||
57 | } | ||
58 | } | ||
59 | } | ||
60 | +#endif | ||
61 | |||
62 | cpuinfo = info; | ||
63 | return info; | ||
64 | -- | ||
65 | 2.34.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Brad Smith <brad@comstyle.com> | ||
2 | 1 | ||
3 | Signed-off-by: Brad Smith <brad@comstyle.com> | ||
4 | Message-Id: <Zn9cJ3puWr5lIgsg@humpty.home.comstyle.com> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | --- | ||
7 | util/cpuinfo-ppc.c | 9 ++++++++- | ||
8 | 1 file changed, 8 insertions(+), 1 deletion(-) | ||
9 | |||
10 | diff --git a/util/cpuinfo-ppc.c b/util/cpuinfo-ppc.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/util/cpuinfo-ppc.c | ||
13 | +++ b/util/cpuinfo-ppc.c | ||
14 | @@ -XXX,XX +XXX,XX @@ | ||
15 | # include "elf.h" | ||
16 | # endif | ||
17 | #endif | ||
18 | +#ifdef __FreeBSD__ | ||
19 | +# include <machine/cpu.h> | ||
20 | +# ifndef PPC_FEATURE2_ARCH_3_1 | ||
21 | +# define PPC_FEATURE2_ARCH_3_1 0 | ||
22 | +# endif | ||
23 | +# define PPC_FEATURE2_VEC_CRYPTO PPC_FEATURE2_HAS_VEC_CRYPTO | ||
24 | +#endif | ||
25 | |||
26 | unsigned cpuinfo; | ||
27 | |||
28 | @@ -XXX,XX +XXX,XX @@ unsigned __attribute__((constructor)) cpuinfo_init(void) | ||
29 | |||
30 | info = CPUINFO_ALWAYS; | ||
31 | |||
32 | -#ifdef CONFIG_LINUX | ||
33 | +#if defined(CONFIG_LINUX) || defined(__FreeBSD__) | ||
34 | unsigned long hwcap = qemu_getauxval(AT_HWCAP); | ||
35 | unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2); | ||
36 | |||
37 | -- | ||
38 | 2.34.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Brad Smith <brad@comstyle.com> | ||
2 | 1 | ||
3 | Signed-off-by: Brad Smith <brad@comstyle.com> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-Id: <ZneEh51XKhxgZKpp@humpty.home.comstyle.com> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | --- | ||
8 | util/cpuinfo-aarch64.c | 36 ++++++++++++++++++++++++++++++++++++ | ||
9 | 1 file changed, 36 insertions(+) | ||
10 | |||
11 | diff --git a/util/cpuinfo-aarch64.c b/util/cpuinfo-aarch64.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/util/cpuinfo-aarch64.c | ||
14 | +++ b/util/cpuinfo-aarch64.c | ||
15 | @@ -XXX,XX +XXX,XX @@ | ||
16 | #ifdef CONFIG_DARWIN | ||
17 | # include <sys/sysctl.h> | ||
18 | #endif | ||
19 | +#ifdef __OpenBSD__ | ||
20 | +# include <machine/armreg.h> | ||
21 | +# include <machine/cpu.h> | ||
22 | +# include <sys/types.h> | ||
23 | +# include <sys/sysctl.h> | ||
24 | +#endif | ||
25 | |||
26 | unsigned cpuinfo; | ||
27 | |||
28 | @@ -XXX,XX +XXX,XX @@ unsigned __attribute__((constructor)) cpuinfo_init(void) | ||
29 | info |= sysctl_for_bool("hw.optional.arm.FEAT_PMULL") * CPUINFO_PMULL; | ||
30 | info |= sysctl_for_bool("hw.optional.arm.FEAT_BTI") * CPUINFO_BTI; | ||
31 | #endif | ||
32 | +#ifdef __OpenBSD__ | ||
33 | + int mib[2]; | ||
34 | + uint64_t isar0; | ||
35 | + uint64_t pfr1; | ||
36 | + size_t len; | ||
37 | + | ||
38 | + mib[0] = CTL_MACHDEP; | ||
39 | + mib[1] = CPU_ID_AA64ISAR0; | ||
40 | + len = sizeof(isar0); | ||
41 | + if (sysctl(mib, 2, &isar0, &len, NULL, 0) != -1) { | ||
42 | + if (ID_AA64ISAR0_ATOMIC(isar0) >= ID_AA64ISAR0_ATOMIC_IMPL) { | ||
43 | + info |= CPUINFO_LSE; | ||
44 | + } | ||
45 | + if (ID_AA64ISAR0_AES(isar0) >= ID_AA64ISAR0_AES_BASE) { | ||
46 | + info |= CPUINFO_AES; | ||
47 | + } | ||
48 | + if (ID_AA64ISAR0_AES(isar0) >= ID_AA64ISAR0_AES_PMULL) { | ||
49 | + info |= CPUINFO_PMULL; | ||
50 | + } | ||
51 | + } | ||
52 | + | ||
53 | + mib[0] = CTL_MACHDEP; | ||
54 | + mib[1] = CPU_ID_AA64PFR1; | ||
55 | + len = sizeof(pfr1); | ||
56 | + if (sysctl(mib, 2, &pfr1, &len, NULL, 0) != -1) { | ||
57 | + if (ID_AA64PFR1_BT(pfr1) >= ID_AA64PFR1_BT_IMPL) { | ||
58 | + info |= CPUINFO_BTI; | ||
59 | + } | ||
60 | + } | ||
61 | +#endif | ||
62 | |||
63 | cpuinfo = info; | ||
64 | return info; | ||
65 | -- | ||
66 | 2.34.1 | diff view generated by jsdifflib |
1 | Argument ordering for setcond2 is: | 1 | When allocating new temps during tcg_optmize, do not re-use |
---|---|---|---|
2 | any EBB temps that were used within the TB. We do not have | ||
3 | any idea what span of the TB in which the temp was live. | ||
2 | 4 | ||
3 | output, a_low, a_high, b_low, b_high, cond | 5 | Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize, |
4 | 6 | as well as replacing the equivalent in plugin_gen_inject and | |
5 | The test is supposed to be against b_low, not a_high. | 7 | tcg_func_start. |
6 | 8 | ||
7 | Cc: qemu-stable@nongnu.org | 9 | Cc: qemu-stable@nongnu.org |
8 | Fixes: ceb9ee06b71 ("tcg/optimize: Handle TCG_COND_TST{EQ,NE}") | 10 | Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported") |
9 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2413 | 11 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711 |
12 | Reported-by: wannacu <wannacu2049@gmail.com> | ||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 13 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
11 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | 14 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
12 | Message-Id: <20240701024623.1265028-1-richard.henderson@linaro.org> | 15 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
13 | --- | 16 | --- |
14 | tcg/optimize.c | 2 +- | 17 | include/tcg/tcg-temp-internal.h | 6 ++++++ |
15 | tests/tcg/x86_64/test-2413.c | 30 ++++++++++++++++++++++++++++++ | 18 | accel/tcg/plugin-gen.c | 2 +- |
16 | tests/tcg/x86_64/Makefile.target | 2 ++ | 19 | tcg/tcg.c | 5 ++++- |
17 | 3 files changed, 33 insertions(+), 1 deletion(-) | 20 | 3 files changed, 11 insertions(+), 2 deletions(-) |
18 | create mode 100644 tests/tcg/x86_64/test-2413.c | ||
19 | 21 | ||
20 | diff --git a/tcg/optimize.c b/tcg/optimize.c | 22 | diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h |
21 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/tcg/optimize.c | 24 | --- a/include/tcg/tcg-temp-internal.h |
23 | +++ b/tcg/optimize.c | 25 | +++ b/include/tcg/tcg-temp-internal.h |
24 | @@ -XXX,XX +XXX,XX @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op) | 26 | @@ -XXX,XX +XXX,XX @@ TCGv_i64 tcg_temp_ebb_new_i64(void); |
25 | 27 | TCGv_ptr tcg_temp_ebb_new_ptr(void); | |
26 | case TCG_COND_TSTEQ: | 28 | TCGv_i128 tcg_temp_ebb_new_i128(void); |
27 | case TCG_COND_TSTNE: | 29 | |
28 | - if (arg_is_const_val(op->args[2], 0)) { | 30 | +/* Forget all freed EBB temps, so that new allocations produce new temps. */ |
29 | + if (arg_is_const_val(op->args[3], 0)) { | 31 | +static inline void tcg_temp_ebb_reset_freed(TCGContext *s) |
30 | goto do_setcond_high; | ||
31 | } | ||
32 | if (arg_is_const_val(op->args[4], 0)) { | ||
33 | diff --git a/tests/tcg/x86_64/test-2413.c b/tests/tcg/x86_64/test-2413.c | ||
34 | new file mode 100644 | ||
35 | index XXXXXXX..XXXXXXX | ||
36 | --- /dev/null | ||
37 | +++ b/tests/tcg/x86_64/test-2413.c | ||
38 | @@ -XXX,XX +XXX,XX @@ | ||
39 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ | ||
40 | +/* Copyright 2024 Linaro, Ltd. */ | ||
41 | +/* See https://gitlab.com/qemu-project/qemu/-/issues/2413 */ | ||
42 | + | ||
43 | +#include <assert.h> | ||
44 | + | ||
45 | +void test(unsigned long *a, unsigned long *d, unsigned long c) | ||
46 | +{ | 32 | +{ |
47 | + asm("xorl %%eax, %%eax\n\t" | 33 | + memset(s->free_temps, 0, sizeof(s->free_temps)); |
48 | + "xorl %%edx, %%edx\n\t" | ||
49 | + "testb $0x20, %%cl\n\t" | ||
50 | + "sete %%al\n\t" | ||
51 | + "setne %%dl\n\t" | ||
52 | + "shll %%cl, %%eax\n\t" | ||
53 | + "shll %%cl, %%edx\n\t" | ||
54 | + : "=a"(*a), "=d"(*d) | ||
55 | + : "c"(c)); | ||
56 | +} | 34 | +} |
57 | + | 35 | + |
58 | +int main(void) | 36 | #endif /* TCG_TEMP_FREE_H */ |
59 | +{ | 37 | diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c |
60 | + unsigned long a, c, d; | 38 | index XXXXXXX..XXXXXXX 100644 |
39 | --- a/accel/tcg/plugin-gen.c | ||
40 | +++ b/accel/tcg/plugin-gen.c | ||
41 | @@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb) | ||
42 | * that might be live within the existing opcode stream. | ||
43 | * The simplest solution is to release them all and create new. | ||
44 | */ | ||
45 | - memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps)); | ||
46 | + tcg_temp_ebb_reset_freed(tcg_ctx); | ||
47 | |||
48 | QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) { | ||
49 | switch (op->opc) { | ||
50 | diff --git a/tcg/tcg.c b/tcg/tcg.c | ||
51 | index XXXXXXX..XXXXXXX 100644 | ||
52 | --- a/tcg/tcg.c | ||
53 | +++ b/tcg/tcg.c | ||
54 | @@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s) | ||
55 | s->nb_temps = s->nb_globals; | ||
56 | |||
57 | /* No temps have been previously allocated for size or locality. */ | ||
58 | - memset(s->free_temps, 0, sizeof(s->free_temps)); | ||
59 | + tcg_temp_ebb_reset_freed(s); | ||
60 | |||
61 | /* No constant temps have been previously allocated. */ | ||
62 | for (int i = 0; i < TCG_TYPE_COUNT; ++i) { | ||
63 | @@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start) | ||
64 | } | ||
65 | #endif | ||
66 | |||
67 | + /* Do not reuse any EBB that may be allocated within the TB. */ | ||
68 | + tcg_temp_ebb_reset_freed(s); | ||
61 | + | 69 | + |
62 | + for (c = 0; c < 64; c++) { | 70 | tcg_optimize(s); |
63 | + test(&a, &d, c); | 71 | |
64 | + assert(a == (c & 0x20 ? 0 : 1u << (c & 0x1f))); | 72 | reachable_code_pass(s); |
65 | + assert(d == (c & 0x20 ? 1u << (c & 0x1f) : 0)); | ||
66 | + } | ||
67 | + return 0; | ||
68 | +} | ||
69 | diff --git a/tests/tcg/x86_64/Makefile.target b/tests/tcg/x86_64/Makefile.target | ||
70 | index XXXXXXX..XXXXXXX 100644 | ||
71 | --- a/tests/tcg/x86_64/Makefile.target | ||
72 | +++ b/tests/tcg/x86_64/Makefile.target | ||
73 | @@ -XXX,XX +XXX,XX @@ | ||
74 | |||
75 | include $(SRC_PATH)/tests/tcg/i386/Makefile.target | ||
76 | |||
77 | +X86_64_TESTS += test-2413 | ||
78 | + | ||
79 | ifeq ($(filter %-linux-user, $(TARGET)),$(TARGET)) | ||
80 | X86_64_TESTS += vsyscall | ||
81 | X86_64_TESTS += noexec | ||
82 | -- | 73 | -- |
83 | 2.34.1 | 74 | 2.43.0 |
84 | 75 | ||
85 | 76 | diff view generated by jsdifflib |
1 | With recent linux kernels, there is a syscall to probe for various | 1 | From: Roman Artemev <roman.artemev@syntacore.com> |
---|---|---|---|
2 | ISA extensions. These bits were phased in over several kernel | ||
3 | releases, so we still require checks for symbol availability. | ||
4 | 2 | ||
5 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | 3 | On RISC-V to StoreStore barrier corresponds |
6 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 4 | `fence w, w` not `fence r, r` |
5 | |||
6 | Cc: qemu-stable@nongnu.org | ||
7 | Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions") | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com> | ||
10 | Signed-off-by: Roman Artemev <roman.artemev@syntacore.com> | ||
11 | Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | --- | 13 | --- |
9 | meson.build | 6 ++++++ | 14 | tcg/riscv/tcg-target.c.inc | 2 +- |
10 | util/cpuinfo-riscv.c | 26 ++++++++++++++++++++++++++ | 15 | 1 file changed, 1 insertion(+), 1 deletion(-) |
11 | 2 files changed, 32 insertions(+) | ||
12 | 16 | ||
13 | diff --git a/meson.build b/meson.build | 17 | diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc |
14 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/meson.build | 19 | --- a/tcg/riscv/tcg-target.c.inc |
16 | +++ b/meson.build | 20 | +++ b/tcg/riscv/tcg-target.c.inc |
17 | @@ -XXX,XX +XXX,XX @@ have_cpuid_h = cc.links(''' | 21 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) |
18 | }''') | 22 | insn |= 0x02100000; |
19 | config_host_data.set('CONFIG_CPUID_H', have_cpuid_h) | 23 | } |
20 | 24 | if (a0 & TCG_MO_ST_ST) { | |
21 | +# Don't bother to advertise asm/hwprobe.h for old versions that do | 25 | - insn |= 0x02200000; |
22 | +# not contain RISCV_HWPROBE_EXT_ZBA. | 26 | + insn |= 0x01100000; |
23 | +config_host_data.set('CONFIG_ASM_HWPROBE_H', | 27 | } |
24 | + cc.has_header_symbol('asm/hwprobe.h', | 28 | tcg_out32(s, insn); |
25 | + 'RISCV_HWPROBE_EXT_ZBA')) | 29 | } |
26 | + | ||
27 | config_host_data.set('CONFIG_AVX2_OPT', get_option('avx2') \ | ||
28 | .require(have_cpuid_h, error_message: 'cpuid.h not available, cannot enable AVX2') \ | ||
29 | .require(cc.links(''' | ||
30 | diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/util/cpuinfo-riscv.c | ||
33 | +++ b/util/cpuinfo-riscv.c | ||
34 | @@ -XXX,XX +XXX,XX @@ | ||
35 | #include "qemu/osdep.h" | ||
36 | #include "host/cpuinfo.h" | ||
37 | |||
38 | +#ifdef CONFIG_ASM_HWPROBE_H | ||
39 | +#include <asm/hwprobe.h> | ||
40 | +#include <sys/syscall.h> | ||
41 | +#endif | ||
42 | + | ||
43 | unsigned cpuinfo; | ||
44 | static volatile sig_atomic_t got_sigill; | ||
45 | |||
46 | @@ -XXX,XX +XXX,XX @@ unsigned __attribute__((constructor)) cpuinfo_init(void) | ||
47 | #endif | ||
48 | left &= ~info; | ||
49 | |||
50 | +#ifdef CONFIG_ASM_HWPROBE_H | ||
51 | + if (left) { | ||
52 | + /* | ||
53 | + * TODO: glibc 2.40 will introduce <sys/hwprobe.h>, which | ||
54 | + * provides __riscv_hwprobe and __riscv_hwprobe_one, | ||
55 | + * which is a slightly cleaner interface. | ||
56 | + */ | ||
57 | + struct riscv_hwprobe pair = { .key = RISCV_HWPROBE_KEY_IMA_EXT_0 }; | ||
58 | + if (syscall(__NR_riscv_hwprobe, &pair, 1, 0, NULL, 0) == 0 | ||
59 | + && pair.key >= 0) { | ||
60 | + info |= pair.value & RISCV_HWPROBE_EXT_ZBA ? CPUINFO_ZBA : 0; | ||
61 | + info |= pair.value & RISCV_HWPROBE_EXT_ZBB ? CPUINFO_ZBB : 0; | ||
62 | + left &= ~(CPUINFO_ZBA | CPUINFO_ZBB); | ||
63 | +#ifdef RISCV_HWPROBE_EXT_ZICOND | ||
64 | + info |= pair.value & RISCV_HWPROBE_EXT_ZICOND ? CPUINFO_ZICOND : 0; | ||
65 | + left &= ~CPUINFO_ZICOND; | ||
66 | +#endif | ||
67 | + } | ||
68 | + } | ||
69 | +#endif /* CONFIG_ASM_HWPROBE_H */ | ||
70 | + | ||
71 | if (left) { | ||
72 | struct sigaction sa_old, sa_new; | ||
73 | |||
74 | -- | 30 | -- |
75 | 2.34.1 | 31 | 2.43.0 | diff view generated by jsdifflib |
1 | Reported-by: Brad Smith <brad@comstyle.com> | 1 | This allows targets to declare that the helper requires a |
---|---|---|---|
2 | float_status pointer and instead of a generic void pointer. | ||
3 | |||
2 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 4 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
3 | Acked-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
4 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | --- | 6 | --- |
7 | util/cpuinfo-riscv.c | 7 +++++++ | 7 | include/exec/helper-head.h.inc | 3 +++ |
8 | 1 file changed, 7 insertions(+) | 8 | 1 file changed, 3 insertions(+) |
9 | 9 | ||
10 | diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c | 10 | diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc |
11 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
12 | --- a/util/cpuinfo-riscv.c | 12 | --- a/include/exec/helper-head.h.inc |
13 | +++ b/util/cpuinfo-riscv.c | 13 | +++ b/include/exec/helper-head.h.inc |
14 | @@ -XXX,XX +XXX,XX @@ static void sigill_handler(int signo, siginfo_t *si, void *data) | 14 | @@ -XXX,XX +XXX,XX @@ |
15 | { | 15 | #define dh_alias_ptr ptr |
16 | /* Skip the faulty instruction */ | 16 | #define dh_alias_cptr ptr |
17 | ucontext_t *uc = (ucontext_t *)data; | 17 | #define dh_alias_env ptr |
18 | + | 18 | +#define dh_alias_fpst ptr |
19 | +#ifdef __linux__ | 19 | #define dh_alias_void void |
20 | uc->uc_mcontext.__gregs[REG_PC] += 4; | 20 | #define dh_alias_noreturn noreturn |
21 | +#elif defined(__OpenBSD__) | 21 | #define dh_alias(t) glue(dh_alias_, t) |
22 | + uc->sc_sepc += 4; | 22 | @@ -XXX,XX +XXX,XX @@ |
23 | +#else | 23 | #define dh_ctype_ptr void * |
24 | +# error Unsupported OS | 24 | #define dh_ctype_cptr const void * |
25 | +#endif | 25 | #define dh_ctype_env CPUArchState * |
26 | 26 | +#define dh_ctype_fpst float_status * | |
27 | got_sigill = 1; | 27 | #define dh_ctype_void void |
28 | } | 28 | #define dh_ctype_noreturn G_NORETURN void |
29 | #define dh_ctype(t) dh_ctype_##t | ||
30 | @@ -XXX,XX +XXX,XX @@ | ||
31 | #define dh_typecode_f64 dh_typecode_i64 | ||
32 | #define dh_typecode_cptr dh_typecode_ptr | ||
33 | #define dh_typecode_env dh_typecode_ptr | ||
34 | +#define dh_typecode_fpst dh_typecode_ptr | ||
35 | #define dh_typecode(t) dh_typecode_##t | ||
36 | |||
37 | #define dh_callflag_i32 0 | ||
29 | -- | 38 | -- |
30 | 2.34.1 | 39 | 2.43.0 |
31 | 40 | ||
32 | 41 | diff view generated by jsdifflib |
1 | Move detection code out of tcg, similar to other hosts. | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | 3 | Rather than manually copying each register, use |
4 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 4 | the libc memcpy(), which is well optimized nowadays. |
5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 5 | |
6 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 6 | Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
7 | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
10 | Message-ID: <20241205205418.67613-1-philmd@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | --- | 12 | --- |
9 | host/include/riscv/host/cpuinfo.h | 23 +++++++++ | 13 | target/sparc/win_helper.c | 26 ++++++++------------------ |
10 | tcg/riscv/tcg-target.h | 46 ++++++++--------- | 14 | 1 file changed, 8 insertions(+), 18 deletions(-) |
11 | util/cpuinfo-riscv.c | 85 +++++++++++++++++++++++++++++++ | ||
12 | tcg/riscv/tcg-target.c.inc | 84 +++--------------------------- | ||
13 | util/meson.build | 2 + | ||
14 | 5 files changed, 139 insertions(+), 101 deletions(-) | ||
15 | create mode 100644 host/include/riscv/host/cpuinfo.h | ||
16 | create mode 100644 util/cpuinfo-riscv.c | ||
17 | 15 | ||
18 | diff --git a/host/include/riscv/host/cpuinfo.h b/host/include/riscv/host/cpuinfo.h | 16 | diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c |
19 | new file mode 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
20 | index XXXXXXX..XXXXXXX | 18 | --- a/target/sparc/win_helper.c |
21 | --- /dev/null | 19 | +++ b/target/sparc/win_helper.c |
22 | +++ b/host/include/riscv/host/cpuinfo.h | ||
23 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ |
24 | +/* | 21 | #include "exec/helper-proto.h" |
25 | + * SPDX-License-Identifier: GPL-2.0-or-later | 22 | #include "trace.h" |
26 | + * Host specific cpu identification for RISC-V. | 23 | |
27 | + */ | 24 | -static inline void memcpy32(target_ulong *dst, const target_ulong *src) |
28 | + | ||
29 | +#ifndef HOST_CPUINFO_H | ||
30 | +#define HOST_CPUINFO_H | ||
31 | + | ||
32 | +#define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */ | ||
33 | +#define CPUINFO_ZBA (1u << 1) | ||
34 | +#define CPUINFO_ZBB (1u << 2) | ||
35 | +#define CPUINFO_ZICOND (1u << 3) | ||
36 | + | ||
37 | +/* Initialized with a constructor. */ | ||
38 | +extern unsigned cpuinfo; | ||
39 | + | ||
40 | +/* | ||
41 | + * We cannot rely on constructor ordering, so other constructors must | ||
42 | + * use the function interface rather than the variable above. | ||
43 | + */ | ||
44 | +unsigned cpuinfo_init(void); | ||
45 | + | ||
46 | +#endif /* HOST_CPUINFO_H */ | ||
47 | diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/tcg/riscv/tcg-target.h | ||
50 | +++ b/tcg/riscv/tcg-target.h | ||
51 | @@ -XXX,XX +XXX,XX @@ | ||
52 | #ifndef RISCV_TCG_TARGET_H | ||
53 | #define RISCV_TCG_TARGET_H | ||
54 | |||
55 | +#include "host/cpuinfo.h" | ||
56 | + | ||
57 | #define TCG_TARGET_INSN_UNIT_SIZE 4 | ||
58 | #define TCG_TARGET_NB_REGS 32 | ||
59 | #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) | ||
60 | @@ -XXX,XX +XXX,XX @@ typedef enum { | ||
61 | #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL | ||
62 | #define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL | ||
63 | |||
64 | -#if defined(__riscv_arch_test) && defined(__riscv_zbb) | ||
65 | -# define have_zbb true | ||
66 | -#else | ||
67 | -extern bool have_zbb; | ||
68 | -#endif | ||
69 | - | ||
70 | /* optional instructions */ | ||
71 | #define TCG_TARGET_HAS_negsetcond_i32 1 | ||
72 | #define TCG_TARGET_HAS_div_i32 1 | ||
73 | #define TCG_TARGET_HAS_rem_i32 1 | ||
74 | #define TCG_TARGET_HAS_div2_i32 0 | ||
75 | -#define TCG_TARGET_HAS_rot_i32 have_zbb | ||
76 | +#define TCG_TARGET_HAS_rot_i32 (cpuinfo & CPUINFO_ZBB) | ||
77 | #define TCG_TARGET_HAS_deposit_i32 0 | ||
78 | #define TCG_TARGET_HAS_extract_i32 0 | ||
79 | #define TCG_TARGET_HAS_sextract_i32 0 | ||
80 | @@ -XXX,XX +XXX,XX @@ extern bool have_zbb; | ||
81 | #define TCG_TARGET_HAS_ext16s_i32 1 | ||
82 | #define TCG_TARGET_HAS_ext8u_i32 1 | ||
83 | #define TCG_TARGET_HAS_ext16u_i32 1 | ||
84 | -#define TCG_TARGET_HAS_bswap16_i32 have_zbb | ||
85 | -#define TCG_TARGET_HAS_bswap32_i32 have_zbb | ||
86 | +#define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB) | ||
87 | +#define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB) | ||
88 | #define TCG_TARGET_HAS_not_i32 1 | ||
89 | -#define TCG_TARGET_HAS_andc_i32 have_zbb | ||
90 | -#define TCG_TARGET_HAS_orc_i32 have_zbb | ||
91 | -#define TCG_TARGET_HAS_eqv_i32 have_zbb | ||
92 | +#define TCG_TARGET_HAS_andc_i32 (cpuinfo & CPUINFO_ZBB) | ||
93 | +#define TCG_TARGET_HAS_orc_i32 (cpuinfo & CPUINFO_ZBB) | ||
94 | +#define TCG_TARGET_HAS_eqv_i32 (cpuinfo & CPUINFO_ZBB) | ||
95 | #define TCG_TARGET_HAS_nand_i32 0 | ||
96 | #define TCG_TARGET_HAS_nor_i32 0 | ||
97 | -#define TCG_TARGET_HAS_clz_i32 have_zbb | ||
98 | -#define TCG_TARGET_HAS_ctz_i32 have_zbb | ||
99 | -#define TCG_TARGET_HAS_ctpop_i32 have_zbb | ||
100 | +#define TCG_TARGET_HAS_clz_i32 (cpuinfo & CPUINFO_ZBB) | ||
101 | +#define TCG_TARGET_HAS_ctz_i32 (cpuinfo & CPUINFO_ZBB) | ||
102 | +#define TCG_TARGET_HAS_ctpop_i32 (cpuinfo & CPUINFO_ZBB) | ||
103 | #define TCG_TARGET_HAS_brcond2 1 | ||
104 | #define TCG_TARGET_HAS_setcond2 1 | ||
105 | #define TCG_TARGET_HAS_qemu_st8_i32 0 | ||
106 | @@ -XXX,XX +XXX,XX @@ extern bool have_zbb; | ||
107 | #define TCG_TARGET_HAS_div_i64 1 | ||
108 | #define TCG_TARGET_HAS_rem_i64 1 | ||
109 | #define TCG_TARGET_HAS_div2_i64 0 | ||
110 | -#define TCG_TARGET_HAS_rot_i64 have_zbb | ||
111 | +#define TCG_TARGET_HAS_rot_i64 (cpuinfo & CPUINFO_ZBB) | ||
112 | #define TCG_TARGET_HAS_deposit_i64 0 | ||
113 | #define TCG_TARGET_HAS_extract_i64 0 | ||
114 | #define TCG_TARGET_HAS_sextract_i64 0 | ||
115 | @@ -XXX,XX +XXX,XX @@ extern bool have_zbb; | ||
116 | #define TCG_TARGET_HAS_ext8u_i64 1 | ||
117 | #define TCG_TARGET_HAS_ext16u_i64 1 | ||
118 | #define TCG_TARGET_HAS_ext32u_i64 1 | ||
119 | -#define TCG_TARGET_HAS_bswap16_i64 have_zbb | ||
120 | -#define TCG_TARGET_HAS_bswap32_i64 have_zbb | ||
121 | -#define TCG_TARGET_HAS_bswap64_i64 have_zbb | ||
122 | +#define TCG_TARGET_HAS_bswap16_i64 (cpuinfo & CPUINFO_ZBB) | ||
123 | +#define TCG_TARGET_HAS_bswap32_i64 (cpuinfo & CPUINFO_ZBB) | ||
124 | +#define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB) | ||
125 | #define TCG_TARGET_HAS_not_i64 1 | ||
126 | -#define TCG_TARGET_HAS_andc_i64 have_zbb | ||
127 | -#define TCG_TARGET_HAS_orc_i64 have_zbb | ||
128 | -#define TCG_TARGET_HAS_eqv_i64 have_zbb | ||
129 | +#define TCG_TARGET_HAS_andc_i64 (cpuinfo & CPUINFO_ZBB) | ||
130 | +#define TCG_TARGET_HAS_orc_i64 (cpuinfo & CPUINFO_ZBB) | ||
131 | +#define TCG_TARGET_HAS_eqv_i64 (cpuinfo & CPUINFO_ZBB) | ||
132 | #define TCG_TARGET_HAS_nand_i64 0 | ||
133 | #define TCG_TARGET_HAS_nor_i64 0 | ||
134 | -#define TCG_TARGET_HAS_clz_i64 have_zbb | ||
135 | -#define TCG_TARGET_HAS_ctz_i64 have_zbb | ||
136 | -#define TCG_TARGET_HAS_ctpop_i64 have_zbb | ||
137 | +#define TCG_TARGET_HAS_clz_i64 (cpuinfo & CPUINFO_ZBB) | ||
138 | +#define TCG_TARGET_HAS_ctz_i64 (cpuinfo & CPUINFO_ZBB) | ||
139 | +#define TCG_TARGET_HAS_ctpop_i64 (cpuinfo & CPUINFO_ZBB) | ||
140 | #define TCG_TARGET_HAS_add2_i64 1 | ||
141 | #define TCG_TARGET_HAS_sub2_i64 1 | ||
142 | #define TCG_TARGET_HAS_mulu2_i64 0 | ||
143 | diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c | ||
144 | new file mode 100644 | ||
145 | index XXXXXXX..XXXXXXX | ||
146 | --- /dev/null | ||
147 | +++ b/util/cpuinfo-riscv.c | ||
148 | @@ -XXX,XX +XXX,XX @@ | ||
149 | +/* | ||
150 | + * SPDX-License-Identifier: GPL-2.0-or-later | ||
151 | + * Host specific cpu identification for RISC-V. | ||
152 | + */ | ||
153 | + | ||
154 | +#include "qemu/osdep.h" | ||
155 | +#include "host/cpuinfo.h" | ||
156 | + | ||
157 | +unsigned cpuinfo; | ||
158 | +static volatile sig_atomic_t got_sigill; | ||
159 | + | ||
160 | +static void sigill_handler(int signo, siginfo_t *si, void *data) | ||
161 | +{ | ||
162 | + /* Skip the faulty instruction */ | ||
163 | + ucontext_t *uc = (ucontext_t *)data; | ||
164 | + uc->uc_mcontext.__gregs[REG_PC] += 4; | ||
165 | + | ||
166 | + got_sigill = 1; | ||
167 | +} | ||
168 | + | ||
169 | +/* Called both as constructor and (possibly) via other constructors. */ | ||
170 | +unsigned __attribute__((constructor)) cpuinfo_init(void) | ||
171 | +{ | ||
172 | + unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND; | ||
173 | + unsigned info = cpuinfo; | ||
174 | + | ||
175 | + if (info) { | ||
176 | + return info; | ||
177 | + } | ||
178 | + | ||
179 | + /* Test for compile-time settings. */ | ||
180 | +#if defined(__riscv_arch_test) && defined(__riscv_zba) | ||
181 | + info |= CPUINFO_ZBA; | ||
182 | +#endif | ||
183 | +#if defined(__riscv_arch_test) && defined(__riscv_zbb) | ||
184 | + info |= CPUINFO_ZBB; | ||
185 | +#endif | ||
186 | +#if defined(__riscv_arch_test) && defined(__riscv_zicond) | ||
187 | + info |= CPUINFO_ZICOND; | ||
188 | +#endif | ||
189 | + left &= ~info; | ||
190 | + | ||
191 | + if (left) { | ||
192 | + struct sigaction sa_old, sa_new; | ||
193 | + | ||
194 | + memset(&sa_new, 0, sizeof(sa_new)); | ||
195 | + sa_new.sa_flags = SA_SIGINFO; | ||
196 | + sa_new.sa_sigaction = sigill_handler; | ||
197 | + sigaction(SIGILL, &sa_new, &sa_old); | ||
198 | + | ||
199 | + if (left & CPUINFO_ZBA) { | ||
200 | + /* Probe for Zba: add.uw zero,zero,zero. */ | ||
201 | + got_sigill = 0; | ||
202 | + asm volatile(".insn r 0x3b, 0, 0x04, zero, zero, zero" | ||
203 | + : : : "memory"); | ||
204 | + info |= got_sigill ? 0 : CPUINFO_ZBA; | ||
205 | + left &= ~CPUINFO_ZBA; | ||
206 | + } | ||
207 | + | ||
208 | + if (left & CPUINFO_ZBB) { | ||
209 | + /* Probe for Zbb: andn zero,zero,zero. */ | ||
210 | + got_sigill = 0; | ||
211 | + asm volatile(".insn r 0x33, 7, 0x20, zero, zero, zero" | ||
212 | + : : : "memory"); | ||
213 | + info |= got_sigill ? 0 : CPUINFO_ZBB; | ||
214 | + left &= ~CPUINFO_ZBB; | ||
215 | + } | ||
216 | + | ||
217 | + if (left & CPUINFO_ZICOND) { | ||
218 | + /* Probe for Zicond: czero.eqz zero,zero,zero. */ | ||
219 | + got_sigill = 0; | ||
220 | + asm volatile(".insn r 0x33, 5, 0x07, zero, zero, zero" | ||
221 | + : : : "memory"); | ||
222 | + info |= got_sigill ? 0 : CPUINFO_ZICOND; | ||
223 | + left &= ~CPUINFO_ZICOND; | ||
224 | + } | ||
225 | + | ||
226 | + sigaction(SIGILL, &sa_old, NULL); | ||
227 | + assert(left == 0); | ||
228 | + } | ||
229 | + | ||
230 | + info |= CPUINFO_ALWAYS; | ||
231 | + cpuinfo = info; | ||
232 | + return info; | ||
233 | +} | ||
234 | diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc | ||
235 | index XXXXXXX..XXXXXXX 100644 | ||
236 | --- a/tcg/riscv/tcg-target.c.inc | ||
237 | +++ b/tcg/riscv/tcg-target.c.inc | ||
238 | @@ -XXX,XX +XXX,XX @@ static const int tcg_target_call_iarg_regs[] = { | ||
239 | TCG_REG_A7, | ||
240 | }; | ||
241 | |||
242 | -#ifndef have_zbb | ||
243 | -bool have_zbb; | ||
244 | -#endif | ||
245 | -#if defined(__riscv_arch_test) && defined(__riscv_zba) | ||
246 | -# define have_zba true | ||
247 | -#else | ||
248 | -static bool have_zba; | ||
249 | -#endif | ||
250 | -#if defined(__riscv_arch_test) && defined(__riscv_zicond) | ||
251 | -# define have_zicond true | ||
252 | -#else | ||
253 | -static bool have_zicond; | ||
254 | -#endif | ||
255 | - | ||
256 | static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) | ||
257 | { | ||
258 | tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); | ||
259 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) | ||
260 | |||
261 | static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) | ||
262 | { | ||
263 | - if (have_zbb) { | ||
264 | + if (cpuinfo & CPUINFO_ZBB) { | ||
265 | tcg_out_opc_reg(s, OPC_ZEXT_H, ret, arg, TCG_REG_ZERO); | ||
266 | } else { | ||
267 | tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); | ||
268 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) | ||
269 | |||
270 | static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) | ||
271 | { | ||
272 | - if (have_zba) { | ||
273 | + if (cpuinfo & CPUINFO_ZBA) { | ||
274 | tcg_out_opc_reg(s, OPC_ADD_UW, ret, arg, TCG_REG_ZERO); | ||
275 | } else { | ||
276 | tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32); | ||
277 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) | ||
278 | |||
279 | static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) | ||
280 | { | ||
281 | - if (have_zbb) { | ||
282 | + if (cpuinfo & CPUINFO_ZBB) { | ||
283 | tcg_out_opc_imm(s, OPC_SEXT_B, ret, arg, 0); | ||
284 | } else { | ||
285 | tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24); | ||
286 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) | ||
287 | |||
288 | static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) | ||
289 | { | ||
290 | - if (have_zbb) { | ||
291 | + if (cpuinfo & CPUINFO_ZBB) { | ||
292 | tcg_out_opc_imm(s, OPC_SEXT_H, ret, arg, 0); | ||
293 | } else { | ||
294 | tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); | ||
295 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, | ||
296 | int tmpflags; | ||
297 | TCGReg t; | ||
298 | |||
299 | - if (!have_zicond && (!c_cmp2 || cmp2 == 0)) { | ||
300 | + if (!(cpuinfo & CPUINFO_ZICOND) && (!c_cmp2 || cmp2 == 0)) { | ||
301 | tcg_out_movcond_br2(s, cond, ret, cmp1, cmp2, | ||
302 | val1, c_val1, val2, c_val2); | ||
303 | return; | ||
304 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, | ||
305 | tmpflags = tcg_out_setcond_int(s, cond, TCG_REG_TMP0, cmp1, cmp2, c_cmp2); | ||
306 | t = tmpflags & ~SETCOND_FLAGS; | ||
307 | |||
308 | - if (have_zicond) { | ||
309 | + if (cpuinfo & CPUINFO_ZICOND) { | ||
310 | if (tmpflags & SETCOND_INV) { | ||
311 | tcg_out_movcond_zicond(s, ret, t, val2, c_val2, val1, c_val1); | ||
312 | } else { | ||
313 | @@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, | ||
314 | /* TLB Hit - translate address using addend. */ | ||
315 | if (addr_type != TCG_TYPE_I32) { | ||
316 | tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2); | ||
317 | - } else if (have_zba) { | ||
318 | + } else if (cpuinfo & CPUINFO_ZBA) { | ||
319 | tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0, | ||
320 | addr_reg, TCG_REG_TMP2); | ||
321 | } else { | ||
322 | @@ -XXX,XX +XXX,XX @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, | ||
323 | if (addr_type != TCG_TYPE_I32) { | ||
324 | tcg_out_opc_reg(s, OPC_ADD, base, addr_reg, | ||
325 | TCG_GUEST_BASE_REG); | ||
326 | - } else if (have_zba) { | ||
327 | + } else if (cpuinfo & CPUINFO_ZBA) { | ||
328 | tcg_out_opc_reg(s, OPC_ADD_UW, base, addr_reg, | ||
329 | TCG_GUEST_BASE_REG); | ||
330 | } else { | ||
331 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_tb_start(TCGContext *s) | ||
332 | /* nothing to do */ | ||
333 | } | ||
334 | |||
335 | -static volatile sig_atomic_t got_sigill; | ||
336 | - | ||
337 | -static void sigill_handler(int signo, siginfo_t *si, void *data) | ||
338 | -{ | 25 | -{ |
339 | - /* Skip the faulty instruction */ | 26 | - dst[0] = src[0]; |
340 | - ucontext_t *uc = (ucontext_t *)data; | 27 | - dst[1] = src[1]; |
341 | - uc->uc_mcontext.__gregs[REG_PC] += 4; | 28 | - dst[2] = src[2]; |
342 | - | 29 | - dst[3] = src[3]; |
343 | - got_sigill = 1; | 30 | - dst[4] = src[4]; |
31 | - dst[5] = src[5]; | ||
32 | - dst[6] = src[6]; | ||
33 | - dst[7] = src[7]; | ||
344 | -} | 34 | -} |
345 | - | 35 | - |
346 | -static void tcg_target_detect_isa(void) | 36 | void cpu_set_cwp(CPUSPARCState *env, int new_cwp) |
347 | -{ | ||
348 | -#if !defined(have_zba) || !defined(have_zbb) || !defined(have_zicond) | ||
349 | - /* | ||
350 | - * TODO: It is expected that this will be determinable via | ||
351 | - * linux riscv_hwprobe syscall, not yet merged. | ||
352 | - * In the meantime, test via sigill. | ||
353 | - */ | ||
354 | - | ||
355 | - struct sigaction sa_old, sa_new; | ||
356 | - | ||
357 | - memset(&sa_new, 0, sizeof(sa_new)); | ||
358 | - sa_new.sa_flags = SA_SIGINFO; | ||
359 | - sa_new.sa_sigaction = sigill_handler; | ||
360 | - sigaction(SIGILL, &sa_new, &sa_old); | ||
361 | - | ||
362 | -#ifndef have_zba | ||
363 | - /* Probe for Zba: add.uw zero,zero,zero. */ | ||
364 | - got_sigill = 0; | ||
365 | - asm volatile(".insn r 0x3b, 0, 0x04, zero, zero, zero" : : : "memory"); | ||
366 | - have_zba = !got_sigill; | ||
367 | -#endif | ||
368 | - | ||
369 | -#ifndef have_zbb | ||
370 | - /* Probe for Zba: andn zero,zero,zero. */ | ||
371 | - got_sigill = 0; | ||
372 | - asm volatile(".insn r 0x33, 7, 0x20, zero, zero, zero" : : : "memory"); | ||
373 | - have_zbb = !got_sigill; | ||
374 | -#endif | ||
375 | - | ||
376 | -#ifndef have_zicond | ||
377 | - /* Probe for Zicond: czero.eqz zero,zero,zero. */ | ||
378 | - got_sigill = 0; | ||
379 | - asm volatile(".insn r 0x33, 5, 0x07, zero, zero, zero" : : : "memory"); | ||
380 | - have_zicond = !got_sigill; | ||
381 | -#endif | ||
382 | - | ||
383 | - sigaction(SIGILL, &sa_old, NULL); | ||
384 | -#endif | ||
385 | -} | ||
386 | - | ||
387 | static void tcg_target_init(TCGContext *s) | ||
388 | { | 37 | { |
389 | - tcg_target_detect_isa(); | 38 | /* put the modified wrap registers at their proper location */ |
390 | - | 39 | if (env->cwp == env->nwindows - 1) { |
391 | tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; | 40 | - memcpy32(env->regbase, env->regbase + env->nwindows * 16); |
392 | tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; | 41 | + memcpy(env->regbase, env->regbase + env->nwindows * 16, |
393 | 42 | + sizeof(env->gregs)); | |
394 | diff --git a/util/meson.build b/util/meson.build | 43 | } |
395 | index XXXXXXX..XXXXXXX 100644 | 44 | env->cwp = new_cwp; |
396 | --- a/util/meson.build | 45 | |
397 | +++ b/util/meson.build | 46 | /* put the wrap registers at their temporary location */ |
398 | @@ -XXX,XX +XXX,XX @@ elif cpu == 'loongarch64' | 47 | if (new_cwp == env->nwindows - 1) { |
399 | util_ss.add(files('cpuinfo-loongarch.c')) | 48 | - memcpy32(env->regbase + env->nwindows * 16, env->regbase); |
400 | elif cpu in ['ppc', 'ppc64'] | 49 | + memcpy(env->regbase + env->nwindows * 16, env->regbase, |
401 | util_ss.add(files('cpuinfo-ppc.c')) | 50 | + sizeof(env->gregs)); |
402 | +elif cpu in ['riscv32', 'riscv64'] | 51 | } |
403 | + util_ss.add(files('cpuinfo-riscv.c')) | 52 | env->regwptr = env->regbase + (new_cwp * 16); |
404 | endif | 53 | } |
54 | @@ -XXX,XX +XXX,XX @@ void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl) | ||
55 | dst = get_gl_gregset(env, env->gl); | ||
56 | |||
57 | if (src != dst) { | ||
58 | - memcpy32(dst, env->gregs); | ||
59 | - memcpy32(env->gregs, src); | ||
60 | + memcpy(dst, env->gregs, sizeof(env->gregs)); | ||
61 | + memcpy(env->gregs, src, sizeof(env->gregs)); | ||
62 | } | ||
63 | } | ||
64 | |||
65 | @@ -XXX,XX +XXX,XX @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate) | ||
66 | /* Switch global register bank */ | ||
67 | src = get_gregset(env, new_pstate_regs); | ||
68 | dst = get_gregset(env, pstate_regs); | ||
69 | - memcpy32(dst, env->gregs); | ||
70 | - memcpy32(env->gregs, src); | ||
71 | + memcpy(dst, env->gregs, sizeof(env->gregs)); | ||
72 | + memcpy(env->gregs, src, sizeof(env->gregs)); | ||
73 | } else { | ||
74 | trace_win_helper_no_switch_pstate(new_pstate_regs); | ||
75 | } | ||
405 | -- | 76 | -- |
406 | 2.34.1 | 77 | 2.43.0 |
407 | 78 | ||
408 | 79 | diff view generated by jsdifflib |