[v3] target/riscv: Expose RV32 cpu to RV64 QEMU

[PATCH v3 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU

LIU Zhiwei posted 7 patches 4 months, 3 weeks ago

Diff against v1 v2 v4 v5 v6 v7
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20240703144921.1281-1-zhiwei._5Fliu@linux.alibaba.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Cleber Rosa <crosa@redhat.com>, "Philippe Mathieu-Daudé" <philmd@linaro.org>, Wainer dos Santos Moschetta <wainersm@redhat.com>, Beraldo Leal <bleal@redhat.com>

There is a newer version of this series

configs/targets/riscv64-softmmu.mak |  2 +-
hw/riscv/boot.c                     | 35 +++++++++++++++++----------
hw/riscv/sifive_u.c                 |  3 ++-
include/hw/riscv/boot.h             |  4 +++-
include/hw/riscv/boot_opensbi.h     | 29 ++++++++++++++++++++++
target/riscv/cpu.c                  | 17 +++++++++----
target/riscv/cpu.h                  |  5 +++-
target/riscv/cpu_helper.c           | 25 +++++++++++++------
target/riscv/pmp.c                  |  2 +-
tests/avocado/boot_linux_console.py | 37 +++++++++++++++++++++++++++++
10 files changed, 131 insertions(+), 28 deletions(-)

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[PATCH v3 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU

Posted by LIU Zhiwei 4 months, 3 weeks ago

This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
qemu-system-riscv64 can directly boot a RV32 Linux.

This patch set has been tested with 6.9.0 Linux Image.
And add an avocado test in tests/avocado.

v3:
  Rebase to the master branch

v2:
  Remove the line that was inadvertently left in PATCH v1 4/6.
  Add an avocado test.

v1:
  https://mail.gnu.org/archive/html/qemu-riscv/2024-06/msg00501.html

TANG Tiancheng (7):
  target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
  target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
  target/riscv: Correct SXL return value for RV32 in RV64 QEMU
  target/riscv: Detect sxl to set bit width for RV32 in RV64
  target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
  target/riscv: Enable RV32 CPU support in RV64 QEMU
  tests/avocado: Add an avocado test for riscv64

 configs/targets/riscv64-softmmu.mak |  2 +-
 hw/riscv/boot.c                     | 35 +++++++++++++++++----------
 hw/riscv/sifive_u.c                 |  3 ++-
 include/hw/riscv/boot.h             |  4 +++-
 include/hw/riscv/boot_opensbi.h     | 29 ++++++++++++++++++++++
 target/riscv/cpu.c                  | 17 +++++++++----
 target/riscv/cpu.h                  |  5 +++-
 target/riscv/cpu_helper.c           | 25 +++++++++++++------
 target/riscv/pmp.c                  |  2 +-
 tests/avocado/boot_linux_console.py | 37 +++++++++++++++++++++++++++++
 10 files changed, 131 insertions(+), 28 deletions(-)

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2.25.1