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git fetch https://github.com/patchew-project/qemu tags/patchew/20240703014635.1020-1-zhiwei._5Fliu@linux.alibaba.com
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
disas/riscv.c | 183 ++++++++++++++++++++
target/riscv/cpu.c | 8 +
target/riscv/cpu_cfg.h | 4 +
target/riscv/insn16.decode | 1 +
target/riscv/insn32.decode | 33 ++++
target/riscv/insn_trans/trans_rva.c.inc | 51 ++----
target/riscv/insn_trans/trans_rvd.c.inc | 14 +-
target/riscv/insn_trans/trans_rvf.c.inc | 14 +-
target/riscv/insn_trans/trans_rvi.c.inc | 6 +
target/riscv/insn_trans/trans_rvzabha.c.inc | 145 ++++++++++++++++
target/riscv/insn_trans/trans_rvzacas.c.inc | 13 --
target/riscv/insn_trans/trans_rvzcmop.c.inc | 29 ++++
target/riscv/insn_trans/trans_rvzimop.c.inc | 37 ++++
target/riscv/tcg/tcg-cpu.c | 5 +
target/riscv/translate.c | 38 ++++
15 files changed, 531 insertions(+), 50 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvzabha.c.inc
create mode 100644 target/riscv/insn_trans/trans_rvzcmop.c.inc
create mode 100644 target/riscv/insn_trans/trans_rvzimop.c.inc