[v3] Support RISC-V CSR read/write in Qtest environment

[RFC PATCH v3 0/2] Support RISC-V CSR read/write in Qtest environment

Ivan Klokov posted 2 patches 5 months ago

Diff against v1 v2 v4 v5 v6 v6
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Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Thomas Huth <thuth@redhat.com>, Laurent Vivier <lvivier@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>

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target/riscv/cpu.c           | 14 ++++++
target/riscv/cpu.h           |  3 ++
target/riscv/csr.c           | 53 +++++++++++++++++++++-
tests/qtest/libqtest.c       | 27 ++++++++++++
tests/qtest/libqtest.h       | 14 ++++++
tests/qtest/meson.build      |  2 +
tests/qtest/riscv-csr-test.c | 85 ++++++++++++++++++++++++++++++++++++
7 files changed, 197 insertions(+), 1 deletion(-)
create mode 100644 tests/qtest/riscv-csr-test.c

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[RFC PATCH v3 0/2] Support RISC-V CSR read/write in Qtest environment

Posted by Ivan Klokov 5 months ago

These patches add functionality for unit testing RISC-V-specific registers.
The first patch adds a Qtest backend, and the second implements a simple test.

---
v3:
   - Refactor, delete additions to libqos framework
---

Ivan Klokov (2):
  target/riscv: Add RISC-V CSR qtest support
  tests/qtest: QTest example for RISC-V CSR register

 target/riscv/cpu.c           | 14 ++++++
 target/riscv/cpu.h           |  3 ++
 target/riscv/csr.c           | 53 +++++++++++++++++++++-
 tests/qtest/libqtest.c       | 27 ++++++++++++
 tests/qtest/libqtest.h       | 14 ++++++
 tests/qtest/meson.build      |  2 +
 tests/qtest/riscv-csr-test.c | 85 ++++++++++++++++++++++++++++++++++++
 7 files changed, 197 insertions(+), 1 deletion(-)
 create mode 100644 tests/qtest/riscv-csr-test.c

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2.34.1