[v1] target-arm queue

[PULL 00/18] target-arm queue

Peter Maydell posted 18 patches 5 months ago

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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20240622120643.3797539-1-peter.maydell@linaro.org

Maintainers: Radoslaw Biernacki <rad@semihalf.com>, Peter Maydell <peter.maydell@linaro.org>, Leif Lindholm <quic_llindhol@quicinc.com>, Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>, Shannon Zhao <shannon.zhaosl@gmail.com>, "Michael S. Tsirkin" <mst@redhat.com>, Igor Mammedov <imammedo@redhat.com>, Ani Sinha <anisinha@redhat.com>, "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, Alistair Francis <alistair@alistair23.me>, Igor Mitsyanko <i.mitsyanko@gmail.com>, Vikram Garhwal <vikram.garhwal@amd.com>, Francisco Iglesias <francisco.iglesias@amd.com>, Pavel Pisa <pisa@cmp.felk.cvut.cz>, Jason Wang <jasowang@redhat.com>

There is a newer version of this series

docs/system/arm/sbsa.rst            |   4 ++
docs/system/arm/virt.rst            |   6 +-
hw/intc/gic_internal.h              |   8 ++-
include/hw/arm/virt.h               |   5 +-
hw/arm/sbsa-ref.c                   |  23 +++++---
hw/arm/virt-acpi-build.c            |  22 +++++---
hw/arm/virt.c                       |  63 ++++++++++++++++++---
hw/arm/xilinx_zynq.c                |   5 +-
hw/misc/exynos4210_rng.c            |   2 +
hw/net/can/xlnx-versal-canfd.c      |   5 +-
hw/timer/a9gtimer.c                 |   5 ++
hw/usb/hcd-dwc2.c                   |   9 ++-
hw/usb/hcd-ohci.c                   |   4 +-
hw/usb/trace-events                 |   1 +
scripts/coverity-scan/COMPONENTS.md | 107 ++++++++++++++++++------------------
15 files changed, 179 insertions(+), 90 deletions(-)

Expand all Fold all

[PULL 00/18] target-arm queue

Posted by Peter Maydell 5 months ago

Hi; here's the latest target-arm pullreq; this is pretty much
just various bugfixes.

-- PMM

The following changes since commit 02d9c38236cf8c9826e5c5be61780c4444cb4ae0:

  Merge tag 'pull-tcg-20240619' of https://gitlab.com/rth7680/qemu into staging (2024-06-19 14:00:39 -0700)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240622

for you to fetch changes up to 3b36cead6ecc0e40edb8b2f3e253baa01ebc1e9a:

  hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine (2024-06-21 16:24:46 +0100)

----------------------------------------------------------------
target-arm queue:
 * hw/net/can/xlnx-versal-canfd: Fix sorting of the tx queue
 * hw/arm/xilinx_zynq: Fix IRQ/FIQ routing
 * hw/intc/arm_gic: Fix deactivation of SPI lines
 * hw/timer/a9gtimer: Handle QTest mode in a9_gtimer_get_current_cpu
 * hw/misc: Set valid access size for Exynos4210 RNG
 * hw/arm/sbsa-ref: switch to 1GHz timer frequency
 * hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine
 * hw/arm/virt: allow creation of a second NonSecure UART
 * hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUs
 * scripts/coverity-scan/COMPONENTS.md: update component regexes
 * hw/usb/hcd-dwc2: Handle invalid address access in read and write functions
 * hw/usb/hcd-ohci: Fix ohci_service_td: accept zero-length TDs where CBP=BE+1

----------------------------------------------------------------
David Hubbard (1):
      hw/usb/hcd-ohci: Fix ohci_service_td: accept zero-length TDs where CBP=BE+1

Edgar E. Iglesias (1):
      hw/intc/arm_gic: Fix deactivation of SPI lines

Marcin Juszkiewicz (1):
      hw/arm/sbsa-ref: switch to 1GHz timer frequency

Peter Maydell (8):
      scripts/coverity-scan/COMPONENTS.md: Update paths to match gitlab CI
      scripts/coverity-scan/COMPONENTS.md: Fix 'char' component
      scripts/coverity-scan/COMPONENTS.md: Add crypto headers in host/include to the crypto component
      scripts/coverity-scan/COMPONENTS.md: Fix monitor component
      scripts/coverity-scan/COMPONENTS.md: Include libqmp in testlibs
      hw/arm/virt: Add serial aliases in DTB
      hw/arm/virt: Rename VIRT_UART and VIRT_SECURE_UART to VIRT_UART[01]
      hw/arm/virt: allow creation of a second NonSecure UART

Sebastian Huber (1):
      hw/arm/xilinx_zynq: Fix IRQ/FIQ routing

Shiva sagar Myana (1):
      hw/net/can/xlnx-versal-canfd: Fix sorting of the tx queue

Xiong Yining (1):
      hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine

Zhenyu Zhang (1):
      hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUs

Zheyu Ma (3):
      hw/timer/a9gtimer: Handle QTest mode in a9_gtimer_get_current_cpu
      hw/usb/hcd-dwc2: Handle invalid address access in read and write functions
      hw/misc: Set valid access size for Exynos4210 RNG

 docs/system/arm/sbsa.rst            |   4 ++
 docs/system/arm/virt.rst            |   6 +-
 hw/intc/gic_internal.h              |   8 ++-
 include/hw/arm/virt.h               |   5 +-
 hw/arm/sbsa-ref.c                   |  23 +++++---
 hw/arm/virt-acpi-build.c            |  22 +++++---
 hw/arm/virt.c                       |  63 ++++++++++++++++++---
 hw/arm/xilinx_zynq.c                |   5 +-
 hw/misc/exynos4210_rng.c            |   2 +
 hw/net/can/xlnx-versal-canfd.c      |   5 +-
 hw/timer/a9gtimer.c                 |   5 ++
 hw/usb/hcd-dwc2.c                   |   9 ++-
 hw/usb/hcd-ohci.c                   |   4 +-
 hw/usb/trace-events                 |   1 +
 scripts/coverity-scan/COMPONENTS.md | 107 ++++++++++++++++++------------------
 15 files changed, 179 insertions(+), 90 deletions(-)

Re: [PULL 00/18] target-arm queue

Posted by Richard Henderson 5 months ago

On 6/22/24 05:06, Peter Maydell wrote:
> Hi; here's the latest target-arm pullreq; this is pretty much
> just various bugfixes.
> 
> -- PMM
> 
> The following changes since commit 02d9c38236cf8c9826e5c5be61780c4444cb4ae0:
> 
>    Merge tag 'pull-tcg-20240619' ofhttps://gitlab.com/rth7680/qemu  into staging (2024-06-19 14:00:39 -0700)
> 
> are available in the Git repository at:
> 
>    https://git.linaro.org/people/pmaydell/qemu-arm.git  tags/pull-target-arm-20240622
> 
> for you to fetch changes up to 3b36cead6ecc0e40edb8b2f3e253baa01ebc1e9a:
> 
>    hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine (2024-06-21 16:24:46 +0100)
> 
> ----------------------------------------------------------------
> target-arm queue:
>   * hw/net/can/xlnx-versal-canfd: Fix sorting of the tx queue
>   * hw/arm/xilinx_zynq: Fix IRQ/FIQ routing
>   * hw/intc/arm_gic: Fix deactivation of SPI lines
>   * hw/timer/a9gtimer: Handle QTest mode in a9_gtimer_get_current_cpu
>   * hw/misc: Set valid access size for Exynos4210 RNG
>   * hw/arm/sbsa-ref: switch to 1GHz timer frequency
>   * hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine
>   * hw/arm/virt: allow creation of a second NonSecure UART
>   * hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUs
>   * scripts/coverity-scan/COMPONENTS.md: update component regexes
>   * hw/usb/hcd-dwc2: Handle invalid address access in read and write functions
>   * hw/usb/hcd-ohci: Fix ohci_service_td: accept zero-length TDs where CBP=BE+1

Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/9.1 as appropriate.


r~