The following changes since commit 046a64b9801343e2e89eef10c7a48eec8d8c0d4f:

Merge tag 'pull-request-2024-06-12' of https://gitlab.com/thuth/qemu into staging (2024-06-13 07:51:58 -0700)

https://github.com/legoater/qemu/ tags/pull-aspeed-20240614

for you to fetch changes up to d9f6311f5393da897e73be8a29c261125d0c1ac2:

MAINTAINERS: Add reviewers for ASPEED BMCs (2024-06-14 07:36:09 +0200)

* Add AST2700 support

Cédric Le Goater (1):

aspeed/smc: Reintroduce "dram-base" property for AST2700

Jamin Lin (18):

aspeed/wdt: Add AST2700 support

aspeed/sli: Add AST2700 support

aspeed/sdmc: remove redundant macros

aspeed/sdmc: fix coding style

aspeed/sdmc: Add AST2700 support

aspeed/smc: correct device description

aspeed/smc: support dma start length and 1 byte length unit

aspeed/smc: support 64 bits dma dram address

aspeed/smc: support different memory region ops for SMC flash region

aspeed/smc: Add AST2700 support

aspeed/scu: Add AST2700 support

aspeed/intc: Add AST2700 support

aspeed/soc: Add AST2700 support

aspeed: Add an AST2700 eval board

aspeed/soc: fix incorrect dram size for AST2700

test/avocado/machine_aspeed.py: Add AST2700 test case

docs:aspeed: Add AST2700 Evaluation board

MAINTAINERS: Add reviewers for ASPEED BMCs

MAINTAINERS | 3 +

docs/system/arm/aspeed.rst | 39 ++-

include/hw/arm/aspeed_soc.h | 30 +-

include/hw/intc/aspeed_intc.h | 44 +++

include/hw/misc/aspeed_scu.h | 47 ++-

include/hw/misc/aspeed_sdmc.h | 5 +-

include/hw/misc/aspeed_sli.h | 27 ++

include/hw/ssi/aspeed_smc.h | 3 +

include/hw/watchdog/wdt_aspeed.h | 3 +-

hw/arm/aspeed.c | 32 ++

hw/arm/aspeed_ast27x0.c | 648 +++++++++++++++++++++++++++++++++++++++

hw/intc/aspeed_intc.c | 360 ++++++++++++++++++++++

hw/misc/aspeed_scu.c | 306 +++++++++++++++++-

hw/misc/aspeed_sdmc.c | 220 +++++++++++--

hw/misc/aspeed_sli.c | 177 +++++++++++

hw/ssi/aspeed_smc.c | 347 +++++++++++++++++++--

hw/watchdog/wdt_aspeed.c | 24 ++

hw/arm/meson.build | 1 +

hw/intc/meson.build | 1 +

hw/intc/trace-events | 13 +

hw/misc/meson.build | 3 +-

hw/misc/trace-events | 11 +

hw/ssi/trace-events | 2 +-

tests/avocado/machine_aspeed.py | 62 ++++

24 files changed, 2350 insertions(+), 58 deletions(-)

create mode 100644 include/hw/intc/aspeed_intc.h

create mode 100644 include/hw/misc/aspeed_sli.h

create mode 100644 hw/arm/aspeed_ast27x0.c

create mode 100644 hw/intc/aspeed_intc.c

create mode 100644 hw/misc/aspeed_sli.c

From: Jamin Lin <jamin_lin@aspeedtech.com>

AST2700 CPU is ARM Cortex-A35 which is 64 bits.

Add TARGET_AARCH64 to build this machine.

According to the design of ast2700, it has a bootmcu(riscv-32) which

is used for executing SPL.

Then, CPUs(cortex-a35) execute u-boot, kernel and rofs.

Currently, qemu not support emulate two CPU architectures

at the same machine. Therefore, qemu will only support

to emulate CPU(cortex-a35) side for ast2700

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

---

hw/arm/aspeed.c | 32 ++++++++++++++++++++++++++++++++

1 file changed, 32 insertions(+)

#define AST2600_EVB_HW_STRAP1 0x000000C0

#define AST2600_EVB_HW_STRAP2 0x00000003

+#ifdef TARGET_AARCH64

+/* AST2700 evb hardware value */

+#define AST2700_EVB_HW_STRAP1 0x000000C0

+#define AST2700_EVB_HW_STRAP2 0x00000003

+#endif

+

/* Tacoma hardware value */

#define TACOMA_BMC_HW_STRAP1 0x00000000

#define TACOMA_BMC_HW_STRAP2 0x00000040

@@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,

aspeed_machine_class_init_cpus_defaults(mc);

}

+#ifdef TARGET_AARCH64

+static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *data)

+{

+ MachineClass *mc = MACHINE_CLASS(oc);

+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);

+

+ mc->desc = "Aspeed AST2700 EVB (Cortex-A35)";

+ amc->soc_name = "ast2700-a0";

+ amc->hw_strap1 = AST2700_EVB_HW_STRAP1;

+ amc->hw_strap2 = AST2700_EVB_HW_STRAP2;

+ amc->fmc_model = "w25q01jvq";

+ amc->spi_model = "w25q512jv";

+ amc->num_cs = 2;

+ amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON;

+ amc->uart_default = ASPEED_DEV_UART12;

+ mc->default_ram_size = 1 * GiB;

+ aspeed_machine_class_init_cpus_defaults(mc);

+}

+#endif

+

static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,

void *data)

.name = MACHINE_TYPE_NAME("ast1030-evb"),

.parent = TYPE_ASPEED_MACHINE,

.class_init = aspeed_minibmc_machine_ast1030_evb_class_init,

+#ifdef TARGET_AARCH64

+ }, {

+ .name = MACHINE_TYPE_NAME("ast2700-evb"),

+ .parent = TYPE_ASPEED_MACHINE,

+ .class_init = aspeed_machine_ast2700_evb_class_init,

+#endif

.name = TYPE_ASPEED_MACHINE,

.parent = TYPE_MACHINE,

2.45.2

Add AST2700 Evaluation board and its boot command.

Reviewed-by: Cédric Le Goater <clg@kaod.org>

docs/system/arm/aspeed.rst | 39 ++++++++++++++++++++++++++++++++++----

1 file changed, 35 insertions(+), 4 deletions(-)

diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst

--- a/docs/system/arm/aspeed.rst

+++ b/docs/system/arm/aspeed.rst

@@ -XXX,XX +XXX,XX @@

-Aspeed family boards (``*-bmc``, ``ast2500-evb``, ``ast2600-evb``)

-==================================================================

+Aspeed family boards (``*-bmc``, ``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``)

+===================================================================================

The QEMU Aspeed machines model BMCs of various OpenPOWER systems and

Aspeed evaluation boards. They are based on different releases of the

Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the

-AST2500 with an ARM1176JZS CPU (800MHz) and more recently the AST2600

-with dual cores ARM Cortex-A7 CPUs (1.2GHz).

+AST2500 with an ARM1176JZS CPU (800MHz), the AST2600

+with dual cores ARM Cortex-A7 CPUs (1.2GHz) and more recently the AST2700

+with quad cores ARM Cortex-A35 64 bits CPUs (1.6GHz)

The SoC comes with RAM, Gigabit ethernet, USB, SD/MMC, USB, SPI, I2C,

etc.

@@ -XXX,XX +XXX,XX @@ AST2600 SoC based machines :

- ``qcom-dc-scm-v1-bmc`` Qualcomm DC-SCM V1 BMC

- ``qcom-firework-bmc`` Qualcomm Firework BMC

+AST2700 SoC based machines :

+

+- ``ast2700-evb`` Aspeed AST2700 Evaluation board (Cortex-A35)

+

Supported devices

-----------------

@@ -XXX,XX +XXX,XX @@ Supported devices

* eMMC Boot Controller (dummy)

* PECI Controller (minimal)

* I3C Controller

+ * Internal Bridge Controller (SLI dummy)

Missing devices

@@ -XXX,XX +XXX,XX @@ or directly from the OpenBMC GitHub release repository :

https://github.com/openbmc/openbmc/releases

+or directly from the ASPEED Forked OpenBMC GitHub release repository :

+

+ https://github.com/AspeedTech-BMC/openbmc/releases

+

To boot a kernel directly from a Linux build tree:

.. code-block:: bash

@@ -XXX,XX +XXX,XX @@ under Linux), use :

-M ast2500-evb,bmc-console=uart3

+

+Boot the AST2700 machine from the flash image, use an MTD drive :

+

+.. code-block:: bash

+

+ IMGDIR=ast2700-default

+ UBOOT_SIZE=$(stat --format=%s -L ${IMGDIR}/u-boot-nodtb.bin)

+

+ $ qemu-system-aarch64 -M ast2700-evb \

+ -device loader,force-raw=on,addr=0x400000000,file=${IMGDIR}/u-boot-nodtb.bin \

+ -device loader,force-raw=on,addr=$((0x400000000 + ${UBOOT_SIZE})),file=${IMGDIR}/u-boot.dtb \

+ -device loader,force-raw=on,addr=0x430000000,file=${IMGDIR}/bl31.bin \

+ -device loader,force-raw=on,addr=0x430080000,file=${IMGDIR}/optee/tee-raw.bin \

+ -device loader,cpu-num=0,addr=0x430000000 \

+ -device loader,cpu-num=1,addr=0x430000000 \

+ -device loader,cpu-num=2,addr=0x430000000 \

+ -device loader,cpu-num=3,addr=0x430000000 \

+ -smp 4 \

+ -drive file=${IMGDIR}/image-bmc,format=raw,if=mtd \

+ -nographic

+

Aspeed minibmc family boards (``ast1030-evb``)

==================================================================

2.45.2

Fix coding style issues from checkpatch.pl

Test command:

scripts/checkpatch.pl --no-tree -f hw/misc/aspeed_sdmc.c

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

---

hw/misc/aspeed_sdmc.c | 11 +++++++----

1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c

--- a/hw/misc/aspeed_sdmc.c

+++ b/hw/misc/aspeed_sdmc.c

@@ -XXX,XX +XXX,XX @@ static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg,

uint32_t data)

{

if (reg == R_PROT) {

- s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;

+ s->regs[reg] =

+ (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;

@@ -XXX,XX +XXX,XX @@ static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg,

uint32_t data)

{

if (reg == R_PROT) {

- s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;

+ s->regs[reg] =

+ (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;

return;

}

@@ -XXX,XX +XXX,XX @@ static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg,

}

if (s->regs[R_PROT] == PROT_HARDLOCKED) {

- qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked until system reset!\n",

- __func__);

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: SDMC is locked until system reset!\n",

+ __func__);

return;

}

2.45.2

AST2700 support the maximum dram size is 8GiB

and has a "DMA DRAM Side Address High Part(0x7C)"

register to support 64 bits dma dram address.

Add helper routines functions to compute the dma dram

address, new features and update trace-event

to support 64 bits dram address.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>

hw/ssi/aspeed_smc.c | 51 ++++++++++++++++++++++++++++++++++++++-------

hw/ssi/trace-events | 2 +-

2 files changed, 44 insertions(+), 9 deletions(-)

diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c

--- a/hw/ssi/aspeed_smc.c

+++ b/hw/ssi/aspeed_smc.c

#define FMC_WDT2_CTRL_BOOT_SOURCE BIT(4) /* O: primary 1: alternate */

#define FMC_WDT2_CTRL_EN BIT(0)

+/* DMA DRAM Side Address High Part (AST2700) */

+#define R_DMA_DRAM_ADDR_HIGH (0x7c / 4)

/* DMA Control/Status Register */

#define R_DMA_CTRL (0x80 / 4)

#define DMA_CTRL_REQUEST (1 << 31)

@@ -XXX,XX +XXX,XX @@

* 0x1FFFFFF: 32M bytes

*/

#define DMA_DRAM_ADDR(asc, val) ((val) & (asc)->dma_dram_mask)

+#define DMA_DRAM_ADDR_HIGH(val) ((val) & 0xf)

#define DMA_FLASH_ADDR(asc, val) ((val) & (asc)->dma_flash_mask)

#define DMA_LENGTH(val) ((val) & 0x01FFFFFF)

@@ -XXX,XX +XXX,XX @@ static const AspeedSegments aspeed_2500_spi2_segments[];

#define ASPEED_SMC_FEATURE_DMA 0x1

#define ASPEED_SMC_FEATURE_DMA_GRANT 0x2

#define ASPEED_SMC_FEATURE_WDT_CONTROL 0x4

+#define ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH 0x08

static inline bool aspeed_smc_has_dma(const AspeedSMCClass *asc)

@@ -XXX,XX +XXX,XX @@ static inline bool aspeed_smc_has_wdt_control(const AspeedSMCClass *asc)

return !!(asc->features & ASPEED_SMC_FEATURE_WDT_CONTROL);

+static inline bool aspeed_smc_has_dma64(const AspeedSMCClass *asc)

+ return !!(asc->features & ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH);

#define aspeed_smc_error(fmt, ...) \

qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt "\n", __func__, ## __VA_ARGS__)

@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)

(aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) ||

(aspeed_smc_has_dma(asc) && addr == R_DMA_FLASH_ADDR) ||

(aspeed_smc_has_dma(asc) && addr == R_DMA_DRAM_ADDR) ||

+ (aspeed_smc_has_dma(asc) && aspeed_smc_has_dma64(asc) &&

+ addr == R_DMA_DRAM_ADDR_HIGH) ||

(aspeed_smc_has_dma(asc) && addr == R_DMA_LEN) ||

(aspeed_smc_has_dma(asc) && addr == R_DMA_CHECKSUM) ||

(addr >= R_SEG_ADDR0 &&

@@ -XXX,XX +XXX,XX @@ static bool aspeed_smc_inject_read_failure(AspeedSMCState *s)

}

}

+static uint64_t aspeed_smc_dma_dram_addr(AspeedSMCState *s)

+ return s->regs[R_DMA_DRAM_ADDR] |

+ ((uint64_t) s->regs[R_DMA_DRAM_ADDR_HIGH] << 32);

static uint32_t aspeed_smc_dma_len(AspeedSMCState *s)

{

AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);

@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s)

static void aspeed_smc_dma_rw(AspeedSMCState *s)

{

+ AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);

+ uint64_t dma_dram_offset;

+ uint64_t dma_dram_addr;

MemTxResult result;

uint32_t dma_len;

uint32_t data;

dma_len = aspeed_smc_dma_len(s);

+ dma_dram_addr = aspeed_smc_dma_dram_addr(s);

+ if (aspeed_smc_has_dma64(asc)) {

+ dma_dram_offset = dma_dram_addr - s->dram_base;

+ } else {

+ dma_dram_offset = dma_dram_addr;

+ }

trace_aspeed_smc_dma_rw(s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE ?

"write" : "read",

s->regs[R_DMA_FLASH_ADDR],

- s->regs[R_DMA_DRAM_ADDR],

+ dma_dram_offset,

dma_len);

while (dma_len) {

if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {

- data = address_space_ldl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR],

+ data = address_space_ldl_le(&s->dram_as, dma_dram_offset,

MEMTXATTRS_UNSPECIFIED, &result);

if (result != MEMTX_OK) {

- aspeed_smc_error("DRAM read failed @%08x",

- s->regs[R_DMA_DRAM_ADDR]);

+ aspeed_smc_error("DRAM read failed @%" PRIx64,

+ dma_dram_offset);

return;

}

@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_dma_rw(AspeedSMCState *s)

return;

}

- address_space_stl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR],

+ address_space_stl_le(&s->dram_as, dma_dram_offset,

data, MEMTXATTRS_UNSPECIFIED, &result);

if (result != MEMTX_OK) {

- aspeed_smc_error("DRAM write failed @%08x",

- s->regs[R_DMA_DRAM_ADDR]);

+ aspeed_smc_error("DRAM write failed @%" PRIx64,

+ dma_dram_offset);

return;

}

}

@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_dma_rw(AspeedSMCState *s)

* When the DMA is on-going, the DMA registers are updated

* with the current working addresses and length.

*/

+ dma_dram_offset += 4;

+ dma_dram_addr += 4;

+ s->regs[R_DMA_DRAM_ADDR_HIGH] = dma_dram_addr >> 32;

+ s->regs[R_DMA_DRAM_ADDR] = dma_dram_addr & 0xffffffff;

s->regs[R_DMA_FLASH_ADDR] += 4;

- s->regs[R_DMA_DRAM_ADDR] += 4;

dma_len -= 4;

s->regs[R_DMA_LEN] = dma_len;

s->regs[R_DMA_CHECKSUM] += data;

@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,

} else if (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN &&

aspeed_smc_dma_granted(s)) {

s->regs[addr] = DMA_LENGTH(value);

+ } else if (aspeed_smc_has_dma(asc) && aspeed_smc_has_dma64(asc) &&

+ addr == R_DMA_DRAM_ADDR_HIGH) {

+ s->regs[addr] = DMA_DRAM_ADDR_HIGH(value);

} else {

qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",

__func__, addr);

diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/ssi/trace-events

+++ b/hw/ssi/trace-events

@@ -XXX,XX +XXX,XX @@ aspeed_smc_do_snoop(int cs, int index, int dummies, int data) "CS%d index:0x%x d

aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d"

aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64

aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x"

-aspeed_smc_dma_rw(const char *dir, uint32_t flash_addr, uint32_t dram_addr, uint32_t size) "%s flash:@0x%08x dram:@0x%08x size:0x%08x"

+aspeed_smc_dma_rw(const char *dir, uint32_t flash_addr, uint64_t dram_addr, uint32_t size) "%s flash:@0x%08x dram:@0x%" PRIx64 " size:0x%08x"

aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64

aspeed_smc_flash_select(int cs, const char *prefix) "CS%d %sselect"

2.45.2

AST2700 wdt controller is similiar to AST2600's wdt, but

the AST2700 has 8 watchdogs, and they each have 0x80 of registers.

Introduce ast2700 object class and increase the number of regs(offset) of

ast2700 model.

Reviewed-by: Cédric Le Goater <clg@kaod.org>

include/hw/watchdog/wdt_aspeed.h | 3 ++-

hw/watchdog/wdt_aspeed.c | 24 ++++++++++++++++++++++++

2 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h

--- a/include/hw/watchdog/wdt_aspeed.h

+++ b/include/hw/watchdog/wdt_aspeed.h

@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(AspeedWDTState, AspeedWDTClass, ASPEED_WDT)

#define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400"

#define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500"

#define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600"

+#define TYPE_ASPEED_2700_WDT TYPE_ASPEED_WDT "-ast2700"

#define TYPE_ASPEED_1030_WDT TYPE_ASPEED_WDT "-ast1030"

-#define ASPEED_WDT_REGS_MAX (0x30 / 4)

+#define ASPEED_WDT_REGS_MAX (0x80 / 4)

struct AspeedWDTState {

/*< private >*/

diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c

--- a/hw/watchdog/wdt_aspeed.c

+++ b/hw/watchdog/wdt_aspeed.c

@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_1030_wdt_info = {

.class_init = aspeed_1030_wdt_class_init,

};

+static void aspeed_2700_wdt_class_init(ObjectClass *klass, void *data)

+ AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);

+ dc->desc = "ASPEED 2700 Watchdog Controller";

+ awc->iosize = 0x80;

+ awc->ext_pulse_width_mask = 0xfffff; /* TODO */

+ awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;

+ awc->reset_pulse = aspeed_2500_wdt_reset_pulse;

+ awc->wdt_reload = aspeed_wdt_reload_1mhz;

+ awc->sanitize_ctrl = aspeed_2600_sanitize_ctrl;

+ awc->default_status = 0x014FB180;

+ awc->default_reload_value = 0x014FB180;

+static const TypeInfo aspeed_2700_wdt_info = {

+ .name = TYPE_ASPEED_2700_WDT,

+ .parent = TYPE_ASPEED_WDT,

+ .instance_size = sizeof(AspeedWDTState),

+ .class_init = aspeed_2700_wdt_class_init,

+};

+

static void wdt_aspeed_register_types(void)

{

type_register_static(&aspeed_wdt_info);

type_register_static(&aspeed_2400_wdt_info);

type_register_static(&aspeed_2500_wdt_info);

type_register_static(&aspeed_2600_wdt_info);

+ type_register_static(&aspeed_2700_wdt_info);

type_register_static(&aspeed_1030_wdt_info);

}

2.45.2

AST2700 dram size calculation is not back compatible AST2600.

According to the DDR capacity hardware behavior,

if users write the data to the address which is beyond the ram size,

it would write the data to the "address % ram_size".

For example:

a. sdram base address "0x4 00000000"

b. sdram size 1 GiB

The available address range is from "0x4 00000000" to "0x4 3FFFFFFF".

If users write 0x12345678 to address "0x5 00000000",

the value of DRAM address 0 (base address 0x4 00000000) will be 0x12345678.

include/hw/arm/aspeed_soc.h | 2 +

hw/arm/aspeed_ast27x0.c | 87 ++++++++++++++++++++++++++++++++++++-

2 files changed, 88 insertions(+), 1 deletion(-)

@@ -XXX,XX +XXX,XX @@

#include "sysemu/sysemu.h"

#include "hw/intc/arm_gicv3.h"

#include "qapi/qmp/qlist.h"

+#include "qemu/log.h"

static const hwaddr aspeed_soc_ast2700_memmap[] = {

[ASPEED_DEV_SPI_BOOT] = 0x400000000,

@@ -XXX,XX +XXX,XX @@ static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev)

return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]);

+static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr,

+ unsigned int size)

+{

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: DRAM read out of ram size, addr:0x%" PRIx64 "\n",

+ __func__, addr);

+ return 0;

+}

+static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data,

+ unsigned int size)

+{

+ AspeedSoCState *s = ASPEED_SOC(opaque);

+ ram_addr_t ram_size;

+ MemTxResult result;

+

+ ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",

+ &error_abort);

+

+ /*

+ * Emulate ddr capacity hardware behavior.

+ * If writes the data to the address which is beyond the ram size,

+ * it would write the data to the "address % ram_size".

+ */

+ result = address_space_write(&s->dram_as, addr % ram_size,

+ MEMTXATTRS_UNSPECIFIED, &data, 4);

+ if (result != MEMTX_OK) {

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: DRAM write failed, addr:0x%" HWADDR_PRIx

+ ", data :0x%" PRIx64 "\n",

+ __func__, addr % ram_size, data);

+ }

+}

+

+static const MemoryRegionOps aspeed_ram_capacity_ops = {

+ .read = aspeed_ram_capacity_read,

+ .write = aspeed_ram_capacity_write,

+ .endianness = DEVICE_LITTLE_ENDIAN,

+ .valid = {

+ .min_access_size = 1,

+ .max_access_size = 8,

+ },

+};

+

+/*

+ * SDMC should be realized first to get correct RAM size and max size

+ * values

+ */

+static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp)

+{

+ ram_addr_t ram_size, max_ram_size;

+ Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);

+ AspeedSoCState *s = ASPEED_SOC(dev);

+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);

+

+ ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",

+ &error_abort);

+ max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",

+ &error_abort);

+

+ memory_region_init(&s->dram_container, OBJECT(s), "ram-container",

+ ram_size);

+ memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);

+ address_space_init(&s->dram_as, s->dram_mr, "dram");

+

+ /*

+ * Add a memory region beyond the RAM region to emulate

+ * ddr capacity hardware behavior.

+ */

+ if (ram_size < max_ram_size) {

+ memory_region_init_io(&a->dram_empty, OBJECT(s),

+ &aspeed_ram_capacity_ops, s,

+ "ram-empty", max_ram_size - ram_size);

+

+ memory_region_add_subregion(s->memory,

+ sc->memmap[ASPEED_DEV_SDRAM] + ram_size,

+ &a->dram_empty);

+ }

+

+ memory_region_add_subregion(s->memory,

+ sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);

+ return true;

+}

+

static void aspeed_soc_ast2700_init(Object *obj)

{

Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj);

@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)

sc->memmap[ASPEED_DEV_SDMC]);

/* RAM */

- if (!aspeed_soc_dram_init(s, errp)) {

+ if (!aspeed_soc_ast2700_dram_init(dev, errp)) {

return;

}

2.45.2

AST2700 have two SCU controllers which are SCU and SCUIO.

Both SCU and SCUIO registers are not compatible previous SOCs

, introduces new registers and adds ast2700 scu, sucio class init handler.

The pclk divider selection of SCUIO is defined in SCUIO280[20:18] and

the pclk divider selection of SCU is defined in SCU280[25:23].

Both of them are not compatible AST2600 SOCs, adds a get_apb_freq function

and trace-event for AST2700 SCU and SCUIO.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

---

include/hw/misc/aspeed_scu.h | 47 +++++-

hw/misc/aspeed_scu.c | 306 ++++++++++++++++++++++++++++++++++-

hw/misc/trace-events | 4 +

3 files changed, 351 insertions(+), 6 deletions(-)

diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h

--- a/include/hw/misc/aspeed_scu.h

+++ b/include/hw/misc/aspeed_scu.h

@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(AspeedSCUState, AspeedSCUClass, ASPEED_SCU)

#define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"

#define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"

#define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600"

+#define TYPE_ASPEED_2700_SCU TYPE_ASPEED_SCU "-ast2700"

+#define TYPE_ASPEED_2700_SCUIO TYPE_ASPEED_SCU "io" "-ast2700"

#define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030"

#define ASPEED_SCU_NR_REGS (0x1A8 >> 2)

#define ASPEED_AST2600_SCU_NR_REGS (0xE20 >> 2)

+#define ASPEED_AST2700_SCU_NR_REGS (0xE20 >> 2)

struct AspeedSCUState {

/*< private >*/

@@ -XXX,XX +XXX,XX @@ struct AspeedSCUState {

/*< public >*/

MemoryRegion iomem;

- uint32_t regs[ASPEED_AST2600_SCU_NR_REGS];

+ uint32_t regs[ASPEED_AST2700_SCU_NR_REGS];

uint32_t silicon_rev;

uint32_t hw_strap1;

uint32_t hw_strap2;

@@ -XXX,XX +XXX,XX @@ struct AspeedSCUState {

#define AST2600_A3_SILICON_REV 0x05030303U

#define AST1030_A0_SILICON_REV 0x80000000U

#define AST1030_A1_SILICON_REV 0x80010000U

+#define AST2700_A0_SILICON_REV 0x06000103U

+#define AST2720_A0_SILICON_REV 0x06000203U

+#define AST2750_A0_SILICON_REV 0x06000003U

#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)

@@ -XXX,XX +XXX,XX @@ uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s);

* 1. 2012/12/29 Ryan Chen Create

*/

-/* SCU08 Clock Selection Register

+/*

+ * SCU08 Clock Selection Register

*

* 31 Enable Video Engine clock dynamic slow down

* 30:28 Video Engine clock slow down setting

@@ -XXX,XX +XXX,XX @@ uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s);

*/

#define SCU_CLK_GET_PCLK_DIV(x) (((x) >> 23) & 0x7)

-/* SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC)

+/*

+ * SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC)

*

* 18 H-PLL parameter selection

* 0: Select H-PLL by strapping resistors

@@ -XXX,XX +XXX,XX @@ uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s);

#define SCU_AST2400_H_PLL_BYPASS_EN (0x1 << 17)

#define SCU_AST2400_H_PLL_OFF (0x1 << 16)

-/* SCU24 H-PLL Parameter Register (for Aspeed AST2500 SOC)

+/*

+ * SCU24 H-PLL Parameter Register (for Aspeed AST2500 SOC)

*

* 21 Enable H-PLL reset

* 20 Enable H-PLL bypass mode

@@ -XXX,XX +XXX,XX @@ uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s);

#define SCU_H_PLL_BYPASS_EN (0x1 << 20)

#define SCU_H_PLL_OFF (0x1 << 19)

-/* SCU70 Hardware Strapping Register definition (for Aspeed AST2400 SOC)

+/*

+ * SCU70 Hardware Strapping Register definition (for Aspeed AST2400 SOC)

*

* 31:29 Software defined strapping registers

* 28:27 DRAM size setting (for VGA driver use)

@@ -XXX,XX +XXX,XX @@ uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s);

*/

#define SCU_AST1030_CLK_GET_PCLK_DIV(x) (((x) >> 8) & 0xf)

+/*

+ * SCU280 Clock Selection 1 Register (for Aspeed AST2700 SCUIO)

+ *

+ * 31:29 MHCLK_DIV

+ * 28 Reserved

+ * 27:25 RGMIICLK_DIV

+ * 24 Reserved

+ * 23:21 RMIICLK_DIV

+ * 20:18 PCLK_DIV

+ * 17:14 SDCLK_DIV

+ * 13 SDCLK_SEL

+ * 12 UART13CLK_SEL

+ * 11 UART12CLK_SEL

+ * 10 UART11CLK_SEL

+ * 9 UART10CLK_SEL

+ * 8 UART9CLK_SEL

+ * 7 UART8CLK_SEL

+ * 6 UART7CLK_SEL

+ * 5 UART6CLK_SEL

+ * 4 UARTDBCLK_SEL

+ * 3 UART4CLK_SEL

+ * 2 UART3CLK_SEL

+ * 1 UART2CLK_SEL

+ * 0 UART1CLK_SEL

+ */

+#define SCUIO_AST2700_CLK_GET_PCLK_DIV(x) (((x) >> 18) & 0x7)

#endif /* ASPEED_SCU_H */

diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/aspeed_scu.c

+++ b/hw/misc/aspeed_scu.c

@@ -XXX,XX +XXX,XX @@

#define AST2600_CLK TO_REG(0x40)

+#define AST2700_SILICON_REV TO_REG(0x00)

+#define AST2700_HW_STRAP1 TO_REG(0x10)

+#define AST2700_HW_STRAP1_CLR TO_REG(0x14)

+#define AST2700_HW_STRAP1_LOCK TO_REG(0x20)

+#define AST2700_HW_STRAP1_SEC1 TO_REG(0x24)

+#define AST2700_HW_STRAP1_SEC2 TO_REG(0x28)

+#define AST2700_HW_STRAP1_SEC3 TO_REG(0x2C)

+#define AST2700_SCU_CLK_SEL_1 TO_REG(0x280)

+#define AST2700_SCU_HPLL_PARAM TO_REG(0x300)

+#define AST2700_SCU_HPLL_EXT_PARAM TO_REG(0x304)

+#define AST2700_SCU_DPLL_PARAM TO_REG(0x308)

+#define AST2700_SCU_DPLL_EXT_PARAM TO_REG(0x30c)

+#define AST2700_SCU_MPLL_PARAM TO_REG(0x310)

+#define AST2700_SCU_MPLL_EXT_PARAM TO_REG(0x314)

+#define AST2700_SCU_D1CLK_PARAM TO_REG(0x320)

+#define AST2700_SCU_D2CLK_PARAM TO_REG(0x330)

+#define AST2700_SCU_CRT1CLK_PARAM TO_REG(0x340)

+#define AST2700_SCU_CRT2CLK_PARAM TO_REG(0x350)

+#define AST2700_SCU_MPHYCLK_PARAM TO_REG(0x360)

+#define AST2700_SCU_FREQ_CNTR TO_REG(0x3b0)

+#define AST2700_SCU_CPU_SCRATCH_0 TO_REG(0x780)

+#define AST2700_SCU_CPU_SCRATCH_1 TO_REG(0x784)

+

+#define AST2700_SCUIO_CLK_STOP_CTL_1 TO_REG(0x240)

+#define AST2700_SCUIO_CLK_STOP_CLR_1 TO_REG(0x244)

+#define AST2700_SCUIO_CLK_STOP_CTL_2 TO_REG(0x260)

+#define AST2700_SCUIO_CLK_STOP_CLR_2 TO_REG(0x264)

+#define AST2700_SCUIO_CLK_SEL_1 TO_REG(0x280)

+#define AST2700_SCUIO_CLK_SEL_2 TO_REG(0x284)

+#define AST2700_SCUIO_HPLL_PARAM TO_REG(0x300)

+#define AST2700_SCUIO_HPLL_EXT_PARAM TO_REG(0x304)

+#define AST2700_SCUIO_APLL_PARAM TO_REG(0x310)

+#define AST2700_SCUIO_APLL_EXT_PARAM TO_REG(0x314)

+#define AST2700_SCUIO_DPLL_PARAM TO_REG(0x320)

+#define AST2700_SCUIO_DPLL_EXT_PARAM TO_REG(0x324)

+#define AST2700_SCUIO_DPLL_PARAM_READ TO_REG(0x328)

+#define AST2700_SCUIO_DPLL_EXT_PARAM_READ TO_REG(0x32c)

+#define AST2700_SCUIO_UARTCLK_GEN TO_REG(0x330)

+#define AST2700_SCUIO_HUARTCLK_GEN TO_REG(0x334)

+#define AST2700_SCUIO_CLK_DUTY_MEAS_RST TO_REG(0x388)

+

#define SCU_IO_REGION_SIZE 0x1000

static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = {

@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_1030_scu_get_apb_freq(AspeedSCUState *s)

/ asc->apb_divider;

+static uint32_t aspeed_2700_scu_get_apb_freq(AspeedSCUState *s)

+{

+ AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s);

+ uint32_t hpll = asc->calc_hpll(s, s->regs[AST2700_SCU_HPLL_PARAM]);

+

+ return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[AST2700_SCU_CLK_SEL_1]) + 1)

+ / asc->apb_divider;

+}

+

+static uint32_t aspeed_2700_scuio_get_apb_freq(AspeedSCUState *s)

+{

+ AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s);

+ uint32_t hpll = asc->calc_hpll(s, s->regs[AST2700_SCUIO_HPLL_PARAM]);

+

+ return hpll /

+ (SCUIO_AST2700_CLK_GET_PCLK_DIV(s->regs[AST2700_SCUIO_CLK_SEL_1]) + 1)

+ / asc->apb_divider;

+}

+

static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)

{

AspeedSCUState *s = ASPEED_SCU(opaque);

@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)

switch (reg) {

case RNG_DATA:

- /* On hardware, RNG_DATA works regardless of

+ /*

+ * On hardware, RNG_DATA works regardless of

* the state of the enable bit in RNG_CTRL

*/

s->regs[RNG_DATA] = aspeed_scu_get_random();

@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_silicon_revs[] = {

AST2600_A3_SILICON_REV,

AST1030_A0_SILICON_REV,

AST1030_A1_SILICON_REV,

+ AST2700_A0_SILICON_REV,

+ AST2720_A0_SILICON_REV,

+ AST2750_A0_SILICON_REV,

};

bool is_supported_silicon_rev(uint32_t silicon_rev)

@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_2600_scu_info = {

.class_init = aspeed_2600_scu_class_init,

};

+static uint64_t aspeed_ast2700_scu_read(void *opaque, hwaddr offset,

+ unsigned size)

+{

+ AspeedSCUState *s = ASPEED_SCU(opaque);

+ int reg = TO_REG(offset);

+

+ if (reg >= ASPEED_AST2700_SCU_NR_REGS) {

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",

+ __func__, offset);

+ return 0;

+ }

+

+ switch (reg) {

+ default:

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Unhandled read at offset 0x%" HWADDR_PRIx "\n",

+ __func__, offset);

+ }

+

+ trace_aspeed_ast2700_scu_read(offset, size, s->regs[reg]);

+ return s->regs[reg];

+}

+

+static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,

+ uint64_t data64, unsigned size)

+{

+ AspeedSCUState *s = ASPEED_SCU(opaque);

+ int reg = TO_REG(offset);

+ /* Truncate here so bitwise operations below behave as expected */

+ uint32_t data = data64;

+

+ if (reg >= ASPEED_AST2700_SCU_NR_REGS) {

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",

+ __func__, offset);

+ trace_aspeed_ast2700_scu_write(offset, size, data);

+

+ switch (reg) {

+ default:

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: Unhandeled write at offset 0x%" HWADDR_PRIx "\n",

+ __func__, offset);

+ break;

+ }

+

+ s->regs[reg] = data;

+}

+

+static const MemoryRegionOps aspeed_ast2700_scu_ops = {

+ .read = aspeed_ast2700_scu_read,

+ .write = aspeed_ast2700_scu_write,

+ .endianness = DEVICE_LITTLE_ENDIAN,

+ .valid.min_access_size = 1,

+ .valid.max_access_size = 8,

+ .valid.unaligned = false,

+};

+

+static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {

+ [AST2700_SILICON_REV] = AST2700_A0_SILICON_REV,

+ [AST2700_HW_STRAP1] = 0x00000800,

+ [AST2700_HW_STRAP1_CLR] = 0xFFF0FFF0,

+ [AST2700_HW_STRAP1_LOCK] = 0x00000FFF,

+ [AST2700_HW_STRAP1_SEC1] = 0x000000FF,

+ [AST2700_HW_STRAP1_SEC2] = 0x00000000,

+ [AST2700_HW_STRAP1_SEC3] = 0x1000408F,

+ [AST2700_SCU_HPLL_PARAM] = 0x0000009f,

+ [AST2700_SCU_HPLL_EXT_PARAM] = 0x8000004f,

+ [AST2700_SCU_DPLL_PARAM] = 0x0080009f,

+ [AST2700_SCU_DPLL_EXT_PARAM] = 0x8000004f,

+ [AST2700_SCU_MPLL_PARAM] = 0x00000040,

+ [AST2700_SCU_MPLL_EXT_PARAM] = 0x80000000,

+ [AST2700_SCU_D1CLK_PARAM] = 0x00050002,

+ [AST2700_SCU_D2CLK_PARAM] = 0x00050002,

+ [AST2700_SCU_CRT1CLK_PARAM] = 0x00050002,

+ [AST2700_SCU_CRT2CLK_PARAM] = 0x00050002,

+ [AST2700_SCU_MPHYCLK_PARAM] = 0x0000004c,

+ [AST2700_SCU_FREQ_CNTR] = 0x000375eb,

+ [AST2700_SCU_CPU_SCRATCH_0] = 0x00000000,

+ [AST2700_SCU_CPU_SCRATCH_1] = 0x00000004,

+};

+

+static void aspeed_ast2700_scu_reset(DeviceState *dev)

+{

+ AspeedSCUState *s = ASPEED_SCU(dev);

+ AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);

+

+ memcpy(s->regs, asc->resets, asc->nr_regs * 4);

+}

+

+static void aspeed_2700_scu_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);

+ AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);

+

+ dc->desc = "ASPEED 2700 System Control Unit";

+ dc->reset = aspeed_ast2700_scu_reset;

+ asc->resets = ast2700_a0_resets;

+ asc->calc_hpll = aspeed_2600_scu_calc_hpll;