[RFC PATCH 0/2] Support RISC-V CSR read/write in Qtest environment

Ivan Klokov posted 2 patches 5 months, 2 weeks ago
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git fetch https://github.com/patchew-project/qemu tags/patchew/20240613095601.16299-1-ivan.klokov@syntacore.com
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Thomas Huth <thuth@redhat.com>, Laurent Vivier <lvivier@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>
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target/riscv/cpu.c             | 13 +++++++
target/riscv/cpu.h             |  3 ++
target/riscv/csr.c             | 49 +++++++++++++++++++++++-
tests/qtest/libqos/meson.build |  3 ++
tests/qtest/libqtest.c         | 27 ++++++++++++++
tests/qtest/libqtest.h         | 14 +++++++
tests/qtest/meson.build        |  2 +
tests/qtest/riscv-csr-test.c   | 68 ++++++++++++++++++++++++++++++++++
8 files changed, 178 insertions(+), 1 deletion(-)
create mode 100644 tests/qtest/riscv-csr-test.c
[RFC PATCH 0/2] Support RISC-V CSR read/write in Qtest environment
Posted by Ivan Klokov 5 months, 2 weeks ago
These patches add functionality for unit testing RISC-V-specific registers.
The first patch adds a Qtest backend, and the second implements a simple test.

Ivan Klokov (2):
  Add RISC-V CSR qtest support
  QTest example for RISC-V CSR register

 target/riscv/cpu.c             | 13 +++++++
 target/riscv/cpu.h             |  3 ++
 target/riscv/csr.c             | 49 +++++++++++++++++++++++-
 tests/qtest/libqos/meson.build |  3 ++
 tests/qtest/libqtest.c         | 27 ++++++++++++++
 tests/qtest/libqtest.h         | 14 +++++++
 tests/qtest/meson.build        |  2 +
 tests/qtest/riscv-csr-test.c   | 68 ++++++++++++++++++++++++++++++++++
 8 files changed, 178 insertions(+), 1 deletion(-)
 create mode 100644 tests/qtest/riscv-csr-test.c

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2.34.1