1
The following changes since commit db2feb2df8d19592c9859efb3f682404e0052957:
1
The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
2
2
3
Merge tag 'pull-misc-20240605' of https://gitlab.com/rth7680/qemu into staging (2024-06-05 14:17:01 -0700)
3
Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)
4
4
5
are available in the Git repository at:
5
are available in the Git repository at:
6
6
7
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240606
7
https://gitlab.com/bibo-mao/qemu.git pull-loongarch-20241213
8
8
9
for you to fetch changes up to 78f932ea1f7b3b9b0ac628dc2a91281318fe51fa:
9
for you to fetch changes up to 78aa256571aa06f32001bd80635a1858187c609b:
10
10
11
target/loongarch: fix a wrong print in cpu dump (2024-06-06 11:58:06 +0800)
11
hw/intc/loongarch_pch: Code cleanup about loongarch_pch_pic (2024-12-13 14:39:39 +0800)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
pull-loongarch-20240606
14
pull-loongarch-20241213
15
15
16
----------------------------------------------------------------
16
----------------------------------------------------------------
17
Bibo Mao (2):
17
Bibo Mao (8):
18
tests/libqos: Add loongarch virt machine node
18
include: Add loongarch_pic_common header file
19
tests/qtest: Add numa test for loongarch system
19
include: Move struct LoongArchPCHPIC to loongarch_pic_common header file
20
hw/intc/loongarch_pch: Merge instance_init() into realize()
21
hw/intc/loongarch_pch: Rename LoongArchPCHPIC with LoongArchPICCommonState
22
hw/intc/loongarch_pch: Move some functions to file loongarch_pic_common
23
hw/intc/loongarch_pch: Inherit from loongarch_pic_common
24
hw/intc/loongarch_pch: Add pre_save and post_load interfaces
25
hw/intc/loongarch_pch: Code cleanup about loongarch_pch_pic
20
26
21
Song Gao (3):
27
hw/intc/loongarch_pch_pic.c | 106 +++++++++++----------------------
22
hw/intc/loongarch_extioi: Add extioi virt extension definition
28
hw/intc/loongarch_pic_common.c | 97 ++++++++++++++++++++++++++++++
23
hw/loongarch/virt: Use MemTxAttrs interface for misc ops
29
hw/intc/meson.build | 2 +-
24
hw/loongarch/virt: Enable extioi virt extension
30
hw/loongarch/virt.c | 2 +-
25
31
include/hw/intc/loongarch_pch_pic.h | 70 +++++-----------------
26
lanyanzhi (1):
32
include/hw/intc/loongarch_pic_common.h | 82 +++++++++++++++++++++++++
27
target/loongarch: fix a wrong print in cpu dump
33
6 files changed, 230 insertions(+), 129 deletions(-)
28
34
create mode 100644 hw/intc/loongarch_pic_common.c
29
hw/intc/loongarch_extioi.c | 88 ++++++++++++-
35
create mode 100644 include/hw/intc/loongarch_pic_common.h
30
hw/loongarch/virt.c | 184 +++++++++++++++++++++++-----
31
include/hw/intc/loongarch_extioi.h | 21 ++++
32
include/hw/loongarch/virt.h | 1 +
33
target/loongarch/cpu.c | 2 +-
34
target/loongarch/cpu.h | 1 +
35
tests/qtest/libqos/loongarch-virt-machine.c | 114 +++++++++++++++++
36
tests/qtest/libqos/meson.build | 1 +
37
tests/qtest/meson.build | 2 +-
38
tests/qtest/numa-test.c | 53 ++++++++
39
10 files changed, 428 insertions(+), 39 deletions(-)
40
create mode 100644 tests/qtest/libqos/loongarch-virt-machine.c
diff view generated by jsdifflib
New patch
1
Add common header file hw/intc/loongarch_pic_common.h, and move
2
some macro definition from hw/intc/loongarch_pch_pic.h to the common
3
header file.
1
4
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
7
---
8
include/hw/intc/loongarch_pch_pic.h | 36 +++-------------------
9
include/hw/intc/loongarch_pic_common.h | 42 ++++++++++++++++++++++++++
10
2 files changed, 47 insertions(+), 31 deletions(-)
11
create mode 100644 include/hw/intc/loongarch_pic_common.h
12
13
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/intc/loongarch_pch_pic.h
16
+++ b/include/hw/intc/loongarch_pch_pic.h
17
@@ -XXX,XX +XXX,XX @@
18
* Copyright (c) 2021 Loongson Technology Corporation Limited
19
*/
20
21
-#include "hw/sysbus.h"
22
+#ifndef HW_LOONGARCH_PCH_PIC_H
23
+#define HW_LOONGARCH_PCH_PIC_H
24
+
25
+#include "hw/intc/loongarch_pic_common.h"
26
27
#define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
28
#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
29
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
30
31
-#define PCH_PIC_INT_ID_VAL 0x7000000UL
32
-#define PCH_PIC_INT_ID_VER 0x1UL
33
-
34
-#define PCH_PIC_INT_ID_LO 0x00
35
-#define PCH_PIC_INT_ID_HI 0x04
36
-#define PCH_PIC_INT_MASK_LO 0x20
37
-#define PCH_PIC_INT_MASK_HI 0x24
38
-#define PCH_PIC_HTMSI_EN_LO 0x40
39
-#define PCH_PIC_HTMSI_EN_HI 0x44
40
-#define PCH_PIC_INT_EDGE_LO 0x60
41
-#define PCH_PIC_INT_EDGE_HI 0x64
42
-#define PCH_PIC_INT_CLEAR_LO 0x80
43
-#define PCH_PIC_INT_CLEAR_HI 0x84
44
-#define PCH_PIC_AUTO_CTRL0_LO 0xc0
45
-#define PCH_PIC_AUTO_CTRL0_HI 0xc4
46
-#define PCH_PIC_AUTO_CTRL1_LO 0xe0
47
-#define PCH_PIC_AUTO_CTRL1_HI 0xe4
48
-#define PCH_PIC_ROUTE_ENTRY_OFFSET 0x100
49
-#define PCH_PIC_ROUTE_ENTRY_END 0x13f
50
-#define PCH_PIC_HTMSI_VEC_OFFSET 0x200
51
-#define PCH_PIC_HTMSI_VEC_END 0x23f
52
-#define PCH_PIC_INT_STATUS_LO 0x3a0
53
-#define PCH_PIC_INT_STATUS_HI 0x3a4
54
-#define PCH_PIC_INT_POL_LO 0x3e0
55
-#define PCH_PIC_INT_POL_HI 0x3e4
56
-
57
-#define STATUS_LO_START 0
58
-#define STATUS_HI_START 0x4
59
-#define POL_LO_START 0x40
60
-#define POL_HI_START 0x44
61
struct LoongArchPCHPIC {
62
SysBusDevice parent_obj;
63
qemu_irq parent_irq[64];
64
@@ -XXX,XX +XXX,XX @@ struct LoongArchPCHPIC {
65
MemoryRegion iomem8;
66
unsigned int irq_num;
67
};
68
+#endif /* HW_LOONGARCH_PCH_PIC_H */
69
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
70
new file mode 100644
71
index XXXXXXX..XXXXXXX
72
--- /dev/null
73
+++ b/include/hw/intc/loongarch_pic_common.h
74
@@ -XXX,XX +XXX,XX @@
75
+/* SPDX-License-Identifier: GPL-2.0-or-later */
76
+/*
77
+ * LoongArch 7A1000 I/O interrupt controller definitions
78
+ * Copyright (c) 2024 Loongson Technology Corporation Limited
79
+ */
80
+
81
+#ifndef HW_LOONGARCH_PIC_COMMON_H
82
+#define HW_LOONGARCH_PIC_COMMON_H
83
+
84
+#include "hw/pci-host/ls7a.h"
85
+#include "hw/sysbus.h"
86
+
87
+#define PCH_PIC_INT_ID_VAL 0x7000000UL
88
+#define PCH_PIC_INT_ID_VER 0x1UL
89
+#define PCH_PIC_INT_ID_LO 0x00
90
+#define PCH_PIC_INT_ID_HI 0x04
91
+#define PCH_PIC_INT_MASK_LO 0x20
92
+#define PCH_PIC_INT_MASK_HI 0x24
93
+#define PCH_PIC_HTMSI_EN_LO 0x40
94
+#define PCH_PIC_HTMSI_EN_HI 0x44
95
+#define PCH_PIC_INT_EDGE_LO 0x60
96
+#define PCH_PIC_INT_EDGE_HI 0x64
97
+#define PCH_PIC_INT_CLEAR_LO 0x80
98
+#define PCH_PIC_INT_CLEAR_HI 0x84
99
+#define PCH_PIC_AUTO_CTRL0_LO 0xc0
100
+#define PCH_PIC_AUTO_CTRL0_HI 0xc4
101
+#define PCH_PIC_AUTO_CTRL1_LO 0xe0
102
+#define PCH_PIC_AUTO_CTRL1_HI 0xe4
103
+#define PCH_PIC_ROUTE_ENTRY_OFFSET 0x100
104
+#define PCH_PIC_ROUTE_ENTRY_END 0x13f
105
+#define PCH_PIC_HTMSI_VEC_OFFSET 0x200
106
+#define PCH_PIC_HTMSI_VEC_END 0x23f
107
+#define PCH_PIC_INT_STATUS_LO 0x3a0
108
+#define PCH_PIC_INT_STATUS_HI 0x3a4
109
+#define PCH_PIC_INT_POL_LO 0x3e0
110
+#define PCH_PIC_INT_POL_HI 0x3e4
111
+
112
+#define STATUS_LO_START 0
113
+#define STATUS_HI_START 0x4
114
+#define POL_LO_START 0x40
115
+#define POL_HI_START 0x44
116
+#endif /* HW_LOONGARCH_PIC_COMMON_H */
117
--
118
2.43.5
diff view generated by jsdifflib
New patch
1
Move structure LoongArchPCHPIC from header file loongarch_pch_pic.h
2
to file loongarch_pic_common.h, and rename structure name with
3
LoongArchPICCommonState.
1
4
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
7
---
8
include/hw/intc/loongarch_pch_pic.h | 27 +------------------------
9
include/hw/intc/loongarch_pic_common.h | 28 ++++++++++++++++++++++++++
10
2 files changed, 29 insertions(+), 26 deletions(-)
11
12
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/include/hw/intc/loongarch_pch_pic.h
15
+++ b/include/hw/intc/loongarch_pch_pic.h
16
@@ -XXX,XX +XXX,XX @@
17
18
#include "hw/intc/loongarch_pic_common.h"
19
20
+#define LoongArchPCHPIC LoongArchPICCommonState
21
#define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
22
#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
23
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
24
25
-struct LoongArchPCHPIC {
26
- SysBusDevice parent_obj;
27
- qemu_irq parent_irq[64];
28
- uint64_t int_mask; /*0x020 interrupt mask register*/
29
- uint64_t htmsi_en; /*0x040 1=msi*/
30
- uint64_t intedge; /*0x060 edge=1 level =0*/
31
- uint64_t intclr; /*0x080 for clean edge int,set 1 clean,set 0 is noused*/
32
- uint64_t auto_crtl0; /*0x0c0*/
33
- uint64_t auto_crtl1; /*0x0e0*/
34
- uint64_t last_intirr; /* edge detection */
35
- uint64_t intirr; /* 0x380 interrupt request register */
36
- uint64_t intisr; /* 0x3a0 interrupt service register */
37
- /*
38
- * 0x3e0 interrupt level polarity selection
39
- * register 0 for high level trigger
40
- */
41
- uint64_t int_polarity;
42
-
43
- uint8_t route_entry[64]; /*0x100 - 0x138*/
44
- uint8_t htmsi_vector[64]; /*0x200 - 0x238*/
45
-
46
- MemoryRegion iomem32_low;
47
- MemoryRegion iomem32_high;
48
- MemoryRegion iomem8;
49
- unsigned int irq_num;
50
-};
51
#endif /* HW_LOONGARCH_PCH_PIC_H */
52
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
53
index XXXXXXX..XXXXXXX 100644
54
--- a/include/hw/intc/loongarch_pic_common.h
55
+++ b/include/hw/intc/loongarch_pic_common.h
56
@@ -XXX,XX +XXX,XX @@
57
#define STATUS_HI_START 0x4
58
#define POL_LO_START 0x40
59
#define POL_HI_START 0x44
60
+
61
+struct LoongArchPICCommonState {
62
+ SysBusDevice parent_obj;
63
+
64
+ qemu_irq parent_irq[64];
65
+ uint64_t int_mask; /* 0x020 interrupt mask register */
66
+ uint64_t htmsi_en; /* 0x040 1=msi */
67
+ uint64_t intedge; /* 0x060 edge=1 level=0 */
68
+ uint64_t intclr; /* 0x080 clean edge int, set 1 clean, 0 noused */
69
+ uint64_t auto_crtl0; /* 0x0c0 */
70
+ uint64_t auto_crtl1; /* 0x0e0 */
71
+ uint64_t last_intirr; /* edge detection */
72
+ uint64_t intirr; /* 0x380 interrupt request register */
73
+ uint64_t intisr; /* 0x3a0 interrupt service register */
74
+ /*
75
+ * 0x3e0 interrupt level polarity selection
76
+ * register 0 for high level trigger
77
+ */
78
+ uint64_t int_polarity;
79
+
80
+ uint8_t route_entry[64]; /* 0x100 - 0x138 */
81
+ uint8_t htmsi_vector[64]; /* 0x200 - 0x238 */
82
+
83
+ MemoryRegion iomem32_low;
84
+ MemoryRegion iomem32_high;
85
+ MemoryRegion iomem8;
86
+ unsigned int irq_num;
87
+};
88
#endif /* HW_LOONGARCH_PIC_COMMON_H */
89
--
90
2.43.5
diff view generated by jsdifflib
New patch
1
Memory region is created in instance_init(), merge it into function
2
realize(). There is no special class_init() for loongarch_pch object.
1
3
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
5
Reviewed-by: Song Gao <gaosong@loongson.cn>
6
---
7
hw/intc/loongarch_pch_pic.c | 15 ++++-----------
8
1 file changed, 4 insertions(+), 11 deletions(-)
9
10
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/intc/loongarch_pch_pic.c
13
+++ b/hw/intc/loongarch_pch_pic.c
14
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
15
static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
16
{
17
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
18
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
19
20
if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
21
error_setg(errp, "Invalid 'pic_irq_num'");
22
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
23
24
qdev_init_gpio_out(dev, s->parent_irq, s->irq_num);
25
qdev_init_gpio_in(dev, pch_pic_irq_handler, s->irq_num);
26
-}
27
-
28
-static void loongarch_pch_pic_init(Object *obj)
29
-{
30
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(obj);
31
- SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
32
-
33
- memory_region_init_io(&s->iomem32_low, obj,
34
+ memory_region_init_io(&s->iomem32_low, OBJECT(dev),
35
&loongarch_pch_pic_reg32_low_ops,
36
s, PCH_PIC_NAME(.reg32_part1), 0x100);
37
- memory_region_init_io(&s->iomem8, obj, &loongarch_pch_pic_reg8_ops,
38
+ memory_region_init_io(&s->iomem8, OBJECT(dev), &loongarch_pch_pic_reg8_ops,
39
s, PCH_PIC_NAME(.reg8), 0x2a0);
40
- memory_region_init_io(&s->iomem32_high, obj,
41
+ memory_region_init_io(&s->iomem32_high, OBJECT(dev),
42
&loongarch_pch_pic_reg32_high_ops,
43
s, PCH_PIC_NAME(.reg32_part2), 0xc60);
44
sysbus_init_mmio(sbd, &s->iomem32_low);
45
@@ -XXX,XX +XXX,XX @@ static const TypeInfo loongarch_pch_pic_info = {
46
.name = TYPE_LOONGARCH_PCH_PIC,
47
.parent = TYPE_SYS_BUS_DEVICE,
48
.instance_size = sizeof(LoongArchPCHPIC),
49
- .instance_init = loongarch_pch_pic_init,
50
.class_init = loongarch_pch_pic_class_init,
51
};
52
53
--
54
2.43.5
diff view generated by jsdifflib
1
This patch adds a new board attribute 'v-eiointc'.
1
With pic vmstate, rename structure name vmstate_loongarch_pch_pic with
2
A value of true enables the virt extended I/O interrupt controller.
2
vmstate_loongarch_pic_common, and with pic property rename
3
VMs working in kvm mode have 'v-eiointc' enabled by default.
3
loongarch_pch_pic_properties with loongarch_pic_common_properties.
4
4
5
Signed-off-by: Song Gao <gaosong@loongson.cn>
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
6
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
7
Message-Id: <20240528083855.1912757-4-gaosong@loongson.cn>
8
---
7
---
9
hw/loongarch/virt.c | 88 +++++++++++++++++++++++++++++++++++--
8
hw/intc/loongarch_pch_pic.c | 52 +++++++++++++++++++++++--------------
10
include/hw/loongarch/virt.h | 1 +
9
1 file changed, 32 insertions(+), 20 deletions(-)
11
target/loongarch/cpu.h | 1 +
12
3 files changed, 87 insertions(+), 3 deletions(-)
13
10
14
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
11
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
15
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/loongarch/virt.c
13
--- a/hw/intc/loongarch_pch_pic.c
17
+++ b/hw/loongarch/virt.c
14
+++ b/hw/intc/loongarch_pch_pic.c
18
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
19
#include "hw/boards.h"
16
s->int_polarity = 0x0;
20
#include "hw/char/serial.h"
17
}
21
#include "sysemu/kvm.h"
18
22
+#include "sysemu/tcg.h"
19
+static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
23
#include "sysemu/sysemu.h"
24
#include "sysemu/qtest.h"
25
#include "sysemu/runstate.h"
26
@@ -XXX,XX +XXX,XX @@
27
#include "hw/virtio/virtio-iommu.h"
28
#include "qemu/error-report.h"
29
30
+static bool virt_is_veiointc_enabled(LoongArchVirtMachineState *lvms)
31
+{
20
+{
32
+ if (lvms->veiointc == ON_OFF_AUTO_OFF) {
21
+ LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
33
+ return false;
22
+
23
+ if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
24
+ error_setg(errp, "Invalid 'pic_irq_num'");
25
+ return;
34
+ }
26
+ }
35
+ return true;
36
+}
27
+}
37
+
28
+
38
+static void virt_get_veiointc(Object *obj, Visitor *v, const char *name,
29
static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
39
+ void *opaque, Error **errp)
30
{
40
+{
31
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
41
+ LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj);
32
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
42
+ OnOffAuto veiointc = lvms->veiointc;
33
+ Error *local_err = NULL;
43
+
34
44
+ visit_type_OnOffAuto(v, name, &veiointc, errp);
35
- if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
45
+}
36
- error_setg(errp, "Invalid 'pic_irq_num'");
46
+
37
+ loongarch_pic_common_realize(dev, &local_err);
47
+static void virt_set_veiointc(Object *obj, Visitor *v, const char *name,
38
+ if (local_err) {
48
+ void *opaque, Error **errp)
39
+ error_propagate(errp, local_err);
49
+{
40
return;
50
+ LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj);
51
+
52
+ visit_type_OnOffAuto(v, name, &lvms->veiointc, errp);
53
+}
54
+
55
static PFlashCFI01 *virt_flash_create1(LoongArchVirtMachineState *lvms,
56
const char *name,
57
const char *alias_prop_name)
58
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
59
/* Create EXTIOI device */
60
extioi = qdev_new(TYPE_LOONGARCH_EXTIOI);
61
qdev_prop_set_uint32(extioi, "num-cpu", ms->smp.cpus);
62
+ if (virt_is_veiointc_enabled(lvms)) {
63
+ qdev_prop_set_bit(extioi, "has-virtualization-extension", true);
64
+ }
65
sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal);
66
memory_region_add_subregion(&lvms->system_iocsr, APIC_BASE,
67
- sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0));
68
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0));
69
+ if (virt_is_veiointc_enabled(lvms)) {
70
+ memory_region_add_subregion(&lvms->system_iocsr, EXTIOI_VIRT_BASE,
71
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 1));
72
+ }
73
74
/*
75
* connect ext irq to the cpu irq
76
@@ -XXX,XX +XXX,XX @@ static void virt_firmware_init(LoongArchVirtMachineState *lvms)
77
}
41
}
42
43
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
44
78
}
45
}
79
46
80
-
47
-static Property loongarch_pch_pic_properties[] = {
81
static MemTxResult virt_iocsr_misc_write(void *opaque, hwaddr addr,
48
- DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPCHPIC, irq_num, 0),
82
uint64_t val, unsigned size,
49
+static Property loongarch_pic_common_properties[] = {
83
MemTxAttrs attrs)
50
+ DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPICCommonState, irq_num, 0),
84
{
51
DEFINE_PROP_END_OF_LIST(),
85
+ LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(opaque);
52
};
86
+ uint64_t features;
53
87
+
54
-static const VMStateDescription vmstate_loongarch_pch_pic = {
88
+ switch (addr) {
55
- .name = TYPE_LOONGARCH_PCH_PIC,
89
+ case MISC_FUNC_REG:
56
+static const VMStateDescription vmstate_loongarch_pic_common = {
90
+ if (!virt_is_veiointc_enabled(lvms)) {
57
+ .name = "loongarch_pch_pic",
91
+ return MEMTX_OK;
58
.version_id = 1,
92
+ }
59
.minimum_version_id = 1,
93
+
60
.fields = (const VMStateField[]) {
94
+ features = address_space_ldl(&lvms->as_iocsr,
61
- VMSTATE_UINT64(int_mask, LoongArchPCHPIC),
95
+ EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG,
62
- VMSTATE_UINT64(htmsi_en, LoongArchPCHPIC),
96
+ attrs, NULL);
63
- VMSTATE_UINT64(intedge, LoongArchPCHPIC),
97
+ if (val & BIT_ULL(IOCSRM_EXTIOI_EN)) {
64
- VMSTATE_UINT64(intclr, LoongArchPCHPIC),
98
+ features |= BIT(EXTIOI_ENABLE);
65
- VMSTATE_UINT64(auto_crtl0, LoongArchPCHPIC),
99
+ }
66
- VMSTATE_UINT64(auto_crtl1, LoongArchPCHPIC),
100
+ if (val & BIT_ULL(IOCSRM_EXTIOI_INT_ENCODE)) {
67
- VMSTATE_UINT8_ARRAY(route_entry, LoongArchPCHPIC, 64),
101
+ features |= BIT(EXTIOI_ENABLE_INT_ENCODE);
68
- VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPCHPIC, 64),
102
+ }
69
- VMSTATE_UINT64(last_intirr, LoongArchPCHPIC),
103
+
70
- VMSTATE_UINT64(intirr, LoongArchPCHPIC),
104
+ address_space_stl(&lvms->as_iocsr,
71
- VMSTATE_UINT64(intisr, LoongArchPCHPIC),
105
+ EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG,
72
- VMSTATE_UINT64(int_polarity, LoongArchPCHPIC),
106
+ features, attrs, NULL);
73
+ VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
107
+ break;
74
+ VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
108
+ default:
75
+ VMSTATE_UINT64(intedge, LoongArchPICCommonState),
109
+ g_assert_not_reached();
76
+ VMSTATE_UINT64(intclr, LoongArchPICCommonState),
110
+ }
77
+ VMSTATE_UINT64(auto_crtl0, LoongArchPICCommonState),
111
+
78
+ VMSTATE_UINT64(auto_crtl1, LoongArchPICCommonState),
112
return MEMTX_OK;
79
+ VMSTATE_UINT8_ARRAY(route_entry, LoongArchPICCommonState, 64),
80
+ VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPICCommonState, 64),
81
+ VMSTATE_UINT64(last_intirr, LoongArchPICCommonState),
82
+ VMSTATE_UINT64(intirr, LoongArchPICCommonState),
83
+ VMSTATE_UINT64(intisr, LoongArchPICCommonState),
84
+ VMSTATE_UINT64(int_polarity, LoongArchPICCommonState),
85
VMSTATE_END_OF_LIST()
86
}
87
};
88
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
89
90
dc->realize = loongarch_pch_pic_realize;
91
device_class_set_legacy_reset(dc, loongarch_pch_pic_reset);
92
- dc->vmsd = &vmstate_loongarch_pch_pic;
93
- device_class_set_props(dc, loongarch_pch_pic_properties);
94
+ dc->vmsd = &vmstate_loongarch_pic_common;
95
+ device_class_set_props(dc, loongarch_pic_common_properties);
113
}
96
}
114
97
115
@@ -XXX,XX +XXX,XX @@ static MemTxResult virt_iocsr_misc_read(void *opaque, hwaddr addr,
98
static const TypeInfo loongarch_pch_pic_info = {
116
uint64_t *data,
117
unsigned size, MemTxAttrs attrs)
118
{
119
+ LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(opaque);
120
uint64_t ret = 0;
121
+ int features;
122
123
switch (addr) {
124
case VERSION_REG:
125
@@ -XXX,XX +XXX,XX @@ static MemTxResult virt_iocsr_misc_read(void *opaque, hwaddr addr,
126
ret = 0x303030354133ULL; /* "3A5000" */
127
break;
128
case MISC_FUNC_REG:
129
- ret = BIT_ULL(IOCSRM_EXTIOI_EN);
130
+ if (!virt_is_veiointc_enabled(lvms)) {
131
+ ret |= BIT_ULL(IOCSRM_EXTIOI_EN);
132
+ break;
133
+ }
134
+
135
+ features = address_space_ldl(&lvms->as_iocsr,
136
+ EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG,
137
+ attrs, NULL);
138
+ if (features & BIT(EXTIOI_ENABLE)) {
139
+ ret |= BIT_ULL(IOCSRM_EXTIOI_EN);
140
+ }
141
+ if (features & BIT(EXTIOI_ENABLE_INT_ENCODE)) {
142
+ ret |= BIT_ULL(IOCSRM_EXTIOI_INT_ENCODE);
143
+ }
144
break;
145
default:
146
g_assert_not_reached();
147
@@ -XXX,XX +XXX,XX @@ static void virt_initfn(Object *obj)
148
{
149
LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj);
150
151
+ if (tcg_enabled()) {
152
+ lvms->veiointc = ON_OFF_AUTO_OFF;
153
+ }
154
lvms->acpi = ON_OFF_AUTO_AUTO;
155
lvms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
156
lvms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
157
@@ -XXX,XX +XXX,XX @@ static void virt_class_init(ObjectClass *oc, void *data)
158
NULL, NULL);
159
object_class_property_set_description(oc, "acpi",
160
"Enable ACPI");
161
+ object_class_property_add(oc, "v-eiointc", "OnOffAuto",
162
+ virt_get_veiointc, virt_set_veiointc,
163
+ NULL, NULL);
164
+ object_class_property_set_description(oc, "v-eiointc",
165
+ "Enable Virt Extend I/O Interrupt Controller.");
166
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
167
#ifdef CONFIG_TPM
168
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
169
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
170
index XXXXXXX..XXXXXXX 100644
171
--- a/include/hw/loongarch/virt.h
172
+++ b/include/hw/loongarch/virt.h
173
@@ -XXX,XX +XXX,XX @@ struct LoongArchVirtMachineState {
174
Notifier machine_done;
175
Notifier powerdown_notifier;
176
OnOffAuto acpi;
177
+ OnOffAuto veiointc;
178
char *oem_id;
179
char *oem_table_id;
180
DeviceState *acpi_ged;
181
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
182
index XXXXXXX..XXXXXXX 100644
183
--- a/target/loongarch/cpu.h
184
+++ b/target/loongarch/cpu.h
185
@@ -XXX,XX +XXX,XX @@
186
#define CPUNAME_REG 0x20
187
#define MISC_FUNC_REG 0x420
188
#define IOCSRM_EXTIOI_EN 48
189
+#define IOCSRM_EXTIOI_INT_ENCODE 49
190
191
#define IOCSR_MEM_SIZE 0x428
192
193
--
99
--
194
2.34.1
100
2.43.5
diff view generated by jsdifflib
1
From: Bibo Mao <maobibo@loongson.cn>
1
Move some common functions to file loongarch_pic_common.c, the common
2
2
functions include loongarch_pic_common_realize(), property structure
3
Add loongarch virt machine to the graph. It is a modified copy of
3
loongarch_pic_common_properties and vmstate structure
4
the existing riscv virtmachine in riscv-virt-machine.c
4
vmstate_loongarch_pic_common.
5
6
It contains a generic-pcihost controller, and an extra function
7
loongarch_config_qpci_bus() to configure GPEX pci host controller
8
information, such as ecam and pio_base addresses.
9
10
Also hotplug handle checking about TYPE_VIRTIO_IOMMU_PCI device is
11
added on loongarch virt machine, since virtio_mmu_pci device requires
12
it.
13
5
14
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
6
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
15
Acked-by: Thomas Huth <thuth@redhat.com>
7
Reviewed-by: Song Gao <gaosong@loongson.cn>
16
Message-Id: <20240528082053.938564-1-maobibo@loongson.cn>
17
Signed-off-by: Song Gao <gaosong@loongson.cn>
18
---
8
---
19
hw/loongarch/virt.c | 2 +
9
hw/intc/loongarch_pch_pic.c | 37 +-----------------------------
20
tests/qtest/libqos/loongarch-virt-machine.c | 114 ++++++++++++++++++++
10
hw/intc/loongarch_pic_common.c | 41 ++++++++++++++++++++++++++++++++++
21
tests/qtest/libqos/meson.build | 1 +
11
2 files changed, 42 insertions(+), 36 deletions(-)
22
3 files changed, 117 insertions(+)
12
create mode 100644 hw/intc/loongarch_pic_common.c
23
create mode 100644 tests/qtest/libqos/loongarch-virt-machine.c
24
13
25
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
14
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
26
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/loongarch/virt.c
16
--- a/hw/intc/loongarch_pch_pic.c
28
+++ b/hw/loongarch/virt.c
17
+++ b/hw/intc/loongarch_pch_pic.c
29
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
30
#include "sysemu/tpm.h"
19
s->int_polarity = 0x0;
31
#include "sysemu/block-backend.h"
20
}
32
#include "hw/block/flash.h"
21
33
+#include "hw/virtio/virtio-iommu.h"
22
-static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
34
#include "qemu/error-report.h"
23
-{
35
24
- LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
36
static PFlashCFI01 *virt_flash_create1(LoongArchVirtMachineState *lvms,
25
-
37
@@ -XXX,XX +XXX,XX @@ static HotplugHandler *virt_get_hotplug_handler(MachineState *machine,
26
- if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
38
MachineClass *mc = MACHINE_GET_CLASS(machine);
27
- error_setg(errp, "Invalid 'pic_irq_num'");
39
28
- return;
40
if (device_is_dynamic_sysbus(mc, dev) ||
29
- }
41
+ object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
30
-}
42
memhp_type_supported(dev)) {
31
-
43
return HOTPLUG_HANDLER(machine);
32
+#include "loongarch_pic_common.c"
44
}
33
static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
45
diff --git a/tests/qtest/libqos/loongarch-virt-machine.c b/tests/qtest/libqos/loongarch-virt-machine.c
34
{
35
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
36
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
37
38
}
39
40
-static Property loongarch_pic_common_properties[] = {
41
- DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPICCommonState, irq_num, 0),
42
- DEFINE_PROP_END_OF_LIST(),
43
-};
44
-
45
-static const VMStateDescription vmstate_loongarch_pic_common = {
46
- .name = "loongarch_pch_pic",
47
- .version_id = 1,
48
- .minimum_version_id = 1,
49
- .fields = (const VMStateField[]) {
50
- VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
51
- VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
52
- VMSTATE_UINT64(intedge, LoongArchPICCommonState),
53
- VMSTATE_UINT64(intclr, LoongArchPICCommonState),
54
- VMSTATE_UINT64(auto_crtl0, LoongArchPICCommonState),
55
- VMSTATE_UINT64(auto_crtl1, LoongArchPICCommonState),
56
- VMSTATE_UINT8_ARRAY(route_entry, LoongArchPICCommonState, 64),
57
- VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPICCommonState, 64),
58
- VMSTATE_UINT64(last_intirr, LoongArchPICCommonState),
59
- VMSTATE_UINT64(intirr, LoongArchPICCommonState),
60
- VMSTATE_UINT64(intisr, LoongArchPICCommonState),
61
- VMSTATE_UINT64(int_polarity, LoongArchPICCommonState),
62
- VMSTATE_END_OF_LIST()
63
- }
64
-};
65
-
66
static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
67
{
68
DeviceClass *dc = DEVICE_CLASS(klass);
69
diff --git a/hw/intc/loongarch_pic_common.c b/hw/intc/loongarch_pic_common.c
46
new file mode 100644
70
new file mode 100644
47
index XXXXXXX..XXXXXXX
71
index XXXXXXX..XXXXXXX
48
--- /dev/null
72
--- /dev/null
49
+++ b/tests/qtest/libqos/loongarch-virt-machine.c
73
+++ b/hw/intc/loongarch_pic_common.c
50
@@ -XXX,XX +XXX,XX @@
74
@@ -XXX,XX +XXX,XX @@
75
+/* SPDX-License-Identifier: GPL-2.0-or-later */
51
+/*
76
+/*
52
+ * libqos driver framework
77
+ * QEMU Loongson 7A1000 I/O interrupt controller.
53
+ *
78
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
54
+ * Copyright (c) 2018 Emanuele Giuseppe Esposito <e.emanuelegiuseppe@gmail.com>
55
+ *
56
+ * This library is free software; you can redistribute it and/or
57
+ * modify it under the terms of the GNU Lesser General Public
58
+ * License version 2.1 as published by the Free Software Foundation.
59
+ *
60
+ * This library is distributed in the hope that it will be useful,
61
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
62
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
63
+ * Lesser General Public License for more details.
64
+ *
65
+ * You should have received a copy of the GNU Lesser General Public
66
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
67
+ */
79
+ */
68
+
80
+
69
+#include "qemu/osdep.h"
81
+static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
70
+#include "../libqtest.h"
82
+{
71
+#include "qemu/module.h"
83
+ LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
72
+#include "libqos-malloc.h"
73
+#include "qgraph.h"
74
+#include "virtio-mmio.h"
75
+#include "generic-pcihost.h"
76
+#include "hw/pci/pci_regs.h"
77
+
84
+
78
+#define LOONGARCH_PAGE_SIZE 0x1000
85
+ if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
79
+#define LOONGARCH_VIRT_RAM_ADDR 0x100000
86
+ error_setg(errp, "Invalid 'pic_irq_num'");
80
+#define LOONGARCH_VIRT_RAM_SIZE 0xFF00000
87
+ return;
88
+ }
89
+}
81
+
90
+
82
+#define LOONGARCH_VIRT_PIO_BASE 0x18000000
91
+static Property loongarch_pic_common_properties[] = {
83
+#define LOONGARCH_VIRT_PCIE_PIO_OFFSET 0x4000
92
+ DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPICCommonState, irq_num, 0),
84
+#define LOONGARCH_VIRT_PCIE_PIO_LIMIT 0x10000
93
+ DEFINE_PROP_END_OF_LIST(),
85
+#define LOONGARCH_VIRT_PCIE_ECAM_BASE 0x20000000
86
+#define LOONGARCH_VIRT_PCIE_MMIO32_BASE 0x40000000
87
+#define LOONGARCH_VIRT_PCIE_MMIO32_LIMIT 0x80000000
88
+
89
+typedef struct QVirtMachine QVirtMachine;
90
+
91
+struct QVirtMachine {
92
+ QOSGraphObject obj;
93
+ QGuestAllocator alloc;
94
+ QVirtioMMIODevice virtio_mmio;
95
+ QGenericPCIHost bridge;
96
+};
94
+};
97
+
95
+
98
+static void virt_destructor(QOSGraphObject *obj)
96
+static const VMStateDescription vmstate_loongarch_pic_common = {
99
+{
97
+ .name = "loongarch_pch_pic",
100
+ QVirtMachine *machine = (QVirtMachine *) obj;
98
+ .version_id = 1,
101
+ alloc_destroy(&machine->alloc);
99
+ .minimum_version_id = 1,
102
+}
100
+ .fields = (const VMStateField[]) {
103
+
101
+ VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
104
+static void *virt_get_driver(void *object, const char *interface)
102
+ VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
105
+{
103
+ VMSTATE_UINT64(intedge, LoongArchPICCommonState),
106
+ QVirtMachine *machine = object;
104
+ VMSTATE_UINT64(intclr, LoongArchPICCommonState),
107
+ if (!g_strcmp0(interface, "memory")) {
105
+ VMSTATE_UINT64(auto_crtl0, LoongArchPICCommonState),
108
+ return &machine->alloc;
106
+ VMSTATE_UINT64(auto_crtl1, LoongArchPICCommonState),
107
+ VMSTATE_UINT8_ARRAY(route_entry, LoongArchPICCommonState, 64),
108
+ VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPICCommonState, 64),
109
+ VMSTATE_UINT64(last_intirr, LoongArchPICCommonState),
110
+ VMSTATE_UINT64(intirr, LoongArchPICCommonState),
111
+ VMSTATE_UINT64(intisr, LoongArchPICCommonState),
112
+ VMSTATE_UINT64(int_polarity, LoongArchPICCommonState),
113
+ VMSTATE_END_OF_LIST()
109
+ }
114
+ }
110
+
115
+};
111
+ fprintf(stderr, "%s not present in loongarch/virtio\n", interface);
112
+ g_assert_not_reached();
113
+}
114
+
115
+static QOSGraphObject *virt_get_device(void *obj, const char *device)
116
+{
117
+ QVirtMachine *machine = obj;
118
+ if (!g_strcmp0(device, "generic-pcihost")) {
119
+ return &machine->bridge.obj;
120
+ } else if (!g_strcmp0(device, "virtio-mmio")) {
121
+ return &machine->virtio_mmio.obj;
122
+ }
123
+
124
+ fprintf(stderr, "%s not present in loongarch/virt\n", device);
125
+ g_assert_not_reached();
126
+}
127
+
128
+static void loongarch_config_qpci_bus(QGenericPCIBus *qpci)
129
+{
130
+ qpci->gpex_pio_base = LOONGARCH_VIRT_PIO_BASE;
131
+ qpci->bus.pio_alloc_ptr = LOONGARCH_VIRT_PCIE_PIO_OFFSET;
132
+ qpci->bus.pio_limit = LOONGARCH_VIRT_PCIE_PIO_LIMIT;
133
+ qpci->bus.mmio_alloc_ptr = LOONGARCH_VIRT_PCIE_MMIO32_BASE;
134
+ qpci->bus.mmio_limit = LOONGARCH_VIRT_PCIE_MMIO32_LIMIT;
135
+ qpci->ecam_alloc_ptr = LOONGARCH_VIRT_PCIE_ECAM_BASE;
136
+}
137
+
138
+static void *qos_create_machine_loongarch_virt(QTestState *qts)
139
+{
140
+ QVirtMachine *machine = g_new0(QVirtMachine, 1);
141
+
142
+ alloc_init(&machine->alloc, 0,
143
+ LOONGARCH_VIRT_RAM_ADDR,
144
+ LOONGARCH_VIRT_RAM_ADDR + LOONGARCH_VIRT_RAM_SIZE,
145
+ LOONGARCH_PAGE_SIZE);
146
+
147
+ qos_create_generic_pcihost(&machine->bridge, qts, &machine->alloc);
148
+ loongarch_config_qpci_bus(&machine->bridge.pci);
149
+
150
+ machine->obj.get_device = virt_get_device;
151
+ machine->obj.get_driver = virt_get_driver;
152
+ machine->obj.destructor = virt_destructor;
153
+ return machine;
154
+}
155
+
156
+static void virt_machine_register_nodes(void)
157
+{
158
+ qos_node_create_machine_args("loongarch64/virt",
159
+ qos_create_machine_loongarch_virt,
160
+ " -cpu la464");
161
+ qos_node_contains("loongarch64/virt", "generic-pcihost", NULL);
162
+}
163
+
164
+libqos_init(virt_machine_register_nodes);
165
diff --git a/tests/qtest/libqos/meson.build b/tests/qtest/libqos/meson.build
166
index XXXXXXX..XXXXXXX 100644
167
--- a/tests/qtest/libqos/meson.build
168
+++ b/tests/qtest/libqos/meson.build
169
@@ -XXX,XX +XXX,XX @@ libqos_srcs = files(
170
'ppc64_pseries-machine.c',
171
'x86_64_pc-machine.c',
172
'riscv-virt-machine.c',
173
+ 'loongarch-virt-machine.c',
174
)
175
176
if have_virtfs
177
--
116
--
178
2.34.1
117
2.43.5
diff view generated by jsdifflib
New patch
1
Set TYPE_LOONGARCH_PIC inherit from TYPE_LOONGARCH_PIC_COMMON object,
2
it shares vmsate and property of TYPE_LOONGARCH_PIC_COMMON, and has
3
its own realize() function.
1
4
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
7
---
8
hw/intc/loongarch_pch_pic.c | 38 ++++++++++++--------------
9
hw/intc/loongarch_pic_common.c | 32 +++++++++++++++++++++-
10
hw/intc/meson.build | 2 +-
11
include/hw/intc/loongarch_pch_pic.h | 21 +++++++++++---
12
include/hw/intc/loongarch_pic_common.h | 10 +++++++
13
5 files changed, 77 insertions(+), 26 deletions(-)
14
15
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/intc/loongarch_pch_pic.c
18
+++ b/hw/intc/loongarch_pch_pic.c
19
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
20
s->int_polarity = 0x0;
21
}
22
23
-#include "loongarch_pic_common.c"
24
-static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
25
+static void loongarch_pic_realize(DeviceState *dev, Error **errp)
26
{
27
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
28
- SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
29
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
30
+ LoongarchPICClass *lpc = LOONGARCH_PIC_GET_CLASS(dev);
31
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
32
Error *local_err = NULL;
33
34
- loongarch_pic_common_realize(dev, &local_err);
35
+ lpc->parent_realize(dev, &local_err);
36
if (local_err) {
37
error_propagate(errp, local_err);
38
return;
39
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
40
41
}
42
43
-static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
44
+static void loongarch_pic_class_init(ObjectClass *klass, void *data)
45
{
46
DeviceClass *dc = DEVICE_CLASS(klass);
47
+ LoongarchPICClass *lpc = LOONGARCH_PIC_CLASS(klass);
48
49
- dc->realize = loongarch_pch_pic_realize;
50
device_class_set_legacy_reset(dc, loongarch_pch_pic_reset);
51
- dc->vmsd = &vmstate_loongarch_pic_common;
52
- device_class_set_props(dc, loongarch_pic_common_properties);
53
+ device_class_set_parent_realize(dc, loongarch_pic_realize,
54
+ &lpc->parent_realize);
55
}
56
57
-static const TypeInfo loongarch_pch_pic_info = {
58
- .name = TYPE_LOONGARCH_PCH_PIC,
59
- .parent = TYPE_SYS_BUS_DEVICE,
60
- .instance_size = sizeof(LoongArchPCHPIC),
61
- .class_init = loongarch_pch_pic_class_init,
62
+static const TypeInfo loongarch_pic_types[] = {
63
+ {
64
+ .name = TYPE_LOONGARCH_PIC,
65
+ .parent = TYPE_LOONGARCH_PIC_COMMON,
66
+ .instance_size = sizeof(LoongarchPICState),
67
+ .class_size = sizeof(LoongarchPICClass),
68
+ .class_init = loongarch_pic_class_init,
69
+ }
70
};
71
72
-static void loongarch_pch_pic_register_types(void)
73
-{
74
- type_register_static(&loongarch_pch_pic_info);
75
-}
76
-
77
-type_init(loongarch_pch_pic_register_types)
78
+DEFINE_TYPES(loongarch_pic_types)
79
diff --git a/hw/intc/loongarch_pic_common.c b/hw/intc/loongarch_pic_common.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/hw/intc/loongarch_pic_common.c
82
+++ b/hw/intc/loongarch_pic_common.c
83
@@ -XXX,XX +XXX,XX @@
84
* Copyright (C) 2024 Loongson Technology Corporation Limited
85
*/
86
87
+#include "qemu/osdep.h"
88
+#include "qapi/error.h"
89
+#include "hw/intc/loongarch_pic_common.h"
90
+#include "hw/qdev-properties.h"
91
+#include "migration/vmstate.h"
92
+
93
static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
94
{
95
- LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
96
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
97
98
if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
99
error_setg(errp, "Invalid 'pic_irq_num'");
100
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_loongarch_pic_common = {
101
VMSTATE_END_OF_LIST()
102
}
103
};
104
+
105
+static void loongarch_pic_common_class_init(ObjectClass *klass, void *data)
106
+{
107
+ DeviceClass *dc = DEVICE_CLASS(klass);
108
+ LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_CLASS(klass);
109
+
110
+ device_class_set_parent_realize(dc, loongarch_pic_common_realize,
111
+ &lpcc->parent_realize);
112
+ device_class_set_props(dc, loongarch_pic_common_properties);
113
+ dc->vmsd = &vmstate_loongarch_pic_common;
114
+}
115
+
116
+static const TypeInfo loongarch_pic_common_types[] = {
117
+ {
118
+ .name = TYPE_LOONGARCH_PIC_COMMON,
119
+ .parent = TYPE_SYS_BUS_DEVICE,
120
+ .instance_size = sizeof(LoongArchPICCommonState),
121
+ .class_size = sizeof(LoongArchPICCommonClass),
122
+ .class_init = loongarch_pic_common_class_init,
123
+ .abstract = true,
124
+ }
125
+};
126
+
127
+DEFINE_TYPES(loongarch_pic_common_types)
128
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
129
index XXXXXXX..XXXXXXX 100644
130
--- a/hw/intc/meson.build
131
+++ b/hw/intc/meson.build
132
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
133
specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true: files('loongson_ipi_common.c'))
134
specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c'))
135
specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c'))
136
-specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c'))
137
+specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c', 'loongarch_pic_common.c'))
138
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c'))
139
specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch_extioi.c'))
140
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
141
index XXXXXXX..XXXXXXX 100644
142
--- a/include/hw/intc/loongarch_pch_pic.h
143
+++ b/include/hw/intc/loongarch_pch_pic.h
144
@@ -XXX,XX +XXX,XX @@
145
146
#include "hw/intc/loongarch_pic_common.h"
147
148
-#define LoongArchPCHPIC LoongArchPICCommonState
149
-#define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
150
-#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
151
-OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
152
+#define TYPE_LOONGARCH_PIC "loongarch_pic"
153
+#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PIC#name
154
+OBJECT_DECLARE_TYPE(LoongarchPICState, LoongarchPICClass, LOONGARCH_PIC)
155
+
156
+struct LoongarchPICState {
157
+ LoongArchPICCommonState parent_obj;
158
+};
159
+
160
+struct LoongarchPICClass {
161
+ LoongArchPICCommonClass parent_class;
162
+
163
+ DeviceRealize parent_realize;
164
+};
165
+
166
+#define TYPE_LOONGARCH_PCH_PIC TYPE_LOONGARCH_PIC
167
+typedef struct LoongArchPICCommonState LoongArchPCHPIC;
168
+#define LOONGARCH_PCH_PIC(obj) ((struct LoongArchPICCommonState *)(obj))
169
170
#endif /* HW_LOONGARCH_PCH_PIC_H */
171
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
172
index XXXXXXX..XXXXXXX 100644
173
--- a/include/hw/intc/loongarch_pic_common.h
174
+++ b/include/hw/intc/loongarch_pic_common.h
175
@@ -XXX,XX +XXX,XX @@
176
#define POL_LO_START 0x40
177
#define POL_HI_START 0x44
178
179
+#define TYPE_LOONGARCH_PIC_COMMON "loongarch_pic_common"
180
+OBJECT_DECLARE_TYPE(LoongArchPICCommonState,
181
+ LoongArchPICCommonClass, LOONGARCH_PIC_COMMON)
182
+
183
struct LoongArchPICCommonState {
184
SysBusDevice parent_obj;
185
186
@@ -XXX,XX +XXX,XX @@ struct LoongArchPICCommonState {
187
MemoryRegion iomem8;
188
unsigned int irq_num;
189
};
190
+
191
+struct LoongArchPICCommonClass {
192
+ SysBusDeviceClass parent_class;
193
+
194
+ DeviceRealize parent_realize;
195
+};
196
#endif /* HW_LOONGARCH_PIC_COMMON_H */
197
--
198
2.43.5
diff view generated by jsdifflib
1
From: Bibo Mao <maobibo@loongson.cn>
1
Add vmstate pre_save and post_load interfaces, which can be used
2
2
by pic kvm driver in future.
3
Add numa test case for loongarch system, it passes to run
4
with command "make check-qtest".
5
3
6
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
7
Acked-by: Thomas Huth <thuth@redhat.com>
5
Reviewed-by: Song Gao <gaosong@loongson.cn>
8
Tested-by: Song Gao <gaosong@loongson.cn>
9
Message-Id: <20240528082155.938586-1-maobibo@loongson.cn>
10
Signed-off-by: Song Gao <gaosong@loongson.cn>
11
---
6
---
12
tests/qtest/meson.build | 2 +-
7
hw/intc/loongarch_pic_common.c | 26 ++++++++++++++++++++++++++
13
tests/qtest/numa-test.c | 53 +++++++++++++++++++++++++++++++++++++++++
8
include/hw/intc/loongarch_pic_common.h | 2 ++
14
2 files changed, 54 insertions(+), 1 deletion(-)
9
2 files changed, 28 insertions(+)
15
10
16
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
11
diff --git a/hw/intc/loongarch_pic_common.c b/hw/intc/loongarch_pic_common.c
17
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
18
--- a/tests/qtest/meson.build
13
--- a/hw/intc/loongarch_pic_common.c
19
+++ b/tests/qtest/meson.build
14
+++ b/hw/intc/loongarch_pic_common.c
20
@@ -XXX,XX +XXX,XX @@ qtests_hppa = ['boot-serial-test'] + \
15
@@ -XXX,XX +XXX,XX @@
21
(config_all_devices.has_key('CONFIG_VGA') ? ['display-vga-test'] : [])
16
#include "hw/qdev-properties.h"
22
17
#include "migration/vmstate.h"
23
qtests_loongarch64 = qtests_filter + \
18
24
- ['boot-serial-test']
19
+static int loongarch_pic_pre_save(void *opaque)
25
+ ['boot-serial-test', 'numa-test']
26
27
qtests_m68k = ['boot-serial-test'] + \
28
qtests_filter
29
diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/tests/qtest/numa-test.c
32
+++ b/tests/qtest/numa-test.c
33
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
34
qtest_quit(qts);
35
}
36
37
+static void loongarch64_numa_cpu(const void *data)
38
+{
20
+{
39
+ QDict *resp;
21
+ LoongArchPICCommonState *s = (LoongArchPICCommonState *)opaque;
40
+ QList *cpus;
22
+ LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_GET_CLASS(s);
41
+ QObject *e;
42
+ QTestState *qts;
43
+ g_autofree char *cli = NULL;
44
+
23
+
45
+ cli = make_cli(data, "-machine "
24
+ if (lpcc->pre_save) {
46
+ "smp.cpus=2,smp.sockets=2,smp.cores=1,smp.threads=1 "
25
+ return lpcc->pre_save(s);
47
+ "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
48
+ "-numa cpu,node-id=0,socket-id=1,core-id=0,thread-id=0 "
49
+ "-numa cpu,node-id=1,socket-id=0,core-id=0,thread-id=0");
50
+ qts = qtest_init(cli);
51
+ cpus = get_cpus(qts, &resp);
52
+ g_assert(cpus);
53
+
54
+ while ((e = qlist_pop(cpus))) {
55
+ QDict *cpu, *props;
56
+ int64_t socket, core, thread, node;
57
+
58
+ cpu = qobject_to(QDict, e);
59
+ g_assert(qdict_haskey(cpu, "props"));
60
+ props = qdict_get_qdict(cpu, "props");
61
+
62
+ g_assert(qdict_haskey(props, "node-id"));
63
+ node = qdict_get_int(props, "node-id");
64
+ g_assert(qdict_haskey(props, "socket-id"));
65
+ socket = qdict_get_int(props, "socket-id");
66
+ g_assert(qdict_haskey(props, "core-id"));
67
+ core = qdict_get_int(props, "core-id");
68
+ g_assert(qdict_haskey(props, "thread-id"));
69
+ thread = qdict_get_int(props, "thread-id");
70
+
71
+ if (socket == 0 && core == 0 && thread == 0) {
72
+ g_assert_cmpint(node, ==, 1);
73
+ } else if (socket == 1 && core == 0 && thread == 0) {
74
+ g_assert_cmpint(node, ==, 0);
75
+ } else {
76
+ g_assert(false);
77
+ }
78
+ qobject_unref(e);
79
+ }
26
+ }
80
+
27
+
81
+ qobject_unref(resp);
28
+ return 0;
82
+ qtest_quit(qts);
83
+}
29
+}
84
+
30
+
85
static void pc_dynamic_cpu_cfg(const void *data)
31
+static int loongarch_pic_post_load(void *opaque, int version_id)
86
{
32
+{
87
QObject *e;
33
+ LoongArchPICCommonState *s = (LoongArchPICCommonState *)opaque;
88
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
34
+ LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_GET_CLASS(s);
89
aarch64_numa_cpu);
35
+
90
}
36
+ if (lpcc->post_load) {
91
37
+ return lpcc->post_load(s, version_id);
92
+ if (!strcmp(arch, "loongarch64")) {
93
+ qtest_add_data_func("/numa/loongarch64/cpu/explicit", args,
94
+ loongarch64_numa_cpu);
95
+ }
38
+ }
96
+
39
+
97
out:
40
+ return 0;
98
return g_test_run();
41
+}
99
}
42
+
43
static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
44
{
45
LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
46
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_loongarch_pic_common = {
47
.name = "loongarch_pch_pic",
48
.version_id = 1,
49
.minimum_version_id = 1,
50
+ .pre_save = loongarch_pic_pre_save,
51
+ .post_load = loongarch_pic_post_load,
52
.fields = (const VMStateField[]) {
53
VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
54
VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
55
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
56
index XXXXXXX..XXXXXXX 100644
57
--- a/include/hw/intc/loongarch_pic_common.h
58
+++ b/include/hw/intc/loongarch_pic_common.h
59
@@ -XXX,XX +XXX,XX @@ struct LoongArchPICCommonClass {
60
SysBusDeviceClass parent_class;
61
62
DeviceRealize parent_realize;
63
+ int (*pre_save)(LoongArchPICCommonState *s);
64
+ int (*post_load)(LoongArchPICCommonState *s, int version_id);
65
};
66
#endif /* HW_LOONGARCH_PIC_COMMON_H */
100
--
67
--
101
2.34.1
68
2.43.5
diff view generated by jsdifflib
1
Use MemTxAttrs interface read_with_attrs/write_with_attrs
1
Remove definition about LoongArchPCHPIC and LOONGARCH_PCH_PIC, and
2
for virt_iocsr_misc_ops.
2
replace them with LoongArchPICCommonState and LOONGARCH_PIC_COMMON
3
separately. Also remove unnecessary header files.
3
4
4
Signed-off-by: Song Gao <gaosong@loongson.cn>
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
5
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
6
Message-Id: <20240528083855.1912757-3-gaosong@loongson.cn>
7
---
7
---
8
hw/loongarch/virt.c | 36 ++++++++++++++++++++++++------------
8
hw/intc/loongarch_pch_pic.c | 24 ++++++++++--------------
9
1 file changed, 24 insertions(+), 12 deletions(-)
9
hw/loongarch/virt.c | 2 +-
10
include/hw/intc/loongarch_pch_pic.h | 4 ----
11
3 files changed, 11 insertions(+), 19 deletions(-)
10
12
13
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/intc/loongarch_pch_pic.c
16
+++ b/hw/intc/loongarch_pch_pic.c
17
@@ -XXX,XX +XXX,XX @@
18
19
#include "qemu/osdep.h"
20
#include "qemu/bitops.h"
21
-#include "hw/sysbus.h"
22
-#include "hw/loongarch/virt.h"
23
-#include "hw/pci-host/ls7a.h"
24
#include "hw/irq.h"
25
#include "hw/intc/loongarch_pch_pic.h"
26
-#include "hw/qdev-properties.h"
27
-#include "migration/vmstate.h"
28
#include "trace.h"
29
#include "qapi/error.h"
30
31
-static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level)
32
+static void pch_pic_update_irq(LoongArchPICCommonState *s, uint64_t mask,
33
+ int level)
34
{
35
uint64_t val;
36
int irq;
37
@@ -XXX,XX +XXX,XX @@ static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level)
38
39
static void pch_pic_irq_handler(void *opaque, int irq, int level)
40
{
41
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
42
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
43
uint64_t mask = 1ULL << irq;
44
45
assert(irq < s->irq_num);
46
@@ -XXX,XX +XXX,XX @@ static void pch_pic_irq_handler(void *opaque, int irq, int level)
47
static uint64_t loongarch_pch_pic_low_readw(void *opaque, hwaddr addr,
48
unsigned size)
49
{
50
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
51
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
52
uint64_t val = 0;
53
uint32_t offset = addr & 0xfff;
54
55
@@ -XXX,XX +XXX,XX @@ static uint64_t get_writew_val(uint64_t value, uint32_t target, bool hi)
56
static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,
57
uint64_t value, unsigned size)
58
{
59
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
60
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
61
uint32_t offset, old_valid, data = (uint32_t)value;
62
uint64_t old, int_mask;
63
offset = addr & 0xfff;
64
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,
65
static uint64_t loongarch_pch_pic_high_readw(void *opaque, hwaddr addr,
66
unsigned size)
67
{
68
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
69
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
70
uint64_t val = 0;
71
uint32_t offset = addr & 0xfff;
72
73
@@ -XXX,XX +XXX,XX @@ static uint64_t loongarch_pch_pic_high_readw(void *opaque, hwaddr addr,
74
static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr,
75
uint64_t value, unsigned size)
76
{
77
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
78
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
79
uint32_t offset, data = (uint32_t)value;
80
offset = addr & 0xfff;
81
82
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr,
83
static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr,
84
unsigned size)
85
{
86
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
87
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
88
uint64_t val = 0;
89
uint32_t offset = (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET;
90
int64_t offset_tmp;
91
@@ -XXX,XX +XXX,XX @@ static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr,
92
static void loongarch_pch_pic_writeb(void *opaque, hwaddr addr,
93
uint64_t data, unsigned size)
94
{
95
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
96
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
97
int32_t offset_tmp;
98
uint32_t offset = (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET;
99
100
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps loongarch_pch_pic_reg8_ops = {
101
102
static void loongarch_pch_pic_reset(DeviceState *d)
103
{
104
- LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(d);
105
+ LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(d);
106
int i;
107
108
s->int_mask = -1;
11
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
109
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
12
index XXXXXXX..XXXXXXX 100644
110
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/loongarch/virt.c
111
--- a/hw/loongarch/virt.c
14
+++ b/hw/loongarch/virt.c
112
+++ b/hw/loongarch/virt.c
15
@@ -XXX,XX +XXX,XX @@ static void virt_firmware_init(LoongArchVirtMachineState *lvms)
113
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
16
}
114
/* Add Extend I/O Interrupt Controller node */
17
115
fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle);
18
116
19
-static void virt_iocsr_misc_write(void *opaque, hwaddr addr,
117
- pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
20
- uint64_t val, unsigned size)
118
+ pch_pic = qdev_new(TYPE_LOONGARCH_PIC);
21
+static MemTxResult virt_iocsr_misc_write(void *opaque, hwaddr addr,
119
num = VIRT_PCH_PIC_IRQ_NUM;
22
+ uint64_t val, unsigned size,
120
qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
23
+ MemTxAttrs attrs)
121
d = SYS_BUS_DEVICE(pch_pic);
24
{
122
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
25
+ return MEMTX_OK;
123
index XXXXXXX..XXXXXXX 100644
26
}
124
--- a/include/hw/intc/loongarch_pch_pic.h
27
125
+++ b/include/hw/intc/loongarch_pch_pic.h
28
-static uint64_t virt_iocsr_misc_read(void *opaque, hwaddr addr, unsigned size)
126
@@ -XXX,XX +XXX,XX @@ struct LoongarchPICClass {
29
+static MemTxResult virt_iocsr_misc_read(void *opaque, hwaddr addr,
127
DeviceRealize parent_realize;
30
+ uint64_t *data,
128
};
31
+ unsigned size, MemTxAttrs attrs)
129
32
{
130
-#define TYPE_LOONGARCH_PCH_PIC TYPE_LOONGARCH_PIC
33
- uint64_t ret;
131
-typedef struct LoongArchPICCommonState LoongArchPCHPIC;
34
+ uint64_t ret = 0;
132
-#define LOONGARCH_PCH_PIC(obj) ((struct LoongArchPICCommonState *)(obj))
35
133
-
36
switch (addr) {
134
#endif /* HW_LOONGARCH_PCH_PIC_H */
37
case VERSION_REG:
38
- return 0x11ULL;
39
+ ret = 0x11ULL;
40
+ break;
41
case FEATURE_REG:
42
ret = BIT(IOCSRF_MSI) | BIT(IOCSRF_EXTIOI) | BIT(IOCSRF_CSRIPI);
43
if (kvm_enabled()) {
44
ret |= BIT(IOCSRF_VM);
45
}
46
- return ret;
47
+ break;
48
case VENDOR_REG:
49
- return 0x6e6f73676e6f6f4cULL; /* "Loongson" */
50
+ ret = 0x6e6f73676e6f6f4cULL; /* "Loongson" */
51
+ break;
52
case CPUNAME_REG:
53
- return 0x303030354133ULL; /* "3A5000" */
54
+ ret = 0x303030354133ULL; /* "3A5000" */
55
+ break;
56
case MISC_FUNC_REG:
57
- return BIT_ULL(IOCSRM_EXTIOI_EN);
58
+ ret = BIT_ULL(IOCSRM_EXTIOI_EN);
59
+ break;
60
+ default:
61
+ g_assert_not_reached();
62
}
63
- return 0ULL;
64
+
65
+ *data = ret;
66
+ return MEMTX_OK;
67
}
68
69
static const MemoryRegionOps virt_iocsr_misc_ops = {
70
- .read = virt_iocsr_misc_read,
71
- .write = virt_iocsr_misc_write,
72
+ .read_with_attrs = virt_iocsr_misc_read,
73
+ .write_with_attrs = virt_iocsr_misc_write,
74
.endianness = DEVICE_LITTLE_ENDIAN,
75
.valid = {
76
.min_access_size = 4,
77
--
135
--
78
2.34.1
136
2.43.5
diff view generated by jsdifflib
1
On LoongArch, IRQs can be routed to four vcpus with hardware extended
1
Add common header file include/hw/intc/loongarch_extioi_common.h, and
2
IRQ model. This patch adds the virt extension definition so that
2
move some macro definition from include/hw/intc/loongarch_extioi.h to
3
the IRQ can route to 256 vcpus.
3
the common header file.
4
4
5
1.Extended IRQ model:
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
6
|
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
7
+-----------+ +-------------|--------+ +-----------+
7
---
8
| IPI/Timer | --> | CPUINTC(0-3)|(4-255) | <-- | IPI/Timer |
8
include/hw/intc/loongarch_extioi.h | 50 +------------------
9
+-----------+ +-------------|--------+ +-----------+
9
include/hw/intc/loongarch_extioi_common.h | 58 +++++++++++++++++++++++
10
^ |
10
2 files changed, 59 insertions(+), 49 deletions(-)
11
|
11
create mode 100644 include/hw/intc/loongarch_extioi_common.h
12
+---------+
13
| EIOINTC |
14
+---------+
15
^ ^
16
| |
17
+---------+ +---------+
18
| PCH-PIC | | PCH-MSI |
19
+---------+ +---------+
20
^ ^ ^
21
| | |
22
+--------+ +---------+ +---------+
23
| UARTs | | Devices | | Devices |
24
+--------+ +---------+ +---------+
25
12
26
2.Virt extended IRQ model:
27
28
+-----+ +---------------+ +-------+
29
| IPI |--> | CPUINTC(0-255)| <-- | Timer |
30
+-----+ +---------------+ +-------+
31
^
32
|
33
+-----------+
34
| V-EIOINTC |
35
+-----------+
36
^ ^
37
| |
38
+---------+ +---------+
39
| PCH-PIC | | PCH-MSI |
40
+---------+ +---------+
41
^ ^ ^
42
| | |
43
+--------+ +---------+ +---------+
44
| UARTs | | Devices | | Devices |
45
+--------+ +---------+ +---------+
46
47
Signed-off-by: Song Gao <gaosong@loongson.cn>
48
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
49
Message-Id: <20240528083855.1912757-2-gaosong@loongson.cn>
50
---
51
hw/intc/loongarch_extioi.c | 88 ++++++++++++++++++++++++++++--
52
hw/loongarch/virt.c | 60 +++++++++++++-------
53
include/hw/intc/loongarch_extioi.h | 21 +++++++
54
3 files changed, 146 insertions(+), 23 deletions(-)
55
56
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/intc/loongarch_extioi.c
59
+++ b/hw/intc/loongarch_extioi.c
60
@@ -XXX,XX +XXX,XX @@ static inline void extioi_update_sw_coremap(LoongArchExtIOI *s, int irq,
61
62
for (i = 0; i < 4; i++) {
63
cpu = val & 0xff;
64
- cpu = ctz32(cpu);
65
- cpu = (cpu >= 4) ? 0 : cpu;
66
val = val >> 8;
67
68
+ if (!(s->status & BIT(EXTIOI_ENABLE_CPU_ENCODE))) {
69
+ cpu = ctz32(cpu);
70
+ cpu = (cpu >= 4) ? 0 : cpu;
71
+ }
72
+
73
if (s->sw_coremap[irq + i] == cpu) {
74
continue;
75
}
76
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps extioi_ops = {
77
.endianness = DEVICE_LITTLE_ENDIAN,
78
};
79
80
+static MemTxResult extioi_virt_readw(void *opaque, hwaddr addr, uint64_t *data,
81
+ unsigned size, MemTxAttrs attrs)
82
+{
83
+ LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
84
+
85
+ switch (addr) {
86
+ case EXTIOI_VIRT_FEATURES:
87
+ *data = s->features;
88
+ break;
89
+ case EXTIOI_VIRT_CONFIG:
90
+ *data = s->status;
91
+ break;
92
+ default:
93
+ g_assert_not_reached();
94
+ }
95
+
96
+ return MEMTX_OK;
97
+}
98
+
99
+static MemTxResult extioi_virt_writew(void *opaque, hwaddr addr,
100
+ uint64_t val, unsigned size,
101
+ MemTxAttrs attrs)
102
+{
103
+ LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
104
+
105
+ switch (addr) {
106
+ case EXTIOI_VIRT_FEATURES:
107
+ return MEMTX_ACCESS_ERROR;
108
+
109
+ case EXTIOI_VIRT_CONFIG:
110
+ /*
111
+ * extioi features can only be set at disabled status
112
+ */
113
+ if ((s->status & BIT(EXTIOI_ENABLE)) && val) {
114
+ return MEMTX_ACCESS_ERROR;
115
+ }
116
+
117
+ s->status = val & s->features;
118
+ break;
119
+ default:
120
+ g_assert_not_reached();
121
+ }
122
+ return MEMTX_OK;
123
+}
124
+
125
+static const MemoryRegionOps extioi_virt_ops = {
126
+ .read_with_attrs = extioi_virt_readw,
127
+ .write_with_attrs = extioi_virt_writew,
128
+ .impl.min_access_size = 4,
129
+ .impl.max_access_size = 4,
130
+ .valid.min_access_size = 4,
131
+ .valid.max_access_size = 8,
132
+ .endianness = DEVICE_LITTLE_ENDIAN,
133
+};
134
+
135
static void loongarch_extioi_realize(DeviceState *dev, Error **errp)
136
{
137
LoongArchExtIOI *s = LOONGARCH_EXTIOI(dev);
138
@@ -XXX,XX +XXX,XX @@ static void loongarch_extioi_realize(DeviceState *dev, Error **errp)
139
memory_region_init_io(&s->extioi_system_mem, OBJECT(s), &extioi_ops,
140
s, "extioi_system_mem", 0x900);
141
sysbus_init_mmio(sbd, &s->extioi_system_mem);
142
+
143
+ if (s->features & BIT(EXTIOI_HAS_VIRT_EXTENSION)) {
144
+ memory_region_init_io(&s->virt_extend, OBJECT(s), &extioi_virt_ops,
145
+ s, "extioi_virt", EXTIOI_VIRT_SIZE);
146
+ sysbus_init_mmio(sbd, &s->virt_extend);
147
+ s->features |= EXTIOI_VIRT_HAS_FEATURES;
148
+ } else {
149
+ s->status |= BIT(EXTIOI_ENABLE);
150
+ }
151
+
152
s->cpu = g_new0(ExtIOICore, s->num_cpu);
153
if (s->cpu == NULL) {
154
error_setg(errp, "Memory allocation for ExtIOICore faile");
155
@@ -XXX,XX +XXX,XX @@ static void loongarch_extioi_finalize(Object *obj)
156
g_free(s->cpu);
157
}
158
159
+static void loongarch_extioi_reset(DeviceState *d)
160
+{
161
+ LoongArchExtIOI *s = LOONGARCH_EXTIOI(d);
162
+
163
+ s->status = 0;
164
+}
165
+
166
static int vmstate_extioi_post_load(void *opaque, int version_id)
167
{
168
LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
169
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_extioi_core = {
170
171
static const VMStateDescription vmstate_loongarch_extioi = {
172
.name = TYPE_LOONGARCH_EXTIOI,
173
- .version_id = 2,
174
- .minimum_version_id = 2,
175
+ .version_id = 3,
176
+ .minimum_version_id = 3,
177
.post_load = vmstate_extioi_post_load,
178
.fields = (const VMStateField[]) {
179
VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOI, EXTIOI_IRQS_GROUP_COUNT),
180
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_loongarch_extioi = {
181
182
VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOI, num_cpu,
183
vmstate_extioi_core, ExtIOICore),
184
+ VMSTATE_UINT32(features, LoongArchExtIOI),
185
+ VMSTATE_UINT32(status, LoongArchExtIOI),
186
VMSTATE_END_OF_LIST()
187
}
188
};
189
190
static Property extioi_properties[] = {
191
DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOI, num_cpu, 1),
192
+ DEFINE_PROP_BIT("has-virtualization-extension", LoongArchExtIOI, features,
193
+ EXTIOI_HAS_VIRT_EXTENSION, 0),
194
DEFINE_PROP_END_OF_LIST(),
195
};
196
197
@@ -XXX,XX +XXX,XX @@ static void loongarch_extioi_class_init(ObjectClass *klass, void *data)
198
DeviceClass *dc = DEVICE_CLASS(klass);
199
200
dc->realize = loongarch_extioi_realize;
201
+ dc->reset = loongarch_extioi_reset;
202
device_class_set_props(dc, extioi_properties);
203
dc->vmsd = &vmstate_loongarch_extioi;
204
}
205
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
206
index XXXXXXX..XXXXXXX 100644
207
--- a/hw/loongarch/virt.c
208
+++ b/hw/loongarch/virt.c
209
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
210
uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_phandle;
211
212
/*
213
- * The connection of interrupts:
214
- * +-----+ +---------+ +-------+
215
- * | IPI |--> | CPUINTC | <-- | Timer |
216
- * +-----+ +---------+ +-------+
217
- * ^
218
- * |
219
- * +---------+
220
- * | EIOINTC |
221
- * +---------+
222
- * ^ ^
223
- * | |
224
- * +---------+ +---------+
225
- * | PCH-PIC | | PCH-MSI |
226
- * +---------+ +---------+
227
- * ^ ^ ^
228
- * | | |
229
- * +--------+ +---------+ +---------+
230
- * | UARTs | | Devices | | Devices |
231
- * +--------+ +---------+ +---------+
232
+ * Extended IRQ model.
233
+ * |
234
+ * +-----------+ +-------------|--------+ +-----------+
235
+ * | IPI/Timer | --> | CPUINTC(0-3)|(4-255) | <-- | IPI/Timer |
236
+ * +-----------+ +-------------|--------+ +-----------+
237
+ * ^ |
238
+ * |
239
+ * +---------+
240
+ * | EIOINTC |
241
+ * +---------+
242
+ * ^ ^
243
+ * | |
244
+ * +---------+ +---------+
245
+ * | PCH-PIC | | PCH-MSI |
246
+ * +---------+ +---------+
247
+ * ^ ^ ^
248
+ * | | |
249
+ * +--------+ +---------+ +---------+
250
+ * | UARTs | | Devices | | Devices |
251
+ * +--------+ +---------+ +---------+
252
+ *
253
+ * Virt extended IRQ model.
254
+ *
255
+ * +-----+ +---------------+ +-------+
256
+ * | IPI |--> | CPUINTC(0-255)| <-- | Timer |
257
+ * +-----+ +---------------+ +-------+
258
+ * ^
259
+ * |
260
+ * +-----------+
261
+ * | V-EIOINTC |
262
+ * +-----------+
263
+ * ^ ^
264
+ * | |
265
+ * +---------+ +---------+
266
+ * | PCH-PIC | | PCH-MSI |
267
+ * +---------+ +---------+
268
+ * ^ ^ ^
269
+ * | | |
270
+ * +--------+ +---------+ +---------+
271
+ * | UARTs | | Devices | | Devices |
272
+ * +--------+ +---------+ +---------+
273
*/
274
275
/* Create IPI device */
276
diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
13
diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
277
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
278
--- a/include/hw/intc/loongarch_extioi.h
15
--- a/include/hw/intc/loongarch_extioi.h
279
+++ b/include/hw/intc/loongarch_extioi.h
16
+++ b/include/hw/intc/loongarch_extioi.h
280
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@
281
#define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET)
18
* Copyright (C) 2021 Loongson Technology Corporation Limited
282
#define EXTIOI_SIZE 0x800
19
*/
283
20
21
-#include "hw/sysbus.h"
22
-#include "hw/loongarch/virt.h"
23
-
24
#ifndef LOONGARCH_EXTIOI_H
25
#define LOONGARCH_EXTIOI_H
26
27
-#define LS3A_INTC_IP 8
28
-#define EXTIOI_IRQS (256)
29
-#define EXTIOI_IRQS_BITMAP_SIZE (256 / 8)
30
-/* irq from EXTIOI is routed to no more than 4 cpus */
31
-#define EXTIOI_CPUS (4)
32
-/* map to ipnum per 32 irqs */
33
-#define EXTIOI_IRQS_IPMAP_SIZE (256 / 32)
34
-#define EXTIOI_IRQS_COREMAP_SIZE 256
35
-#define EXTIOI_IRQS_NODETYPE_COUNT 16
36
-#define EXTIOI_IRQS_GROUP_COUNT 8
37
-
38
-#define APIC_OFFSET 0x400
39
-#define APIC_BASE (0x1000ULL + APIC_OFFSET)
40
-
41
-#define EXTIOI_NODETYPE_START (0x4a0 - APIC_OFFSET)
42
-#define EXTIOI_NODETYPE_END (0x4c0 - APIC_OFFSET)
43
-#define EXTIOI_IPMAP_START (0x4c0 - APIC_OFFSET)
44
-#define EXTIOI_IPMAP_END (0x4c8 - APIC_OFFSET)
45
-#define EXTIOI_ENABLE_START (0x600 - APIC_OFFSET)
46
-#define EXTIOI_ENABLE_END (0x620 - APIC_OFFSET)
47
-#define EXTIOI_BOUNCE_START (0x680 - APIC_OFFSET)
48
-#define EXTIOI_BOUNCE_END (0x6a0 - APIC_OFFSET)
49
-#define EXTIOI_ISR_START (0x700 - APIC_OFFSET)
50
-#define EXTIOI_ISR_END (0x720 - APIC_OFFSET)
51
-#define EXTIOI_COREISR_START (0x800 - APIC_OFFSET)
52
-#define EXTIOI_COREISR_END (0xB20 - APIC_OFFSET)
53
-#define EXTIOI_COREMAP_START (0xC00 - APIC_OFFSET)
54
-#define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET)
55
-#define EXTIOI_SIZE 0x800
56
-
57
-#define EXTIOI_VIRT_BASE (0x40000000)
58
-#define EXTIOI_VIRT_SIZE (0x1000)
59
-#define EXTIOI_VIRT_FEATURES (0x0)
60
-#define EXTIOI_HAS_VIRT_EXTENSION (0)
61
-#define EXTIOI_HAS_ENABLE_OPTION (1)
62
-#define EXTIOI_HAS_INT_ENCODE (2)
63
-#define EXTIOI_HAS_CPU_ENCODE (3)
64
-#define EXTIOI_VIRT_HAS_FEATURES (BIT(EXTIOI_HAS_VIRT_EXTENSION) \
65
- | BIT(EXTIOI_HAS_ENABLE_OPTION) \
66
- | BIT(EXTIOI_HAS_CPU_ENCODE))
67
-#define EXTIOI_VIRT_CONFIG (0x4)
68
-#define EXTIOI_ENABLE (1)
69
-#define EXTIOI_ENABLE_INT_ENCODE (2)
70
-#define EXTIOI_ENABLE_CPU_ENCODE (3)
71
-#define EXTIOI_VIRT_COREMAP_START (0x40)
72
-#define EXTIOI_VIRT_COREMAP_END (0x240)
73
+#include "hw/intc/loongarch_extioi_common.h"
74
75
typedef struct ExtIOICore {
76
uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
77
diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h
78
new file mode 100644
79
index XXXXXXX..XXXXXXX
80
--- /dev/null
81
+++ b/include/hw/intc/loongarch_extioi_common.h
82
@@ -XXX,XX +XXX,XX @@
83
+/* SPDX-License-Identifier: GPL-2.0-or-later */
84
+/*
85
+ * LoongArch 3A5000 ext interrupt controller definitions
86
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
87
+ */
88
+
89
+#ifndef LOONGARCH_EXTIOI_COMMON_H
90
+#define LOONGARCH_EXTIOI_COMMON_H
91
+
92
+#include "hw/sysbus.h"
93
+#include "hw/loongarch/virt.h"
94
+
95
+#define LS3A_INTC_IP 8
96
+#define EXTIOI_IRQS (256)
97
+#define EXTIOI_IRQS_BITMAP_SIZE (256 / 8)
98
+/* irq from EXTIOI is routed to no more than 4 cpus */
99
+#define EXTIOI_CPUS (4)
100
+/* map to ipnum per 32 irqs */
101
+#define EXTIOI_IRQS_IPMAP_SIZE (256 / 32)
102
+#define EXTIOI_IRQS_COREMAP_SIZE 256
103
+#define EXTIOI_IRQS_NODETYPE_COUNT 16
104
+#define EXTIOI_IRQS_GROUP_COUNT 8
105
+
106
+#define APIC_OFFSET 0x400
107
+#define APIC_BASE (0x1000ULL + APIC_OFFSET)
108
+#define EXTIOI_NODETYPE_START (0x4a0 - APIC_OFFSET)
109
+#define EXTIOI_NODETYPE_END (0x4c0 - APIC_OFFSET)
110
+#define EXTIOI_IPMAP_START (0x4c0 - APIC_OFFSET)
111
+#define EXTIOI_IPMAP_END (0x4c8 - APIC_OFFSET)
112
+#define EXTIOI_ENABLE_START (0x600 - APIC_OFFSET)
113
+#define EXTIOI_ENABLE_END (0x620 - APIC_OFFSET)
114
+#define EXTIOI_BOUNCE_START (0x680 - APIC_OFFSET)
115
+#define EXTIOI_BOUNCE_END (0x6a0 - APIC_OFFSET)
116
+#define EXTIOI_ISR_START (0x700 - APIC_OFFSET)
117
+#define EXTIOI_ISR_END (0x720 - APIC_OFFSET)
118
+#define EXTIOI_COREISR_START (0x800 - APIC_OFFSET)
119
+#define EXTIOI_COREISR_END (0xB20 - APIC_OFFSET)
120
+#define EXTIOI_COREMAP_START (0xC00 - APIC_OFFSET)
121
+#define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET)
122
+#define EXTIOI_SIZE 0x800
123
+
284
+#define EXTIOI_VIRT_BASE (0x40000000)
124
+#define EXTIOI_VIRT_BASE (0x40000000)
285
+#define EXTIOI_VIRT_SIZE (0x1000)
125
+#define EXTIOI_VIRT_SIZE (0x1000)
286
+#define EXTIOI_VIRT_FEATURES (0x0)
126
+#define EXTIOI_VIRT_FEATURES (0x0)
287
+#define EXTIOI_HAS_VIRT_EXTENSION (0)
127
+#define EXTIOI_HAS_VIRT_EXTENSION (0)
288
+#define EXTIOI_HAS_ENABLE_OPTION (1)
128
+#define EXTIOI_HAS_ENABLE_OPTION (1)
289
+#define EXTIOI_HAS_INT_ENCODE (2)
129
+#define EXTIOI_HAS_INT_ENCODE (2)
290
+#define EXTIOI_HAS_CPU_ENCODE (3)
130
+#define EXTIOI_HAS_CPU_ENCODE (3)
291
+#define EXTIOI_VIRT_HAS_FEATURES (BIT(EXTIOI_HAS_VIRT_EXTENSION) \
131
+#define EXTIOI_VIRT_HAS_FEATURES (BIT(EXTIOI_HAS_VIRT_EXTENSION) \
292
+ | BIT(EXTIOI_HAS_ENABLE_OPTION) \
132
+ | BIT(EXTIOI_HAS_ENABLE_OPTION) \
293
+ | BIT(EXTIOI_HAS_INT_ENCODE) \
294
+ | BIT(EXTIOI_HAS_CPU_ENCODE))
133
+ | BIT(EXTIOI_HAS_CPU_ENCODE))
295
+#define EXTIOI_VIRT_CONFIG (0x4)
134
+#define EXTIOI_VIRT_CONFIG (0x4)
296
+#define EXTIOI_ENABLE (1)
135
+#define EXTIOI_ENABLE (1)
297
+#define EXTIOI_ENABLE_INT_ENCODE (2)
136
+#define EXTIOI_ENABLE_INT_ENCODE (2)
298
+#define EXTIOI_ENABLE_CPU_ENCODE (3)
137
+#define EXTIOI_ENABLE_CPU_ENCODE (3)
299
+#define EXTIOI_VIRT_COREMAP_START (0x40)
138
+#define EXTIOI_VIRT_COREMAP_START (0x40)
300
+#define EXTIOI_VIRT_COREMAP_END (0x240)
139
+#define EXTIOI_VIRT_COREMAP_END (0x240)
301
+
140
+#endif /* LOONGARCH_EXTIOI_H */
302
typedef struct ExtIOICore {
303
uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
304
DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS);
305
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(LoongArchExtIOI, LOONGARCH_EXTIOI)
306
struct LoongArchExtIOI {
307
SysBusDevice parent_obj;
308
uint32_t num_cpu;
309
+ uint32_t features;
310
+ uint32_t status;
311
/* hardware state */
312
uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
313
uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
314
@@ -XXX,XX +XXX,XX @@ struct LoongArchExtIOI {
315
qemu_irq irq[EXTIOI_IRQS];
316
ExtIOICore *cpu;
317
MemoryRegion extioi_system_mem;
318
+ MemoryRegion virt_extend;
319
};
320
#endif /* LOONGARCH_EXTIOI_H */
321
--
141
--
322
2.34.1
142
2.43.5
diff view generated by jsdifflib
New patch
1
Move definiton of structure LoongArchExtIOI from header file loongarch_extioi.h
2
to file loongarch_extioi_common.h.
1
3
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
5
Reviewed-by: Song Gao <gaosong@loongson.cn>
6
---
7
include/hw/intc/loongarch_extioi.h | 26 ----------------------
8
include/hw/intc/loongarch_extioi_common.h | 27 +++++++++++++++++++++++
9
2 files changed, 27 insertions(+), 26 deletions(-)
10
11
diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/intc/loongarch_extioi.h
14
+++ b/include/hw/intc/loongarch_extioi.h
15
@@ -XXX,XX +XXX,XX @@
16
17
#include "hw/intc/loongarch_extioi_common.h"
18
19
-typedef struct ExtIOICore {
20
- uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
21
- DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS);
22
- qemu_irq parent_irq[LS3A_INTC_IP];
23
-} ExtIOICore;
24
-
25
#define TYPE_LOONGARCH_EXTIOI "loongarch.extioi"
26
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchExtIOI, LOONGARCH_EXTIOI)
27
-struct LoongArchExtIOI {
28
- SysBusDevice parent_obj;
29
- uint32_t num_cpu;
30
- uint32_t features;
31
- uint32_t status;
32
- /* hardware state */
33
- uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
34
- uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
35
- uint32_t isr[EXTIOI_IRQS / 32];
36
- uint32_t enable[EXTIOI_IRQS / 32];
37
- uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4];
38
- uint32_t coremap[EXTIOI_IRQS / 4];
39
- uint32_t sw_pending[EXTIOI_IRQS / 32];
40
- uint8_t sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE];
41
- uint8_t sw_coremap[EXTIOI_IRQS];
42
- qemu_irq irq[EXTIOI_IRQS];
43
- ExtIOICore *cpu;
44
- MemoryRegion extioi_system_mem;
45
- MemoryRegion virt_extend;
46
-};
47
#endif /* LOONGARCH_EXTIOI_H */
48
diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/include/hw/intc/loongarch_extioi_common.h
51
+++ b/include/hw/intc/loongarch_extioi_common.h
52
@@ -XXX,XX +XXX,XX @@
53
#define EXTIOI_ENABLE_CPU_ENCODE (3)
54
#define EXTIOI_VIRT_COREMAP_START (0x40)
55
#define EXTIOI_VIRT_COREMAP_END (0x240)
56
+
57
+typedef struct ExtIOICore {
58
+ uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
59
+ DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS);
60
+ qemu_irq parent_irq[LS3A_INTC_IP];
61
+} ExtIOICore;
62
+
63
+struct LoongArchExtIOI {
64
+ SysBusDevice parent_obj;
65
+ uint32_t num_cpu;
66
+ uint32_t features;
67
+ uint32_t status;
68
+ /* hardware state */
69
+ uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
70
+ uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
71
+ uint32_t isr[EXTIOI_IRQS / 32];
72
+ uint32_t enable[EXTIOI_IRQS / 32];
73
+ uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4];
74
+ uint32_t coremap[EXTIOI_IRQS / 4];
75
+ uint32_t sw_pending[EXTIOI_IRQS / 32];
76
+ uint8_t sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE];
77
+ uint8_t sw_coremap[EXTIOI_IRQS];
78
+ qemu_irq irq[EXTIOI_IRQS];
79
+ ExtIOICore *cpu;
80
+ MemoryRegion extioi_system_mem;
81
+ MemoryRegion virt_extend;
82
+};
83
#endif /* LOONGARCH_EXTIOI_H */
84
--
85
2.43.5
diff view generated by jsdifflib
New patch
1
Rename structure LoongArchExtIOI with LoongArchExtIOICommonState,
2
since it is defined in file loongarch_extioi_common.h
1
3
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
5
Reviewed-by: Song Gao <gaosong@loongson.cn>
6
---
7
include/hw/intc/loongarch_extioi.h | 1 +
8
include/hw/intc/loongarch_extioi_common.h | 2 +-
9
2 files changed, 2 insertions(+), 1 deletion(-)
10
11
diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/intc/loongarch_extioi.h
14
+++ b/include/hw/intc/loongarch_extioi.h
15
@@ -XXX,XX +XXX,XX @@
16
17
#include "hw/intc/loongarch_extioi_common.h"
18
19
+#define LoongArchExtIOI LoongArchExtIOICommonState
20
#define TYPE_LOONGARCH_EXTIOI "loongarch.extioi"
21
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchExtIOI, LOONGARCH_EXTIOI)
22
#endif /* LOONGARCH_EXTIOI_H */
23
diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/intc/loongarch_extioi_common.h
26
+++ b/include/hw/intc/loongarch_extioi_common.h
27
@@ -XXX,XX +XXX,XX @@ typedef struct ExtIOICore {
28
qemu_irq parent_irq[LS3A_INTC_IP];
29
} ExtIOICore;
30
31
-struct LoongArchExtIOI {
32
+struct LoongArchExtIOICommonState {
33
SysBusDevice parent_obj;
34
uint32_t num_cpu;
35
uint32_t features;
36
--
37
2.43.5
diff view generated by jsdifflib
1
From: lanyanzhi <lanyanzhi22b@ict.ac.cn>
1
With some structure such as vmstate and property, rename LoongArchExtIOI
2
with LoongArchExtIOICommonState, these common structure will be moved
3
to common file.
2
4
3
description:
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
4
loongarch_cpu_dump_state() want to dump all loongarch cpu
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
5
state registers, but there is a tiny typographical error when
7
---
6
printing "PRCFG2".
8
hw/intc/loongarch_extioi.c | 41 +++++++++++++++++++++++---------------
9
1 file changed, 25 insertions(+), 16 deletions(-)
7
10
8
Cc: qemu-stable@nongnu.org
11
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
9
Signed-off-by: lanyanzhi <lanyanzhi22b@ict.ac.cn>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Song Gao <gaosong@loongson.cn>
12
Message-Id: <20240604073831.666690-1-lanyanzhi22b@ict.ac.cn>
13
Signed-off-by: Song Gao <gaosong@loongson.cn>
14
---
15
target/loongarch/cpu.c | 2 +-
16
1 file changed, 1 insertion(+), 1 deletion(-)
17
18
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
19
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
20
--- a/target/loongarch/cpu.c
13
--- a/hw/intc/loongarch_extioi.c
21
+++ b/target/loongarch/cpu.c
14
+++ b/hw/intc/loongarch_extioi.c
22
@@ -XXX,XX +XXX,XX @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
15
@@ -XXX,XX +XXX,XX @@ static int vmstate_extioi_post_load(void *opaque, int version_id)
23
qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY);
16
return 0;
24
qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 ","
17
}
25
" PRCFG3=%016" PRIx64 "\n",
18
26
- env->CSR_PRCFG1, env->CSR_PRCFG3, env->CSR_PRCFG3);
19
+static int loongarch_extioi_common_post_load(void *opaque, int version_id)
27
+ env->CSR_PRCFG1, env->CSR_PRCFG2, env->CSR_PRCFG3);
20
+{
28
qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY);
21
+ return vmstate_extioi_post_load(opaque, version_id);
29
qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV);
22
+}
30
qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA);
23
+
24
static const VMStateDescription vmstate_extioi_core = {
25
.name = "extioi-core",
26
.version_id = 1,
27
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_extioi_core = {
28
};
29
30
static const VMStateDescription vmstate_loongarch_extioi = {
31
- .name = TYPE_LOONGARCH_EXTIOI,
32
+ .name = "loongarch.extioi",
33
.version_id = 3,
34
.minimum_version_id = 3,
35
- .post_load = vmstate_extioi_post_load,
36
+ .post_load = loongarch_extioi_common_post_load,
37
.fields = (const VMStateField[]) {
38
- VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOI, EXTIOI_IRQS_GROUP_COUNT),
39
- VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOI,
40
+ VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOICommonState,
41
+ EXTIOI_IRQS_GROUP_COUNT),
42
+ VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOICommonState,
43
EXTIOI_IRQS_NODETYPE_COUNT / 2),
44
- VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOI, EXTIOI_IRQS / 32),
45
- VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOI, EXTIOI_IRQS / 32),
46
- VMSTATE_UINT32_ARRAY(ipmap, LoongArchExtIOI, EXTIOI_IRQS_IPMAP_SIZE / 4),
47
- VMSTATE_UINT32_ARRAY(coremap, LoongArchExtIOI, EXTIOI_IRQS / 4),
48
-
49
- VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOI, num_cpu,
50
- vmstate_extioi_core, ExtIOICore),
51
- VMSTATE_UINT32(features, LoongArchExtIOI),
52
- VMSTATE_UINT32(status, LoongArchExtIOI),
53
+ VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOICommonState,
54
+ EXTIOI_IRQS / 32),
55
+ VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOICommonState,
56
+ EXTIOI_IRQS / 32),
57
+ VMSTATE_UINT32_ARRAY(ipmap, LoongArchExtIOICommonState,
58
+ EXTIOI_IRQS_IPMAP_SIZE / 4),
59
+ VMSTATE_UINT32_ARRAY(coremap, LoongArchExtIOICommonState,
60
+ EXTIOI_IRQS / 4),
61
+ VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOICommonState,
62
+ num_cpu, vmstate_extioi_core, ExtIOICore),
63
+ VMSTATE_UINT32(features, LoongArchExtIOICommonState),
64
+ VMSTATE_UINT32(status, LoongArchExtIOICommonState),
65
VMSTATE_END_OF_LIST()
66
}
67
};
68
69
static Property extioi_properties[] = {
70
- DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOI, num_cpu, 1),
71
- DEFINE_PROP_BIT("has-virtualization-extension", LoongArchExtIOI, features,
72
- EXTIOI_HAS_VIRT_EXTENSION, 0),
73
+ DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOICommonState, num_cpu, 1),
74
+ DEFINE_PROP_BIT("has-virtualization-extension", LoongArchExtIOICommonState,
75
+ features, EXTIOI_HAS_VIRT_EXTENSION, 0),
76
DEFINE_PROP_END_OF_LIST(),
77
};
78
31
--
79
--
32
2.34.1
80
2.43.5
diff view generated by jsdifflib