hw/intc/arm_gic: Fix deactivation of SPI lines

[PATCH v1 0/1] hw/intc/arm_gic: Fix deactivation of SPI lines

Edgar E. Iglesias posted 1 patch 5 months, 3 weeks ago

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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20240605143044.2029444-1-edgar.iglesias@gmail.com

Maintainers: Peter Maydell <peter.maydell@linaro.org>

hw/intc/gic_internal.h | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)

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[PATCH v1 0/1] hw/intc/arm_gic: Fix deactivation of SPI lines

Posted by Edgar E. Iglesias 5 months, 3 weeks ago

From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>

Julien reported that he has seen strange behaviour when running
Xen on QEMU using GICv2. When Xen migrates a guest's vCPU to
another pCPU while the vCPU is handling an interrupt the guest
is unable to properly deactivate interrupts.

It sounds like something rare but in some setups it actually
happens all the time.

Looking at it a little closer, our GICv2 model treats
deactivation of SPI lines as if they were PPI's, i.e banked per
CPU core. The state for active interrupts should only be banked
for PPI lines, not for SPI lines.

When deactivating SPI lines, I think we need to handle the state
as unbanked, similar to how we handle writes to GICD_ICACTIVER.

This fixes the problem on my side.

Cheers,
Edgar


Edgar E. Iglesias (1):
  hw/intc/arm_gic: Fix deactivation of SPI lines

 hw/intc/gic_internal.h | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)


base-commit: d16cab541ab9217977e2a39abf3d79f914146741
-- 
2.40.1

Re: [PATCH v1 0/1] hw/intc/arm_gic: Fix deactivation of SPI lines

Posted by Peter Maydell 5 months, 2 weeks ago

On Wed, 5 Jun 2024 at 15:43, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
>
> From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
>
> Julien reported that he has seen strange behaviour when running
> Xen on QEMU using GICv2. When Xen migrates a guest's vCPU to
> another pCPU while the vCPU is handling an interrupt the guest
> is unable to properly deactivate interrupts.
>
> It sounds like something rare but in some setups it actually
> happens all the time.
>
> Looking at it a little closer, our GICv2 model treats
> deactivation of SPI lines as if they were PPI's, i.e banked per
> CPU core. The state for active interrupts should only be banked
> for PPI lines, not for SPI lines.
>
> When deactivating SPI lines, I think we need to handle the state
> as unbanked, similar to how we handle writes to GICD_ICACTIVER.
>
> This fixes the problem on my side.

Applied to target-arm.next, thanks.

(I'm surprised anybody's still using GICv2 seriously at
this point...)

-- PMM