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[PATCH v5 00/17] Add AST2700 support

Jamin Lin via posted 17 patches 5 months, 3 weeks ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20240604054438.3424349-1-jamin._5Flin@aspeedtech.com
Maintainers: "Cédric Le Goater" <clg@kaod.org>, Peter Maydell <peter.maydell@linaro.org>, Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>, Alistair Francis <alistair@alistair23.me>, Cleber Rosa <crosa@redhat.com>, "Philippe Mathieu-Daudé" <philmd@linaro.org>, Wainer dos Santos Moschetta <wainersm@redhat.com>, Beraldo Leal <bleal@redhat.com>
docs/system/arm/aspeed.rst       |  39 +-
hw/arm/aspeed.c                  |  32 ++
hw/arm/aspeed_ast27x0.c          | 648 +++++++++++++++++++++++++++++++
hw/arm/meson.build               |   1 +
hw/intc/aspeed_intc.c            | 360 +++++++++++++++++
hw/intc/meson.build              |   1 +
hw/intc/trace-events             |  13 +
hw/misc/aspeed_scu.c             | 306 ++++++++++++++-
hw/misc/aspeed_sdmc.c            | 220 +++++++++--
hw/misc/aspeed_sli.c             | 177 +++++++++
hw/misc/meson.build              |   3 +-
hw/misc/trace-events             |  11 +
hw/ssi/aspeed_smc.c              | 346 ++++++++++++++++-
hw/ssi/trace-events              |   2 +-
hw/watchdog/wdt_aspeed.c         |  24 ++
include/hw/arm/aspeed_soc.h      |  30 +-
include/hw/intc/aspeed_intc.h    |  44 +++
include/hw/misc/aspeed_scu.h     |  47 ++-
include/hw/misc/aspeed_sdmc.h    |   5 +-
include/hw/misc/aspeed_sli.h     |  27 ++
include/hw/ssi/aspeed_smc.h      |   2 +
include/hw/watchdog/wdt_aspeed.h |   3 +-
tests/avocado/machine_aspeed.py  |  62 +++
23 files changed, 2345 insertions(+), 58 deletions(-)
create mode 100644 hw/arm/aspeed_ast27x0.c
create mode 100644 hw/intc/aspeed_intc.c
create mode 100644 hw/misc/aspeed_sli.c
create mode 100644 include/hw/intc/aspeed_intc.h
create mode 100644 include/hw/misc/aspeed_sli.h
[PATCH v5 00/17] Add AST2700 support
Posted by Jamin Lin via 5 months, 3 weeks ago 
Changes from v1:
The patch series supports WDT, SDMC, SMC, SCU, SLI and INTC for AST2700 SoC.

Changes from v2:
- replace is_aarch64 with is_bus64bit for sdmc patch review.
- fix incorrect dram size for AST2700

Changes from v3:
- Add AST2700 Evaluation board in ASPEED document
- Add avocado test cases for AST2700 Evaluation board
- Fix reviewers review issues and add reviewers suggestions
- Implement INTC model GICINT 128 to GICINT136 for AST2700

Changes from v4:
- support 64 bits dma dram address associated with review issues
- support dma start length and 1 byte length unit associated with review issues
- refactor intc model to fix serial console stuck issue and associated with review issues

Changes from v5:
- sdmc: incrementing the version of vmstate to 2.
- smc: support different memory region ops for SMC flash region
       introduce a new "const MemoryRegionOps *" attribute in AspeedSMCClass and
       use it in aspeed_smc_flash_realize function.
- intc: fix associated with review issues
- dram size detect: change to use address space API and simplify with write
                    transaction on the DRAM memory region of the SoC.
- ast27x0_soc: update aspeed_soc_ast2700_gic function associated with review issues
               and rename to aspeed_soc_ast2700_gic_realize

Test Version:
qemu commit:
https://github.com/qemu/qemu/commit/74abb45dac6979e7ff76172b7f0a24e869405184
applied patch:
https://patchew.org/QEMU/20240527124315.35356-1-clg@redhat.com/

Test steps:
1. Download the latest openbmc image for AST2700 from AspeedTech-BMC/openbmc
   repository, https://github.com/AspeedTech-BMC/openbmc/releases/tag/v09.01
   link: https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.01/ast2700-default-obmc.tar.gz
2. untar ast2700-default-obmc.tar.gz
   ```
   tar -xf ast2700-default-obmc.tar.gz
   ```
3. Run and the contents of scripts as following
IMGDIR=ast2700-default
UBOOT_SIZE=$(stat --format=%s -L ${IMGDIR}/u-boot-nodtb.bin)
UBOOT_DTB_ADDR=$((0x400000000 + ${UBOOT_SIZE}))

qemu-system-aarch64 -M ast2700-evb -nographic\
 -device loader,addr=0x400000000,file=${IMGDIR}/u-boot-nodtb.bin,force-raw=on\
 -device loader,addr=${UBOOT_DTB_ADDR},file=${IMGDIR}/u-boot.dtb,force-raw=on\
 -device loader,addr=0x430000000,file=${IMGDIR}/bl31.bin,force-raw=on\
 -device loader,addr=0x430080000,file=${IMGDIR}/optee/tee-raw.bin,force-raw=on\
 -device loader,addr=0x430000000,cpu-num=0\
 -device loader,addr=0x430000000,cpu-num=1\
 -device loader,addr=0x430000000,cpu-num=2\
 -device loader,addr=0x430000000,cpu-num=3\
 -smp 4\
 -drive file=${IMGDIR}/image-bmc,format=raw,if=mtd\
 -serial mon:stdio\
 -snapshot

Jamin Lin (17):
  aspeed/wdt: Add AST2700 support
  aspeed/sli: Add AST2700 support
  aspeed/sdmc: remove redundant macros
  aspeed/sdmc: fix coding style
  aspeed/sdmc: Add AST2700 support
  aspeed/smc: correct device description
  aspeed/smc: support dma start length and 1 byte length unit
  aspeed/smc: support 64 bits dma dram address
  aspeed/smc: support different memory region ops for SMC flash region
  aspeed/smc: Add AST2700 support
  aspeed/scu: Add AST2700 support
  aspeed/intc: Add AST2700 support
  aspeed/soc: Add AST2700 support
  aspeed: Add an AST2700 eval board
  aspeed/soc: fix incorrect dram size for AST2700
  test/avocado/machine_aspeed.py: Add AST2700 test case
  docs:aspeed: Add AST2700 Evaluation board

 docs/system/arm/aspeed.rst       |  39 +-
 hw/arm/aspeed.c                  |  32 ++
 hw/arm/aspeed_ast27x0.c          | 648 +++++++++++++++++++++++++++++++
 hw/arm/meson.build               |   1 +
 hw/intc/aspeed_intc.c            | 360 +++++++++++++++++
 hw/intc/meson.build              |   1 +
 hw/intc/trace-events             |  13 +
 hw/misc/aspeed_scu.c             | 306 ++++++++++++++-
 hw/misc/aspeed_sdmc.c            | 220 +++++++++--
 hw/misc/aspeed_sli.c             | 177 +++++++++
 hw/misc/meson.build              |   3 +-
 hw/misc/trace-events             |  11 +
 hw/ssi/aspeed_smc.c              | 346 ++++++++++++++++-
 hw/ssi/trace-events              |   2 +-
 hw/watchdog/wdt_aspeed.c         |  24 ++
 include/hw/arm/aspeed_soc.h      |  30 +-
 include/hw/intc/aspeed_intc.h    |  44 +++
 include/hw/misc/aspeed_scu.h     |  47 ++-
 include/hw/misc/aspeed_sdmc.h    |   5 +-
 include/hw/misc/aspeed_sli.h     |  27 ++
 include/hw/ssi/aspeed_smc.h      |   2 +
 include/hw/watchdog/wdt_aspeed.h |   3 +-
 tests/avocado/machine_aspeed.py  |  62 +++
 23 files changed, 2345 insertions(+), 58 deletions(-)
 create mode 100644 hw/arm/aspeed_ast27x0.c
 create mode 100644 hw/intc/aspeed_intc.c
 create mode 100644 hw/misc/aspeed_sli.c
 create mode 100644 include/hw/intc/aspeed_intc.h
 create mode 100644 include/hw/misc/aspeed_sli.h

-- 
2.25.1
Re: [PATCH v5 00/17] Add AST2700 support
Posted by Cédric Le Goater 5 months, 2 weeks ago 
On 6/4/24 7:44 AM, Jamin Lin wrote:
> Changes from v1:
> The patch series supports WDT, SDMC, SMC, SCU, SLI and INTC for AST2700 SoC.
> 
> Changes from v2:
> - replace is_aarch64 with is_bus64bit for sdmc patch review.
> - fix incorrect dram size for AST2700
> 
> Changes from v3:
> - Add AST2700 Evaluation board in ASPEED document
> - Add avocado test cases for AST2700 Evaluation board
> - Fix reviewers review issues and add reviewers suggestions
> - Implement INTC model GICINT 128 to GICINT136 for AST2700
> 
> Changes from v4:
> - support 64 bits dma dram address associated with review issues
> - support dma start length and 1 byte length unit associated with review issues
> - refactor intc model to fix serial console stuck issue and associated with review issues
> 
> Changes from v5:
> - sdmc: incrementing the version of vmstate to 2.
> - smc: support different memory region ops for SMC flash region
>         introduce a new "const MemoryRegionOps *" attribute in AspeedSMCClass and
>         use it in aspeed_smc_flash_realize function.
> - intc: fix associated with review issues
> - dram size detect: change to use address space API and simplify with write
>                      transaction on the DRAM memory region of the SoC.
> - ast27x0_soc: update aspeed_soc_ast2700_gic function associated with review issues
>                 and rename to aspeed_soc_ast2700_gic_realize
> 
> Test Version:
> qemu commit:
> https://github.com/qemu/qemu/commit/74abb45dac6979e7ff76172b7f0a24e869405184
> applied patch:
> https://patchew.org/QEMU/20240527124315.35356-1-clg@redhat.com/
> 
> Test steps:
> 1. Download the latest openbmc image for AST2700 from AspeedTech-BMC/openbmc
>     repository, https://github.com/AspeedTech-BMC/openbmc/releases/tag/v09.01
>     link: https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.01/ast2700-default-obmc.tar.gz
> 2. untar ast2700-default-obmc.tar.gz
>     ```
>     tar -xf ast2700-default-obmc.tar.gz
>     ```
> 3. Run and the contents of scripts as following
> IMGDIR=ast2700-default
> UBOOT_SIZE=$(stat --format=%s -L ${IMGDIR}/u-boot-nodtb.bin)
> UBOOT_DTB_ADDR=$((0x400000000 + ${UBOOT_SIZE}))
> 
> qemu-system-aarch64 -M ast2700-evb -nographic\
>   -device loader,addr=0x400000000,file=${IMGDIR}/u-boot-nodtb.bin,force-raw=on\
>   -device loader,addr=${UBOOT_DTB_ADDR},file=${IMGDIR}/u-boot.dtb,force-raw=on\
>   -device loader,addr=0x430000000,file=${IMGDIR}/bl31.bin,force-raw=on\
>   -device loader,addr=0x430080000,file=${IMGDIR}/optee/tee-raw.bin,force-raw=on\
>   -device loader,addr=0x430000000,cpu-num=0\
>   -device loader,addr=0x430000000,cpu-num=1\
>   -device loader,addr=0x430000000,cpu-num=2\
>   -device loader,addr=0x430000000,cpu-num=3\
>   -smp 4\
>   -drive file=${IMGDIR}/image-bmc,format=raw,if=mtd\
>   -serial mon:stdio\
>   -snapshot
> 
> Jamin Lin (17):
>    aspeed/wdt: Add AST2700 support
>    aspeed/sli: Add AST2700 support
>    aspeed/sdmc: remove redundant macros
>    aspeed/sdmc: fix coding style
>    aspeed/sdmc: Add AST2700 support
>    aspeed/smc: correct device description
>    aspeed/smc: support dma start length and 1 byte length unit
>    aspeed/smc: support 64 bits dma dram address
>    aspeed/smc: support different memory region ops for SMC flash region
>    aspeed/smc: Add AST2700 support
>    aspeed/scu: Add AST2700 support
>    aspeed/intc: Add AST2700 support
>    aspeed/soc: Add AST2700 support
>    aspeed: Add an AST2700 eval board
>    aspeed/soc: fix incorrect dram size for AST2700
>    test/avocado/machine_aspeed.py: Add AST2700 test case
>    docs:aspeed: Add AST2700 Evaluation board
> 
>   docs/system/arm/aspeed.rst       |  39 +-
>   hw/arm/aspeed.c                  |  32 ++
>   hw/arm/aspeed_ast27x0.c          | 648 +++++++++++++++++++++++++++++++
>   hw/arm/meson.build               |   1 +
>   hw/intc/aspeed_intc.c            | 360 +++++++++++++++++
>   hw/intc/meson.build              |   1 +
>   hw/intc/trace-events             |  13 +
>   hw/misc/aspeed_scu.c             | 306 ++++++++++++++-
>   hw/misc/aspeed_sdmc.c            | 220 +++++++++--
>   hw/misc/aspeed_sli.c             | 177 +++++++++
>   hw/misc/meson.build              |   3 +-
>   hw/misc/trace-events             |  11 +
>   hw/ssi/aspeed_smc.c              | 346 ++++++++++++++++-
>   hw/ssi/trace-events              |   2 +-
>   hw/watchdog/wdt_aspeed.c         |  24 ++
>   include/hw/arm/aspeed_soc.h      |  30 +-
>   include/hw/intc/aspeed_intc.h    |  44 +++
>   include/hw/misc/aspeed_scu.h     |  47 ++-
>   include/hw/misc/aspeed_sdmc.h    |   5 +-
>   include/hw/misc/aspeed_sli.h     |  27 ++
>   include/hw/ssi/aspeed_smc.h      |   2 +
>   include/hw/watchdog/wdt_aspeed.h |   3 +-
>   tests/avocado/machine_aspeed.py  |  62 +++
>   23 files changed, 2345 insertions(+), 58 deletions(-)
>   create mode 100644 hw/arm/aspeed_ast27x0.c
>   create mode 100644 hw/intc/aspeed_intc.c
>   create mode 100644 hw/misc/aspeed_sli.c
>   create mode 100644 include/hw/intc/aspeed_intc.h
>   create mode 100644 include/hw/misc/aspeed_sli.h
> 


Applied to aspeed-next.

Thanks,

C.
Re: [PATCH v5 00/17] Add AST2700 support
Posted by Cédric Le Goater 5 months, 3 weeks ago 
On 6/4/24 07:44, Jamin Lin wrote:
> Changes from v1:
> The patch series supports WDT, SDMC, SMC, SCU, SLI and INTC for AST2700 SoC.
> 
> Changes from v2:
> - replace is_aarch64 with is_bus64bit for sdmc patch review.
> - fix incorrect dram size for AST2700
> 
> Changes from v3:
> - Add AST2700 Evaluation board in ASPEED document
> - Add avocado test cases for AST2700 Evaluation board
> - Fix reviewers review issues and add reviewers suggestions
> - Implement INTC model GICINT 128 to GICINT136 for AST2700
> 
> Changes from v4:
> - support 64 bits dma dram address associated with review issues
> - support dma start length and 1 byte length unit associated with review issues
> - refactor intc model to fix serial console stuck issue and associated with review issues
> 
> Changes from v5:
> - sdmc: incrementing the version of vmstate to 2.
> - smc: support different memory region ops for SMC flash region
>         introduce a new "const MemoryRegionOps *" attribute in AspeedSMCClass and
>         use it in aspeed_smc_flash_realize function.
> - intc: fix associated with review issues
> - dram size detect: change to use address space API and simplify with write
>                      transaction on the DRAM memory region of the SoC.
> - ast27x0_soc: update aspeed_soc_ast2700_gic function associated with review issues
>                 and rename to aspeed_soc_ast2700_gic_realize

v5 looks good to me.

Do you plan to send a MAINTAINERS file ?

Thanks,

C.




> 
> Test Version:
> qemu commit:
> https://github.com/qemu/qemu/commit/74abb45dac6979e7ff76172b7f0a24e869405184
> applied patch:
> https://patchew.org/QEMU/20240527124315.35356-1-clg@redhat.com/
> 
> Test steps:
> 1. Download the latest openbmc image for AST2700 from AspeedTech-BMC/openbmc
>     repository, https://github.com/AspeedTech-BMC/openbmc/releases/tag/v09.01
>     link: https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.01/ast2700-default-obmc.tar.gz
> 2. untar ast2700-default-obmc.tar.gz
>     ```
>     tar -xf ast2700-default-obmc.tar.gz
>     ```
> 3. Run and the contents of scripts as following
> IMGDIR=ast2700-default
> UBOOT_SIZE=$(stat --format=%s -L ${IMGDIR}/u-boot-nodtb.bin)
> UBOOT_DTB_ADDR=$((0x400000000 + ${UBOOT_SIZE}))
> 
> qemu-system-aarch64 -M ast2700-evb -nographic\
>   -device loader,addr=0x400000000,file=${IMGDIR}/u-boot-nodtb.bin,force-raw=on\
>   -device loader,addr=${UBOOT_DTB_ADDR},file=${IMGDIR}/u-boot.dtb,force-raw=on\
>   -device loader,addr=0x430000000,file=${IMGDIR}/bl31.bin,force-raw=on\
>   -device loader,addr=0x430080000,file=${IMGDIR}/optee/tee-raw.bin,force-raw=on\
>   -device loader,addr=0x430000000,cpu-num=0\
>   -device loader,addr=0x430000000,cpu-num=1\
>   -device loader,addr=0x430000000,cpu-num=2\
>   -device loader,addr=0x430000000,cpu-num=3\
>   -smp 4\
>   -drive file=${IMGDIR}/image-bmc,format=raw,if=mtd\
>   -serial mon:stdio\
>   -snapshot
> 
> Jamin Lin (17):
>    aspeed/wdt: Add AST2700 support
>    aspeed/sli: Add AST2700 support
>    aspeed/sdmc: remove redundant macros
>    aspeed/sdmc: fix coding style
>    aspeed/sdmc: Add AST2700 support
>    aspeed/smc: correct device description
>    aspeed/smc: support dma start length and 1 byte length unit
>    aspeed/smc: support 64 bits dma dram address
>    aspeed/smc: support different memory region ops for SMC flash region
>    aspeed/smc: Add AST2700 support
>    aspeed/scu: Add AST2700 support
>    aspeed/intc: Add AST2700 support
>    aspeed/soc: Add AST2700 support
>    aspeed: Add an AST2700 eval board
>    aspeed/soc: fix incorrect dram size for AST2700
>    test/avocado/machine_aspeed.py: Add AST2700 test case
>    docs:aspeed: Add AST2700 Evaluation board
> 
>   docs/system/arm/aspeed.rst       |  39 +-
>   hw/arm/aspeed.c                  |  32 ++
>   hw/arm/aspeed_ast27x0.c          | 648 +++++++++++++++++++++++++++++++
>   hw/arm/meson.build               |   1 +
>   hw/intc/aspeed_intc.c            | 360 +++++++++++++++++
>   hw/intc/meson.build              |   1 +
>   hw/intc/trace-events             |  13 +
>   hw/misc/aspeed_scu.c             | 306 ++++++++++++++-
>   hw/misc/aspeed_sdmc.c            | 220 +++++++++--
>   hw/misc/aspeed_sli.c             | 177 +++++++++
>   hw/misc/meson.build              |   3 +-
>   hw/misc/trace-events             |  11 +
>   hw/ssi/aspeed_smc.c              | 346 ++++++++++++++++-
>   hw/ssi/trace-events              |   2 +-
>   hw/watchdog/wdt_aspeed.c         |  24 ++
>   include/hw/arm/aspeed_soc.h      |  30 +-
>   include/hw/intc/aspeed_intc.h    |  44 +++
>   include/hw/misc/aspeed_scu.h     |  47 ++-
>   include/hw/misc/aspeed_sdmc.h    |   5 +-
>   include/hw/misc/aspeed_sli.h     |  27 ++
>   include/hw/ssi/aspeed_smc.h      |   2 +
>   include/hw/watchdog/wdt_aspeed.h |   3 +-
>   tests/avocado/machine_aspeed.py  |  62 +++
>   23 files changed, 2345 insertions(+), 58 deletions(-)
>   create mode 100644 hw/arm/aspeed_ast27x0.c
>   create mode 100644 hw/intc/aspeed_intc.c
>   create mode 100644 hw/misc/aspeed_sli.c
>   create mode 100644 include/hw/intc/aspeed_intc.h
>   create mode 100644 include/hw/misc/aspeed_sli.h
>
RE: [PATCH v5 00/17] Add AST2700 support
Posted by Jamin Lin 5 months, 3 weeks ago 
Hi Cedric,

> From: Cédric Le Goater <clg@kaod.org>
> Sent: Tuesday, June 4, 2024 7:52 PM
> To: Jamin Lin <jamin_lin@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Andrew Jeffery <andrew@codeconstruct.com.au>;
> Joel Stanley <joel@jms.id.au>; Alistair Francis <alistair@alistair23.me>; Cleber
> Rosa <crosa@redhat.com>; Philippe Mathieu-Daudé <philmd@linaro.org>;
> Wainer dos Santos Moschetta <wainersm@redhat.com>; Beraldo Leal
> <bleal@redhat.com>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
> list:All patches CC here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> <yunlin.tang@aspeedtech.com>
> Subject: Re: [PATCH v5 00/17] Add AST2700 support
> 
> On 6/4/24 07:44, Jamin Lin wrote:
> > Changes from v1:
> > The patch series supports WDT, SDMC, SMC, SCU, SLI and INTC for AST2700
> SoC.
> >
> > Changes from v2:
> > - replace is_aarch64 with is_bus64bit for sdmc patch review.
> > - fix incorrect dram size for AST2700
> >
> > Changes from v3:
> > - Add AST2700 Evaluation board in ASPEED document
> > - Add avocado test cases for AST2700 Evaluation board
> > - Fix reviewers review issues and add reviewers suggestions
> > - Implement INTC model GICINT 128 to GICINT136 for AST2700
> >
> > Changes from v4:
> > - support 64 bits dma dram address associated with review issues
> > - support dma start length and 1 byte length unit associated with
> > review issues
> > - refactor intc model to fix serial console stuck issue and associated
> > with review issues
> >
> > Changes from v5:
> > - sdmc: incrementing the version of vmstate to 2.
> > - smc: support different memory region ops for SMC flash region
> >         introduce a new "const MemoryRegionOps *" attribute in
> AspeedSMCClass and
> >         use it in aspeed_smc_flash_realize function.
> > - intc: fix associated with review issues
> > - dram size detect: change to use address space API and simplify with write
> >                      transaction on the DRAM memory region of the
> SoC.
> > - ast27x0_soc: update aspeed_soc_ast2700_gic function associated with
> review issues
> >                 and rename to aspeed_soc_ast2700_gic_realize
> 
> v5 looks good to me.
> 
> Do you plan to send a MAINTAINERS file ?
> 
Thanks for your kindly support and appreciate your help.
Yes, I am studying MAINTAINERS rules and will send a patch.
I will notify you via this email after I send the patch.
Thanks-Jamin

> Thanks,
> 
> C.
> 
> 
> 
> 
> >
> > Test Version:
> > qemu commit:
> >
> https://github.com/qemu/qemu/commit/74abb45dac6979e7ff76172b7f0a24e
> 869
> > 405184
> > applied patch:
> > https://patchew.org/QEMU/20240527124315.35356-1-clg@redhat.com/
> >
> > Test steps:
> > 1. Download the latest openbmc image for AST2700 from
> AspeedTech-BMC/openbmc
> >     repository,
> https://github.com/AspeedTech-BMC/openbmc/releases/tag/v09.01
> >     link:
> >
> https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.01/ast
> > 2700-default-obmc.tar.gz
> > 2. untar ast2700-default-obmc.tar.gz
> >     ```
> >     tar -xf ast2700-default-obmc.tar.gz
> >     ```
> > 3. Run and the contents of scripts as following IMGDIR=ast2700-default
> > UBOOT_SIZE=$(stat --format=%s -L ${IMGDIR}/u-boot-nodtb.bin)
> > UBOOT_DTB_ADDR=$((0x400000000 + ${UBOOT_SIZE}))
> >
> > qemu-system-aarch64 -M ast2700-evb -nographic\
> >   -device
> loader,addr=0x400000000,file=${IMGDIR}/u-boot-nodtb.bin,force-raw=on\
> >   -device
> loader,addr=${UBOOT_DTB_ADDR},file=${IMGDIR}/u-boot.dtb,force-raw=on\
> >   -device loader,addr=0x430000000,file=${IMGDIR}/bl31.bin,force-raw=on\
> >   -device
> loader,addr=0x430080000,file=${IMGDIR}/optee/tee-raw.bin,force-raw=on\
> >   -device loader,addr=0x430000000,cpu-num=0\
> >   -device loader,addr=0x430000000,cpu-num=1\
> >   -device loader,addr=0x430000000,cpu-num=2\
> >   -device loader,addr=0x430000000,cpu-num=3\
> >   -smp 4\
> >   -drive file=${IMGDIR}/image-bmc,format=raw,if=mtd\
> >   -serial mon:stdio\
> >   -snapshot
> >
> > Jamin Lin (17):
> >    aspeed/wdt: Add AST2700 support
> >    aspeed/sli: Add AST2700 support
> >    aspeed/sdmc: remove redundant macros
> >    aspeed/sdmc: fix coding style
> >    aspeed/sdmc: Add AST2700 support
> >    aspeed/smc: correct device description
> >    aspeed/smc: support dma start length and 1 byte length unit
> >    aspeed/smc: support 64 bits dma dram address
> >    aspeed/smc: support different memory region ops for SMC flash region
> >    aspeed/smc: Add AST2700 support
> >    aspeed/scu: Add AST2700 support
> >    aspeed/intc: Add AST2700 support
> >    aspeed/soc: Add AST2700 support
> >    aspeed: Add an AST2700 eval board
> >    aspeed/soc: fix incorrect dram size for AST2700
> >    test/avocado/machine_aspeed.py: Add AST2700 test case
> >    docs:aspeed: Add AST2700 Evaluation board
> >
> >   docs/system/arm/aspeed.rst       |  39 +-
> >   hw/arm/aspeed.c                  |  32 ++
> >   hw/arm/aspeed_ast27x0.c          | 648
> +++++++++++++++++++++++++++++++
> >   hw/arm/meson.build               |   1 +
> >   hw/intc/aspeed_intc.c            | 360 +++++++++++++++++
> >   hw/intc/meson.build              |   1 +
> >   hw/intc/trace-events             |  13 +
> >   hw/misc/aspeed_scu.c             | 306 ++++++++++++++-
> >   hw/misc/aspeed_sdmc.c            | 220 +++++++++--
> >   hw/misc/aspeed_sli.c             | 177 +++++++++
> >   hw/misc/meson.build              |   3 +-
> >   hw/misc/trace-events             |  11 +
> >   hw/ssi/aspeed_smc.c              | 346 ++++++++++++++++-
> >   hw/ssi/trace-events              |   2 +-
> >   hw/watchdog/wdt_aspeed.c         |  24 ++
> >   include/hw/arm/aspeed_soc.h      |  30 +-
> >   include/hw/intc/aspeed_intc.h    |  44 +++
> >   include/hw/misc/aspeed_scu.h     |  47 ++-
> >   include/hw/misc/aspeed_sdmc.h    |   5 +-
> >   include/hw/misc/aspeed_sli.h     |  27 ++
> >   include/hw/ssi/aspeed_smc.h      |   2 +
> >   include/hw/watchdog/wdt_aspeed.h |   3 +-
> >   tests/avocado/machine_aspeed.py  |  62 +++
> >   23 files changed, 2345 insertions(+), 58 deletions(-)
> >   create mode 100644 hw/arm/aspeed_ast27x0.c
> >   create mode 100644 hw/intc/aspeed_intc.c
> >   create mode 100644 hw/misc/aspeed_sli.c
> >   create mode 100644 include/hw/intc/aspeed_intc.h
> >   create mode 100644 include/hw/misc/aspeed_sli.h
> >

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