[v2] riscv-to-apply queue

[PULL v2 00/27] riscv-to-apply queue

Posted by Alistair Francis 5 months, 3 weeks ago

The following changes since commit 74abb45dac6979e7ff76172b7f0a24e869405184:

  Merge tag 'pull-target-arm-20240531' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-05-31 11:10:10 -0700)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240603

for you to fetch changes up to 915758c537b5fe09575291f4acd87e2d377a93de:

  disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs (2024-06-03 11:12:12 +1000)

----------------------------------------------------------------
RISC-V PR for 9.1

* APLICs add child earlier than realize
* Fix exposure of Zkr
* Raise exceptions on wrs.nto
* Implement SBI debug console (DBCN) calls for KVM
* Support 64-bit addresses for initrd
* Change RISCV_EXCP_SEMIHOST exception number to 63
* Tolerate KVM disable ext errors
* Set tval in breakpoints
* Add support for Zve32x extension
* Add support for Zve64x extension
* Relax vector register check in RISCV gdbstub
* Fix the element agnostic Vector function problem
* Fix Zvkb extension config
* Implement dynamic establishment of custom decoder
* Add th.sxstatus CSR emulation
* Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
* Check single width operator for vector fp widen instructions
* Check single width operator for vfncvt.rod.f.f.w
* Remove redudant SEW checking for vector fp narrow/widen instructions
* Prioritize pmp errors in raise_mmu_exception()
* Do not set mtval2 for non guest-page faults
* Remove experimental prefix from "B" extension
* Fixup CBO extension register calculation
* Fix the hart bit setting of AIA
* Fix reg_width in ricsv_gen_dynamic_vector_feature()
* Decode all of the pmpcfg and pmpaddr CSRs

----------------------------------------------------------------
Alexei Filippov (1):
      target/riscv: do not set mtval2 for non guest-page faults

Alistair Francis (2):
      target/riscv: rvzicbo: Fixup CBO extension register calculation
      disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs

Andrew Jones (2):
      target/riscv/kvm: Fix exposure of Zkr
      target/riscv: Raise exceptions on wrs.nto

Cheng Yang (1):
      hw/riscv/boot.c: Support 64-bit address for initrd

Christoph Müllner (1):
      riscv: thead: Add th.sxstatus CSR emulation

Clément Léger (1):
      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

Daniel Henrique Barboza (6):
      target/riscv/kvm: implement SBI debug console (DBCN) calls
      target/riscv/kvm: tolerate KVM disable ext errors
      target/riscv/debug: set tval=pc in breakpoint exceptions
      trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
      target/riscv: prioritize pmp errors in raise_mmu_exception()
      riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()

Huang Tao (2):
      target/riscv: Fix the element agnostic function problem
      target/riscv: Implement dynamic establishment of custom decoder

Jason Chien (3):
      target/riscv: Add support for Zve32x extension
      target/riscv: Add support for Zve64x extension
      target/riscv: Relax vector register check in RISCV gdbstub

Max Chou (4):
      target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
      target/riscv: rvv: Check single width operator for vector fp widen instructions
      target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
      target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions

Rob Bradford (1):
      target/riscv: Remove experimental prefix from "B" extension

Yangyu Chen (1):
      target/riscv/cpu.c: fix Zvkb extension config

Yong-Xuan Wang (1):
      target/riscv/kvm.c: Fix the hart bit setting of AIA

yang.zhang (1):
      hw/intc/riscv_aplic: APLICs should add child earlier than realize

 MAINTAINERS                                    |   1 +
 target/riscv/cpu.h                             |   7 ++
 target/riscv/cpu_bits.h                        |   2 +-
 target/riscv/cpu_cfg.h                         |   2 +
 target/riscv/helper.h                          |   1 +
 target/riscv/sbi_ecall_interface.h             |  17 +++
 target/riscv/tcg/tcg-cpu.h                     |  15 +++
 disas/riscv.c                                  |  65 +++++++++-
 hw/intc/riscv_aplic.c                          |   8 +-
 hw/riscv/boot.c                                |   4 +-
 target/riscv/cpu.c                             |  10 +-
 target/riscv/cpu_helper.c                      |  37 +++---
 target/riscv/csr.c                             |  20 +++-
 target/riscv/debug.c                           |   3 +
 target/riscv/gdbstub.c                         |   8 +-
 target/riscv/kvm/kvm-cpu.c                     | 157 ++++++++++++++++++++++++-
 target/riscv/op_helper.c                       |  11 ++
 target/riscv/tcg/tcg-cpu.c                     |  50 +++++---
 target/riscv/th_csr.c                          |  79 +++++++++++++
 target/riscv/translate.c                       |  31 +++--
 target/riscv/vector_internals.c                |  22 ++++
 target/riscv/insn_trans/trans_privileged.c.inc |   2 +
 target/riscv/insn_trans/trans_rvv.c.inc        |  46 +++++---
 target/riscv/insn_trans/trans_rvzawrs.c.inc    |  29 +++--
 target/riscv/insn_trans/trans_rvzicbo.c.inc    |  16 ++-
 target/riscv/meson.build                       |   1 +
 26 files changed, 543 insertions(+), 101 deletions(-)
 create mode 100644 target/riscv/th_csr.c

Re: [PULL v2 00/27] riscv-to-apply queue

Posted by Richard Henderson 5 months, 3 weeks ago

On 6/3/24 06:16, Alistair Francis wrote:
> The following changes since commit 74abb45dac6979e7ff76172b7f0a24e869405184:
> 
>    Merge tag 'pull-target-arm-20240531' ofhttps://git.linaro.org/people/pmaydell/qemu-arm  into staging (2024-05-31 11:10:10 -0700)
> 
> are available in the Git repository at:
> 
>    https://github.com/alistair23/qemu.git  tags/pull-riscv-to-apply-20240603
> 
> for you to fetch changes up to 915758c537b5fe09575291f4acd87e2d377a93de:
> 
>    disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs (2024-06-03 11:12:12 +1000)
> 
> ----------------------------------------------------------------
> RISC-V PR for 9.1
> 
> * APLICs add child earlier than realize
> * Fix exposure of Zkr
> * Raise exceptions on wrs.nto
> * Implement SBI debug console (DBCN) calls for KVM
> * Support 64-bit addresses for initrd
> * Change RISCV_EXCP_SEMIHOST exception number to 63
> * Tolerate KVM disable ext errors
> * Set tval in breakpoints
> * Add support for Zve32x extension
> * Add support for Zve64x extension
> * Relax vector register check in RISCV gdbstub
> * Fix the element agnostic Vector function problem
> * Fix Zvkb extension config
> * Implement dynamic establishment of custom decoder
> * Add th.sxstatus CSR emulation
> * Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
> * Check single width operator for vector fp widen instructions
> * Check single width operator for vfncvt.rod.f.f.w
> * Remove redudant SEW checking for vector fp narrow/widen instructions
> * Prioritize pmp errors in raise_mmu_exception()
> * Do not set mtval2 for non guest-page faults
> * Remove experimental prefix from "B" extension
> * Fixup CBO extension register calculation
> * Fix the hart bit setting of AIA
> * Fix reg_width in ricsv_gen_dynamic_vector_feature()
> * Decode all of the pmpcfg and pmpaddr CSRs

Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/9.1 as appropriate.


r~

Re: [PULL v2 00/27] riscv-to-apply queue

Posted by Philippe Mathieu-Daudé 5 months, 3 weeks ago

Hi Alistair,

On 3/6/24 13:16, Alistair Francis wrote:
> The following changes since commit 74abb45dac6979e7ff76172b7f0a24e869405184:
> 
>    Merge tag 'pull-target-arm-20240531' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-05-31 11:10:10 -0700)
> 
> are available in the Git repository at:
> 
>    https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240603
> 
> for you to fetch changes up to 915758c537b5fe09575291f4acd87e2d377a93de:
> 
>    disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs (2024-06-03 11:12:12 +1000)
> 
> ----------------------------------------------------------------
> RISC-V PR for 9.1
> 
> * APLICs add child earlier than realize
> * Fix exposure of Zkr
> * Raise exceptions on wrs.nto
> * Implement SBI debug console (DBCN) calls for KVM
> * Support 64-bit addresses for initrd
> * Change RISCV_EXCP_SEMIHOST exception number to 63
> * Tolerate KVM disable ext errors
> * Set tval in breakpoints
> * Add support for Zve32x extension
> * Add support for Zve64x extension
> * Relax vector register check in RISCV gdbstub
> * Fix the element agnostic Vector function problem
> * Fix Zvkb extension config
> * Implement dynamic establishment of custom decoder
> * Add th.sxstatus CSR emulation
> * Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
> * Check single width operator for vector fp widen instructions
> * Check single width operator for vfncvt.rod.f.f.w
> * Remove redudant SEW checking for vector fp narrow/widen instructions
> * Prioritize pmp errors in raise_mmu_exception()
> * Do not set mtval2 for non guest-page faults
> * Remove experimental prefix from "B" extension
> * Fixup CBO extension register calculation
> * Fix the hart bit setting of AIA
> * Fix reg_width in ricsv_gen_dynamic_vector_feature()
> * Decode all of the pmpcfg and pmpaddr CSRs
> 
> ----------------------------------------------------------------

Please have a look at this bugfix:
https://lore.kernel.org/qemu-devel/20240419110514.69697-1-philmd@linaro.org/