hw/i386/intel_iommu.c | 302 +++++++++++++++++++++++++++++++++ hw/i386/intel_iommu_internal.h | 54 +++++- hw/pci/pci.c | 37 ++++ hw/pci/pcie.c | 42 +++++ include/exec/memory.h | 65 +++++++ include/hw/pci/pci.h | 45 +++++ include/hw/pci/pci_bus.h | 1 + include/hw/pci/pcie.h | 7 +- include/hw/pci/pcie_regs.h | 4 + system/memory.c | 49 ++++++ 10 files changed, 604 insertions(+), 2 deletions(-)
This series belongs to a list of series that add SVM support for VT-d.
Here we focus on the implementation of PRI support in the IOMMU and on a PCI-level
API for PRI to be used by virtual devices.
This work is based on the VT-d specification version 4.1 (March 2023).
Here is a link to a GitHub repository where you can find the following elements :
- Qemu with all the patches for SVM
- ATS
- PRI
- Device IOTLB invalidations
- Requests with already translated addresses
- A demo device
- A simple driver for the demo device
- A userspace program (for testing and demonstration purposes)
https://github.com/BullSequana/Qemu-in-guest-SVM-demo
Clément Mathieu--Drif (8):
pcie: add a helper to declare the PRI capability for a pcie device
pcie: helper functions to check to check if PRI is enabled
pcie: add a way to get the outstanding page request allocation (pri)
from the config space.
pci: declare structures and IOMMU operation for PRI
pci: add a PCI-level API for PRI
intel_iommu: declare PRI constants and structures
intel_iommu: declare registers for PRI
intel_iommu: add PRI operations support
hw/i386/intel_iommu.c | 302 +++++++++++++++++++++++++++++++++
hw/i386/intel_iommu_internal.h | 54 +++++-
hw/pci/pci.c | 37 ++++
hw/pci/pcie.c | 42 +++++
include/exec/memory.h | 65 +++++++
include/hw/pci/pci.h | 45 +++++
include/hw/pci/pci_bus.h | 1 +
include/hw/pci/pcie.h | 7 +-
include/hw/pci/pcie_regs.h | 4 +
system/memory.c | 49 ++++++
10 files changed, 604 insertions(+), 2 deletions(-)
--
2.45.1
On Thu, May 30, 2024 at 12:24:58PM +0000, CLEMENT MATHIEU--DRIF wrote: > This series belongs to a list of series that add SVM support for VT-d. > > Here we focus on the implementation of PRI support in the IOMMU and on a PCI-level > API for PRI to be used by virtual devices. > > This work is based on the VT-d specification version 4.1 (March 2023). > Here is a link to a GitHub repository where you can find the following elements : > - Qemu with all the patches for SVM > - ATS > - PRI > - Device IOTLB invalidations > - Requests with already translated addresses > - A demo device > - A simple driver for the demo device > - A userspace program (for testing and demonstration purposes) > > https://github.com/BullSequana/Qemu-in-guest-SVM-demo To make things clear, is this patchset independent or does it have a dependency, too? > Clément Mathieu--Drif (8): > pcie: add a helper to declare the PRI capability for a pcie device > pcie: helper functions to check to check if PRI is enabled > pcie: add a way to get the outstanding page request allocation (pri) > from the config space. > pci: declare structures and IOMMU operation for PRI > pci: add a PCI-level API for PRI > intel_iommu: declare PRI constants and structures > intel_iommu: declare registers for PRI > intel_iommu: add PRI operations support > > hw/i386/intel_iommu.c | 302 +++++++++++++++++++++++++++++++++ > hw/i386/intel_iommu_internal.h | 54 +++++- > hw/pci/pci.c | 37 ++++ > hw/pci/pcie.c | 42 +++++ > include/exec/memory.h | 65 +++++++ > include/hw/pci/pci.h | 45 +++++ > include/hw/pci/pci_bus.h | 1 + > include/hw/pci/pcie.h | 7 +- > include/hw/pci/pcie_regs.h | 4 + > system/memory.c | 49 ++++++ > 10 files changed, 604 insertions(+), 2 deletions(-) > > -- > 2.45.1
________________________________ From: Michael S. Tsirkin <mst@redhat.com> Sent: 04 July 2024 08:24 To: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com> Cc: qemu-devel@nongnu.org <qemu-devel@nongnu.org>; jasowang@redhat.com <jasowang@redhat.com>; zhenzhong.duan@intel.com <zhenzhong.duan@intel.com>; kevin.tian@intel.com <kevin.tian@intel.com>; yi.l.liu@intel.com <yi.l.liu@intel.com>; joao.m.martins@oracle.com <joao.m.martins@oracle.com>; peterx@redhat.com <peterx@redhat.com> Subject: Re: [PATCH v1 0/8] PRI support for VT-d Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. On Thu, May 30, 2024 at 12:24:58PM +0000, CLEMENT MATHIEU--DRIF wrote: > This series belongs to a list of series that add SVM support for VT-d. > > Here we focus on the implementation of PRI support in the IOMMU and on a PCI-level > API for PRI to be used by virtual devices. > > This work is based on the VT-d specification version 4.1 (March 2023). > Here is a link to a GitHub repository where you can find the following elements : > - Qemu with all the patches for SVM > - ATS > - PRI > - Device IOTLB invalidations > - Requests with already translated addresses > - A demo device > - A simple driver for the demo device > - A userspace program (for testing and demonstration purposes) > > https://eur06.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2FBullSequana%2FQemu-in-guest-SVM-demo&data=05%7C02%7Cclement.mathieu--drif%40eviden.com%7C0b2efce63b3b400a2a9408dc9bf1f45c%7C7d1c77852d8a437db8421ed5d8fbe00a%7C0%7C0%7C638556710682005347%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=QzUQdYTeIxZ0poSL0MvM2x%2F8ar4R%2B7YioDTO3WQeFAU%3D&reserved=0<https://github.com/BullSequana/Qemu-in-guest-SVM-demo> To make things clear, is this patchset independent or does it have a dependency, too? Hi Michael, This also depends on the ATS series (which also has dependencies itself). I will make this very clear in future versions. > Clément Mathieu--Drif (8): > pcie: add a helper to declare the PRI capability for a pcie device > pcie: helper functions to check to check if PRI is enabled > pcie: add a way to get the outstanding page request allocation (pri) > from the config space. > pci: declare structures and IOMMU operation for PRI > pci: add a PCI-level API for PRI > intel_iommu: declare PRI constants and structures > intel_iommu: declare registers for PRI > intel_iommu: add PRI operations support > > hw/i386/intel_iommu.c | 302 +++++++++++++++++++++++++++++++++ > hw/i386/intel_iommu_internal.h | 54 +++++- > hw/pci/pci.c | 37 ++++ > hw/pci/pcie.c | 42 +++++ > include/exec/memory.h | 65 +++++++ > include/hw/pci/pci.h | 45 +++++ > include/hw/pci/pci_bus.h | 1 + > include/hw/pci/pcie.h | 7 +- > include/hw/pci/pcie_regs.h | 4 + > system/memory.c | 49 ++++++ > 10 files changed, 604 insertions(+), 2 deletions(-) > > -- > 2.45.1
Hi, Just adding Michael in Cc: Thanks >cmd On 30/05/2024 14:24, CLEMENT MATHIEU--DRIF wrote: > This series belongs to a list of series that add SVM support for VT-d. > > Here we focus on the implementation of PRI support in the IOMMU and on a PCI-level > API for PRI to be used by virtual devices. > > This work is based on the VT-d specification version 4.1 (March 2023). > Here is a link to a GitHub repository where you can find the following elements : > - Qemu with all the patches for SVM > - ATS > - PRI > - Device IOTLB invalidations > - Requests with already translated addresses > - A demo device > - A simple driver for the demo device > - A userspace program (for testing and demonstration purposes) > > https://github.com/BullSequana/Qemu-in-guest-SVM-demo > > Clément Mathieu--Drif (8): > pcie: add a helper to declare the PRI capability for a pcie device > pcie: helper functions to check to check if PRI is enabled > pcie: add a way to get the outstanding page request allocation (pri) > from the config space. > pci: declare structures and IOMMU operation for PRI > pci: add a PCI-level API for PRI > intel_iommu: declare PRI constants and structures > intel_iommu: declare registers for PRI > intel_iommu: add PRI operations support > > hw/i386/intel_iommu.c | 302 +++++++++++++++++++++++++++++++++ > hw/i386/intel_iommu_internal.h | 54 +++++- > hw/pci/pci.c | 37 ++++ > hw/pci/pcie.c | 42 +++++ > include/exec/memory.h | 65 +++++++ > include/hw/pci/pci.h | 45 +++++ > include/hw/pci/pci_bus.h | 1 + > include/hw/pci/pcie.h | 7 +- > include/hw/pci/pcie_regs.h | 4 + > system/memory.c | 49 ++++++ > 10 files changed, 604 insertions(+), 2 deletions(-) >
On 2024/5/30 20:24, CLEMENT MATHIEU--DRIF wrote: > This series belongs to a list of series that add SVM support for VT-d. > > Here we focus on the implementation of PRI support in the IOMMU and on a PCI-level > API for PRI to be used by virtual devices. > > This work is based on the VT-d specification version 4.1 (March 2023). > Here is a link to a GitHub repository where you can find the following elements : > - Qemu with all the patches for SVM > - ATS > - PRI > - Device IOTLB invalidations > - Requests with already translated addresses > - A demo device > - A simple driver for the demo device > - A userspace program (for testing and demonstration purposes) I didn't see the drain PRQ related logics in this series. Please consider adding it in next version. It's needed when repurposing a PASID. > https://github.com/BullSequana/Qemu-in-guest-SVM-demo > > Clément Mathieu--Drif (8): > pcie: add a helper to declare the PRI capability for a pcie device > pcie: helper functions to check to check if PRI is enabled > pcie: add a way to get the outstanding page request allocation (pri) > from the config space. > pci: declare structures and IOMMU operation for PRI > pci: add a PCI-level API for PRI > intel_iommu: declare PRI constants and structures > intel_iommu: declare registers for PRI > intel_iommu: add PRI operations support > > hw/i386/intel_iommu.c | 302 +++++++++++++++++++++++++++++++++ > hw/i386/intel_iommu_internal.h | 54 +++++- > hw/pci/pci.c | 37 ++++ > hw/pci/pcie.c | 42 +++++ > include/exec/memory.h | 65 +++++++ > include/hw/pci/pci.h | 45 +++++ > include/hw/pci/pci_bus.h | 1 + > include/hw/pci/pcie.h | 7 +- > include/hw/pci/pcie_regs.h | 4 + > system/memory.c | 49 ++++++ > 10 files changed, 604 insertions(+), 2 deletions(-) > -- Regards, Yi Liu
On 05/07/2024 05:03, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, > unless this email comes from a known sender and you know the content > is safe. > > > On 2024/5/30 20:24, CLEMENT MATHIEU--DRIF wrote: >> This series belongs to a list of series that add SVM support for VT-d. >> >> Here we focus on the implementation of PRI support in the IOMMU and >> on a PCI-level >> API for PRI to be used by virtual devices. >> >> This work is based on the VT-d specification version 4.1 (March 2023). >> Here is a link to a GitHub repository where you can find the >> following elements : >> - Qemu with all the patches for SVM >> - ATS >> - PRI >> - Device IOTLB invalidations >> - Requests with already translated addresses >> - A demo device >> - A simple driver for the demo device >> - A userspace program (for testing and demonstration purposes) > > I didn't see the drain PRQ related logics in this series. Please consider > adding it in next version. It's needed when repurposing a PASID. Hi, Are you talking about wait descriptors with SW = 0, IF = 0, FN = 1 (section 7.10 of VT-d)? I'll move that to the PRI series. > >> https://github.com/BullSequana/Qemu-in-guest-SVM-demo >> >> >> Clément Mathieu--Drif (8): >> pcie: add a helper to declare the PRI capability for a pcie device >> pcie: helper functions to check to check if PRI is enabled >> pcie: add a way to get the outstanding page request allocation (pri) >> from the config space. >> pci: declare structures and IOMMU operation for PRI >> pci: add a PCI-level API for PRI >> intel_iommu: declare PRI constants and structures >> intel_iommu: declare registers for PRI >> intel_iommu: add PRI operations support >> >> hw/i386/intel_iommu.c | 302 +++++++++++++++++++++++++++++++++ >> hw/i386/intel_iommu_internal.h | 54 +++++- >> hw/pci/pci.c | 37 ++++ >> hw/pci/pcie.c | 42 +++++ >> include/exec/memory.h | 65 +++++++ >> include/hw/pci/pci.h | 45 +++++ >> include/hw/pci/pci_bus.h | 1 + >> include/hw/pci/pcie.h | 7 +- >> include/hw/pci/pcie_regs.h | 4 + >> system/memory.c | 49 ++++++ >> 10 files changed, 604 insertions(+), 2 deletions(-) >> > > -- > Regards, > Yi Liu
On 2024/7/5 13:13, CLEMENT MATHIEU--DRIF wrote: > > On 05/07/2024 05:03, Yi Liu wrote: >> Caution: External email. Do not open attachments or click links, >> unless this email comes from a known sender and you know the content >> is safe. >> >> >> On 2024/5/30 20:24, CLEMENT MATHIEU--DRIF wrote: >>> This series belongs to a list of series that add SVM support for VT-d. >>> >>> Here we focus on the implementation of PRI support in the IOMMU and >>> on a PCI-level >>> API for PRI to be used by virtual devices. >>> >>> This work is based on the VT-d specification version 4.1 (March 2023). >>> Here is a link to a GitHub repository where you can find the >>> following elements : >>> - Qemu with all the patches for SVM >>> - ATS >>> - PRI >>> - Device IOTLB invalidations >>> - Requests with already translated addresses >>> - A demo device >>> - A simple driver for the demo device >>> - A userspace program (for testing and demonstration purposes) >> >> I didn't see the drain PRQ related logics in this series. Please consider >> adding it in next version. It's needed when repurposing a PASID. > > Hi, > > Are you talking about wait descriptors with SW = 0, IF = 0, FN = 1 > (section 7.10 of VT-d)? > > I'll move that to the PRI series. yes. But not only that patch. When guest software submitting the descriptors per CH7.10 of VT-d spec, QEMU need to emulate the PRQ drain behavior. >> >>> https://github.com/BullSequana/Qemu-in-guest-SVM-demo >>> >>> >>> Clément Mathieu--Drif (8): >>> pcie: add a helper to declare the PRI capability for a pcie device >>> pcie: helper functions to check to check if PRI is enabled >>> pcie: add a way to get the outstanding page request allocation (pri) >>> from the config space. >>> pci: declare structures and IOMMU operation for PRI >>> pci: add a PCI-level API for PRI >>> intel_iommu: declare PRI constants and structures >>> intel_iommu: declare registers for PRI >>> intel_iommu: add PRI operations support >>> >>> hw/i386/intel_iommu.c | 302 +++++++++++++++++++++++++++++++++ >>> hw/i386/intel_iommu_internal.h | 54 +++++- >>> hw/pci/pci.c | 37 ++++ >>> hw/pci/pcie.c | 42 +++++ >>> include/exec/memory.h | 65 +++++++ >>> include/hw/pci/pci.h | 45 +++++ >>> include/hw/pci/pci_bus.h | 1 + >>> include/hw/pci/pcie.h | 7 +- >>> include/hw/pci/pcie_regs.h | 4 + >>> system/memory.c | 49 ++++++ >>> 10 files changed, 604 insertions(+), 2 deletions(-) >>> >> >> -- >> Regards, >> Yi Liu -- Regards, Yi Liu
On 05/07/2024 08:20, Yi Liu wrote: > On 2024/7/5 13:13, CLEMENT MATHIEU--DRIF wrote: >> >> On 05/07/2024 05:03, Yi Liu wrote: >>> Caution: External email. Do not open attachments or click links, >>> unless this email comes from a known sender and you know the content >>> is safe. >>> >>> >>> On 2024/5/30 20:24, CLEMENT MATHIEU--DRIF wrote: >>>> This series belongs to a list of series that add SVM support for VT-d. >>>> >>>> Here we focus on the implementation of PRI support in the IOMMU and >>>> on a PCI-level >>>> API for PRI to be used by virtual devices. >>>> >>>> This work is based on the VT-d specification version 4.1 (March 2023). >>>> Here is a link to a GitHub repository where you can find the >>>> following elements : >>>> - Qemu with all the patches for SVM >>>> - ATS >>>> - PRI >>>> - Device IOTLB invalidations >>>> - Requests with already translated addresses >>>> - A demo device >>>> - A simple driver for the demo device >>>> - A userspace program (for testing and demonstration purposes) >>> >>> I didn't see the drain PRQ related logics in this series. Please >>> consider >>> adding it in next version. It's needed when repurposing a PASID. >> >> Hi, >> >> Are you talking about wait descriptors with SW = 0, IF = 0, FN = 1 >> (section 7.10 of VT-d)? >> >> I'll move that to the PRI series. > > yes. But not only that patch. When guest software submitting the > descriptors per CH7.10 of VT-d spec, QEMU need to emulate the > PRQ drain behavior. > Ok, will check >>> >>>> https://github.com/BullSequana/Qemu-in-guest-SVM-demo >>>> >>>> >>>> Clément Mathieu--Drif (8): >>>> pcie: add a helper to declare the PRI capability for a pcie device >>>> pcie: helper functions to check to check if PRI is enabled >>>> pcie: add a way to get the outstanding page request allocation >>>> (pri) >>>> from the config space. >>>> pci: declare structures and IOMMU operation for PRI >>>> pci: add a PCI-level API for PRI >>>> intel_iommu: declare PRI constants and structures >>>> intel_iommu: declare registers for PRI >>>> intel_iommu: add PRI operations support >>>> >>>> hw/i386/intel_iommu.c | 302 >>>> +++++++++++++++++++++++++++++++++ >>>> hw/i386/intel_iommu_internal.h | 54 +++++- >>>> hw/pci/pci.c | 37 ++++ >>>> hw/pci/pcie.c | 42 +++++ >>>> include/exec/memory.h | 65 +++++++ >>>> include/hw/pci/pci.h | 45 +++++ >>>> include/hw/pci/pci_bus.h | 1 + >>>> include/hw/pci/pcie.h | 7 +- >>>> include/hw/pci/pcie_regs.h | 4 + >>>> system/memory.c | 49 ++++++ >>>> 10 files changed, 604 insertions(+), 2 deletions(-) >>>> >>> >>> -- >>> Regards, >>> Yi Liu >
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