The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:

Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528

for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:

target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)

RISC-V PR for 9.1

* APLICs add child earlier than realize

* Fix exposure of Zkr

* Raise exceptions on wrs.nto

* Implement SBI debug console (DBCN) calls for KVM

* Support 64-bit addresses for initrd

* Change RISCV_EXCP_SEMIHOST exception number to 63

* Tolerate KVM disable ext errors

* Set tval in breakpoints

* Add support for Zve32x extension

* Add support for Zve64x extension

* Relax vector register check in RISCV gdbstub

* Fix the element agnostic Vector function problem

* Fix Zvkb extension config

* Implement dynamic establishment of custom decoder

* Add th.sxstatus CSR emulation

* Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions

* Check single width operator for vector fp widen instructions

* Check single width operator for vfncvt.rod.f.f.w

* Remove redudant SEW checking for vector fp narrow/widen instructions

* Prioritize pmp errors in raise_mmu_exception()

* Do not set mtval2 for non guest-page faults

* Remove experimental prefix from "B" extension

* Fixup CBO extension register calculation

* Fix the hart bit setting of AIA

* Fix reg_width in ricsv_gen_dynamic_vector_feature()

* Decode all of the pmpcfg and pmpaddr CSRs

* Raise an exception when CSRRS/CSRRC writes a read-only CSR

Alexei Filippov (1):

target/riscv: do not set mtval2 for non guest-page faults

Alistair Francis (2):

target/riscv: rvzicbo: Fixup CBO extension register calculation

disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs

Andrew Jones (2):

target/riscv/kvm: Fix exposure of Zkr

target/riscv: Raise exceptions on wrs.nto

Cheng Yang (1):

hw/riscv/boot.c: Support 64-bit address for initrd

Christoph Müllner (1):

riscv: thead: Add th.sxstatus CSR emulation

Clément Léger (1):

target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

Daniel Henrique Barboza (6):

target/riscv/kvm: implement SBI debug console (DBCN) calls

target/riscv/kvm: tolerate KVM disable ext errors

target/riscv/debug: set tval=pc in breakpoint exceptions

trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint

target/riscv: prioritize pmp errors in raise_mmu_exception()

riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()

Huang Tao (2):

target/riscv: Fix the element agnostic function problem

target/riscv: Implement dynamic establishment of custom decoder

Jason Chien (3):

target/riscv: Add support for Zve32x extension

target/riscv: Add support for Zve64x extension

target/riscv: Relax vector register check in RISCV gdbstub

Max Chou (4):

target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions

target/riscv: rvv: Check single width operator for vector fp widen instructions

target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w

target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions

Rob Bradford (1):

target/riscv: Remove experimental prefix from "B" extension

Yangyu Chen (1):

target/riscv/cpu.c: fix Zvkb extension config

Yong-Xuan Wang (1):

target/riscv/kvm.c: Fix the hart bit setting of AIA

Yu-Ming Chang (1):

target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

yang.zhang (1):

hw/intc/riscv_aplic: APLICs should add child earlier than realize

MAINTAINERS | 1 +

target/riscv/cpu.h | 11 ++

target/riscv/cpu_bits.h | 2 +-

target/riscv/cpu_cfg.h | 2 +

target/riscv/helper.h | 1 +

target/riscv/sbi_ecall_interface.h | 17 +++

target/riscv/tcg/tcg-cpu.h | 15 +++

disas/riscv.c | 65 +++++++++-

hw/intc/riscv_aplic.c | 8 +-

hw/riscv/boot.c | 4 +-

target/riscv/cpu.c | 10 +-

target/riscv/cpu_helper.c | 37 +++---

target/riscv/csr.c | 71 +++++++++--

target/riscv/debug.c | 3 +

target/riscv/gdbstub.c | 8 +-

target/riscv/kvm/kvm-cpu.c | 157 ++++++++++++++++++++++++-

target/riscv/op_helper.c | 17 ++-

target/riscv/tcg/tcg-cpu.c | 50 +++++---

target/riscv/th_csr.c | 79 +++++++++++++

target/riscv/translate.c | 31 +++--

target/riscv/vector_internals.c | 22 ++++

target/riscv/insn_trans/trans_privileged.c.inc | 2 +

target/riscv/insn_trans/trans_rvv.c.inc | 46 +++++---

target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 +++--

target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++-

target/riscv/meson.build | 1 +

26 files changed, 596 insertions(+), 109 deletions(-)

create mode 100644 target/riscv/th_csr.c

From: Christoph Müllner <christoph.muellner@vrull.eu>

The th.sxstatus CSR can be used to identify available custom extension

on T-Head CPUs. The CSR is documented here:

https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc

An important property of this patch is, that the th.sxstatus MAEE field

is not set (indicating that XTheadMae is not available).

XTheadMae is a memory attribute extension (similar to Svpbmt) which is

implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits

in PTEs that are marked as reserved. QEMU maintainers prefer to not

implement XTheadMae, so we need give kernels a mechanism to identify

if XTheadMae is available in a system or not. And this patch introduces

this mechanism in QEMU in a way that's compatible with real HW

(i.e., probing the th.sxstatus.MAEE bit).

Further context can be found on the list:

https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html

Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>

MAINTAINERS | 1 +

target/riscv/cpu.h | 3 ++

target/riscv/cpu.c | 1 +

target/riscv/th_csr.c | 79 ++++++++++++++++++++++++++++++++++++++++

target/riscv/meson.build | 1 +

5 files changed, 85 insertions(+)

create mode 100644 target/riscv/th_csr.c

F: target/riscv/insn_trans/trans_xthead.c.inc

F: target/riscv/xthead*.decode

+F: target/riscv/th_*

F: disas/riscv-xthead*

RISC-V XVentanaCondOps extension

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/target/riscv/cpu.h

+++ b/target/riscv/cpu.h

@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,

uint8_t satp_mode_max_from_map(uint32_t map);

const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);

+/* Implemented in th_csr.c */

+void th_register_custom_csrs(RISCVCPU *cpu);

+

#endif /* RISCV_CPU_H */

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c

index XXXXXXX..XXXXXXX 100644

--- a/target/riscv/cpu.c

+++ b/target/riscv/cpu.c

@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)

cpu->cfg.mvendorid = THEAD_VENDOR_ID;

#ifndef CONFIG_USER_ONLY

set_satp_mode_max_supported(cpu, VM_1_10_SV39);

+ th_register_custom_csrs(cpu);

#endif

/* inherited from parent obj via riscv_cpu_init() */

diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/target/riscv/th_csr.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * T-Head-specific CSRs.

+ *

+ * Copyright (c) 2024 VRULL GmbH

+ *

+ * This program is free software; you can redistribute it and/or modify it

+ * under the terms and conditions of the GNU General Public License,

+ * version 2 or later, as published by the Free Software Foundation.

+ *

+ * This program is distributed in the hope it will be useful, but WITHOUT

+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for

+ * more details.

+ *

+ * You should have received a copy of the GNU General Public License along with

+ * this program. If not, see <http://www.gnu.org/licenses/>.

+ */

+

+#include "qemu/osdep.h"

+#include "cpu.h"

+#include "cpu_vendorid.h"

+

+#define CSR_TH_SXSTATUS 0x5c0

+

+/* TH_SXSTATUS bits */

+#define TH_SXSTATUS_UCME BIT(16)

+#define TH_SXSTATUS_MAEE BIT(21)

+#define TH_SXSTATUS_THEADISAEE BIT(22)

+

+typedef struct {

+ int csrno;

+ int (*insertion_test)(RISCVCPU *cpu);

+ riscv_csr_operations csr_ops;

+} riscv_csr;

+

+static RISCVException smode(CPURISCVState *env, int csrno)

+{

+ if (riscv_has_ext(env, RVS)) {

+ return RISCV_EXCP_NONE;

+ }

+

+ return RISCV_EXCP_ILLEGAL_INST;

+}

+

+static int test_thead_mvendorid(RISCVCPU *cpu)

+{

+ if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {

+ return -1;

+ }

+

+ return 0;

+}

+

+static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,

+ target_ulong *val)

+{

+ /* We don't set MAEE here, because QEMU does not implement MAEE. */

+ *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;

+ return RISCV_EXCP_NONE;

+}

+

+static riscv_csr th_csr_list[] = {

+ {

+ .csrno = CSR_TH_SXSTATUS,

+ .insertion_test = test_thead_mvendorid,

+ .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }

+ }

+};

+

+void th_register_custom_csrs(RISCVCPU *cpu)

+{

+ for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {

+ int csrno = th_csr_list[i].csrno;

+ riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;

+ if (!th_csr_list[i].insertion_test(cpu)) {

+ riscv_set_csr_ops(csrno, csr_ops);

+ }

+ }

+}

diff --git a/target/riscv/meson.build b/target/riscv/meson.build

index XXXXXXX..XXXXXXX 100644

--- a/target/riscv/meson.build

+++ b/target/riscv/meson.build

@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(

'monitor.c',

'machine.c',

'pmu.c',

+ 'th_csr.c',

'time_helper.c',

'riscv-qmp-cmds.c',

))

2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length

in bytes, when in this context we want 'reg_width' as the length in

bits.

Fix 'reg_width' back to the value in bits like 7cb59921c05a

("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set

beforehand.

While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more

clarity about what the variable represents. 'bitsize' is also used in

riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to

gdb_feature_builder_append_reg().

Cc: Akihiko Odaki <akihiko.odaki@daynix.com>

Cc: Alex Bennée <alex.bennee@linaro.org>

Reported-by: Robin Dapp <rdapp.gcc@gmail.com>

Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Acked-by: Alex Bennée <alex.bennee@linaro.org>

Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>

Cc: qemu-stable <qemu-stable@nongnu.org>

Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>

target/riscv/gdbstub.c | 6 +++---

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c

--- a/target/riscv/gdbstub.c

+++ b/target/riscv/gdbstub.c

@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)

static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)

{

RISCVCPU *cpu = RISCV_CPU(cs);

- int reg_width = cpu->cfg.vlenb;

+ int bitsize = cpu->cfg.vlenb << 3;

GDBFeatureBuilder builder;

int i;

@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)

/* First define types and totals in a whole VL */

for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {

- int count = reg_width / vec_lanes[i].size;

+ int count = bitsize / vec_lanes[i].size;

gdb_feature_builder_append_tag(

&builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",

vec_lanes[i].id, vec_lanes[i].gdb_type, count);

@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)

/* Define vector registers */

for (i = 0; i < 32; i++) {

gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),

- reg_width, i, "riscv_vector", "vector");

+ bitsize, i, "riscv_vector", "vector");

}

gdb_feature_builder_end(&builder);

2.45.1

Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr

enabled, will fail with a kernel oops SIGILL right at the start. The

reason is that we can't expose zkr without implementing the SEED CSR.

Disabling zkr in the guest would be a workaround, but if the KVM doesn't

allow it we'll error out and never boot.

In hindsight this is too strict. If we keep proceeding, despite not

disabling the extension in the KVM vcpu, we'll not add the extension in

the riscv,isa. The guest kernel will be unaware of the extension, i.e.

it doesn't matter if the KVM vcpu has it enabled underneath or not. So

it's ok to keep booting in this case.

Change our current logic to not error out if we fail to disable an

extension in kvm_set_one_reg(), but show a warning and keep booting. It

is important to throw a warning because we must make the user aware that

the extension is still available in the vcpu, meaning that an

ill-behaved guest can ignore the riscv,isa settings and use the

extension.

The case we're handling happens with an EINVAL error code. If we fail to

disable the extension in KVM for any other reason, error out.

We'll also keep erroring out when we fail to enable an extension in KVM,

since adding the extension in riscv,isa at this point will cause a guest

malfunction because the extension isn't enabled in the vcpu.

Suggested-by: Andrew Jones <ajones@ventanamicro.com>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Cc: qemu-stable <qemu-stable@nongnu.org>

Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>

target/riscv/kvm/kvm-cpu.c | 12 ++++++++----

1 file changed, 8 insertions(+), 4 deletions(-)

@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)

reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);

ret = kvm_set_one_reg(cs, id, &reg);

if (ret != 0) {

- error_report("Unable to %s extension %s in KVM, error %d",

- reg ? "enable" : "disable",

- multi_ext_cfg->name, ret);

- exit(EXIT_FAILURE);

+ if (!reg && ret == -EINVAL) {

+ warn_report("KVM cannot disable extension %s",

+ multi_ext_cfg->name);

+ } else {

+ error_report("Unable to enable extension %s in KVM, error %d",

+ multi_ext_cfg->name, ret);

+ exit(EXIT_FAILURE);

+ }

}

}

2.45.1