Series comparison

-[PULL 00/28] riscv-to-apply queue
+[PULL v2 00/45] riscv-to-apply queue
-The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:
+From: Alistair Francis <alistair.francis@wdc.com>
-  Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)
+The following changes since commit 222059a0fccf4af3be776fe35a5ea2d6a68f9a0b:
   Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into staging (2022-12-21 18:08:09 +0000)
 are available in the Git repository at:
-  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528
+  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20221222-1
-for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:
+for you to fetch changes up to 71a9bc59728a054036f3db7dd82dab8f8bd2baf9:
-  target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)
+  hw/intc: sifive_plic: Fix the pending register range check (2022-12-22 08:36:30 +1000)
 ----------------------------------------------------------------
-RISC-V PR for 9.1
+First RISC-V PR for QEMU 8.0
-* APLICs add child earlier than realize
+* Fix PMP propagation for tlb
-* Fix exposure of Zkr
+* Collection of bug fixes
-* Raise exceptions on wrs.nto
+* Add the `FIELDx_1CLEAR()` macro
-* Implement SBI debug console (DBCN) calls for KVM
+* Bump the OpenTitan supported version
-* Support 64-bit addresses for initrd
+* Add smstateen support
-* Change RISCV_EXCP_SEMIHOST exception number to 63
+* Support native debug icount trigger
-* Tolerate KVM disable ext errors
+* Remove the redundant ipi-id property in the virt machine
-* Set tval in breakpoints
+* Support cache-related PMU events in virtual mode
-* Add support for Zve32x extension
+* Add some missing PolarFire SoC io regions
-* Add support for Zve64x extension
+* Fix mret exception cause when no pmp rule is configured
-* Relax vector register check in RISCV gdbstub
+* Fix bug where disabling compressed instructions would crash QEMU
-* Fix the element agnostic Vector function problem
+* Add Zawrs ISA extension support
-* Fix Zvkb extension config
+* A range of code refactoring and cleanups
 * Implement dynamic establishment of custom decoder
 * Add th.sxstatus CSR emulation
 * Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
 * Check single width operator for vector fp widen instructions
 * Check single width operator for vfncvt.rod.f.f.w
 * Remove redudant SEW checking for vector fp narrow/widen instructions
 * Prioritize pmp errors in raise_mmu_exception()
 * Do not set mtval2 for non guest-page faults
 * Remove experimental prefix from "B" extension
 * Fixup CBO extension register calculation
 * Fix the hart bit setting of AIA
 * Fix reg_width in ricsv_gen_dynamic_vector_feature()
 * Decode all of the pmpcfg and pmpaddr CSRs
 * Raise an exception when CSRRS/CSRRC writes a read-only CSR
 ----------------------------------------------------------------
-Alexei Filippov (1):
+Anup Patel (1):
-      target/riscv: do not set mtval2 for non guest-page faults
+      target/riscv: Typo fix in sstc() predicate
-Alistair Francis (2):
+Atish Patra (1):
-      target/riscv: rvzicbo: Fixup CBO extension register calculation
+      hw/riscv: virt: Remove the redundant ipi-id property
       disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
-Andrew Jones (2):
+Bin Meng (20):
-      target/riscv/kvm: Fix exposure of Zkr
+      target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state()
-      target/riscv: Raise exceptions on wrs.nto
+      target/riscv: Fix mret exception cause when no pmp rule is configured
       target/riscv: Simplify helper_sret() a little bit
       target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+
       hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC
       hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers
       hw/riscv: Fix opentitan dependency to SIFIVE_PLIC
       hw/riscv: Sort machines Kconfig options in alphabetical order
       hw/riscv: spike: Remove misleading comments
       hw/intc: sifive_plic: Drop PLICMode_H
       hw/intc: sifive_plic: Improve robustness of the PLIC config parser
       hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize()
       hw/intc: sifive_plic: Update "num-sources" property default value
       hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC
       hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC
       hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"
       hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb
       hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0
       hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization
       hw/intc: sifive_plic: Fix the pending register range check
-Cheng Yang (1):
+Christoph Muellner (1):
-      hw/riscv/boot.c: Support 64-bit address for initrd
+      RISC-V: Add Zawrs ISA extension support
-Christoph Müllner (1):
+Conor Dooley (3):
-      riscv: thead: Add th.sxstatus CSR emulation
+      hw/misc: pfsoc: add fabric clocks to ioscb
       hw/riscv: pfsoc: add missing FICs as unimplemented
       hw/{misc, riscv}: pfsoc: add system controller as unimplemented
-Clément Léger (1):
+Frédéric Pétrot (1):
-      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
+      hw/intc: sifive_plic: Renumber the S irqs for numa support
-Daniel Henrique Barboza (6):
+Jim Shu (2):
-      target/riscv/kvm: implement SBI debug console (DBCN) calls
+      target/riscv: support cache-related PMU events in virtual mode
-      target/riscv/kvm: tolerate KVM disable ext errors
+      hw/intc: sifive_plic: fix out-of-bound access of source_priority array
       target/riscv/debug: set tval=pc in breakpoint exceptions
       trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
       target/riscv: prioritize pmp errors in raise_mmu_exception()
       riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
-Huang Tao (2):
+LIU Zhiwei (5):
-      target/riscv: Fix the element agnostic function problem
+      target/riscv: Fix PMP propagation for tlb
-      target/riscv: Implement dynamic establishment of custom decoder
+      target/riscv: Add itrigger support when icount is not enabled
       target/riscv: Add itrigger support when icount is enabled
       target/riscv: Enable native debug itrigger
       target/riscv: Add itrigger_enabled field to CPURISCVState
-Jason Chien (3):
+Mayuresh Chitale (3):
-      target/riscv: Add support for Zve32x extension
+      target/riscv: Add smstateen support
-      target/riscv: Add support for Zve64x extension
+      target/riscv: smstateen check for h/s/envcfg
-      target/riscv: Relax vector register check in RISCV gdbstub
+      target/riscv: generate virtual instruction exception
-Max Chou (4):
+Richard Henderson (4):
-      target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
+      tcg/riscv: Fix range matched by TCG_CT_CONST_M12
-      target/riscv: rvv: Check single width operator for vector fp widen instructions
+      tcg/riscv: Fix reg overlap case in tcg_out_addsub2
-      target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
+      tcg/riscv: Fix base register for user-only qemu_ld/st
-      target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
+      target/riscv: Set pc_succ_insn for !rvc illegal insn
-Rob Bradford (1):
+Wilfred Mallawa (4):
-      target/riscv: Remove experimental prefix from "B" extension
+      hw/registerfields: add `FIELDx_1CLEAR()` macro
       hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro
       hw/riscv/opentitan: bump opentitan
       hw/riscv/opentitan: add aon_timer base unimpl
-Yangyu Chen (1):
+ include/hw/intc/sifive_plic.h                  |   1 -
-      target/riscv/cpu.c: fix Zvkb extension config
+ include/hw/misc/mchp_pfsoc_ioscb.h             |   4 +
+ include/hw/misc/mchp_pfsoc_sysreg.h            |   1 +
-Yong-Xuan Wang (1):
+ include/hw/registerfields.h                    |  22 ++
-      target/riscv/kvm.c: Fix the hart bit setting of AIA
+ include/hw/riscv/microchip_pfsoc.h             |   7 +-
+ include/hw/riscv/opentitan.h                   |  10 +-
-Yu-Ming Chang (1):
+ include/hw/riscv/shakti_c.h                    |   2 +-
-      target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
+ include/hw/riscv/sifive_e.h                    |   9 +-
+ include/hw/riscv/sifive_u.h                    |   2 +-
-yang.zhang (1):
+ include/hw/riscv/virt.h                        |   8 +-
-      hw/intc/riscv_aplic: APLICs should add child earlier than realize
+ target/riscv/cpu.h                             |  10 +
+ target/riscv/cpu_bits.h                        |  37 +++
- MAINTAINERS                                    |   1 +
+ target/riscv/debug.h                           |  13 +
- target/riscv/cpu.h                             |  11 ++
+ target/riscv/helper.h                          |   2 +
- target/riscv/cpu_bits.h                        |   2 +-
+ target/riscv/pmp.h                             |   6 +-
- target/riscv/cpu_cfg.h                         |   2 +
+ target/riscv/insn32.decode                     |   4 +
- target/riscv/helper.h                          |   1 +
+ hw/intc/sifive_plic.c                          |  66 +++--
- target/riscv/sbi_ecall_interface.h             |  17 +++
+ hw/misc/mchp_pfsoc_ioscb.c                     |  78 ++++-
- target/riscv/tcg/tcg-cpu.h                     |  15 +++
+ hw/misc/mchp_pfsoc_sysreg.c                    |  18 +-
- disas/riscv.c                                  |  65 +++++++++-
+ hw/riscv/microchip_pfsoc.c                     | 121 ++++----
- hw/intc/riscv_aplic.c                          |   8 +-
+ hw/riscv/opentitan.c                           |  26 +-
- hw/riscv/boot.c                                |   4 +-
+ hw/riscv/sifive_u.c                            |   3 +-
- target/riscv/cpu.c                             |  10 +-
+ hw/riscv/spike.c                               |   1 -
- target/riscv/cpu_helper.c                      |  37 +++---
+ hw/riscv/virt.c                                |   7 +-
- target/riscv/csr.c                             |  71 +++++++++--
+ hw/ssi/ibex_spi_host.c                         |  21 +-
- target/riscv/debug.c                           |   3 +
+ target/riscv/cpu.c                             |  11 +
- target/riscv/gdbstub.c                         |   8 +-
+ target/riscv/cpu_helper.c                      |  26 +-
- target/riscv/kvm/kvm-cpu.c                     | 157 ++++++++++++++++++++++++-
+ target/riscv/csr.c                             | 393 ++++++++++++++++++++++++-
- target/riscv/op_helper.c                       |  17 ++-
+ target/riscv/debug.c                           | 205 +++++++++++++
- target/riscv/tcg/tcg-cpu.c                     |  50 +++++---
+ target/riscv/machine.c                         |  36 +++
- target/riscv/th_csr.c                          |  79 +++++++++++++
+ target/riscv/op_helper.c                       |  28 +-
- target/riscv/translate.c                       |  31 +++--
+ target/riscv/pmp.c                             |  90 ++----
- target/riscv/vector_internals.c                |  22 ++++
+ target/riscv/translate.c                       |  54 +++-
- target/riscv/insn_trans/trans_privileged.c.inc |   2 +
+ target/riscv/insn_trans/trans_privileged.c.inc |   4 +-
- target/riscv/insn_trans/trans_rvv.c.inc        |  46 +++++---
+ target/riscv/insn_trans/trans_rvi.c.inc        |   8 +-
- target/riscv/insn_trans/trans_rvzawrs.c.inc    |  29 +++--
+ target/riscv/insn_trans/trans_rvv.c.inc        |   4 +-
- target/riscv/insn_trans/trans_rvzicbo.c.inc    |  16 ++-
+ target/riscv/insn_trans/trans_rvzawrs.c.inc    |  51 ++++
- target/riscv/meson.build                       |   1 +
+ tcg/riscv/tcg-target.c.inc                     |  68 +++--
-files changed, 596 insertions(+), 109 deletions(-)
+ hw/intc/Kconfig                                |   3 +
- create mode 100644 target/riscv/th_csr.c
+ hw/riscv/Kconfig                               |  22 +-
+ tests/tcg/Makefile.target                      |   2 +
  tests/tcg/riscv64/Makefile.target              |   6 +
  tests/tcg/riscv64/test-noc.S                   |  32 ++
 files changed, 1256 insertions(+), 266 deletions(-)
  create mode 100644 target/riscv/insn_trans/trans_rvzawrs.c.inc
  create mode 100644 tests/tcg/riscv64/test-noc.S

-[PULL 21/28] target/riscv: prioritize pmp errors in raise_mmu_exception()
+[PULL v2 01/45] target/riscv: Fix PMP propagation for tlb
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-raise_mmu_exception(), as is today, is prioritizing guest page faults by
+Only the pmp index that be checked by pmp_hart_has_privs can be used
-checking first if virt_enabled && !first_stage, and then considering the
+by pmp_get_tlb_size to avoid an error pmp index.
-regular inst/load/store faults.
+Before modification, we may use an error pmp index. For example,
-There's no mention in the spec about guest page fault being a higher
+we check address 0x4fc, and the size 0x4 in pmp_hart_has_privs. If there
-priority that PMP faults. In fact, privileged spec section 3.7.1 says:
+is an pmp rule, valid range is [0x4fc, 0x500), then pmp_hart_has_privs
+will return true;
-"Attempting to fetch an instruction from a PMP region that does not have
-execute permissions raises an instruction access-fault exception.
+However, this checked pmp index is discarded as pmp_hart_has_privs
-Attempting to execute a load or load-reserved instruction which accesses
+return bool value. In pmp_is_range_in_tlb, it will traverse all pmp
-a physical address within a PMP region without read permissions raises a
+rules. The tlb_sa will be 0x0, and tlb_ea will be 0xfff. If there is
-load access-fault exception. Attempting to execute a store,
+a pmp rule [0x10, 0x14), it will be misused as it is legal in
-store-conditional, or AMO instruction which accesses a physical address
+pmp_get_tlb_size.
-within a PMP region without write permissions raises a store
-access-fault exception."
+As we have already known the correct pmp index, just remove the
+remove the pmp_is_range_in_tlb and get tlb size directly from
-So, in fact, we're doing it wrong - PMP faults should always be thrown,
+pmp_get_tlb_size.
-regardless of also being a first or second stage fault.
+Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 The way riscv_cpu_tlb_fill() and get_physical_address() work is
 adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
 reflected in the 'pmp_violation' flag. What we need is to change
 raise_mmu_exception() to prioritize it.
 Reported-by: Joseph Chan <jchan@ventanamicro.com>
 Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
+Message-Id: <20221012060016.30856-1-zhiwei_liu@linux.alibaba.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 22 ++++++++++++----------
+ target/riscv/pmp.h        |  6 +--
-file changed, 12 insertions(+), 10 deletions(-)
+ target/riscv/cpu_helper.c | 16 ++++---
+ target/riscv/pmp.c        | 90 +++++++++++++--------------------------
 files changed, 42 insertions(+), 70 deletions(-)
 diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/pmp.h
 +++ b/target/riscv/pmp.h
@@ -XXX,XX +XXX,XX @@ target_ulong mseccfg_csr_read(CPURISCVState *env);
  void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
      target_ulong val);
  target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
 -bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
 +int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
      target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
      target_ulong mode);
 -bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
 -                         target_ulong *tlb_size);
 +target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
 +                              target_ulong tlb_sa, target_ulong tlb_ea);
  void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
  void pmp_update_rule_nums(CPURISCVState *env);
  uint32_t pmp_get_num_rules(CPURISCVState *env);
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
+@@ -XXX,XX +XXX,XX @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
+                                     int mode)
-     switch (access_type) {
+ {
-     case MMU_INST_FETCH:
+     pmp_priv_t pmp_priv;
--        if (env->virt_enabled && !first_stage) {
+-    target_ulong tlb_size_pmp = 0;
-+        if (pmp_violation) {
++    int pmp_index = -1;
-+            cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
-+        } else if (env->virt_enabled && !first_stage) {
+     if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
-             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
+         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
-         } else {
+         return TRANSLATE_SUCCESS;
--            cs->exception_index = pmp_violation ?
+     }
--                RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
-+            cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
+-    if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
 -                            mode)) {
 +    pmp_index = pmp_hart_has_privs(env, addr, size, 1 << access_type,
 +                                   &pmp_priv, mode);
 +    if (pmp_index < 0) {
          *prot = 0;
          return TRANSLATE_PMP_FAIL;
      }
      *prot = pmp_priv_to_page_prot(pmp_priv);
 -    if (tlb_size != NULL) {
 -        if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
 -            *tlb_size = tlb_size_pmp;
 -        }
 +    if ((tlb_size != NULL) && pmp_index != MAX_RISCV_PMPS) {
 +        target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1);
 +        target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1;
 +
 +        *tlb_size = pmp_get_tlb_size(env, pmp_index, tlb_sa, tlb_ea);
      }
      return TRANSLATE_SUCCESS;
 diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/pmp.c
 +++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
  /*
   * Check if the address has required RWX privs to complete desired operation
 + * Return PMP rule index if a pmp rule match
 + * Return MAX_RISCV_PMPS if default match
 + * Return negtive value if no match
   */
 -bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
 +int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
      target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
      target_ulong mode)
  {
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
      /* Short cut if no rules */
      if (0 == pmp_get_num_rules(env)) {
 -        return pmp_hart_has_privs_default(env, addr, size, privs,
 -                                          allowed_privs, mode);
 +        if (pmp_hart_has_privs_default(env, addr, size, privs,
 +                                       allowed_privs, mode)) {
 +            ret = MAX_RISCV_PMPS;
 +        }
      }
      if (size == 0) {
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
          if ((s + e) == 1) {
              qemu_log_mask(LOG_GUEST_ERROR,
                            "pmp violation - access is partially inside\n");
 -            ret = 0;
 +            ret = -1;
              break;
          }
-         break;
-     case MMU_DATA_LOAD:
+@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
--        if (two_stage && !first_stage) {
+                 }
-+        if (pmp_violation) {
+             }
-+            cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
-+        } else if (two_stage && !first_stage) {
+-            ret = ((privs & *allowed_privs) == privs);
-             cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
++            if ((privs & *allowed_privs) == privs) {
-         } else {
++                ret = i;
--            cs->exception_index = pmp_violation ?
++            }
--                RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
+             break;
 +            cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
          }
-         break;
+     }
-     case MMU_DATA_STORE:
--        if (two_stage && !first_stage) {
+     /* No rule matched */
-+        if (pmp_violation) {
+     if (ret == -1) {
-+            cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
+-        return pmp_hart_has_privs_default(env, addr, size, privs,
-+        } else if (two_stage && !first_stage) {
+-                                          allowed_privs, mode);
-             cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
++        if (pmp_hart_has_privs_default(env, addr, size, privs,
-         } else {
++                                       allowed_privs, mode)) {
--            cs->exception_index = pmp_violation ?
++            ret = MAX_RISCV_PMPS;
--                RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
++        }
--                RISCV_EXCP_STORE_PAGE_FAULT;
+     }
-+            cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
-         }
+-    return ret == 1 ? true : false;
-         break;
++    return ret;
-     default:
+ }
  /*
@@ -XXX,XX +XXX,XX @@ target_ulong mseccfg_csr_read(CPURISCVState *env)
   * Calculate the TLB size if the start address or the end address of
   * PMP entry is presented in the TLB page.
   */
 -static target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
 -                                     target_ulong tlb_sa, target_ulong tlb_ea)
 +target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
 +                              target_ulong tlb_sa, target_ulong tlb_ea)
  {
      target_ulong pmp_sa = env->pmp_state.addr[pmp_index].sa;
      target_ulong pmp_ea = env->pmp_state.addr[pmp_index].ea;
 -    if (pmp_sa >= tlb_sa && pmp_ea <= tlb_ea) {
 -        return pmp_ea - pmp_sa + 1;
 -    }
 -
 -    if (pmp_sa >= tlb_sa && pmp_sa <= tlb_ea && pmp_ea >= tlb_ea) {
 -        return tlb_ea - pmp_sa + 1;
 -    }
 -
 -    if (pmp_ea <= tlb_ea && pmp_ea >= tlb_sa && pmp_sa <= tlb_sa) {
 -        return pmp_ea - tlb_sa + 1;
 -    }
 -
 -    return 0;
 -}
 -
 -/*
 - * Check is there a PMP entry which range covers this page. If so,
 - * try to find the minimum granularity for the TLB size.
 - */
 -bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
 -                         target_ulong *tlb_size)
 -{
 -    int i;
 -    target_ulong val;
 -    target_ulong tlb_ea = (tlb_sa + TARGET_PAGE_SIZE - 1);
 -
 -    for (i = 0; i < MAX_RISCV_PMPS; i++) {
 -        val = pmp_get_tlb_size(env, i, tlb_sa, tlb_ea);
 -        if (val) {
 -            if (*tlb_size == 0 || *tlb_size > val) {
 -                *tlb_size = val;
 -            }
 -        }
 -    }
 -
 -    if (*tlb_size != 0) {
 +    if (pmp_sa <= tlb_sa && pmp_ea >= tlb_ea) {
 +        return TARGET_PAGE_SIZE;
 +    } else {
          /*
 -         * At this point we have a tlb_size that is the smallest possible size
 -         * That fits within a TARGET_PAGE_SIZE and the PMP region.
 -         *
 -         * If the size is less then TARGET_PAGE_SIZE we drop the size to 1.
 -         * This means the result isn't cached in the TLB and is only used for
 -         * a single translation.
 -         */
 -        if (*tlb_size < TARGET_PAGE_SIZE) {
 -            *tlb_size = 1;
 -        }
 -
 -        return true;
 +        * At this point we have a tlb_size that is the smallest possible size
 +        * That fits within a TARGET_PAGE_SIZE and the PMP region.
 +        *
 +        * If the size is less then TARGET_PAGE_SIZE we drop the size to 1.
 +        * This means the result isn't cached in the TLB and is only used for
 +        * a single translation.
 +        */
 +        return 1;
      }
 -
 -    return false;
  }
  /*
 --
-.45.1
+.38.1

-New patch
+[PULL v2 02/45] hw/registerfields: add `FIELDx_1CLEAR()` macro
+From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+Adds a helper macro that implements the register `w1c`
+functionality.
+Ex:
+  uint32_t data = FIELD32_1CLEAR(val, REG, FIELD);
+If ANY bits of the specified `FIELD` is set
+then the respective field is cleared and returned to `data`.
+If the field is cleared (0), then no change and
+val is returned.
+Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <20221017054950.317584-2-wilfred.mallawa@opensource.wdc.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ include/hw/registerfields.h | 22 ++++++++++++++++++++++
+file changed, 22 insertions(+)
+diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/registerfields.h
++++ b/include/hw/registerfields.h
+@@ -XXX,XX +XXX,XX @@
+                   R_ ## reg ## _ ## field ## _LENGTH, _v.v);              \
+     _d; })
++/*
++ * Clear the specified field in storage if
++ * any field bits are set, else no changes made. Implements
++ * single/multi-bit `w1c`
++ *
++ */
++#define FIELD8_1CLEAR(storage, reg, field)                                \
++    (FIELD_EX8(storage, reg, field) ?                                     \
++    FIELD_DP8(storage, reg, field, 0x00) : storage)
++
++#define FIELD16_1CLEAR(storage, reg, field)                               \
++    (FIELD_EX16(storage, reg, field) ?                                    \
++    FIELD_DP16(storage, reg, field, 0x00) : storage)
++
++#define FIELD32_1CLEAR(storage, reg, field)                               \
++    (FIELD_EX32(storage, reg, field) ?                                    \
++    FIELD_DP32(storage, reg, field, 0x00) : storage)
++
++#define FIELD64_1CLEAR(storage, reg, field)                               \
++    (FIELD_EX64(storage, reg, field) ?                                    \
++    FIELD_DP64(storage, reg, field, 0x00) : storage)
++
+ #define FIELD_SDP8(storage, reg, field, val) ({                           \
+     struct {                                                              \
+         signed int v:R_ ## reg ## _ ## field ## _LENGTH;                  \
+--
+.38.1

-New patch
+[PULL v2 03/45] hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro
+From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+use the `FIELD32_1CLEAR` macro to implement register
+`rw1c` functionality to `ibex_spi`.
+This change was tested by running the `SPI_HOST` from TockOS.
+Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <20221017054950.317584-3-wilfred.mallawa@opensource.wdc.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/ssi/ibex_spi_host.c | 21 +++++++++------------
+file changed, 9 insertions(+), 12 deletions(-)
+diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/ssi/ibex_spi_host.c
++++ b/hw/ssi/ibex_spi_host.c
+@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
+ {
+     IbexSPIHostState *s = opaque;
+     uint32_t val32 = val64;
+-    uint32_t shift_mask = 0xff, status = 0, data = 0;
++    uint32_t shift_mask = 0xff, status = 0;
+     uint8_t txqd_len;
+     trace_ibex_spi_host_write(addr, size, val64);
+@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
+     case IBEX_SPI_HOST_INTR_STATE:
+         /* rw1c status register */
+         if (FIELD_EX32(val32, INTR_STATE, ERROR)) {
+-            data = FIELD_DP32(data, INTR_STATE, ERROR, 0);
++            s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], INTR_STATE, ERROR);
+         }
+         if (FIELD_EX32(val32, INTR_STATE, SPI_EVENT)) {
+-            data = FIELD_DP32(data, INTR_STATE, SPI_EVENT, 0);
++            s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], INTR_STATE, SPI_EVENT);
+         }
+-        s->regs[addr] = data;
+         break;
+     case IBEX_SPI_HOST_INTR_ENABLE:
+         s->regs[addr] = val32;
+@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
+      *  When an error occurs, the corresponding bit must be cleared
+      *  here before issuing any further commands
+      */
+-        status = s->regs[addr];
+         /* rw1c status register */
+         if (FIELD_EX32(val32, ERROR_STATUS, CMDBUSY)) {
+-            status = FIELD_DP32(status, ERROR_STATUS, CMDBUSY, 0);
++            s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, CMDBUSY);
+         }
+         if (FIELD_EX32(val32, ERROR_STATUS, OVERFLOW)) {
+-            status = FIELD_DP32(status, ERROR_STATUS, OVERFLOW, 0);
++            s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, OVERFLOW);
+         }
+         if (FIELD_EX32(val32, ERROR_STATUS, UNDERFLOW)) {
+-            status = FIELD_DP32(status, ERROR_STATUS, UNDERFLOW, 0);
++            s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, UNDERFLOW);
+         }
+         if (FIELD_EX32(val32, ERROR_STATUS, CMDINVAL)) {
+-            status = FIELD_DP32(status, ERROR_STATUS, CMDINVAL, 0);
++            s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, CMDINVAL);
+         }
+         if (FIELD_EX32(val32, ERROR_STATUS, CSIDINVAL)) {
+-            status = FIELD_DP32(status, ERROR_STATUS, CSIDINVAL, 0);
++            s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, CSIDINVAL);
+         }
+         if (FIELD_EX32(val32, ERROR_STATUS, ACCESSINVAL)) {
+-            status = FIELD_DP32(status, ERROR_STATUS, ACCESSINVAL, 0);
++            s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, ACCESSINVAL);
+         }
+-        s->regs[addr] = status;
+         break;
+     case IBEX_SPI_HOST_EVENT_ENABLE:
+     /* Controls which classes of SPI events raise an interrupt. */
+--
+.38.1

-New patch
+[PULL v2 04/45] tcg/riscv: Fix range matched by TCG_CT_CONST_M12
+From: Richard Henderson <richard.henderson@linaro.org>
+We were matching a signed 13-bit range, not a 12-bit range.
+Expand the commentary within the function and be explicit
+about all of the ranges.
+Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <20221022095821.2441874-1-richard.henderson@linaro.org>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ tcg/riscv/tcg-target.c.inc | 19 ++++++++++++++++---
+file changed, 16 insertions(+), 3 deletions(-)
+diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/riscv/tcg-target.c.inc
++++ b/tcg/riscv/tcg-target.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
+     if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
+         return 1;
+     }
+-    if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
++    /*
++     * Sign extended from 12 bits: [-0x800, 0x7ff].
++     * Used for most arithmetic, as this is the isa field.
++     */
++    if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) {
+         return 1;
+     }
+-    if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) {
++    /*
++     * Sign extended from 12 bits, negated: [-0x7ff, 0x800].
++     * Used for subtraction, where a constant must be handled by ADDI.
++     */
++    if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) {
+         return 1;
+     }
+-    if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) {
++    /*
++     * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff].
++     * Used by addsub2, which may need the negative operation,
++     * and requires the modified constant to be representable.
++     */
++    if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) {
+         return 1;
+     }
+     return 0;
+--
+.38.1

-New patch
+[PULL v2 05/45] tcg/riscv: Fix reg overlap case in tcg_out_addsub2
+From: Richard Henderson <richard.henderson@linaro.org>
+There was a typo using opc_addi instead of opc_add with the
+two registers.  While we're at it, simplify the gating test
+to al == bl to improve dynamic scheduling even when the
+output register does not overlap the inputs.
+Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <20221020233836.2341671-1-richard.henderson@linaro.org>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ tcg/riscv/tcg-target.c.inc | 10 ++++++++--
+file changed, 8 insertions(+), 2 deletions(-)
+diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/riscv/tcg-target.c.inc
++++ b/tcg/riscv/tcg-target.c.inc
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_addsub2(TCGContext *s,
+         if (cbl) {
+             tcg_out_opc_imm(s, opc_addi, rl, al, bl);
+             tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl);
+-        } else if (rl == al && rl == bl) {
++        } else if (al == bl) {
++            /*
++             * If the input regs overlap, this is a simple doubling
++             * and carry-out is the input msb.  This special case is
++             * required when the output reg overlaps the input,
++             * but we might as well use it always.
++             */
+             tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0);
+-            tcg_out_opc_reg(s, opc_addi, rl, al, bl);
++            tcg_out_opc_reg(s, opc_add, rl, al, al);
+         } else {
+             tcg_out_opc_reg(s, opc_add, rl, al, bl);
+             tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0,
+--
+.38.1

-[PULL 24/28] target/riscv: rvzicbo: Fixup CBO extension register calculation
+[PULL v2 06/45] tcg/riscv: Fix base register for user-only qemu_ld/st
-From: Alistair Francis <alistair23@gmail.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-When running the instruction
+When guest_base != 0, we were not coordinating the usage of
 TCG_REG_TMP0 as base properly, leading to a previous zero-extend
 of the input address being discarded.
-```
+Shuffle the alignment check to the front, because that does not
-    cbo.flush 0(x0)
+depend on the zero-extend, and it keeps the register usage clear.
-```
+Set base after each step of the address arithmetic instead of before.
-QEMU would segfault.
+Return the base register used from tcg_out_tlb_load, so as to
 keep that register choice localized to that function.
-The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
+Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-allocated.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-In order to fix this let's use the existing get_address()
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-helper. This also has the benefit of performing pointer mask
+Message-Id: <20221023233337.2846860-1-richard.henderson@linaro.org>
 calculations on the address specified in rs1.
 The pointer masking specificiation specifically states:
 """
 Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
 """
 So this is the correct behaviour and we previously have been incorrectly
 not masking the address.
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
 Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
+ tcg/riscv/tcg-target.c.inc | 39 +++++++++++++++++++++-----------------
-file changed, 12 insertions(+), 4 deletions(-)
+file changed, 22 insertions(+), 17 deletions(-)
-diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
+diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
+--- a/tcg/riscv/tcg-target.c.inc
-+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
++++ b/tcg/riscv/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target)
- static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
+     tcg_debug_assert(ok);
  }
 -static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
 -                             TCGReg addrh, MemOpIdx oi,
 -                             tcg_insn_unit **label_ptr, bool is_load)
 +static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
 +                               TCGReg addrh, MemOpIdx oi,
 +                               tcg_insn_unit **label_ptr, bool is_load)
  {
-     REQUIRE_ZICBOM(ctx);
+     MemOp opc = get_memop(oi);
--    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+     unsigned s_bits = opc & MO_SIZE;
-+    TCGv src = get_address(ctx, a->rs1, 0);
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
-+
+         addrl = TCG_REG_TMP0;
-+    gen_helper_cbo_clean_flush(tcg_env, src);
+     }
-     return true;
+     tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl);
 +    return TCG_REG_TMP0;
  }
- static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
+ static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi,
- {
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
-     REQUIRE_ZICBOM(ctx);
+ #else
--    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+     unsigned a_bits;
-+    TCGv src = get_address(ctx, a->rs1, 0);
+ #endif
-+
+-    TCGReg base = TCG_REG_TMP0;
-+    gen_helper_cbo_clean_flush(tcg_env, src);
++    TCGReg base;
-     return true;
- }
+     data_regl = *args++;
+     data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
- static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
- {
+     opc = get_memop(oi);
-     REQUIRE_ZICBOM(ctx);
--    gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
+ #if defined(CONFIG_SOFTMMU)
-+    TCGv src = get_address(ctx, a->rs1, 0);
+-    tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1);
-+
++    base = tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1);
-+    gen_helper_cbo_inval(tcg_env, src);
+     tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
-     return true;
+     add_qemu_ldst_label(s, 1, oi,
- }
+                         (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
+                         data_regl, data_regh, addr_regl, addr_regh,
- static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
+                         s->code_ptr, label_ptr);
- {
+ #else
-     REQUIRE_ZICBOZ(ctx);
+-    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
--    gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
+-        tcg_out_ext32u(s, base, addr_regl);
-+    TCGv src = get_address(ctx, a->rs1, 0);
+-        addr_regl = base;
-+
+-    }
-+    gen_helper_cbo_zero(tcg_env, src);
+     a_bits = get_alignment_bits(opc);
-     return true;
+     if (a_bits) {
- }
+         tcg_out_test_alignment(s, true, addr_regl, a_bits);
      }
 +    base = addr_regl;
 +    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
 +        tcg_out_ext32u(s, TCG_REG_TMP0, base);
 +        base = TCG_REG_TMP0;
 +    }
      if (guest_base != 0) {
 -        tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
 +        tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base);
 +        base = TCG_REG_TMP0;
      }
      tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
  #endif
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
  #else
      unsigned a_bits;
  #endif
 -    TCGReg base = TCG_REG_TMP0;
 +    TCGReg base;
      data_regl = *args++;
      data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
      opc = get_memop(oi);
  #if defined(CONFIG_SOFTMMU)
 -    tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0);
 +    base = tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0);
      tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
      add_qemu_ldst_label(s, 0, oi,
                          (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
                          data_regl, data_regh, addr_regl, addr_regh,
                          s->code_ptr, label_ptr);
  #else
 -    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
 -        tcg_out_ext32u(s, base, addr_regl);
 -        addr_regl = base;
 -    }
      a_bits = get_alignment_bits(opc);
      if (a_bits) {
          tcg_out_test_alignment(s, false, addr_regl, a_bits);
      }
 +    base = addr_regl;
 +    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
 +        tcg_out_ext32u(s, TCG_REG_TMP0, base);
 +        base = TCG_REG_TMP0;
 +    }
      if (guest_base != 0) {
 -        tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
 +        tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base);
 +        base = TCG_REG_TMP0;
      }
      tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
  #endif
 --
-.45.1
+.38.1

-New patch
+[PULL v2 07/45] hw/riscv/opentitan: bump opentitan
+From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+This patch updates the OpenTitan model to match
+the specified register layout as per [1]. Which is also the latest
+commit of OpenTitan supported by TockOS.
+Note: Pinmux and Padctrl has been merged into Pinmux [2][3], this patch removes
+any references to Padctrl. Note: OpenTitan doc [2] has not yet specified
+much detail regarding this, except for a note that states `TODO: this
+section needs to be updated to reflect the pinmux/padctrl merger`
+[1] https://github.com/lowRISC/opentitan/blob/d072ac505f82152678d6e04be95c72b728a347b8/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
+[2] https://docs.opentitan.org/hw/top_earlgrey/doc/design/
+[3] https://docs.opentitan.org/hw/ip/pinmux/doc/#overview
+Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-Id: <20221025043335.339815-2-wilfred.mallawa@opensource.wdc.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ include/hw/riscv/opentitan.h |  9 ++++-----
+ hw/riscv/opentitan.c         | 21 +++++++++++++--------
+files changed, 17 insertions(+), 13 deletions(-)
+diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/riscv/opentitan.h
++++ b/include/hw/riscv/opentitan.h
+@@ -XXX,XX +XXX,XX @@ enum {
+     IBEX_DEV_RSTMGR,
+     IBEX_DEV_CLKMGR,
+     IBEX_DEV_PINMUX,
+-    IBEX_DEV_PADCTRL,
+     IBEX_DEV_USBDEV,
+     IBEX_DEV_FLASH_CTRL,
+     IBEX_DEV_PLIC,
+@@ -XXX,XX +XXX,XX @@ enum {
+     IBEX_UART0_RX_TIMEOUT_IRQ     = 7,
+     IBEX_UART0_RX_PARITY_ERR_IRQ  = 8,
+     IBEX_TIMER_TIMEREXPIRED0_0    = 127,
+-    IBEX_SPI_HOST0_ERR_IRQ        = 151,
+-    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 152,
+-    IBEX_SPI_HOST1_ERR_IRQ        = 153,
+-    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 154,
++    IBEX_SPI_HOST0_ERR_IRQ        = 134,
++    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 135,
++    IBEX_SPI_HOST1_ERR_IRQ        = 136,
++    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 137,
+ };
+ #endif
+diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/opentitan.c
++++ b/hw/riscv/opentitan.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/units.h"
+ #include "sysemu/sysemu.h"
++/*
++ * This version of the OpenTitan machine currently supports
++ * OpenTitan RTL version:
++ * <lowRISC/opentitan@d072ac505f82152678d6e04be95c72b728a347b8>
++ *
++ * MMIO mapping as per (specified commit):
++ * lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
++ */
+ static const MemMapEntry ibex_memmap[] = {
+-    [IBEX_DEV_ROM] =            {  0x00008000,   0x8000 },
++    [IBEX_DEV_ROM] =            {  0x00008000,  0x8000 },
+     [IBEX_DEV_RAM] =            {  0x10000000,  0x20000 },
+     [IBEX_DEV_FLASH] =          {  0x20000000,  0x100000 },
+     [IBEX_DEV_UART] =           {  0x40000000,  0x1000  },
+@@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = {
+     [IBEX_DEV_I2C] =            {  0x40080000,  0x1000  },
+     [IBEX_DEV_PATTGEN] =        {  0x400e0000,  0x1000  },
+     [IBEX_DEV_TIMER] =          {  0x40100000,  0x1000  },
+-    [IBEX_DEV_SENSOR_CTRL] =    {  0x40110000,  0x1000  },
+     [IBEX_DEV_OTP_CTRL] =       {  0x40130000,  0x4000  },
+     [IBEX_DEV_LC_CTRL] =        {  0x40140000,  0x1000  },
+-    [IBEX_DEV_USBDEV] =         {  0x40150000,  0x1000  },
++    [IBEX_DEV_ALERT_HANDLER] =  {  0x40150000,  0x1000  },
+     [IBEX_DEV_SPI_HOST0] =      {  0x40300000,  0x1000  },
+     [IBEX_DEV_SPI_HOST1] =      {  0x40310000,  0x1000  },
++    [IBEX_DEV_USBDEV] =         {  0x40320000,  0x1000  },
+     [IBEX_DEV_PWRMGR] =         {  0x40400000,  0x1000  },
+     [IBEX_DEV_RSTMGR] =         {  0x40410000,  0x1000  },
+     [IBEX_DEV_CLKMGR] =         {  0x40420000,  0x1000  },
+     [IBEX_DEV_PINMUX] =         {  0x40460000,  0x1000  },
+-    [IBEX_DEV_PADCTRL] =        {  0x40470000,  0x1000  },
++    [IBEX_DEV_SENSOR_CTRL] =    {  0x40490000,  0x1000  },
+     [IBEX_DEV_FLASH_CTRL] =     {  0x41000000,  0x1000  },
+     [IBEX_DEV_AES] =            {  0x41100000,  0x1000  },
+     [IBEX_DEV_HMAC] =           {  0x41110000,  0x1000  },
+@@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = {
+     [IBEX_DEV_ENTROPY] =        {  0x41160000,  0x1000  },
+     [IBEX_DEV_EDNO] =           {  0x41170000,  0x1000  },
+     [IBEX_DEV_EDN1] =           {  0x41180000,  0x1000  },
+-    [IBEX_DEV_ALERT_HANDLER] =  {  0x411b0000,  0x1000  },
+     [IBEX_DEV_NMI_GEN] =        {  0x411c0000,  0x1000  },
+     [IBEX_DEV_PERI] =           {  0x411f0000,  0x10000 },
+-    [IBEX_DEV_PLIC] =           {  0x48000000,  0x4005000  },
++    [IBEX_DEV_PLIC] =           {  0x48000000,  0x4005000 },
+     [IBEX_DEV_FLASH_VIRTUAL] =  {  0x80000000,  0x80000 },
+ };
+@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
+         memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
+     create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
+         memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
+-    create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
+-        memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size);
+     create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
+         memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
+     create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
+--
+.38.1

-New patch
+[PULL v2 08/45] hw/riscv/opentitan: add aon_timer base unimpl
+From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+Adds the updated `aon_timer` base as an unimplemented device. This is
+used by TockOS, patch ensures the guest doesn't hit load faults.
+Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <20221025043335.339815-3-wilfred.mallawa@opensource.wdc.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ include/hw/riscv/opentitan.h | 1 +
+ hw/riscv/opentitan.c         | 3 +++
+files changed, 4 insertions(+)
+diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/riscv/opentitan.h
++++ b/include/hw/riscv/opentitan.h
+@@ -XXX,XX +XXX,XX @@ enum {
+     IBEX_DEV_RSTMGR,
+     IBEX_DEV_CLKMGR,
+     IBEX_DEV_PINMUX,
++    IBEX_DEV_AON_TIMER,
+     IBEX_DEV_USBDEV,
+     IBEX_DEV_FLASH_CTRL,
+     IBEX_DEV_PLIC,
+diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/opentitan.c
++++ b/hw/riscv/opentitan.c
+@@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = {
+     [IBEX_DEV_RSTMGR] =         {  0x40410000,  0x1000  },
+     [IBEX_DEV_CLKMGR] =         {  0x40420000,  0x1000  },
+     [IBEX_DEV_PINMUX] =         {  0x40460000,  0x1000  },
++    [IBEX_DEV_AON_TIMER] =      {  0x40470000,  0x1000  },
+     [IBEX_DEV_SENSOR_CTRL] =    {  0x40490000,  0x1000  },
+     [IBEX_DEV_FLASH_CTRL] =     {  0x41000000,  0x1000  },
+     [IBEX_DEV_AES] =            {  0x41100000,  0x1000  },
+@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
+         memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
+     create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
+         memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
++    create_unimplemented_device("riscv.lowrisc.ibex.aon_timer",
++        memmap[IBEX_DEV_AON_TIMER].base, memmap[IBEX_DEV_AON_TIMER].size);
+     create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
+         memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
+     create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
+--
+.38.1

-[PULL 02/28] target/riscv/kvm: Fix exposure of Zkr
+[PULL v2 09/45] target/riscv: Add smstateen support
-From: Andrew Jones <ajones@ventanamicro.com>
+From: Mayuresh Chitale <mchitale@ventanamicro.com>
-The Zkr extension may only be exposed to KVM guests if the VMM
+Smstateen extension specifies a mechanism to close
-implements the SEED CSR. Use the same implementation as TCG.
+the potential covert channels that could cause security issues.
-Without this patch, running with a KVM which does not forward the
+This patch adds the CSRs defined in the specification and
-SEED CSR access to QEMU will result in an ILL exception being
+the corresponding predicates and read/write functions.
 injected into the guest (this results in Linux guests crashing on
 boot). And, when running with a KVM which does forward the access,
 QEMU will crash, since QEMU doesn't know what to do with the exit.
-Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
+Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
-Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-Id: <20221016124726.102129-2-mchitale@ventanamicro.com>
 Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h         |  3 +++
+ target/riscv/cpu.h      |   4 +
- target/riscv/csr.c         | 18 ++++++++++++++----
+ target/riscv/cpu_bits.h |  37 +++++
- target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
+ target/riscv/csr.c      | 316 ++++++++++++++++++++++++++++++++++++++++
-files changed, 42 insertions(+), 4 deletions(-)
+ target/riscv/machine.c  |  21 +++
 files changed, 378 insertions(+)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
+@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
- void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
+     /* CSRs for execution enviornment configuration */
+     uint64_t menvcfg;
-+target_ulong riscv_new_csr_seed(target_ulong new_value,
++    uint64_t mstateen[SMSTATEEN_MAX_COUNT];
-+                                target_ulong write_mask);
++    uint64_t hstateen[SMSTATEEN_MAX_COUNT];
-+
++    uint64_t sstateen[SMSTATEEN_MAX_COUNT];
- uint8_t satp_mode_max_from_map(uint32_t map);
+     target_ulong senvcfg;
- const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
+     uint64_t henvcfg;
+ #endif
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
      bool ext_ifencei;
      bool ext_icsr;
      bool ext_zihintpause;
 +    bool ext_smstateen;
      bool ext_sstc;
      bool ext_svinval;
      bool ext_svnapot;
 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_bits.h
 +++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
  /* Supervisor Configuration CSRs */
  #define CSR_SENVCFG         0x10A
 +/* Supervisor state CSRs */
 +#define CSR_SSTATEEN0       0x10C
 +#define CSR_SSTATEEN1       0x10D
 +#define CSR_SSTATEEN2       0x10E
 +#define CSR_SSTATEEN3       0x10F
 +
  /* Supervisor Trap Handling */
  #define CSR_SSCRATCH        0x140
  #define CSR_SEPC            0x141
@@ -XXX,XX +XXX,XX @@
  #define CSR_HENVCFG         0x60A
  #define CSR_HENVCFGH        0x61A
 +/* Hypervisor state CSRs */
 +#define CSR_HSTATEEN0       0x60C
 +#define CSR_HSTATEEN0H      0x61C
 +#define CSR_HSTATEEN1       0x60D
 +#define CSR_HSTATEEN1H      0x61D
 +#define CSR_HSTATEEN2       0x60E
 +#define CSR_HSTATEEN2H      0x61E
 +#define CSR_HSTATEEN3       0x60F
 +#define CSR_HSTATEEN3H      0x61F
 +
  /* Virtual CSRs */
  #define CSR_VSSTATUS        0x200
  #define CSR_VSIE            0x204
@@ -XXX,XX +XXX,XX @@
  #define CSR_MENVCFG         0x30A
  #define CSR_MENVCFGH        0x31A
 +/* Machine state CSRs */
 +#define CSR_MSTATEEN0       0x30C
 +#define CSR_MSTATEEN0H      0x31C
 +#define CSR_MSTATEEN1       0x30D
 +#define CSR_MSTATEEN1H      0x31D
 +#define CSR_MSTATEEN2       0x30E
 +#define CSR_MSTATEEN2H      0x31E
 +#define CSR_MSTATEEN3       0x30F
 +#define CSR_MSTATEEN3H      0x31F
 +
 +/* Common defines for all smstateen */
 +#define SMSTATEEN_MAX_COUNT 4
 +#define SMSTATEEN0_CS       (1ULL << 0)
 +#define SMSTATEEN0_FCSR     (1ULL << 1)
 +#define SMSTATEEN0_HSCONTXT (1ULL << 57)
 +#define SMSTATEEN0_IMSIC    (1ULL << 58)
 +#define SMSTATEEN0_AIA      (1ULL << 59)
 +#define SMSTATEEN0_SVSLCT   (1ULL << 60)
 +#define SMSTATEEN0_HSENVCFG (1ULL << 62)
 +#define SMSTATEEN_STATEEN   (1ULL << 63)
 +
  /* Enhanced Physical Memory Protection (ePMP) */
  #define CSR_MSECCFG         0x747
  #define CSR_MSECCFGH        0x757
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
+@@ -XXX,XX +XXX,XX @@ static RISCVException umode32(CPURISCVState *env, int csrno)
- #endif
+     return umode(env, csrno);
+ }
- /* Crypto Extension */
--static RISCVException rmw_seed(CPURISCVState *env, int csrno,
++static RISCVException mstateen(CPURISCVState *env, int csrno)
--                               target_ulong *ret_value,
++{
--                               target_ulong new_value,
++    CPUState *cs = env_cpu(env);
--                               target_ulong write_mask)
++    RISCVCPU *cpu = RISCV_CPU(cs);
-+target_ulong riscv_new_csr_seed(target_ulong new_value,
++
-+                                target_ulong write_mask)
++    if (!cpu->cfg.ext_smstateen) {
 +        return RISCV_EXCP_ILLEGAL_INST;
 +    }
 +
 +    return any(env, csrno);
 +}
 +
 +static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
 +{
 +    CPUState *cs = env_cpu(env);
 +    RISCVCPU *cpu = RISCV_CPU(cs);
 +
 +    if (!cpu->cfg.ext_smstateen) {
 +        return RISCV_EXCP_ILLEGAL_INST;
 +    }
 +
 +    if (env->priv < PRV_M) {
 +        if (!(env->mstateen[csrno - base] & SMSTATEEN_STATEEN)) {
 +            return RISCV_EXCP_ILLEGAL_INST;
 +        }
 +    }
 +
 +    return hmode(env, csrno);
 +}
 +
 +static RISCVException hstateen(CPURISCVState *env, int csrno)
 +{
 +    return hstateen_pred(env, csrno, CSR_HSTATEEN0);
 +}
 +
 +static RISCVException hstateenh(CPURISCVState *env, int csrno)
 +{
 +    return hstateen_pred(env, csrno, CSR_HSTATEEN0H);
 +}
 +
 +static RISCVException sstateen(CPURISCVState *env, int csrno)
 +{
 +    bool virt = riscv_cpu_virt_enabled(env);
 +    int index = csrno - CSR_SSTATEEN0;
 +    CPUState *cs = env_cpu(env);
 +    RISCVCPU *cpu = RISCV_CPU(cs);
 +
 +    if (!cpu->cfg.ext_smstateen) {
 +        return RISCV_EXCP_ILLEGAL_INST;
 +    }
 +
 +    if (env->priv < PRV_M) {
 +        if (!(env->mstateen[index] & SMSTATEEN_STATEEN)) {
 +            return RISCV_EXCP_ILLEGAL_INST;
 +        }
 +
 +        if (virt) {
 +            if (!(env->hstateen[index] & SMSTATEEN_STATEEN)) {
 +                return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 +            }
 +        }
 +    }
 +
 +    return smode(env, csrno);
 +}
 +
  /* Checks if PointerMasking registers could be accessed */
  static RISCVException pointer_masking(CPURISCVState *env, int csrno)
  {
-     uint16_t random_v;
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
-     Error *random_e = NULL;
+     return RISCV_EXCP_NONE;
-@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+ }
-         rval = random_v | SEED_OPST_ES16;
 +static RISCVException read_mstateen(CPURISCVState *env, int csrno,
 +                                    target_ulong *val)
 +{
 +    *val = env->mstateen[csrno - CSR_MSTATEEN0];
 +
 +    return RISCV_EXCP_NONE;
 +}
 +
 +static RISCVException write_mstateen(CPURISCVState *env, int csrno,
 +                                     uint64_t wr_mask, target_ulong new_val)
 +{
 +    uint64_t *reg;
 +
 +    reg = &env->mstateen[csrno - CSR_MSTATEEN0];
 +    *reg = (*reg & ~wr_mask) | (new_val & wr_mask);
 +
 +    return RISCV_EXCP_NONE;
 +}
 +
 +static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
 +                                      target_ulong new_val)
 +{
 +    uint64_t wr_mask = SMSTATEEN_STATEEN;
 +
 +    return write_mstateen(env, csrno, wr_mask, new_val);
 +}
 +
 +static RISCVException write_mstateen_1_3(CPURISCVState *env, int csrno,
 +                                      target_ulong new_val)
 +{
 +    return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
 +}
 +
 +static RISCVException read_mstateenh(CPURISCVState *env, int csrno,
 +                                      target_ulong *val)
 +{
 +    *val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32;
 +
 +    return RISCV_EXCP_NONE;
 +}
 +
 +static RISCVException write_mstateenh(CPURISCVState *env, int csrno,
 +                                      uint64_t wr_mask, target_ulong new_val)
 +{
 +    uint64_t *reg, val;
 +
 +    reg = &env->mstateen[csrno - CSR_MSTATEEN0H];
 +    val = (uint64_t)new_val << 32;
 +    val |= *reg & 0xFFFFFFFF;
 +    *reg = (*reg & ~wr_mask) | (val & wr_mask);
 +
 +    return RISCV_EXCP_NONE;
 +}
 +
 +static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
 +                                      target_ulong new_val)
 +{
 +    uint64_t wr_mask = SMSTATEEN_STATEEN;
 +
 +    return write_mstateenh(env, csrno, wr_mask, new_val);
 +}
 +
 +static RISCVException write_mstateenh_1_3(CPURISCVState *env, int csrno,
 +                                      target_ulong new_val)
 +{
 +    return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
 +}
 +
 +static RISCVException read_hstateen(CPURISCVState *env, int csrno,
 +                                    target_ulong *val)
 +{
 +    int index = csrno - CSR_HSTATEEN0;
 +
 +    *val = env->hstateen[index] & env->mstateen[index];
 +
 +    return RISCV_EXCP_NONE;
 +}
 +
 +static RISCVException write_hstateen(CPURISCVState *env, int csrno,
 +                                     uint64_t mask, target_ulong new_val)
 +{
 +    int index = csrno - CSR_HSTATEEN0;
 +    uint64_t *reg, wr_mask;
 +
 +    reg = &env->hstateen[index];
 +    wr_mask = env->mstateen[index] & mask;
 +    *reg = (*reg & ~wr_mask) | (new_val & wr_mask);
 +
 +    return RISCV_EXCP_NONE;
 +}
 +
 +static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
 +                                      target_ulong new_val)
 +{
 +    uint64_t wr_mask = SMSTATEEN_STATEEN;
 +
 +    return write_hstateen(env, csrno, wr_mask, new_val);
 +}
 +
 +static RISCVException write_hstateen_1_3(CPURISCVState *env, int csrno,
 +                                      target_ulong new_val)
 +{
 +    return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
 +}
 +
 +static RISCVException read_hstateenh(CPURISCVState *env, int csrno,
 +                                     target_ulong *val)
 +{
 +    int index = csrno - CSR_HSTATEEN0H;
 +
 +    *val = (env->hstateen[index] >> 32) & (env->mstateen[index] >> 32);
 +
 +    return RISCV_EXCP_NONE;
 +}
 +
 +static RISCVException write_hstateenh(CPURISCVState *env, int csrno,
 +                                      uint64_t mask, target_ulong new_val)
 +{
 +    int index = csrno - CSR_HSTATEEN0H;
 +    uint64_t *reg, wr_mask, val;
 +
 +    reg = &env->hstateen[index];
 +    val = (uint64_t)new_val << 32;
 +    val |= *reg & 0xFFFFFFFF;
 +    wr_mask = env->mstateen[index] & mask;
 +    *reg = (*reg & ~wr_mask) | (val & wr_mask);
 +
 +    return RISCV_EXCP_NONE;
 +}
 +
 +static RISCVException write_hstateen0h(CPURISCVState *env, int csrno,
 +                                       target_ulong new_val)
 +{
 +    uint64_t wr_mask = SMSTATEEN_STATEEN;
 +
 +    return write_hstateenh(env, csrno, wr_mask, new_val);
 +}
 +
 +static RISCVException write_hstateenh_1_3(CPURISCVState *env, int csrno,
 +                                       target_ulong new_val)
 +{
 +    return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
 +}
 +
 +static RISCVException read_sstateen(CPURISCVState *env, int csrno,
 +                                    target_ulong *val)
 +{
 +    bool virt = riscv_cpu_virt_enabled(env);
 +    int index = csrno - CSR_SSTATEEN0;
 +
 +    *val = env->sstateen[index] & env->mstateen[index];
 +    if (virt) {
 +        *val &= env->hstateen[index];
 +    }
 +
 +    return RISCV_EXCP_NONE;
 +}
 +
 +static RISCVException write_sstateen(CPURISCVState *env, int csrno,
 +                                     uint64_t mask, target_ulong new_val)
 +{
 +    bool virt = riscv_cpu_virt_enabled(env);
 +    int index = csrno - CSR_SSTATEEN0;
 +    uint64_t wr_mask;
 +    uint64_t *reg;
 +
 +    wr_mask = env->mstateen[index] & mask;
 +    if (virt) {
 +        wr_mask &= env->hstateen[index];
 +    }
 +
 +    reg = &env->sstateen[index];
 +    *reg = (*reg & ~wr_mask) | (new_val & wr_mask);
 +
 +    return RISCV_EXCP_NONE;
 +}
 +
 +static RISCVException write_sstateen0(CPURISCVState *env, int csrno,
 +                                      target_ulong new_val)
 +{
 +    uint64_t wr_mask = SMSTATEEN_STATEEN;
 +
 +    return write_sstateen(env, csrno, wr_mask, new_val);
 +}
 +
 +static RISCVException write_sstateen_1_3(CPURISCVState *env, int csrno,
 +                                      target_ulong new_val)
 +{
 +    return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
 +}
 +
  static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
                                  uint64_t *ret_val,
                                  uint64_t new_val, uint64_t wr_mask)
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
      [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh,
                         .min_priv_ver = PRIV_VERSION_1_12_0              },
 +    /* Smstateen extension CSRs */
 +    [CSR_MSTATEEN0] = { "mstateen0", mstateen, read_mstateen, write_mstateen0,
 +                        .min_priv_ver = PRIV_VERSION_1_12_0 },
 +    [CSR_MSTATEEN0H] = { "mstateen0h", mstateen, read_mstateenh,
 +                          write_mstateen0h,
 +                         .min_priv_ver = PRIV_VERSION_1_12_0 },
 +    [CSR_MSTATEEN1] = { "mstateen1", mstateen, read_mstateen,
 +                        write_mstateen_1_3,
 +                        .min_priv_ver = PRIV_VERSION_1_12_0 },
 +    [CSR_MSTATEEN1H] = { "mstateen1h", mstateen, read_mstateenh,
 +                         write_mstateenh_1_3,
 +                         .min_priv_ver = PRIV_VERSION_1_12_0 },
 +    [CSR_MSTATEEN2] = { "mstateen2", mstateen, read_mstateen,
 +                        write_mstateen_1_3,
 +                        .min_priv_ver = PRIV_VERSION_1_12_0 },
 +    [CSR_MSTATEEN2H] = { "mstateen2h", mstateen, read_mstateenh,
 +                         write_mstateenh_1_3,
 +                         .min_priv_ver = PRIV_VERSION_1_12_0 },
 +    [CSR_MSTATEEN3] = { "mstateen3", mstateen, read_mstateen,
 +                        write_mstateen_1_3,
 +                        .min_priv_ver = PRIV_VERSION_1_12_0 },
 +    [CSR_MSTATEEN3H] = { "mstateen3h", mstateen, read_mstateenh,
 +                         write_mstateenh_1_3,
 +                         .min_priv_ver = PRIV_VERSION_1_12_0 },
 +    [CSR_HSTATEEN0] = { "hstateen0", hstateen, read_hstateen, write_hstateen0,
 +                        .min_priv_ver = PRIV_VERSION_1_12_0 },
 +    [CSR_HSTATEEN0H] = { "hstateen0h", hstateenh, read_hstateenh,
 +                         write_hstateen0h,
 +                         .min_priv_ver = PRIV_VERSION_1_12_0 },
 +    [CSR_HSTATEEN1] = { "hstateen1", hstateen, read_hstateen,
 +                        write_hstateen_1_3,
 +                        .min_priv_ver = PRIV_VERSION_1_12_0 },
 +    [CSR_HSTATEEN1H] = { "hstateen1h", hstateenh, read_hstateenh,
 +                         write_hstateenh_1_3,
 +                         .min_priv_ver = PRIV_VERSION_1_12_0 },
 +    [CSR_HSTATEEN2] = { "hstateen2", hstateen, read_hstateen,
 +                        write_hstateen_1_3,
 +                        .min_priv_ver = PRIV_VERSION_1_12_0 },
 +    [CSR_HSTATEEN2H] = { "hstateen2h", hstateenh, read_hstateenh,
 +                         write_hstateenh_1_3,
 +                         .min_priv_ver = PRIV_VERSION_1_12_0 },
 +    [CSR_HSTATEEN3] = { "hstateen3", hstateen, read_hstateen,
 +                        write_hstateen_1_3,
 +                        .min_priv_ver = PRIV_VERSION_1_12_0 },
 +    [CSR_HSTATEEN3H] = { "hstateen3h", hstateenh, read_hstateenh,
 +                         write_hstateenh_1_3,
 +                         .min_priv_ver = PRIV_VERSION_1_12_0 },
 +    [CSR_SSTATEEN0] = { "sstateen0", sstateen, read_sstateen, write_sstateen0,
 +                        .min_priv_ver = PRIV_VERSION_1_12_0 },
 +    [CSR_SSTATEEN1] = { "sstateen1", sstateen, read_sstateen,
 +                        write_sstateen_1_3,
 +                        .min_priv_ver = PRIV_VERSION_1_12_0 },
 +    [CSR_SSTATEEN2] = { "sstateen2", sstateen, read_sstateen,
 +                        write_sstateen_1_3,
 +                        .min_priv_ver = PRIV_VERSION_1_12_0 },
 +    [CSR_SSTATEEN3] = { "sstateen3", sstateen, read_sstateen,
 +                        write_sstateen_1_3,
 +                        .min_priv_ver = PRIV_VERSION_1_12_0 },
 +
      /* Supervisor Trap Setup */
      [CSR_SSTATUS]    = { "sstatus",    smode, read_sstatus,    write_sstatus,
                           NULL,                read_sstatus_i128               },
 diff --git a/target/riscv/machine.c b/target/riscv/machine.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/machine.c
 +++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static int riscv_cpu_post_load(void *opaque, int version_id)
      return 0;
  }
 +static bool smstateen_needed(void *opaque)
 +{
 +    RISCVCPU *cpu = opaque;
 +
 +    return cpu->cfg.ext_smstateen;
 +}
 +
 +static const VMStateDescription vmstate_smstateen = {
 +    .name = "cpu/smtateen",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .needed = smstateen_needed,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4),
 +        VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4),
 +        VMSTATE_UINT64_ARRAY(env.sstateen, RISCVCPU, 4),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
  static bool envcfg_needed(void *opaque)
  {
      RISCVCPU *cpu = opaque;
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
          &vmstate_kvmtimer,
          &vmstate_envcfg,
          &vmstate_debug,
 +        &vmstate_smstateen,
          NULL
      }
+ };
 +    return rval;
 +}
 +
 +static RISCVException rmw_seed(CPURISCVState *env, int csrno,
 +                               target_ulong *ret_value,
 +                               target_ulong new_value,
 +                               target_ulong write_mask)
 +{
 +    target_ulong rval;
 +
 +    rval = riscv_new_csr_seed(new_value, write_mask);
 +
      if (ret_value) {
          *ret_value = rval;
      }
 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm/kvm-cpu.c
 +++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
      return ret;
  }
 +static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
 +{
 +    target_ulong csr_num = run->riscv_csr.csr_num;
 +    target_ulong new_value = run->riscv_csr.new_value;
 +    target_ulong write_mask = run->riscv_csr.write_mask;
 +    int ret = 0;
 +
 +    switch (csr_num) {
 +    case CSR_SEED:
 +        run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
 +        break;
 +    default:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "%s: un-handled CSR EXIT for CSR %lx\n",
 +                      __func__, csr_num);
 +        ret = -1;
 +        break;
 +    }
 +
 +    return ret;
 +}
 +
  int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
  {
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
      case KVM_EXIT_RISCV_SBI:
          ret = kvm_riscv_handle_sbi(cs, run);
          break;
 +    case KVM_EXIT_RISCV_CSR:
 +        ret = kvm_riscv_handle_csr(cs, run);
 +        break;
      default:
          qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
                        __func__, run->exit_reason);
 --
-.45.1
+.38.1

-[PULL 28/28] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
+[PULL v2 10/45] target/riscv: smstateen check for h/s/envcfg
-From: Yu-Ming Chang <yumin686@andestech.com>
+From: Mayuresh Chitale <mchitale@ventanamicro.com>
-Both CSRRS and CSRRC always read the addressed CSR and cause any read side
+Accesses to henvcfg, henvcfgh and senvcfg are allowed only if the corresponding
-effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
+bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is
-holding a zero value other than x0, the instruction will still attempt to write
+generated.
 the unmodified value back to the CSR and will cause any attendant side effects.
-So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
+Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
-a register holding a zero value, an illegal instruction exception should be
+Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
 raised.
 Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
+Message-Id: <20221016124726.102129-3-mchitale@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h       |  4 ++++
+ target/riscv/csr.c | 87 ++++++++++++++++++++++++++++++++++++++++++----
- target/riscv/csr.c       | 51 ++++++++++++++++++++++++++++++++++++----
+file changed, 80 insertions(+), 7 deletions(-)
  target/riscv/op_helper.c |  6 ++---
 files changed, 53 insertions(+), 8 deletions(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
- void riscv_cpu_update_mask(CPURISCVState *env);
- bool riscv_cpu_is_32bit(RISCVCPU *cpu);
-+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
-+                          target_ulong *ret_value);
- RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
-                            target_ulong *ret_value,
-                            target_ulong new_value, target_ulong write_mask);
-@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
-                                           target_ulong new_value,
-                                           target_ulong write_mask);
-+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
-+                               Int128 *ret_value);
- RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
-                                 Int128 *ret_value,
-                                 Int128 new_value, Int128 write_mask);
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
+ }
- static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
-                                                int csrno,
+ /* Predicates */
--                                               bool write_mask)
++#if !defined(CONFIG_USER_ONLY)
-+                                               bool write)
++static RISCVException smstateen_acc_ok(CPURISCVState *env, int index,
 +                                       uint64_t bit)
 +{
 +    bool virt = riscv_cpu_virt_enabled(env);
 +    CPUState *cs = env_cpu(env);
 +    RISCVCPU *cpu = RISCV_CPU(cs);
 +
 +    if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) {
 +        return RISCV_EXCP_NONE;
 +    }
 +
 +    if (!(env->mstateen[index] & bit)) {
 +        return RISCV_EXCP_ILLEGAL_INST;
 +    }
 +
 +    if (virt) {
 +        if (!(env->hstateen[index] & bit)) {
 +            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 +        }
 +
 +        if (env->priv == PRV_U && !(env->sstateen[index] & bit)) {
 +            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 +        }
 +    }
 +
 +    if (env->priv == PRV_U && riscv_has_ext(env, RVS)) {
 +        if (!(env->sstateen[index] & bit)) {
 +            return RISCV_EXCP_ILLEGAL_INST;
 +        }
 +    }
 +
 +    return RISCV_EXCP_NONE;
 +}
 +#endif
 +
  static RISCVException fs(CPURISCVState *env, int csrno)
  {
-     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
+ #if !defined(CONFIG_USER_ONLY)
-     bool read_only = get_field(csrno, 0xC00) == 3;
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
-@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
+ static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
-     }
+                                  target_ulong *val)
+ {
-     /* read / write check */
++    RISCVException ret;
--    if (write_mask && read_only) {
++
-+    if (write && read_only) {
++    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
          return RISCV_EXCP_ILLEGAL_INST;
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
      return RISCV_EXCP_NONE;
  }
 +RISCVException riscv_csrr(CPURISCVState *env, int csrno,
 +                           target_ulong *ret_value)
 +{
 +    RISCVException ret = riscv_csrrw_check(env, csrno, false);
 +    if (ret != RISCV_EXCP_NONE) {
 +        return ret;
 +    }
 +
-+    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
+     *val = env->senvcfg;
 +}
 +
  RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                             target_ulong *ret_value,
                             target_ulong new_value, target_ulong write_mask)
  {
 -    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
 +    RISCVException ret = riscv_csrrw_check(env, csrno, true);
      if (ret != RISCV_EXCP_NONE) {
          return ret;
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
      return RISCV_EXCP_NONE;
  }
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
-+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                                   target_ulong val)
-+                               Int128 *ret_value)
+ {
-+{
+     uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE;
 +    RISCVException ret;
 -    env->senvcfg = (env->senvcfg & ~mask) | (val & mask);
 +    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
 +    if (ret != RISCV_EXCP_NONE) {
 +        return ret;
 +    }
 +    env->senvcfg = (env->senvcfg & ~mask) | (val & mask);
      return RISCV_EXCP_NONE;
  }
  static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
                                   target_ulong *val)
  {
 +    RISCVException ret;
 +
-+    ret = riscv_csrrw_check(env, csrno, false);
++    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
 +    if (ret != RISCV_EXCP_NONE) {
 +        return ret;
 +    }
 +
-+    if (csr_ops[csrno].read128) {
+     *val = env->henvcfg;
-+        return riscv_csrrw_do128(env, csrno, ret_value,
+     return RISCV_EXCP_NONE;
-+                                 int128_zero(), int128_zero());
+ }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
                                    target_ulong val)
  {
      uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE;
 +    RISCVException ret;
 +
 +    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
 +    if (ret != RISCV_EXCP_NONE) {
 +        return ret;
 +    }
      if (riscv_cpu_mxl(env) == MXL_RV64) {
          mask |= HENVCFG_PBMTE | HENVCFG_STCE;
@@ -XXX,XX +XXX,XX @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
  static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
                                   target_ulong *val)
  {
 +    RISCVException ret;
 +
 +    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
 +    if (ret != RISCV_EXCP_NONE) {
 +        return ret;
 +    }
 +
-+    /*
+     *val = env->henvcfg >> 32;
-+     * Fall back to 64-bit version for now, if the 128-bit alternative isn't
+     return RISCV_EXCP_NONE;
-+     * at all defined.
+ }
-+     * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
-+     * significant), for those, this fallback is correctly handling the
+ {
-+     * accesses
+     uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
-+     */
+     uint64_t valh = (uint64_t)val << 32;
-+    target_ulong old_value;
++    RISCVException ret;
-+    ret = riscv_csrrw_do64(env, csrno, &old_value,
-+                           (target_ulong)0,
+-    env->henvcfg = (env->henvcfg & ~mask) | (valh & mask);
-+                           (target_ulong)0);
++    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
-+    if (ret == RISCV_EXCP_NONE && ret_value) {
++    if (ret != RISCV_EXCP_NONE) {
-+        *ret_value = int128_make64(old_value);
++        return ret;
 +    }
-+    return ret;
-+}
++    env->henvcfg = (env->henvcfg & ~mask) | (valh & mask);
-+
+     return RISCV_EXCP_NONE;
- RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
+ }
-                                 Int128 *ret_value,
-                                 Int128 new_value, Int128 write_mask)
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstateen(CPURISCVState *env, int csrno,
  static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
                                        target_ulong new_val)
  {
-     RISCVException ret;
+-    uint64_t wr_mask = SMSTATEEN_STATEEN;
++    uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
--    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
-+    ret = riscv_csrrw_check(env, csrno, true);
+     return write_mstateen(env, csrno, wr_mask, new_val);
-     if (ret != RISCV_EXCP_NONE) {
+ }
-         return ret;
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstateenh(CPURISCVState *env, int csrno,
-     }
+ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
-diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
+                                       target_ulong new_val)
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/op_helper.c
 +++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
      }
      target_ulong val = 0;
 -    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
 +    RISCVException ret = riscv_csrr(env, csr, &val);
      if (ret != RISCV_EXCP_NONE) {
          riscv_raise_exception(env, ret, GETPC());
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
  target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
  {
-     Int128 rv = int128_zero();
+-    uint64_t wr_mask = SMSTATEEN_STATEEN;
--    RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
++    uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
--                                          int128_zero(),
--                                          int128_zero());
+     return write_mstateenh(env, csrno, wr_mask, new_val);
-+    RISCVException ret = riscv_csrr_i128(env, csr, &rv);
+ }
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_hstateen(CPURISCVState *env, int csrno,
-     if (ret != RISCV_EXCP_NONE) {
+ static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
-         riscv_raise_exception(env, ret, GETPC());
+                                       target_ulong new_val)
  {
 -    uint64_t wr_mask = SMSTATEEN_STATEEN;
 +    uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
      return write_hstateen(env, csrno, wr_mask, new_val);
  }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_hstateenh(CPURISCVState *env, int csrno,
  static RISCVException write_hstateen0h(CPURISCVState *env, int csrno,
                                         target_ulong new_val)
  {
 -    uint64_t wr_mask = SMSTATEEN_STATEEN;
 +    uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
      return write_hstateenh(env, csrno, wr_mask, new_val);
  }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_sstateen(CPURISCVState *env, int csrno,
  static RISCVException write_sstateen0(CPURISCVState *env, int csrno,
                                        target_ulong new_val)
  {
 -    uint64_t wr_mask = SMSTATEEN_STATEEN;
 +    uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
      return write_sstateen(env, csrno, wr_mask, new_val);
  }
 --
-.45.1
+.38.1

-[PULL 13/28] target/riscv: Fix the element agnostic function problem
+[PULL v2 11/45] target/riscv: generate virtual instruction exception
-From: Huang Tao <eric.huang@linux.alibaba.com>
+From: Mayuresh Chitale <mchitale@ventanamicro.com>
-In RVV and vcrypto instructions, the masked and tail elements are set to 1s
+This patch adds a mechanism to generate a virtual instruction
-using vext_set_elems_1s function if the vma/vta bit is set. It is the element
+instruction exception instead of an illegal instruction exception
-agnostic policy.
+during instruction decode when virt is enabled.
-However, this function can't deal the big endian situation. This patch fixes
+Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
-the problem by adding handling of such case.
+Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
+Message-Id: <20221016124726.102129-4-mchitale@ventanamicro.com>
 Suggested-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
+ target/riscv/translate.c | 8 +++++++-
-file changed, 22 insertions(+)
+file changed, 7 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/vector_internals.c
+--- a/target/riscv/translate.c
-+++ b/target/riscv/vector_internals.c
++++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
+@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
-     if (tot - cnt == 0) {
+        to reset this known value.  */
-         return ;
+     int frm;
-     }
+     RISCVMXL ol;
-+
++    bool virt_inst_excp;
-+    if (HOST_BIG_ENDIAN) {
+     bool virt_enabled;
-+        /*
+     const RISCVCPUConfig *cfg_ptr;
-+         * Deal the situation when the elements are insdie
+     bool hlsx;
-+         * only one uint64 block including setting the
+@@ -XXX,XX +XXX,XX @@ static void gen_exception_illegal(DisasContext *ctx)
-+         * masked-off element.
+ {
-+         */
+     tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
-+        if (((tot - 1) ^ cnt) < 8) {
+                    offsetof(CPURISCVState, bins));
-+            memset(base + H1(tot - 1), -1, tot - cnt);
+-    generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
-+            return;
++    if (ctx->virt_inst_excp) {
-+        }
++        generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
-+        /*
++    } else {
-+         * Otherwise, at least cross two uint64_t blocks.
++        generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
 +         * Set first unaligned block.
 +         */
 +        if (cnt % 8 != 0) {
 +            uint32_t j = ROUND_UP(cnt, 8);
 +            memset(base + H1(j - 1), -1, j - cnt);
 +            cnt = j;
 +        }
 +        /* Set other 64bit aligend blocks */
 +    }
-     memset(base + cnt, -1, tot - cnt);
  }
+ static void gen_exception_inst_addr_mis(DisasContext *ctx)
+@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
+         { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
+     };
++    ctx->virt_inst_excp = false;
+     /* Check for compressed insn */
+     if (insn_len(opcode) == 2) {
+         if (!has_ext(ctx, RVC)) {
 --
-.45.1
+.38.1

-[PULL 10/28] target/riscv: Add support for Zve32x extension
+[PULL v2 12/45] target/riscv: Add itrigger support when icount is not enabled
-From: Jason Chien <jason.chien@sifive.com>
+From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-Add support for Zve32x extension and replace some checks for Zve32f with
+When icount is not enabled, there is no API in QEMU that can get the
-Zve32x, since Zve32f depends on Zve32x.
+guest instruction number.
-Signed-off-by: Jason Chien <jason.chien@sifive.com>
+Translate the guest code in a way that each TB only has one instruction.
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
+After executing the instruction, decrease the count by 1 until it reaches 0
-Reviewed-by: Max Chou <max.chou@sifive.com>
+where the itrigger fires.
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
+Note that only when priviledge matches the itrigger configuration,
 the count will decrease.
 Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-Id: <20221013062946.7530-2-zhiwei_liu@linux.alibaba.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_cfg.h                  |  1 +
+ target/riscv/cpu.h                            |  2 +
- target/riscv/cpu.c                      |  2 ++
+ target/riscv/debug.h                          | 12 ++++
- target/riscv/cpu_helper.c               |  2 +-
+ target/riscv/helper.h                         |  2 +
- target/riscv/csr.c                      |  2 +-
+ target/riscv/cpu_helper.c                     |  6 ++
- target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
+ target/riscv/debug.c                          | 71 +++++++++++++++++++
- target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
+ target/riscv/translate.c                      | 33 ++++++++-
-files changed, 15 insertions(+), 12 deletions(-)
+ .../riscv/insn_trans/trans_privileged.c.inc   |  4 +-
+ target/riscv/insn_trans/trans_rvi.c.inc       |  8 +--
-diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
+ target/riscv/insn_trans/trans_rvv.c.inc       |  4 +-
-index XXXXXXX..XXXXXXX 100644
+files changed, 131 insertions(+), 11 deletions(-)
---- a/target/riscv/cpu_cfg.h
-+++ b/target/riscv/cpu_cfg.h
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+index XXXXXXX..XXXXXXX 100644
-     bool ext_zhinx;
+--- a/target/riscv/cpu.h
-     bool ext_zhinxmin;
++++ b/target/riscv/cpu.h
-     bool ext_zve32f;
+@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
-+    bool ext_zve32x;
+ FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
-     bool ext_zve64f;
+ FIELD(TB_FLAGS, VTA, 24, 1)
-     bool ext_zve64d;
+ FIELD(TB_FLAGS, VMA, 25, 1)
-     bool ext_zvbb;
++/* Native debug itrigger */
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
++FIELD(TB_FLAGS, ITRIGGER, 26, 1)
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
+ #ifdef TARGET_RISCV32
-+++ b/target/riscv/cpu.c
+ #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
-@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
+diff --git a/target/riscv/debug.h b/target/riscv/debug.h
-     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
+index XXXXXXX..XXXXXXX 100644
-     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
+--- a/target/riscv/debug.h
-     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
++++ b/target/riscv/debug.h
-+    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
+@@ -XXX,XX +XXX,XX @@ enum {
-     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
+     SIZE_NUM = 16
-     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
+ };
-     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
-@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
++/* itrigger filed masks */
-     MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
++#define ITRIGGER_ACTION       0x3f
-     MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
++#define ITRIGGER_U            BIT(6)
-     MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
++#define ITRIGGER_S            BIT(7)
-+    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
++#define ITRIGGER_PENDING      BIT(8)
-     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
++#define ITRIGGER_M            BIT(9)
-     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
++#define ITRIGGER_COUNT        (0x3fff << 10)
-     MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
++#define ITRIGGER_HIT          BIT(24)
 +#define ITRIGGER_VU           BIT(25)
 +#define ITRIGGER_VS           BIT(26)
 +
  bool tdata_available(CPURISCVState *env, int tdata_index);
  target_ulong tselect_csr_read(CPURISCVState *env);
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
  void riscv_trigger_init(CPURISCVState *env);
 +bool riscv_itrigger_enabled(CPURISCVState *env);
  #endif /* RISCV_DEBUG_H */
 diff --git a/target/riscv/helper.h b/target/riscv/helper.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/helper.h
 +++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(sret, tl, env)
  DEF_HELPER_1(mret, tl, env)
  DEF_HELPER_1(wfi, void, env)
  DEF_HELPER_1(tlb_flush, void, env)
 +/* Native Debug */
 +DEF_HELPER_1(itrigger_match, void, env)
  #endif
  /* Hypervisor functions */
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
+@@ -XXX,XX +XXX,XX @@
-     *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
+ #include "tcg/tcg-op.h"
-     *cs_base = 0;
+ #include "trace.h"
+ #include "semihosting/common-semi.h"
--    if (cpu->cfg.ext_zve32f) {
++#include "sysemu/cpu-timers.h"
-+    if (cpu->cfg.ext_zve32x) {
+ #include "cpu_bits.h"
-         /*
++#include "debug.h"
-          * If env->vl equals to VLMAX, we can use generic vector operation
-          * expanders (GVEC) to accerlate the vector operations.
+ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
  static RISCVException vs(CPURISCVState *env, int csrno)
  {
--    if (riscv_cpu_cfg(env)->ext_zve32f) {
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
-+    if (riscv_cpu_cfg(env)->ext_zve32x) {
+         flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
- #if !defined(CONFIG_USER_ONLY)
+                            get_field(env->mstatus_hs, MSTATUS_VS));
          if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
              return RISCV_EXCP_ILLEGAL_INST;
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
          return;
      }
++    if (riscv_feature(env, RISCV_FEATURE_DEBUG) && !icount_enabled()) {
--    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
++        flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER,
--        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
++                           riscv_itrigger_enabled(env));
--        return;
++    }
-+    /* The Zve32f extension depends on the Zve32x extension */
+ #endif
-+    if (cpu->cfg.ext_zve32f) {
-+        if (!riscv_has_ext(env, RVF)) {
+     flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
-+            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
+diff --git a/target/riscv/debug.c b/target/riscv/debug.c
-+            return;
+index XXXXXXX..XXXXXXX 100644
-+        }
+--- a/target/riscv/debug.c
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
++++ b/target/riscv/debug.c
@@ -XXX,XX +XXX,XX @@
  #include "cpu.h"
  #include "trace.h"
  #include "exec/exec-all.h"
 +#include "exec/helper-proto.h"
  /*
   * The following M-mode trigger CSRs are implemented:
@@ -XXX,XX +XXX,XX @@ static void type6_reg_write(CPURISCVState *env, target_ulong index,
      return;
  }
 +/* icount trigger type */
 +static inline int
 +itrigger_get_count(CPURISCVState *env, int index)
 +{
 +    return get_field(env->tdata1[index], ITRIGGER_COUNT);
 +}
 +
 +static inline void
 +itrigger_set_count(CPURISCVState *env, int index, int value)
 +{
 +    env->tdata1[index] = set_field(env->tdata1[index],
 +                                   ITRIGGER_COUNT, value);
 +}
 +
 +static bool check_itrigger_priv(CPURISCVState *env, int index)
 +{
 +    target_ulong tdata1 = env->tdata1[index];
 +    if (riscv_cpu_virt_enabled(env)) {
 +        /* check VU/VS bit against current privilege level */
 +        return (get_field(tdata1, ITRIGGER_VS) == env->priv) ||
 +               (get_field(tdata1, ITRIGGER_VU) == env->priv);
 +    } else {
 +        /* check U/S/M bit against current privilege level */
 +        return (get_field(tdata1, ITRIGGER_M) == env->priv) ||
 +               (get_field(tdata1, ITRIGGER_S) == env->priv) ||
 +               (get_field(tdata1, ITRIGGER_U) == env->priv);
 +    }
 +}
 +
 +bool riscv_itrigger_enabled(CPURISCVState *env)
 +{
 +    int count;
 +    for (int i = 0; i < RV_MAX_TRIGGERS; i++) {
 +        if (get_trigger_type(env, i) != TRIGGER_TYPE_INST_CNT) {
 +            continue;
 +        }
 +        if (check_itrigger_priv(env, i)) {
 +            continue;
 +        }
 +        count = itrigger_get_count(env, i);
 +        if (!count) {
 +            continue;
 +        }
 +        return true;
 +    }
 +
 +    return false;
 +}
 +
 +void helper_itrigger_match(CPURISCVState *env)
 +{
 +    int count;
 +    for (int i = 0; i < RV_MAX_TRIGGERS; i++) {
 +        if (get_trigger_type(env, i) != TRIGGER_TYPE_INST_CNT) {
 +            continue;
 +        }
 +        if (check_itrigger_priv(env, i)) {
 +            continue;
 +        }
 +        count = itrigger_get_count(env, i);
 +        if (!count) {
 +            continue;
 +        }
 +        itrigger_set_count(env, i, count--);
 +        if (!count) {
 +            do_trigger_action(env, i);
 +        }
 +    }
 +}
 +
  target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
  {
      switch (tdata_index) {
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
      /* PointerMasking extension */
      bool pm_mask_enabled;
      bool pm_base_enabled;
 +    /* Use icount trigger for native debug */
 +    bool itrigger;
      /* TCG of the current insn_start */
      TCGOp *insn_start;
  } DisasContext;
@@ -XXX,XX +XXX,XX @@ static void gen_exception_inst_addr_mis(DisasContext *ctx)
      generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS);
  }
 +static void lookup_and_goto_ptr(DisasContext *ctx)
 +{
 +#ifndef CONFIG_USER_ONLY
 +    if (ctx->itrigger) {
 +        gen_helper_itrigger_match(cpu_env);
 +    }
 +#endif
 +    tcg_gen_lookup_and_goto_ptr();
 +}
 +
 +static void exit_tb(DisasContext *ctx)
 +{
 +#ifndef CONFIG_USER_ONLY
 +    if (ctx->itrigger) {
 +        gen_helper_itrigger_match(cpu_env);
 +    }
 +#endif
 +    tcg_gen_exit_tb(NULL, 0);
 +}
 +
  static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
  {
 -    if (translator_use_goto_tb(&ctx->base, dest)) {
 +     /*
 +      * Under itrigger, instruction executes one by one like singlestep,
 +      * direct block chain benefits will be small.
 +      */
 +    if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) {
          tcg_gen_goto_tb(n);
          gen_set_pc_imm(ctx, dest);
          tcg_gen_exit_tb(ctx->base.tb, n);
      } else {
          gen_set_pc_imm(ctx, dest);
 -        tcg_gen_lookup_and_goto_ptr();
 +        lookup_and_goto_ptr(ctx);
      }
+ }
-     if (cpu->cfg.ext_zvfh) {
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
-         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
+     memset(ctx->ftemp, 0, sizeof(ctx->ftemp));
      ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
      ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
 +    ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
      ctx->zero = tcg_constant_tl(0);
  }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
      /* Only the first insn within a TB is allowed to cross a page boundary. */
      if (ctx->base.is_jmp == DISAS_NEXT) {
 -        if (!is_same_page(&ctx->base, ctx->base.pc_next)) {
 +        if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) {
              ctx->base.is_jmp = DISAS_TOO_MANY;
          } else {
              unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK;
 diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_privileged.c.inc
 +++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
      if (has_ext(ctx, RVS)) {
          decode_save_opc(ctx);
          gen_helper_sret(cpu_pc, cpu_env);
 -        tcg_gen_exit_tb(NULL, 0); /* no chaining */
 +        exit_tb(ctx); /* no chaining */
          ctx->base.is_jmp = DISAS_NORETURN;
      } else {
          return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
  #ifndef CONFIG_USER_ONLY
      decode_save_opc(ctx);
      gen_helper_mret(cpu_pc, cpu_env);
 -    tcg_gen_exit_tb(NULL, 0); /* no chaining */
 +    exit_tb(ctx); /* no chaining */
      ctx->base.is_jmp = DISAS_NORETURN;
      return true;
  #else
 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvi.c.inc
 +++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
      }
--    /*
+     gen_set_gpri(ctx, a->rd, ctx->pc_succ_insn);
--     * In principle Zve*x would also suffice here, were they supported
+-    tcg_gen_lookup_and_goto_ptr();
--     * in qemu
++    lookup_and_goto_ptr(ctx);
--     */
-     if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
+     if (misaligned) {
-          cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
+         gen_set_label(misaligned);
--         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
+@@ -XXX,XX +XXX,XX @@ static bool trans_pause(DisasContext *ctx, arg_pause *a)
-+         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
+      * end the TB and return to main loop
-         error_setg(errp,
+      */
-                    "Vector crypto extensions require V or Zve* extensions");
+     gen_set_pc_imm(ctx, ctx->pc_succ_insn);
-         return;
+-    tcg_gen_exit_tb(NULL, 0);
 +    exit_tb(ctx);
      ctx->base.is_jmp = DISAS_NORETURN;
      return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
       * however we need to end the translation block
       */
      gen_set_pc_imm(ctx, ctx->pc_succ_insn);
 -    tcg_gen_exit_tb(NULL, 0);
 +    exit_tb(ctx);
      ctx->base.is_jmp = DISAS_NORETURN;
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool do_csr_post(DisasContext *ctx)
      decode_save_opc(ctx);
      /* We may have changed important cpu state -- exit to main loop. */
      gen_set_pc_imm(ctx, ctx->pc_succ_insn);
 -    tcg_gen_exit_tb(NULL, 0);
 +    exit_tb(ctx);
      ctx->base.is_jmp = DISAS_NORETURN;
      return true;
  }
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
 @@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
- {
+     mark_vs_dirty(s);
-     TCGv s1, dst;
+     gen_set_pc_imm(s, s->pc_succ_insn);
--    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+-    tcg_gen_lookup_and_goto_ptr();
-+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
++    lookup_and_goto_ptr(s);
-         return false;
+     s->base.is_jmp = DISAS_NORETURN;
-     }
+     if (rd == 0 && rs1 == 0) {
 @@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
- {
+     gen_set_gpr(s, rd, dst);
-     TCGv dst;
+     mark_vs_dirty(s);
+     gen_set_pc_imm(s, s->pc_succ_insn);
--    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+-    tcg_gen_lookup_and_goto_ptr();
-+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
++    lookup_and_goto_ptr(s);
-         return false;
+     s->base.is_jmp = DISAS_NORETURN;
-     }
+     return true;
 --
-.45.1
+.38.1

-[PULL 15/28] target/riscv: Implement dynamic establishment of custom decoder
+[PULL v2 13/45] target/riscv: Add itrigger support when icount is enabled
-From: Huang Tao <eric.huang@linux.alibaba.com>
+From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-In this patch, we modify the decoder to be a freely composable data
+The max count in itrigger can be 0x3FFF, which will cause a no trivial
-structure instead of a hardcoded one. It can be dynamically builded up
+translation and execution overload.
 according to the extensions.
 This approach has several benefits:
 . Provides support for heterogeneous cpu architectures. As we add decoder in
    RISCVCPU, each cpu can have their own decoder, and the decoders can be
    different due to cpu's features.
 . Improve the decoding efficiency. We run the guard_func to see if the decoder
    can be added to the dynamic_decoder when building up the decoder. Therefore,
    there is no need to run the guard_func when decoding each instruction. It can
    improve the decoding efficiency
 . For vendor or dynamic cpus, it allows them to customize their own decoder
    functions to improve decoding efficiency, especially when vendor-defined
    instruction sets increase. Because of dynamic building up, it can skip the other
    decoder guard functions when decoding.
 . Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
    overhead for users that don't need this particular vendor decoder.
-Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
+When icount is enabled, QEMU provides API that can fetch guest
-Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
+instruction number. Thus, we can set an timer for itrigger with
-Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+the count as deadline.
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Only when timer expires or priviledge mode changes, do lazy update
 to count.
 Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
+Message-Id: <20221013062946.7530-3-zhiwei_liu@linux.alibaba.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h         |  1 +
+ target/riscv/cpu.h        |  2 ++
- target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
+ target/riscv/debug.h      |  1 +
- target/riscv/cpu.c         |  1 +
+ target/riscv/cpu_helper.c |  3 ++
- target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
+ target/riscv/debug.c      | 59 +++++++++++++++++++++++++++++++++++++++
- target/riscv/translate.c   | 31 +++++++++++++++----------------
+files changed, 65 insertions(+)
 files changed, 47 insertions(+), 16 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
+@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
-     uint32_t pmu_avail_ctrs;
+     target_ulong tdata3[RV_MAX_TRIGGERS];
-     /* Mapping of events to counters */
+     struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS];
-     GHashTable *pmu_event_ctr_map;
+     struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS];
-+    const GPtrArray *decoders;
++    QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS];
- };
++    int64_t last_icount;
- /**
+     /* machine specific rdtime callback */
-diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
+     uint64_t (*rdtime_fn)(void *);
 diff --git a/target/riscv/debug.h b/target/riscv/debug.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/tcg/tcg-cpu.h
+--- a/target/riscv/debug.h
-+++ b/target/riscv/tcg/tcg-cpu.h
++++ b/target/riscv/debug.h
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
- void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
+ void riscv_trigger_init(CPURISCVState *env);
- bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
+ bool riscv_itrigger_enabled(CPURISCVState *env);
-+struct DisasContext;
++void riscv_itrigger_update_priv(CPURISCVState *env);
-+struct RISCVCPUConfig;
+ #endif /* RISCV_DEBUG_H */
-+typedef struct RISCVDecoder {
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 +    bool (*guard_func)(const struct RISCVCPUConfig *);
 +    bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
 +} RISCVDecoder;
 +
 +typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
 +
 +extern const size_t decoder_table_size;
 +
 +extern const RISCVDecoder decoder_table[];
 +
 +void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
 +
  #endif
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
+--- a/target/riscv/cpu_helper.c
-+++ b/target/riscv/cpu.c
++++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
-             error_propagate(errp, local_err);
+     if (newpriv == PRV_H) {
-             return;
+         newpriv = PRV_U;
-         }
+     }
-+        riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
++    if (icount_enabled() && newpriv != env->priv) {
-     } else if (kvm_enabled()) {
++        riscv_itrigger_update_priv(env);
-         riscv_kvm_cpu_finalize_features(cpu, &local_err);
++    }
-         if (local_err != NULL) {
+     /* tlb_flush is unnecessary as mode is contained in mmu_idx */
-diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
+     env->priv = newpriv;
      env->xl = cpu_recompute_xl(env);
 diff --git a/target/riscv/debug.c b/target/riscv/debug.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/tcg/tcg-cpu.c
+--- a/target/riscv/debug.c
-+++ b/target/riscv/tcg/tcg-cpu.c
++++ b/target/riscv/debug.c
-@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
+@@ -XXX,XX +XXX,XX @@
  #include "trace.h"
  #include "exec/exec-all.h"
  #include "exec/helper-proto.h"
 +#include "sysemu/cpu-timers.h"
  /*
   * The following M-mode trigger CSRs are implemented:
@@ -XXX,XX +XXX,XX @@ void helper_itrigger_match(CPURISCVState *env)
      }
  }
-+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
++static void riscv_itrigger_update_count(CPURISCVState *env)
 +{
-+    GPtrArray *dynamic_decoders;
++    int count, executed;
-+    dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
++    /*
-+    for (size_t i = 0; i < decoder_table_size; ++i) {
++     * Record last icount, so that we can evaluate the executed instructions
-+        if (decoder_table[i].guard_func &&
++     * since last priviledge mode change or timer expire.
-+            decoder_table[i].guard_func(&cpu->cfg)) {
++     */
-+            g_ptr_array_add(dynamic_decoders,
++    int64_t last_icount = env->last_icount, current_icount;
-+                            (gpointer)decoder_table[i].riscv_cpu_decode_fn);
++    current_icount = env->last_icount = icount_get_raw();
 +
 +    for (int i = 0; i < RV_MAX_TRIGGERS; i++) {
 +        if (get_trigger_type(env, i) != TRIGGER_TYPE_INST_CNT) {
 +            continue;
 +        }
 +        count = itrigger_get_count(env, i);
 +        if (!count) {
 +            continue;
 +        }
 +        /*
 +         * Only when priviledge is changed or itrigger timer expires,
 +         * the count field in itrigger tdata1 register is updated.
 +         * And the count field in itrigger only contains remaining value.
 +         */
 +        if (check_itrigger_priv(env, i)) {
 +            /*
 +             * If itrigger enabled in this priviledge mode, the number of
 +             * executed instructions since last priviledge change
 +             * should be reduced from current itrigger count.
 +             */
 +            executed = current_icount - last_icount;
 +            itrigger_set_count(env, i, count - executed);
 +            if (count == executed) {
 +                do_trigger_action(env, i);
 +            }
 +        } else {
 +            /*
 +             * If itrigger is not enabled in this priviledge mode,
 +             * the number of executed instructions will be discard and
 +             * the count field in itrigger will not change.
 +             */
 +            timer_mod(env->itrigger_timer[i],
 +                      current_icount + count);
 +        }
 +    }
-+
-+    cpu->decoders = dynamic_decoders;
 +}
 +
- bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
++static void riscv_itrigger_timer_cb(void *opaque)
 +{
 +    riscv_itrigger_update_count((CPURISCVState *)opaque);
 +}
 +
 +void riscv_itrigger_update_priv(CPURISCVState *env)
 +{
 +    riscv_itrigger_update_count(env);
 +}
 +
  target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
  {
-     return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
+     switch (tdata_index) {
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+@@ -XXX,XX +XXX,XX @@ void riscv_trigger_init(CPURISCVState *env)
-index XXXXXXX..XXXXXXX 100644
+         env->tdata3[i] = 0;
---- a/target/riscv/translate.c
+         env->cpu_breakpoint[i] = NULL;
-+++ b/target/riscv/translate.c
+         env->cpu_watchpoint[i] = NULL;
-@@ -XXX,XX +XXX,XX @@
++        env->itrigger_timer[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL,
- #include "exec/helper-info.c.inc"
++                                              riscv_itrigger_timer_cb, env);
- #undef  HELPER_H
+     }
 +#include "tcg/tcg-cpu.h"
 +
  /* global register indices */
  static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
  static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
      /* FRM is known to contain a valid value. */
      bool frm_valid;
      bool insn_start_updated;
 +    const GPtrArray *decoders;
  } DisasContext;
  static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
      return (first_word & 3) == 3 ? 4 : 2;
  }
-+const RISCVDecoder decoder_table[] = {
-+    { always_true_p, decode_insn32 },
-+    { has_xthead_p, decode_xthead},
-+    { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
-+};
-+
-+const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
-+
- static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
- {
--    /*
--     * A table with predicate (i.e., guard) functions and decoder functions
--     * that are tested in-order until a decoder matches onto the opcode.
--     */
--    static const struct {
--        bool (*guard_func)(const RISCVCPUConfig *);
--        bool (*decode_func)(DisasContext *, uint32_t);
--    } decoders[] = {
--        { always_true_p,  decode_insn32 },
--        { has_xthead_p, decode_xthead },
--        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
--    };
--
-     ctx->virt_inst_excp = false;
-     ctx->cur_insn_len = insn_len(opcode);
-     /* Check for compressed insn */
-@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
-                                              ctx->base.pc_next + 2));
-         ctx->opcode = opcode32;
--        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
--            if (decoders[i].guard_func(ctx->cfg_ptr) &&
--                decoders[i].decode_func(ctx, opcode32)) {
-+        for (guint i = 0; i < ctx->decoders->len; ++i) {
-+            riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
-+            if (func(ctx, opcode32)) {
-                 return;
-             }
-         }
-@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
-     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
-     ctx->zero = tcg_constant_tl(0);
-     ctx->virt_inst_excp = false;
-+    ctx->decoders = cpu->decoders;
- }
- static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
 --
-.45.1
+.38.1

-[PULL 17/28] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
+[PULL v2 14/45] target/riscv: Enable native debug itrigger
-From: Max Chou <max.chou@sifive.com>
+From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
+When QEMU is not in icount mode, execute instruction one by one. The
-instructions will be affected by Zvfhmin extension.
+tdata1 can be read directly.
 And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
 conversions of
-* From 1*SEW(16/32) to 2*SEW(32/64)
+When QEMU is in icount mode, use a timer to simulate the itrigger. The
-* From 2*SEW(32/64) to 1*SEW(16/32)
+tdata1 may be not right because of lazy update of count in tdata1. Thus,
 We should pack the adjusted count into tdata1 before read it back.
-Signed-off-by: Max Chou <max.chou@sifive.com>
+Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-Id: <20221013062946.7530-4-zhiwei_liu@linux.alibaba.com>
 Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
+ target/riscv/debug.c | 72 ++++++++++++++++++++++++++++++++++++++++++++
-file changed, 18 insertions(+), 2 deletions(-)
+file changed, 72 insertions(+)
-diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+diff --git a/target/riscv/debug.c b/target/riscv/debug.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.c.inc
+--- a/target/riscv/debug.c
-+++ b/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/debug.c
-@@ -XXX,XX +XXX,XX @@ static bool require_rvf(DisasContext *s)
+@@ -XXX,XX +XXX,XX @@ void riscv_itrigger_update_priv(CPURISCVState *env)
-     }
+     riscv_itrigger_update_count(env);
  }
-+static bool require_rvfmin(DisasContext *s)
++static target_ulong itrigger_validate(CPURISCVState *env,
 +                                      target_ulong ctrl)
 +{
-+    if (s->mstatus_fs == EXT_STATUS_DISABLED) {
++    target_ulong val;
-+        return false;
++
 +    /* validate the generic part first */
 +    val = tdata1_validate(env, ctrl, TRIGGER_TYPE_INST_CNT);
 +
 +    /* validate unimplemented (always zero) bits */
 +    warn_always_zero_bit(ctrl, ITRIGGER_ACTION, "action");
 +    warn_always_zero_bit(ctrl, ITRIGGER_HIT, "hit");
 +    warn_always_zero_bit(ctrl, ITRIGGER_PENDING, "pending");
 +
 +    /* keep the mode and attribute bits */
 +    val |= ctrl & (ITRIGGER_VU | ITRIGGER_VS | ITRIGGER_U | ITRIGGER_S |
 +                   ITRIGGER_M | ITRIGGER_COUNT);
 +
 +    return val;
 +}
 +
 +static void itrigger_reg_write(CPURISCVState *env, target_ulong index,
 +                               int tdata_index, target_ulong val)
 +{
 +    target_ulong new_val;
 +
 +    switch (tdata_index) {
 +    case TDATA1:
 +        /* set timer for icount */
 +        new_val = itrigger_validate(env, val);
 +        if (new_val != env->tdata1[index]) {
 +            env->tdata1[index] = new_val;
 +            if (icount_enabled()) {
 +                env->last_icount = icount_get_raw();
 +                /* set the count to timer */
 +                timer_mod(env->itrigger_timer[index],
 +                          env->last_icount + itrigger_get_count(env, index));
 +            }
 +        }
 +        break;
 +    case TDATA2:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "tdata2 is not supported for icount trigger\n");
 +        break;
 +    case TDATA3:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "tdata3 is not supported for icount trigger\n");
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
 +
-+    switch (s->sew) {
++    return;
 +    case MO_16:
 +        return s->cfg_ptr->ext_zvfhmin;
 +    case MO_32:
 +        return s->cfg_ptr->ext_zve32f;
 +    default:
 +        return false;
 +    }
 +}
 +
- static bool require_scale_rvf(DisasContext *s)
++static int itrigger_get_adjust_count(CPURISCVState *env)
 +{
 +    int count = itrigger_get_count(env, env->trigger_cur), executed;
 +    if ((count != 0) && check_itrigger_priv(env, env->trigger_cur)) {
 +        executed = icount_get_raw() - env->last_icount;
 +        count += executed;
 +    }
 +    return count;
 +}
 +
  target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
  {
-     if (s->mstatus_fs == EXT_STATUS_DISABLED) {
++    int trigger_type;
-@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvfmin(DisasContext *s)
+     switch (tdata_index) {
-     }
+     case TDATA1:
++        trigger_type = extract_trigger_type(env, env->tdata1[env->trigger_cur]);
-     switch (s->sew) {
++        if ((trigger_type == TRIGGER_TYPE_INST_CNT) && icount_enabled()) {
--    case MO_8:
++            return deposit64(env->tdata1[env->trigger_cur], 10, 14,
--        return s->cfg_ptr->ext_zvfhmin;
++                             itrigger_get_adjust_count(env));
-     case MO_16:
++        }
-         return s->cfg_ptr->ext_zve32f;
+         return env->tdata1[env->trigger_cur];
-     case MO_32:
+     case TDATA2:
-@@ -XXX,XX +XXX,XX @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
+         return env->tdata2[env->trigger_cur];
- static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
+@@ -XXX,XX +XXX,XX @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
- {
+         type6_reg_write(env, env->trigger_cur, tdata_index, val);
-     return opfv_widen_check(s, a) &&
+         break;
-+           require_rvfmin(s) &&
+     case TRIGGER_TYPE_INST_CNT:
-            require_scale_rvfmin(s) &&
++        itrigger_reg_write(env, env->trigger_cur, tdata_index, val);
-            (s->sew != MO_8);
++        break;
- }
+     case TRIGGER_TYPE_INT:
-@@ -XXX,XX +XXX,XX @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
+     case TRIGGER_TYPE_EXCP:
- static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
+     case TRIGGER_TYPE_EXT_SRC:
  {
      return opfv_narrow_check(s, a) &&
 +           require_rvfmin(s) &&
             require_scale_rvfmin(s) &&
             (s->sew != MO_8);
  }
 --
-.45.1
+.38.1

-[PULL 08/28] target/riscv/debug: set tval=pc in breakpoint exceptions
+[PULL v2 15/45] target/riscv: Add itrigger_enabled field to CPURISCVState
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-We're not setting (s/m)tval when triggering breakpoints of type 2
+Avoid calling riscv_itrigger_enabled() when calculate the tbflags.
-(mcontrol) and 6 (mcontrol6). According to the debug spec section
+As the itrigger enable status can only be changed when write
-.7.12, "Match Control Type 6":
+tdata1, migration load or itrigger fire, update env->itrigger_enabled
 at these places.
-"The Privileged Spec says that breakpoint exceptions that occur on
+Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 instruction fetches, loads, or stores update the tval CSR with either
 zero or the faulting virtual address. The faulting virtual address for
 an mcontrol6 trigger with action = 0 is the address being accessed and
 which caused that trigger to fire."
 A similar text is also found in the Debug spec section 5.7.11 w.r.t.
 mcontrol.
 Note that what we're doing ATM is not violating the spec, but it's
 simple enough to set mtval/stval and it makes life easier for any
 software that relies on this info.
 Given that we always use action = 0, save the faulting address for the
 mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
 used as as scratch area for traps with address information. 'tval' is
 then set during riscv_cpu_do_interrupt().
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Message-Id: <20221013062946.7530-5-zhiwei_liu@linux.alibaba.com>
 Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 1 +
+ target/riscv/cpu.h        |  1 +
- target/riscv/debug.c      | 3 +++
+ target/riscv/cpu_helper.c |  3 +--
-files changed, 4 insertions(+)
+ target/riscv/debug.c      |  3 +++
  target/riscv/machine.c    | 15 +++++++++++++++
 files changed, 20 insertions(+), 2 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
+     struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS];
+     QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS];
+     int64_t last_icount;
++    bool itrigger_enabled;
+     /* machine specific rdtime callback */
+     uint64_t (*rdtime_fn)(void *);
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
-             tval = env->bins;
+                            get_field(env->mstatus_hs, MSTATUS_VS));
-             break;
+     }
-         case RISCV_EXCP_BREAKPOINT:
+     if (riscv_feature(env, RISCV_FEATURE_DEBUG) && !icount_enabled()) {
-+            tval = env->badaddr;
+-        flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER,
-             if (cs->watchpoint_hit) {
+-                           riscv_itrigger_enabled(env));
-                 tval = cs->watchpoint_hit->hitaddr;
++        flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
-                 cs->watchpoint_hit = NULL;
+     }
  #endif
 diff --git a/target/riscv/debug.c b/target/riscv/debug.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/debug.c
 +++ b/target/riscv/debug.c
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
+@@ -XXX,XX +XXX,XX @@ void helper_itrigger_match(CPURISCVState *env)
-                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
+         }
-                     /* check U/S/M bit against current privilege level */
+         itrigger_set_count(env, i, count--);
-                     if ((ctrl >> 3) & BIT(env->priv)) {
+         if (!count) {
-+                        env->badaddr = pc;
++            env->itrigger_enabled = riscv_itrigger_enabled(env);
-                         return true;
+             do_trigger_action(env, i);
-                     }
+         }
-                 }
+     }
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
+@@ -XXX,XX +XXX,XX @@ static void itrigger_reg_write(CPURISCVState *env, target_ulong index,
-                     if (env->virt_enabled) {
+                 /* set the count to timer */
-                         /* check VU/VS bit against current privilege level */
+                 timer_mod(env->itrigger_timer[index],
-                         if ((ctrl >> 23) & BIT(env->priv)) {
+                           env->last_icount + itrigger_get_count(env, index));
-+                            env->badaddr = pc;
++            } else {
-                             return true;
++                env->itrigger_enabled = riscv_itrigger_enabled(env);
-                         }
+             }
-                     } else {
+         }
-                         /* check U/S/M bit against current privilege level */
+         break;
-                         if ((ctrl >> 3) & BIT(env->priv)) {
+diff --git a/target/riscv/machine.c b/target/riscv/machine.c
-+                            env->badaddr = pc;
+index XXXXXXX..XXXXXXX 100644
-                             return true;
+--- a/target/riscv/machine.c
-                         }
++++ b/target/riscv/machine.c
-                     }
+@@ -XXX,XX +XXX,XX @@
  #include "qemu/error-report.h"
  #include "sysemu/kvm.h"
  #include "migration/cpu.h"
 +#include "sysemu/cpu-timers.h"
 +#include "debug.h"
  static bool pmp_needed(void *opaque)
  {
@@ -XXX,XX +XXX,XX @@ static bool debug_needed(void *opaque)
      return riscv_feature(env, RISCV_FEATURE_DEBUG);
  }
 +static int debug_post_load(void *opaque, int version_id)
 +{
 +    RISCVCPU *cpu = opaque;
 +    CPURISCVState *env = &cpu->env;
 +
 +    if (icount_enabled()) {
 +        env->itrigger_enabled = riscv_itrigger_enabled(env);
 +    }
 +
 +    return 0;
 +}
 +
  static const VMStateDescription vmstate_debug = {
      .name = "cpu/debug",
      .version_id = 2,
      .minimum_version_id = 2,
      .needed = debug_needed,
 +    .post_load = debug_post_load,
      .fields = (VMStateField[]) {
          VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
          VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS),
 --
-.45.1
+.38.1

-[PULL 05/28] hw/riscv/boot.c: Support 64-bit address for initrd
+[PULL v2 16/45] hw/intc: sifive_plic: Renumber the S irqs for numa support
-From: Cheng Yang <yangcheng.work@foxmail.com>
+From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
-Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
+Commit 40244040a7a changed the way the S irqs are numbered. This breaks when
-to set the address of initrd in FDT to support 64-bit address.
+using numa configuration, e.g.:
 ./qemu-system-riscv64 -nographic -machine virt,dumpdtb=numa-tree.dtb \
                       -m 2G -smp cpus=16 \
               -object memory-backend-ram,id=mem0,size=512M \
               -object memory-backend-ram,id=mem1,size=512M \
               -object memory-backend-ram,id=mem2,size=512M \
               -object memory-backend-ram,id=mem3,size=512M \
               -numa node,cpus=0-3,memdev=mem0,nodeid=0 \
               -numa node,cpus=4-7,memdev=mem1,nodeid=1 \
               -numa node,cpus=8-11,memdev=mem2,nodeid=2 \
               -numa node,cpus=12-15,memdev=mem3,nodeid=3
 leads to:
 Unexpected error in object_property_find_err() at ../qom/object.c:1304:
 qemu-system-riscv64: Property 'riscv.sifive.plic.unnamed-gpio-out[8]' not
 found
-Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
+This patch makes the nubering of the S irqs identical to what it was before.
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
 Message-Id: <20221114135122.1668703-1-frederic.petrot@univ-grenoble-alpes.fr>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/boot.c | 4 ++--
+ hw/intc/sifive_plic.c | 4 ++--
 file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
+diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/boot.c
+--- a/hw/intc/sifive_plic.c
-+++ b/hw/riscv/boot.c
++++ b/hw/intc/sifive_plic.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
+@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
-     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
+         CPUState *cpu = qemu_get_cpu(cpu_num);
-     if (fdt) {
-         end = start + size;
+         if (plic->addr_config[i].mode == PLICMode_M) {
--        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
+-            qdev_connect_gpio_out(dev, num_harts - plic->hartid_base + cpu_num,
--        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
++            qdev_connect_gpio_out(dev, cpu_num - hartid_base + num_harts,
-+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
+                                   qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
-+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
+         }
          if (plic->addr_config[i].mode == PLICMode_S) {
 -            qdev_connect_gpio_out(dev, cpu_num,
 +            qdev_connect_gpio_out(dev, cpu_num - hartid_base,
                                    qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
          }
      }
- }
 --
-.45.1
+.38.1

-[PULL 06/28] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
+[PULL v2 17/45] target/riscv: Typo fix in sstc() predicate
-From: Clément Léger <cleger@rivosinc.com>
+From: Anup Patel <apatel@ventanamicro.com>
-The current semihost exception number (16) is a reserved number (range
+We should use "&&" instead of "&" when checking hcounteren.TM and
-[16-17]). The upcoming double trap specification uses that number for
+henvcfg.STCE bits.
 the double trap exception. Since the privileged spec (Table 22) defines
 ranges for custom uses change the semihosting exception number to 63
 which belongs to the range [48-63] in order to avoid any future
 collisions with reserved exception.
-Signed-off-by: Clément Léger <cleger@rivosinc.com>
+Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
+Signed-off-by: Anup Patel <apatel@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
+Message-Id: <20221108125703.1463577-2-apatel@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_bits.h | 2 +-
+ target/riscv/csr.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_bits.h
+--- a/target/riscv/csr.c
-+++ b/target/riscv/cpu_bits.h
++++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
+@@ -XXX,XX +XXX,XX @@ static RISCVException sstc(CPURISCVState *env, int csrno)
-     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
+     }
-     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
-     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
+     if (riscv_cpu_virt_enabled(env)) {
--    RISCV_EXCP_SEMIHOST = 0x10,
+-        if (!(get_field(env->hcounteren, COUNTEREN_TM) &
-     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
++        if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
-     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
+               get_field(env->henvcfg, HENVCFG_STCE))) {
-     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
+             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
-     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
+         }
 +    RISCV_EXCP_SEMIHOST = 0x3f,
  } RISCVException;
  #define RISCV_EXCP_INT_FLAG                0x80000000
 --
-.45.1
+.38.1

-New patch
+[PULL v2 18/45] hw/riscv: virt: Remove the redundant ipi-id property
+From: Atish Patra <atishp@rivosinc.com>
+The imsic DT binding[1] has changed and no longer require an ipi-id.
+The latest IMSIC driver dynamically allocates ipi id if slow-ipi
+is not defined.
+Get rid of the unused dt property which may lead to confusion.
+[1] https://lore.kernel.org/lkml/20221111044207.1478350-5-apatel@ventanamicro.com/
+Signed-off-by: Atish Patra <atishp@rivosinc.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <20221122080529.1692533-1-atishp@rivosinc.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ include/hw/riscv/virt.h | 1 -
+ hw/riscv/virt.c         | 4 ----
+files changed, 5 deletions(-)
+diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/riscv/virt.h
++++ b/include/hw/riscv/virt.h
+@@ -XXX,XX +XXX,XX @@ enum {
+ #define VIRT_PLATFORM_BUS_NUM_IRQS 32
+-#define VIRT_IRQCHIP_IPI_MSI 1
+ #define VIRT_IRQCHIP_NUM_MSIS 255
+ #define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV
+ #define VIRT_IRQCHIP_NUM_PRIO_BITS 3
+diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/virt.c
++++ b/hw/riscv/virt.c
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
+         riscv_socket_count(mc) * sizeof(uint32_t) * 4);
+     qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
+         VIRT_IRQCHIP_NUM_MSIS);
+-    qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id",
+-        VIRT_IRQCHIP_IPI_MSI);
+     if (riscv_socket_count(mc) > 1) {
+         qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
+             imsic_num_bits(imsic_max_hart_per_socket));
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
+         riscv_socket_count(mc) * sizeof(uint32_t) * 4);
+     qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
+         VIRT_IRQCHIP_NUM_MSIS);
+-    qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id",
+-        VIRT_IRQCHIP_IPI_MSI);
+     if (imsic_guest_bits) {
+         qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits",
+             imsic_guest_bits);
+--
+.38.1

-[PULL 22/28] target/riscv: do not set mtval2 for non guest-page faults
+[PULL v2 19/45] target/riscv: support cache-related PMU events in virtual mode
-From: Alexei Filippov <alexei.filippov@syntacore.com>
+From: Jim Shu <jim.shu@sifive.com>
-Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
+let tlb_fill() function also increments PMU counter when it is from
-setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
+two-stage translation, so QEMU could also monitor these PMU events when
-translation part, mtval2 will be set in case of successes 2 stage translation but
+CPU runs in VS/VU mode (like running guest OS).
 failed pmp check.
-In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
+Signed-off-by: Jim Shu <jim.shu@sifive.com>
 riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
 should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
 page-fault is taken into M-mode, mtval2 is written with either zero or guest
 physical address that faulted, shifted by 2 bits. *For other traps, mtval2
 is set to zero...*
 Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
+Message-Id: <20221123090635.6574-1-jim.shu@sifive.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 12 ++++++------
+ target/riscv/cpu_helper.c | 2 +-
-file changed, 6 insertions(+), 6 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
 @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-                               __func__, pa, ret, prot_pmp, tlb_size);
+         }
+     }
-                 prot &= prot_pmp;
--            }
++    pmu_tlb_fill_incr_ctr(cpu, access_type);
--
+     if (riscv_cpu_virt_enabled(env) ||
--            if (ret != TRANSLATE_SUCCESS) {
+         ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
-+            } else {
+          access_type != MMU_INST_FETCH)) {
-                 /*
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                   * Guest physical address translation failed, this is a HS
                   * level exception
                   */
                  first_stage_error = false;
 -                env->guest_phys_fault_addr = (im_address |
 -                                              (address &
 -                                               (TARGET_PAGE_SIZE - 1))) >> 2;
 +                if (ret != TRANSLATE_PMP_FAIL) {
 +                    env->guest_phys_fault_addr = (im_address |
 +                                                  (address &
 +                                                   (TARGET_PAGE_SIZE - 1))) >> 2;
 +                }
              }
          }
      } else {
+-        pmu_tlb_fill_incr_ctr(cpu, access_type);
+         /* Single stage lookup */
+         ret = get_physical_address(env, &pa, &prot, address, NULL,
+                                    access_type, mmu_idx, true, false, false);
 --
-.45.1
+.38.1

-[PULL 14/28] target/riscv/cpu.c: fix Zvkb extension config
+[PULL v2 20/45] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state()
-From: Yangyu Chen <cyy@cyyself.name>
+From: Bin Meng <bmeng@tinylab.org>
-This code has a typo that writes zvkb to zvkg, causing users can't
+sstatus register dump is currently missing in riscv_cpu_dump_state().
-enable zvkb through the config. This patch gets this fixed.
+As sstatus is a copy of mstatus, which is described in the priv spec,
 it seems redundant to print the same information twice.
-Signed-off-by: Yangyu Chen <cyy@cyyself.name>
+Add some comments for this to let people know this is intentional.
-Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
-Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Signed-off-by: Bin Meng <bmeng@tinylab.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Max Chou <max.chou@sifive.com>
+Message-Id: <20221125050354.3166023-1-bmeng@tinylab.org>
 Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
 Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.c | 2 +-
+ target/riscv/cpu.c | 4 ++++
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 4 insertions(+)
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
-     /* Vector cryptography extensions */
+             CSR_MHARTID,
-     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
+             CSR_MSTATUS,
-     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
+             CSR_MSTATUSH,
--    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
++            /*
-+    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
++             * CSR_SSTATUS is intentionally omitted here as its value
-     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
++             * can be figured out by looking at CSR_MSTATUS
-     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
++             */
-     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
+             CSR_HSTATUS,
              CSR_VSSTATUS,
              CSR_MIP,
 --
-.45.1
+.38.1

-New patch
+[PULL v2 21/45] hw/misc: pfsoc: add fabric clocks to ioscb
+From: Conor Dooley <conor.dooley@microchip.com>
+On PolarFire SoC, some peripherals (eg the PCI root port) are clocked by
+"Clock Conditioning Circuitry" in the FPGA. The specific clock depends
+on the FPGA bitstream & can be locked to one particular {D,P}LL - in the
+Icicle Kit Reference Design v2022.09 or later this is/will be the case.
+Linux v6.1+ will have a driver for this peripheral and devicetrees that
+previously relied on "fixed-frequency" clock nodes have been switched
+over to clock-controller nodes. The IOSCB region is represented in QEMU,
+but the specific region of it that the CCCs occupy has not so v6.1-rcN
+kernels fail to boot in QEMU.
+Add the regions as unimplemented so that the status-quo in terms of boot
+is maintained.
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
+Message-Id: <20221117225518.4102575-2-conor@kernel.org>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ include/hw/misc/mchp_pfsoc_ioscb.h | 1 +
+ hw/misc/mchp_pfsoc_ioscb.c         | 6 ++++++
+files changed, 7 insertions(+)
+diff --git a/include/hw/misc/mchp_pfsoc_ioscb.h b/include/hw/misc/mchp_pfsoc_ioscb.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/misc/mchp_pfsoc_ioscb.h
++++ b/include/hw/misc/mchp_pfsoc_ioscb.h
+@@ -XXX,XX +XXX,XX @@ typedef struct MchpPfSoCIoscbState {
+     MemoryRegion lane23;
+     MemoryRegion ctrl;
+     MemoryRegion cfg;
++    MemoryRegion ccc;
+     MemoryRegion pll_mss;
+     MemoryRegion cfm_mss;
+     MemoryRegion pll_ddr;
+diff --git a/hw/misc/mchp_pfsoc_ioscb.c b/hw/misc/mchp_pfsoc_ioscb.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/misc/mchp_pfsoc_ioscb.c
++++ b/hw/misc/mchp_pfsoc_ioscb.c
+@@ -XXX,XX +XXX,XX @@
+  */
+ #define IOSCB_WHOLE_REG_SIZE        0x10000000
+ #define IOSCB_SUBMOD_REG_SIZE       0x1000
++#define IOSCB_CCC_REG_SIZE          0x2000000
+ /*
+  * There are many sub-modules in the IOSCB module.
+@@ -XXX,XX +XXX,XX @@
+ #define IOSCB_LANE23_BASE           0x06510000
+ #define IOSCB_CTRL_BASE             0x07020000
+ #define IOSCB_CFG_BASE              0x07080000
++#define IOSCB_CCC_BASE              0x08000000
+ #define IOSCB_PLL_MSS_BASE          0x0E001000
+ #define IOSCB_CFM_MSS_BASE          0x0E002000
+ #define IOSCB_PLL_DDR_BASE          0x0E010000
+@@ -XXX,XX +XXX,XX @@ static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp)
+                           "mchp.pfsoc.ioscb.cfg", IOSCB_SUBMOD_REG_SIZE);
+     memory_region_add_subregion(&s->container, IOSCB_CFG_BASE, &s->cfg);
++    memory_region_init_io(&s->ccc, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
++                          "mchp.pfsoc.ioscb.ccc", IOSCB_CCC_REG_SIZE);
++    memory_region_add_subregion(&s->container, IOSCB_CCC_BASE, &s->ccc);
++
+     memory_region_init_io(&s->pll_mss, OBJECT(s), &mchp_pfsoc_pll_ops, s,
+                           "mchp.pfsoc.ioscb.pll_mss", IOSCB_SUBMOD_REG_SIZE);
+     memory_region_add_subregion(&s->container, IOSCB_PLL_MSS_BASE, &s->pll_mss);
+--
+.38.1

-New patch
+[PULL v2 22/45] hw/riscv: pfsoc: add missing FICs as unimplemented
+From: Conor Dooley <conor.dooley@microchip.com>
+The Fabric Interconnect Controllers provide interfaces between the FPGA
+fabric and the core complex. There are 5 FICs on PolarFire SoC, numbered
+through 4. FIC2 is an AXI4 slave interface from the FPGA fabric and
+does not show up on the MSS memory map. FIC4 is dedicated to the User
+Crypto Processor and does not show up on the MSS memory map either.
+FIC 0, 1 & 3 do show up in the MSS memory map and neither FICs 0 or 1
+are represented in QEMU, leading to load access violations while booting
+Linux for Icicle if PCIe is enabled as the root port is connected via
+either FIC 0 or 1.
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
+Message-Id: <20221117225518.4102575-3-conor@kernel.org>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ include/hw/riscv/microchip_pfsoc.h |   2 +
+ hw/riscv/microchip_pfsoc.c         | 115 ++++++++++++++++-------------
+files changed, 65 insertions(+), 52 deletions(-)
+diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/riscv/microchip_pfsoc.h
++++ b/include/hw/riscv/microchip_pfsoc.h
+@@ -XXX,XX +XXX,XX @@ enum {
+     MICROCHIP_PFSOC_USB,
+     MICROCHIP_PFSOC_QSPI_XIP,
+     MICROCHIP_PFSOC_IOSCB,
++    MICROCHIP_PFSOC_FABRIC_FIC0,
++    MICROCHIP_PFSOC_FABRIC_FIC1,
+     MICROCHIP_PFSOC_FABRIC_FIC3,
+     MICROCHIP_PFSOC_DRAM_LO,
+     MICROCHIP_PFSOC_DRAM_LO_ALIAS,
+diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/microchip_pfsoc.c
++++ b/hw/riscv/microchip_pfsoc.c
+@@ -XXX,XX +XXX,XX @@
+  *     describes the complete IOSCB modules memory maps
+  */
+ static const MemMapEntry microchip_pfsoc_memmap[] = {
+-    [MICROCHIP_PFSOC_RSVD0] =           {        0x0,      0x100 },
+-    [MICROCHIP_PFSOC_DEBUG] =           {      0x100,      0xf00 },
+-    [MICROCHIP_PFSOC_E51_DTIM] =        {  0x1000000,     0x2000 },
+-    [MICROCHIP_PFSOC_BUSERR_UNIT0] =    {  0x1700000,     0x1000 },
+-    [MICROCHIP_PFSOC_BUSERR_UNIT1] =    {  0x1701000,     0x1000 },
+-    [MICROCHIP_PFSOC_BUSERR_UNIT2] =    {  0x1702000,     0x1000 },
+-    [MICROCHIP_PFSOC_BUSERR_UNIT3] =    {  0x1703000,     0x1000 },
+-    [MICROCHIP_PFSOC_BUSERR_UNIT4] =    {  0x1704000,     0x1000 },
+-    [MICROCHIP_PFSOC_CLINT] =           {  0x2000000,    0x10000 },
+-    [MICROCHIP_PFSOC_L2CC] =            {  0x2010000,     0x1000 },
+-    [MICROCHIP_PFSOC_DMA] =             {  0x3000000,   0x100000 },
+-    [MICROCHIP_PFSOC_L2LIM] =           {  0x8000000,  0x2000000 },
+-    [MICROCHIP_PFSOC_PLIC] =            {  0xc000000,  0x4000000 },
+-    [MICROCHIP_PFSOC_MMUART0] =         { 0x20000000,     0x1000 },
+-    [MICROCHIP_PFSOC_WDOG0] =           { 0x20001000,     0x1000 },
+-    [MICROCHIP_PFSOC_SYSREG] =          { 0x20002000,     0x2000 },
+-    [MICROCHIP_PFSOC_AXISW] =           { 0x20004000,     0x1000 },
+-    [MICROCHIP_PFSOC_MPUCFG] =          { 0x20005000,     0x1000 },
+-    [MICROCHIP_PFSOC_FMETER] =          { 0x20006000,     0x1000 },
+-    [MICROCHIP_PFSOC_DDR_SGMII_PHY] =   { 0x20007000,     0x1000 },
+-    [MICROCHIP_PFSOC_EMMC_SD] =         { 0x20008000,     0x1000 },
+-    [MICROCHIP_PFSOC_DDR_CFG] =         { 0x20080000,    0x40000 },
+-    [MICROCHIP_PFSOC_MMUART1] =         { 0x20100000,     0x1000 },
+-    [MICROCHIP_PFSOC_MMUART2] =         { 0x20102000,     0x1000 },
+-    [MICROCHIP_PFSOC_MMUART3] =         { 0x20104000,     0x1000 },
+-    [MICROCHIP_PFSOC_MMUART4] =         { 0x20106000,     0x1000 },
+-    [MICROCHIP_PFSOC_WDOG1] =           { 0x20101000,     0x1000 },
+-    [MICROCHIP_PFSOC_WDOG2] =           { 0x20103000,     0x1000 },
+-    [MICROCHIP_PFSOC_WDOG3] =           { 0x20105000,     0x1000 },
+-    [MICROCHIP_PFSOC_WDOG4] =           { 0x20106000,     0x1000 },
+-    [MICROCHIP_PFSOC_SPI0] =            { 0x20108000,     0x1000 },
+-    [MICROCHIP_PFSOC_SPI1] =            { 0x20109000,     0x1000 },
+-    [MICROCHIP_PFSOC_I2C0] =            { 0x2010a000,     0x1000 },
+-    [MICROCHIP_PFSOC_I2C1] =            { 0x2010b000,     0x1000 },
+-    [MICROCHIP_PFSOC_CAN0] =            { 0x2010c000,     0x1000 },
+-    [MICROCHIP_PFSOC_CAN1] =            { 0x2010d000,     0x1000 },
+-    [MICROCHIP_PFSOC_GEM0] =            { 0x20110000,     0x2000 },
+-    [MICROCHIP_PFSOC_GEM1] =            { 0x20112000,     0x2000 },
+-    [MICROCHIP_PFSOC_GPIO0] =           { 0x20120000,     0x1000 },
+-    [MICROCHIP_PFSOC_GPIO1] =           { 0x20121000,     0x1000 },
+-    [MICROCHIP_PFSOC_GPIO2] =           { 0x20122000,     0x1000 },
+-    [MICROCHIP_PFSOC_RTC] =             { 0x20124000,     0x1000 },
+-    [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,     0x1000 },
+-    [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
+-    [MICROCHIP_PFSOC_USB] =             { 0x20201000,     0x1000 },
+-    [MICROCHIP_PFSOC_QSPI_XIP] =        { 0x21000000,  0x1000000 },
+-    [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000, 0x10000000 },
+-    [MICROCHIP_PFSOC_FABRIC_FIC3] =     { 0x40000000, 0x20000000 },
+-    [MICROCHIP_PFSOC_DRAM_LO] =         { 0x80000000, 0x40000000 },
+-    [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =   { 0xc0000000, 0x40000000 },
+-    [MICROCHIP_PFSOC_DRAM_HI] =       { 0x1000000000,        0x0 },
+-    [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000,        0x0 },
++    [MICROCHIP_PFSOC_RSVD0] =           {        0x0,        0x100 },
++    [MICROCHIP_PFSOC_DEBUG] =           {      0x100,        0xf00 },
++    [MICROCHIP_PFSOC_E51_DTIM] =        {  0x1000000,       0x2000 },
++    [MICROCHIP_PFSOC_BUSERR_UNIT0] =    {  0x1700000,       0x1000 },
++    [MICROCHIP_PFSOC_BUSERR_UNIT1] =    {  0x1701000,       0x1000 },
++    [MICROCHIP_PFSOC_BUSERR_UNIT2] =    {  0x1702000,       0x1000 },
++    [MICROCHIP_PFSOC_BUSERR_UNIT3] =    {  0x1703000,       0x1000 },
++    [MICROCHIP_PFSOC_BUSERR_UNIT4] =    {  0x1704000,       0x1000 },
++    [MICROCHIP_PFSOC_CLINT] =           {  0x2000000,      0x10000 },
++    [MICROCHIP_PFSOC_L2CC] =            {  0x2010000,       0x1000 },
++    [MICROCHIP_PFSOC_DMA] =             {  0x3000000,     0x100000 },
++    [MICROCHIP_PFSOC_L2LIM] =           {  0x8000000,    0x2000000 },
++    [MICROCHIP_PFSOC_PLIC] =            {  0xc000000,    0x4000000 },
++    [MICROCHIP_PFSOC_MMUART0] =         { 0x20000000,       0x1000 },
++    [MICROCHIP_PFSOC_WDOG0] =           { 0x20001000,       0x1000 },
++    [MICROCHIP_PFSOC_SYSREG] =          { 0x20002000,       0x2000 },
++    [MICROCHIP_PFSOC_AXISW] =           { 0x20004000,       0x1000 },
++    [MICROCHIP_PFSOC_MPUCFG] =          { 0x20005000,       0x1000 },
++    [MICROCHIP_PFSOC_FMETER] =          { 0x20006000,       0x1000 },
++    [MICROCHIP_PFSOC_DDR_SGMII_PHY] =   { 0x20007000,       0x1000 },
++    [MICROCHIP_PFSOC_EMMC_SD] =         { 0x20008000,       0x1000 },
++    [MICROCHIP_PFSOC_DDR_CFG] =         { 0x20080000,      0x40000 },
++    [MICROCHIP_PFSOC_MMUART1] =         { 0x20100000,       0x1000 },
++    [MICROCHIP_PFSOC_MMUART2] =         { 0x20102000,       0x1000 },
++    [MICROCHIP_PFSOC_MMUART3] =         { 0x20104000,       0x1000 },
++    [MICROCHIP_PFSOC_MMUART4] =         { 0x20106000,       0x1000 },
++    [MICROCHIP_PFSOC_WDOG1] =           { 0x20101000,       0x1000 },
++    [MICROCHIP_PFSOC_WDOG2] =           { 0x20103000,       0x1000 },
++    [MICROCHIP_PFSOC_WDOG3] =           { 0x20105000,       0x1000 },
++    [MICROCHIP_PFSOC_WDOG4] =           { 0x20106000,       0x1000 },
++    [MICROCHIP_PFSOC_SPI0] =            { 0x20108000,       0x1000 },
++    [MICROCHIP_PFSOC_SPI1] =            { 0x20109000,       0x1000 },
++    [MICROCHIP_PFSOC_I2C0] =            { 0x2010a000,       0x1000 },
++    [MICROCHIP_PFSOC_I2C1] =            { 0x2010b000,       0x1000 },
++    [MICROCHIP_PFSOC_CAN0] =            { 0x2010c000,       0x1000 },
++    [MICROCHIP_PFSOC_CAN1] =            { 0x2010d000,       0x1000 },
++    [MICROCHIP_PFSOC_GEM0] =            { 0x20110000,       0x2000 },
++    [MICROCHIP_PFSOC_GEM1] =            { 0x20112000,       0x2000 },
++    [MICROCHIP_PFSOC_GPIO0] =           { 0x20120000,       0x1000 },
++    [MICROCHIP_PFSOC_GPIO1] =           { 0x20121000,       0x1000 },
++    [MICROCHIP_PFSOC_GPIO2] =           { 0x20122000,       0x1000 },
++    [MICROCHIP_PFSOC_RTC] =             { 0x20124000,       0x1000 },
++    [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,       0x1000 },
++    [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,      0x20000 },
++    [MICROCHIP_PFSOC_USB] =             { 0x20201000,       0x1000 },
++    [MICROCHIP_PFSOC_QSPI_XIP] =        { 0x21000000,    0x1000000 },
++    [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000,   0x10000000 },
++    [MICROCHIP_PFSOC_FABRIC_FIC0] =   { 0x2000000000, 0x1000000000 },
++    [MICROCHIP_PFSOC_FABRIC_FIC1] =   { 0x3000000000, 0x1000000000 },
++    [MICROCHIP_PFSOC_FABRIC_FIC3] =     { 0x40000000,   0x20000000 },
++    [MICROCHIP_PFSOC_DRAM_LO] =         { 0x80000000,   0x40000000 },
++    [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =   { 0xc0000000,   0x40000000 },
++    [MICROCHIP_PFSOC_DRAM_HI] =       { 0x1000000000,          0x0 },
++    [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000,          0x0 },
++
+ };
+ static void microchip_pfsoc_soc_instance_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
+     create_unimplemented_device("microchip.pfsoc.fabricfic3",
+         memmap[MICROCHIP_PFSOC_FABRIC_FIC3].base,
+         memmap[MICROCHIP_PFSOC_FABRIC_FIC3].size);
++    /* FPGA Fabric */
++    create_unimplemented_device("microchip.pfsoc.fabricfic0",
++        memmap[MICROCHIP_PFSOC_FABRIC_FIC0].base,
++        memmap[MICROCHIP_PFSOC_FABRIC_FIC0].size);
++    /* FPGA Fabric */
++    create_unimplemented_device("microchip.pfsoc.fabricfic1",
++        memmap[MICROCHIP_PFSOC_FABRIC_FIC1].base,
++        memmap[MICROCHIP_PFSOC_FABRIC_FIC1].size);
+     /* QSPI Flash */
+     memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
+--
+.38.1

-[PULL 04/28] target/riscv/kvm: implement SBI debug console (DBCN) calls
+[PULL v2 23/45] hw/{misc, riscv}: pfsoc: add system controller as unimplemented
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Conor Dooley <conor.dooley@microchip.com>
-SBI defines a Debug Console extension "DBCN" that will, in time, replace
+The system controller on PolarFire SoC is access via a mailbox. The
-the legacy console putchar and getchar SBI extensions.
+control registers for this mailbox lie in the "IOSCB" region & the
+interrupt is cleared via write to the "SYSREG" region. It also has a
-The appeal of the DBCN extension is that it allows multiple bytes to be
+QSPI controller, usually connected to a flash chip, that is used for
-read/written in the SBI console in a single SBI call.
+storing FPGA bitstreams and used for In-Application Programming (IAP).
-As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
+Linux has an implementation of the system controller, through which the
-module to userspace. But this will only happens if the KVM module
+hwrng is accessed, leading to load/store access faults.
-actually supports this SBI extension and we activate it.
+Add the QSPI as unimplemented and a very basic (effectively
-We'll check for DBCN support during init time, checking if get-reg-list
+unimplemented) version of the system controller's mailbox. Rather than
-is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
+purely marking the regions as unimplemented, service the mailbox
-kvm_set_one_reg() during kvm_arch_init_vcpu().
+requests by reporting failures and raising the interrupt so a guest can
+better handle the lack of support.
-Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
-SBI_EXT_DBCN, reading and writing as required.
+Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
-A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
+Message-Id: <20221117225518.4102575-4-conor@kernel.org>
 host, takes around 20 seconds to boot without using DBCN. With this
 patch we're taking around 14 seconds to boot due to the speed-up in the
 terminal output.  There's no change in boot time if the guest isn't
 using earlycon.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/sbi_ecall_interface.h |  17 +++++
+ include/hw/misc/mchp_pfsoc_ioscb.h  |  3 ++
- target/riscv/kvm/kvm-cpu.c         | 111 +++++++++++++++++++++++++++++
+ include/hw/misc/mchp_pfsoc_sysreg.h |  1 +
-files changed, 128 insertions(+)
+ include/hw/riscv/microchip_pfsoc.h  |  1 +
+ hw/misc/mchp_pfsoc_ioscb.c          | 72 ++++++++++++++++++++++++++++-
-diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
+ hw/misc/mchp_pfsoc_sysreg.c         | 18 ++++++--
-index XXXXXXX..XXXXXXX 100644
+ hw/riscv/microchip_pfsoc.c          |  6 +++
---- a/target/riscv/sbi_ecall_interface.h
+files changed, 95 insertions(+), 6 deletions(-)
-+++ b/target/riscv/sbi_ecall_interface.h
-@@ -XXX,XX +XXX,XX @@
+diff --git a/include/hw/misc/mchp_pfsoc_ioscb.h b/include/hw/misc/mchp_pfsoc_ioscb.h
+index XXXXXXX..XXXXXXX 100644
- /* clang-format off */
+--- a/include/hw/misc/mchp_pfsoc_ioscb.h
++++ b/include/hw/misc/mchp_pfsoc_ioscb.h
-+#define SBI_SUCCESS                      0
+@@ -XXX,XX +XXX,XX @@ typedef struct MchpPfSoCIoscbState {
-+#define SBI_ERR_FAILED                  -1
+     MemoryRegion lane01;
-+#define SBI_ERR_NOT_SUPPORTED           -2
+     MemoryRegion lane23;
-+#define SBI_ERR_INVALID_PARAM           -3
+     MemoryRegion ctrl;
-+#define SBI_ERR_DENIED                  -4
++    MemoryRegion qspixip;
-+#define SBI_ERR_INVALID_ADDRESS         -5
++    MemoryRegion mailbox;
-+#define SBI_ERR_ALREADY_AVAILABLE       -6
+     MemoryRegion cfg;
-+#define SBI_ERR_ALREADY_STARTED         -7
+     MemoryRegion ccc;
-+#define SBI_ERR_ALREADY_STOPPED         -8
+     MemoryRegion pll_mss;
-+#define SBI_ERR_NO_SHMEM                -9
+@@ -XXX,XX +XXX,XX @@ typedef struct MchpPfSoCIoscbState {
-+
+     MemoryRegion cfm_sgmii;
- /* SBI Extension IDs */
+     MemoryRegion bc_sgmii;
- #define SBI_EXT_0_1_SET_TIMER           0x0
+     MemoryRegion io_calib_sgmii;
- #define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
++    qemu_irq irq;
-@@ -XXX,XX +XXX,XX @@
+ } MchpPfSoCIoscbState;
- #define SBI_EXT_IPI                     0x735049
- #define SBI_EXT_RFENCE                  0x52464E43
+ #define TYPE_MCHP_PFSOC_IOSCB "mchp.pfsoc.ioscb"
- #define SBI_EXT_HSM                     0x48534D
+diff --git a/include/hw/misc/mchp_pfsoc_sysreg.h b/include/hw/misc/mchp_pfsoc_sysreg.h
-+#define SBI_EXT_DBCN                    0x4442434E
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/misc/mchp_pfsoc_sysreg.h
- /* SBI function IDs for BASE extension */
++++ b/include/hw/misc/mchp_pfsoc_sysreg.h
- #define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
+@@ -XXX,XX +XXX,XX @@
-@@ -XXX,XX +XXX,XX @@
+ typedef struct MchpPfSoCSysregState {
- #define SBI_EXT_HSM_HART_STOP           0x1
+     SysBusDevice parent;
- #define SBI_EXT_HSM_HART_GET_STATUS     0x2
+     MemoryRegion sysreg;
++    qemu_irq irq;
-+/* SBI function IDs for DBCN extension */
+ } MchpPfSoCSysregState;
-+#define SBI_EXT_DBCN_CONSOLE_WRITE      0x0
-+#define SBI_EXT_DBCN_CONSOLE_READ       0x1
+ #define TYPE_MCHP_PFSOC_SYSREG "mchp.pfsoc.sysreg"
-+#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
+diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
-+
+index XXXXXXX..XXXXXXX 100644
- #define SBI_HSM_HART_STATUS_STARTED     0x0
+--- a/include/hw/riscv/microchip_pfsoc.h
- #define SBI_HSM_HART_STATUS_STOPPED     0x1
++++ b/include/hw/riscv/microchip_pfsoc.h
- #define SBI_HSM_HART_STATUS_START_PENDING   0x2
+@@ -XXX,XX +XXX,XX @@ enum {
-diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
+     MICROCHIP_PFSOC_MMUART2_IRQ = 92,
-index XXXXXXX..XXXXXXX 100644
+     MICROCHIP_PFSOC_MMUART3_IRQ = 93,
---- a/target/riscv/kvm/kvm-cpu.c
+     MICROCHIP_PFSOC_MMUART4_IRQ = 94,
-+++ b/target/riscv/kvm/kvm-cpu.c
++    MICROCHIP_PFSOC_MAILBOX_IRQ = 96,
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
                     KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
  };
-+static KVMCPUConfig kvm_sbi_dbcn = {
+ #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT    1
-+    .name = "sbi_dbcn",
+diff --git a/hw/misc/mchp_pfsoc_ioscb.c b/hw/misc/mchp_pfsoc_ioscb.c
-+    .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
+index XXXXXXX..XXXXXXX 100644
-+                  KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
+--- a/hw/misc/mchp_pfsoc_ioscb.c
-+};
++++ b/hw/misc/mchp_pfsoc_ioscb.c
-+
+@@ -XXX,XX +XXX,XX @@
- static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
+ #include "qemu/bitops.h"
- {
+ #include "qemu/log.h"
-     CPURISCVState *env = &cpu->env;
+ #include "qapi/error.h"
-@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
++#include "hw/irq.h"
-     return 0;
+ #include "hw/sysbus.h"
- }
+ #include "hw/misc/mchp_pfsoc_ioscb.h"
-+static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
+@@ -XXX,XX +XXX,XX @@
-+                                             KVMScratchCPU *kvmcpu,
+ #define IOSCB_WHOLE_REG_SIZE        0x10000000
-+                                             struct kvm_reg_list *reglist)
+ #define IOSCB_SUBMOD_REG_SIZE       0x1000
  #define IOSCB_CCC_REG_SIZE          0x2000000
 +#define IOSCB_CTRL_REG_SIZE         0x800
 +#define IOSCB_QSPIXIP_REG_SIZE      0x200
 +
  /*
   * There are many sub-modules in the IOSCB module.
@@ -XXX,XX +XXX,XX @@
  #define IOSCB_LANE01_BASE           0x06500000
  #define IOSCB_LANE23_BASE           0x06510000
  #define IOSCB_CTRL_BASE             0x07020000
 +#define IOSCB_QSPIXIP_BASE          0x07020100
 +#define IOSCB_MAILBOX_BASE          0x07020800
  #define IOSCB_CFG_BASE              0x07080000
  #define IOSCB_CCC_BASE              0x08000000
  #define IOSCB_PLL_MSS_BASE          0x0E001000
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps mchp_pfsoc_io_calib_ddr_ops = {
      .endianness = DEVICE_LITTLE_ENDIAN,
  };
 +#define SERVICES_CR             0x50
 +#define SERVICES_SR             0x54
 +#define SERVICES_STATUS_SHIFT   16
 +
 +static uint64_t mchp_pfsoc_ctrl_read(void *opaque, hwaddr offset,
 +                                     unsigned size)
 +{
-+    struct kvm_reg_list *reg_search;
++    uint32_t val = 0;
 +
-+    reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
++    switch (offset) {
-+                         sizeof(uint64_t), uint64_cmp);
++    case SERVICES_SR:
-+
++        /*
-+    if (reg_search) {
++         * Although some services have no error codes, most do. All services
-+        kvm_sbi_dbcn.supported = true;
++         * that do implement errors, begin their error codes at 1. Treat all
 +         * service requests as failures & return 1.
 +         * See the "PolarFire® FPGA and PolarFire SoC FPGA System Services"
 +         * user guide for more information on service error codes.
 +         */
 +        val = 1u << SERVICES_STATUS_SHIFT;
 +        break;
 +    default:
 +        qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
 +                      "(size %d, offset 0x%" HWADDR_PRIx ")\n",
 +                      __func__, size, offset);
 +    }
 +
 +    return val;
 +}
 +
 +static void mchp_pfsoc_ctrl_write(void *opaque, hwaddr offset,
 +                                  uint64_t value, unsigned size)
 +{
 +    MchpPfSoCIoscbState *s = opaque;
 +
 +    switch (offset) {
 +    case SERVICES_CR:
 +        qemu_irq_raise(s->irq);
 +        break;
 +    default:
 +        qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
 +                      "(size %d, value 0x%" PRIx64
 +                      ", offset 0x%" HWADDR_PRIx ")\n",
 +                      __func__, size, value, offset);
 +    }
 +}
 +
- static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
++static const MemoryRegionOps mchp_pfsoc_ctrl_ops = {
-                                  struct kvm_reg_list *reglist)
++    .read = mchp_pfsoc_ctrl_read,
 +    .write = mchp_pfsoc_ctrl_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +};
 +
  static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp)
  {
-@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
+     MchpPfSoCIoscbState *s = MCHP_PFSOC_IOSCB(dev);
-     if (riscv_has_ext(&cpu->env, RVV)) {
+@@ -XXX,XX +XXX,XX @@ static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp)
-         kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
+                           "mchp.pfsoc.ioscb.lane23", IOSCB_SUBMOD_REG_SIZE);
-     }
+     memory_region_add_subregion(&s->container, IOSCB_LANE23_BASE, &s->lane23);
-+
-+    kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
+-    memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
 -                          "mchp.pfsoc.ioscb.ctrl", IOSCB_SUBMOD_REG_SIZE);
 +    memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_ctrl_ops, s,
 +                          "mchp.pfsoc.ioscb.ctrl", IOSCB_CTRL_REG_SIZE);
      memory_region_add_subregion(&s->container, IOSCB_CTRL_BASE, &s->ctrl);
 +    memory_region_init_io(&s->qspixip, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
 +                          "mchp.pfsoc.ioscb.qspixip", IOSCB_QSPIXIP_REG_SIZE);
 +    memory_region_add_subregion(&s->container, IOSCB_QSPIXIP_BASE, &s->qspixip);
 +
 +    memory_region_init_io(&s->mailbox, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
 +                          "mchp.pfsoc.ioscb.mailbox", IOSCB_SUBMOD_REG_SIZE);
 +    memory_region_add_subregion(&s->container, IOSCB_MAILBOX_BASE, &s->mailbox);
 +
      memory_region_init_io(&s->cfg, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
                            "mchp.pfsoc.ioscb.cfg", IOSCB_SUBMOD_REG_SIZE);
      memory_region_add_subregion(&s->container, IOSCB_CFG_BASE, &s->cfg);
@@ -XXX,XX +XXX,XX @@ static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp)
                            IOSCB_SUBMOD_REG_SIZE);
      memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_SGMII_BASE,
                                  &s->io_calib_sgmii);
 +
 +    sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
  }
- static void riscv_init_kvm_registers(Object *cpu_obj)
+ static void mchp_pfsoc_ioscb_class_init(ObjectClass *klass, void *data)
-@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
+diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c
-     return ret;
+index XXXXXXX..XXXXXXX 100644
- }
+--- a/hw/misc/mchp_pfsoc_sysreg.c
++++ b/hw/misc/mchp_pfsoc_sysreg.c
-+static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
+@@ -XXX,XX +XXX,XX @@
-+{
+ #include "qemu/bitops.h"
-+    target_ulong reg = 1;
+ #include "qemu/log.h"
-+
+ #include "qapi/error.h"
-+    if (!kvm_sbi_dbcn.supported) {
++#include "hw/irq.h"
-+        return 0;
+ #include "hw/sysbus.h"
-+    }
+ #include "hw/misc/mchp_pfsoc_sysreg.h"
-+
-+    return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
+ #define ENVM_CR         0xb8
-+}
++#define MESSAGE_INT     0x118c
-+
- int kvm_arch_init_vcpu(CPUState *cs)
+ static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset,
                                         unsigned size)
@@ -XXX,XX +XXX,XX @@ static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset,
  static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset,
                                      uint64_t value, unsigned size)
  {
-     int ret = 0;
+-    qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
-@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
+-                  "(size %d, value 0x%" PRIx64
-     kvm_riscv_update_cpu_misa_ext(cpu, cs);
+-                  ", offset 0x%" HWADDR_PRIx ")\n",
-     kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
+-                  __func__, size, value, offset);
++    MchpPfSoCSysregState *s = opaque;
-+    ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
++    switch (offset) {
-+
++    case MESSAGE_INT:
-     return ret;
++        qemu_irq_lower(s->irq);
  }
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
      return true;
  }
 +static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
 +{
 +    g_autofree uint8_t *buf = NULL;
 +    RISCVCPU *cpu = RISCV_CPU(cs);
 +    target_ulong num_bytes;
 +    uint64_t addr;
 +    unsigned char ch;
 +    int ret;
 +
 +    switch (run->riscv_sbi.function_id) {
 +    case SBI_EXT_DBCN_CONSOLE_READ:
 +    case SBI_EXT_DBCN_CONSOLE_WRITE:
 +        num_bytes = run->riscv_sbi.args[0];
 +
 +        if (num_bytes == 0) {
 +            run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +            run->riscv_sbi.ret[1] = 0;
 +            break;
 +        }
 +
 +        addr = run->riscv_sbi.args[1];
 +
 +        /*
 +         * Handle the case where a 32 bit CPU is running in a
 +         * 64 bit addressing env.
 +         */
 +        if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
 +            addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
 +        }
 +
 +        buf = g_malloc0(num_bytes);
 +
 +        if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
 +            ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
 +            if (ret < 0) {
 +                error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
 +                             "reading chardev");
 +                exit(1);
 +            }
 +
 +            cpu_physical_memory_write(addr, buf, ret);
 +        } else {
 +            cpu_physical_memory_read(addr, buf, num_bytes);
 +
 +            ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
 +            if (ret < 0) {
 +                error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
 +                             "writing chardev");
 +                exit(1);
 +            }
 +        }
 +
 +        run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +        run->riscv_sbi.ret[1] = ret;
 +        break;
 +    case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
 +        ch = run->riscv_sbi.args[0];
 +        ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
 +
 +        if (ret < 0) {
 +            error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
 +                         "writing chardev");
 +            exit(1);
 +        }
 +
 +        run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +        run->riscv_sbi.ret[1] = 0;
 +        break;
 +    default:
-+        run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
++        qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
 +                      "(size %d, value 0x%" PRIx64
 +                      ", offset 0x%" HWADDR_PRIx ")\n",
 +                      __func__, size, value, offset);
 +    }
-+}
+ }
-+
- static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
+ static const MemoryRegionOps mchp_pfsoc_sysreg_ops = {
- {
+@@ -XXX,XX +XXX,XX @@ static void mchp_pfsoc_sysreg_realize(DeviceState *dev, Error **errp)
-     int ret = 0;
+                           "mchp.pfsoc.sysreg",
-@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
+                           MCHP_PFSOC_SYSREG_REG_SIZE);
-         }
+     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysreg);
-         ret = 0;
++    sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
-         break;
+ }
-+    case SBI_EXT_DBCN:
-+        kvm_riscv_handle_sbi_dbcn(cs, run);
+ static void mchp_pfsoc_sysreg_class_init(ObjectClass *klass, void *data)
-+        break;
+diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
-     default:
+index XXXXXXX..XXXXXXX 100644
-         qemu_log_mask(LOG_UNIMP,
+--- a/hw/riscv/microchip_pfsoc.c
-                       "%s: un-handled SBI EXIT, specific reasons is %lu\n",
++++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
      sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp);
      sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0,
                      memmap[MICROCHIP_PFSOC_SYSREG].base);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sysreg), 0,
 +                       qdev_get_gpio_in(DEVICE(s->plic),
 +                       MICROCHIP_PFSOC_MAILBOX_IRQ));
      /* AXISW */
      create_unimplemented_device("microchip.pfsoc.axisw",
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
      sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp);
      sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
                      memmap[MICROCHIP_PFSOC_IOSCB].base);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioscb), 0,
 +                       qdev_get_gpio_in(DEVICE(s->plic),
 +                       MICROCHIP_PFSOC_MAILBOX_IRQ));
      /* FPGA Fabric */
      create_unimplemented_device("microchip.pfsoc.fabricfic3",
 --
-.45.1
+.38.1

-New patch
+[PULL v2 24/45] hw/intc: sifive_plic: fix out-of-bound access of source_priority array
+From: Jim Shu <jim.shu@sifive.com>
+If the number of interrupt is not multiple of 32, PLIC will have
+out-of-bound access to source_priority array. Compute the number of
+interrupt in the last word to avoid this out-of-bound access of array.
+Signed-off-by: Jim Shu <jim.shu@sifive.com>
+Reviewed-by: Bin Meng <bmeng@tinylab.org>
+Message-Id: <20221127165753.30533-1-jim.shu@sifive.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/intc/sifive_plic.c | 12 +++++++++++-
+file changed, 11 insertions(+), 1 deletion(-)
+diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/sifive_plic.c
++++ b/hw/intc/sifive_plic.c
+@@ -XXX,XX +XXX,XX @@ static uint32_t sifive_plic_claimed(SiFivePLICState *plic, uint32_t addrid)
+     uint32_t max_irq = 0;
+     uint32_t max_prio = plic->target_priority[addrid];
+     int i, j;
++    int num_irq_in_word = 32;
+     for (i = 0; i < plic->bitfield_words; i++) {
+         uint32_t pending_enabled_not_claimed =
+@@ -XXX,XX +XXX,XX @@ static uint32_t sifive_plic_claimed(SiFivePLICState *plic, uint32_t addrid)
+             continue;
+         }
+-        for (j = 0; j < 32; j++) {
++        if (i == (plic->bitfield_words - 1)) {
++            /*
++             * If plic->num_sources is not multiple of 32, num-of-irq in last
++             * word is not 32. Compute the num-of-irq of last word to avoid
++             * out-of-bound access of source_priority array.
++             */
++            num_irq_in_word = plic->num_sources - ((plic->bitfield_words - 1) << 5);
++        }
++
++        for (j = 0; j < num_irq_in_word; j++) {
+             int irq = (i << 5) + j;
+             uint32_t prio = plic->source_priority[irq];
+             int enabled = pending_enabled_not_claimed & (1 << j);
+--
+.38.1

-[PULL 26/28] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
+[PULL v2 25/45] target/riscv: Fix mret exception cause when no pmp rule is configured
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Bin Meng <bmeng@tinylab.org>
-Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
+The priv spec v1.12 says:
 in bytes, when in this context we want 'reg_width' as the length in
 bits.
-Fix 'reg_width' back to the value in bits like 7cb59921c05a
+  If no PMP entry matches an M-mode access, the access succeeds. If
-("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
+  no PMP entry matches an S-mode or U-mode access, but at least one
-beforehand.
+  PMP entry is implemented, the access fails. Failed accesses generate
   an instruction, load, or store access-fault exception.
-While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
+At present the exception cause is set to 'illegal instruction' but
-clarity about what the variable represents. 'bitsize' is also used in
+should have been 'instruction access fault'.
 riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
 gdb_feature_builder_append_reg().
-Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
+Fixes: d102f19a2085 ("target/riscv/pmp: Raise exception if no PMP entry is configured")
-Cc: Alex Bennée <alex.bennee@linaro.org>
+Signed-off-by: Bin Meng <bmeng@tinylab.org>
-Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
+Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
 Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Acked-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-Id: <20221205065303.204095-1-bmeng@tinylab.org>
 Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/gdbstub.c | 6 +++---
+ target/riscv/op_helper.c | 2 +-
-file changed, 3 insertions(+), 3 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
+diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/gdbstub.c
+--- a/target/riscv/op_helper.c
-+++ b/target/riscv/gdbstub.c
++++ b/target/riscv/op_helper.c
-@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_mret(CPURISCVState *env)
- static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
- {
+     if (riscv_feature(env, RISCV_FEATURE_PMP) &&
-     RISCVCPU *cpu = RISCV_CPU(cs);
+         !pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
--    int reg_width = cpu->cfg.vlenb;
+-        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
-+    int bitsize = cpu->cfg.vlenb << 3;
++        riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC());
      GDBFeatureBuilder builder;
      int i;
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
      /* First define types and totals in a whole VL */
      for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
 -        int count = reg_width / vec_lanes[i].size;
 +        int count = bitsize / vec_lanes[i].size;
          gdb_feature_builder_append_tag(
              &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
              vec_lanes[i].id, vec_lanes[i].gdb_type, count);
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
      /* Define vector registers */
      for (i = 0; i < 32; i++) {
          gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
 -                                       reg_width, i, "riscv_vector", "vector");
 +                                       bitsize, i, "riscv_vector", "vector");
      }
-     gdb_feature_builder_end(&builder);
+     target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
 --
-.45.1
+.38.1

-New patch
+[PULL v2 26/45] target/riscv: Set pc_succ_insn for !rvc illegal insn
+From: Richard Henderson <richard.henderson@linaro.org>
+Failure to set pc_succ_insn may result in a TB covering zero bytes,
+which triggers an assert within the code generator.
+Cc: qemu-stable@nongnu.org
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1224
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-Id: <20221203175744.151365-1-richard.henderson@linaro.org>
+[ Changes by AF:
+ - Add missing run-plugin-test-noc-% line
+]
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/translate.c          | 12 ++++--------
+ tests/tcg/Makefile.target         |  2 ++
+ tests/tcg/riscv64/Makefile.target |  6 ++++++
+ tests/tcg/riscv64/test-noc.S      | 32 +++++++++++++++++++++++++++++++
+files changed, 44 insertions(+), 8 deletions(-)
+ create mode 100644 tests/tcg/riscv64/test-noc.S
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/translate.c
++++ b/target/riscv/translate.c
+@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
+     ctx->virt_inst_excp = false;
+     /* Check for compressed insn */
+     if (insn_len(opcode) == 2) {
+-        if (!has_ext(ctx, RVC)) {
+-            gen_exception_illegal(ctx);
+-        } else {
+-            ctx->opcode = opcode;
+-            ctx->pc_succ_insn = ctx->base.pc_next + 2;
+-            if (decode_insn16(ctx, opcode)) {
+-                return;
+-            }
++        ctx->opcode = opcode;
++        ctx->pc_succ_insn = ctx->base.pc_next + 2;
++        if (has_ext(ctx, RVC) && decode_insn16(ctx, opcode)) {
++            return;
+         }
+     } else {
+         uint32_t opcode32 = opcode;
+diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/tcg/Makefile.target
++++ b/tests/tcg/Makefile.target
+@@ -XXX,XX +XXX,XX @@ endif
+ %: %.c
+     $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
++%: %.S
++    $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
+ else
+ # For softmmu targets we include a different Makefile fragement as the
+ # build options for bare programs are usually pretty different. They
+diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile.target
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/tcg/riscv64/Makefile.target
++++ b/tests/tcg/riscv64/Makefile.target
+@@ -XXX,XX +XXX,XX @@
+ VPATH += $(SRC_PATH)/tests/tcg/riscv64
+ TESTS += test-div
+ TESTS += noexec
++
++# Disable compressed instructions for test-noc
++TESTS += test-noc
++test-noc: LDFLAGS = -nostdlib -static
++run-test-noc: QEMU_OPTS += -cpu rv64,c=false
++run-plugin-test-noc-%: QEMU_OPTS += -cpu rv64,c=false
+diff --git a/tests/tcg/riscv64/test-noc.S b/tests/tcg/riscv64/test-noc.S
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/tests/tcg/riscv64/test-noc.S
+@@ -XXX,XX +XXX,XX @@
++#include <asm/unistd.h>
++
++    .text
++    .globl _start
++_start:
++    .option    norvc
++    li    a0, 4        /* SIGILL */
++    la    a1, sa
++    li    a2, 0
++    li    a3, 8
++    li    a7, __NR_rt_sigaction
++    scall
++
++    .option    rvc
++    li    a0, 1
++    j    exit
++    .option    norvc
++
++pass:
++    li    a0, 0
++exit:
++    li    a7, __NR_exit
++    scall
++
++    .data
++    /* struct kernel_sigaction sa = { .sa_handler = pass }; */
++    .type    sa, @object
++    .size    sa, 32
++sa:
++    .dword    pass
++    .zero    24
++
+--
+.38.1

-[PULL 11/28] target/riscv: Add support for Zve64x extension
+[PULL v2 27/45] target/riscv: Simplify helper_sret() a little bit
-From: Jason Chien <jason.chien@sifive.com>
+From: Bin Meng <bmeng@tinylab.org>
-Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
+There are 2 paths in helper_sret() and the same mstatus update codes
-enabling Zve64x enables Zve32x according to their dependency.
+are replicated. Extract the common parts to simplify it a little bit.
-Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
+Signed-off-by: Bin Meng <bmeng@tinylab.org>
-Signed-off-by: Jason Chien <jason.chien@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Message-Id: <20221207090037.281452-1-bmeng@tinylab.org>
 Reviewed-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_cfg.h     |  1 +
+ target/riscv/op_helper.c | 20 ++++++--------------
- target/riscv/cpu.c         |  2 ++
+file changed, 6 insertions(+), 14 deletions(-)
  target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
 files changed, 14 insertions(+), 6 deletions(-)
-diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
+diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_cfg.h
+--- a/target/riscv/op_helper.c
-+++ b/target/riscv/cpu_cfg.h
++++ b/target/riscv/op_helper.c
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_sret(CPURISCVState *env)
      bool ext_zve32x;
      bool ext_zve64f;
      bool ext_zve64d;
 +    bool ext_zve64x;
      bool ext_zvbb;
      bool ext_zvbc;
      bool ext_zvkb;
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
      ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
      ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
      ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
 +    ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
      ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
      ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
      ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
      MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
      MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
      MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
 +    MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false),
      MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
      MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false),
      MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false),
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
      /* The Zve64d extension depends on the Zve64f extension */
      if (cpu->cfg.ext_zve64d) {
 +        if (!riscv_has_ext(env, RVD)) {
 +            error_setg(errp, "Zve64d/V extensions require D extension");
 +            return;
 +        }
          cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
      }
--    /* The Zve64f extension depends on the Zve32f extension */
+     mstatus = env->mstatus;
-+    /* The Zve64f extension depends on the Zve64x and Zve32f extensions */
++    prev_priv = get_field(mstatus, MSTATUS_SPP);
-     if (cpu->cfg.ext_zve64f) {
++    mstatus = set_field(mstatus, MSTATUS_SIE,
-+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true);
++                        get_field(mstatus, MSTATUS_SPIE));
-         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
++    mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
 +    mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
 +    env->mstatus = mstatus;
      if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
          /* We support Hypervisor extensions and virtulisation is disabled */
          target_ulong hstatus = env->hstatus;
 -        prev_priv = get_field(mstatus, MSTATUS_SPP);
          prev_virt = get_field(hstatus, HSTATUS_SPV);
          hstatus = set_field(hstatus, HSTATUS_SPV, 0);
 -        mstatus = set_field(mstatus, MSTATUS_SPP, 0);
 -        mstatus = set_field(mstatus, SSTATUS_SIE,
 -                            get_field(mstatus, SSTATUS_SPIE));
 -        mstatus = set_field(mstatus, SSTATUS_SPIE, 1);
 -        env->mstatus = mstatus;
          env->hstatus = hstatus;
          if (prev_virt) {
@@ -XXX,XX +XXX,XX @@ target_ulong helper_sret(CPURISCVState *env)
          }
          riscv_cpu_set_virt_enabled(env, prev_virt);
 -    } else {
 -        prev_priv = get_field(mstatus, MSTATUS_SPP);
 -
 -        mstatus = set_field(mstatus, MSTATUS_SIE,
 -                            get_field(mstatus, MSTATUS_SPIE));
 -        mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
 -        mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
 -        env->mstatus = mstatus;
      }
--    if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
+     riscv_cpu_set_mode(env, prev_priv);
 -        error_setg(errp, "Zve64d/V extensions require D extension");
 -        return;
 +    /* The Zve64x extension depends on the Zve32x extension */
 +    if (cpu->cfg.ext_zve64x) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
      }
      /* The Zve32f extension depends on the Zve32x extension */
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
          return;
      }
 -    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
 +    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) {
          error_setg(
              errp,
 -            "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
 +            "Zvbc and Zvknhb extensions require V or Zve64x extensions");
          return;
      }
 --
-.45.1
+.38.1

-[PULL 03/28] target/riscv: Raise exceptions on wrs.nto
+[PULL v2 28/45] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+
-From: Andrew Jones <ajones@ventanamicro.com>
+From: Bin Meng <bmeng@tinylab.org>
-Implementing wrs.nto to always just return is consistent with the
+Since priv spec v1.12, MRET and SRET now clear mstatus.MPRV when
-specification, as the instruction is permitted to terminate the
+leaving M-mode.
 stall for any reason, but it's not useful for virtualization, where
 we'd like the guest to trap to the hypervisor in order to allow
 scheduling of the lock holding VCPU. Change to always immediately
 raise exceptions when the appropriate conditions are present,
 otherwise continue to just return. Note, immediately raising
 exceptions is also consistent with the specification since the
 time limit that should expire prior to the exception is
 implementation-specific.
-Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
+Signed-off-by: Bin Meng <bmeng@tinylab.org>
 Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
+Message-Id: <20221207090037.281452-2-bmeng@tinylab.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/helper.h                       |  1 +
+ target/riscv/op_helper.c | 6 ++++++
- target/riscv/op_helper.c                    | 11 ++++++++
+file changed, 6 insertions(+)
  target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
 files changed, 32 insertions(+), 9 deletions(-)
-diff --git a/target/riscv/helper.h b/target/riscv/helper.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/helper.h
-+++ b/target/riscv/helper.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
- DEF_HELPER_1(sret, tl, env)
- DEF_HELPER_1(mret, tl, env)
- DEF_HELPER_1(wfi, void, env)
-+DEF_HELPER_1(wrs_nto, void, env)
- DEF_HELPER_1(tlb_flush, void, env)
- DEF_HELPER_1(tlb_flush_all, void, env)
- /* Native Debug */
 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/op_helper.c
 +++ b/target/riscv/op_helper.c
-@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_sret(CPURISCVState *env)
-     }
+                         get_field(mstatus, MSTATUS_SPIE));
- }
+     mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
+     mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
-+void helper_wrs_nto(CPURISCVState *env)
++    if (env->priv_ver >= PRIV_VERSION_1_12_0) {
-+{
++        mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
 +    if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
 +        get_field(env->hstatus, HSTATUS_VTW) &&
 +        !get_field(env->mstatus, MSTATUS_TW)) {
 +        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
 +    } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
 +        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 +    }
-+}
+     env->mstatus = mstatus;
-+
- void helper_tlb_flush(CPURISCVState *env)
+     if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
- {
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_mret(CPURISCVState *env)
-     CPUState *cs = env_cpu(env);
+     mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
-diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
+     mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
-index XXXXXXX..XXXXXXX 100644
+     mstatus = set_field(mstatus, MSTATUS_MPV, 0);
---- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
++    if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {
-+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
++        mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
@@ -XXX,XX +XXX,XX @@
   * this program.  If not, see <http://www.gnu.org/licenses/>.
   */
 -static bool trans_wrs(DisasContext *ctx)
 +static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
  {
      if (!ctx->cfg_ptr->ext_zawrs) {
          return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
      return true;
  }
 -#define GEN_TRANS_WRS(insn)                                     \
 -static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
 -{                                                               \
 -    (void)a;                                                    \
 -    return trans_wrs(ctx);                                      \
 -}
 +static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
 +{
 +    if (!ctx->cfg_ptr->ext_zawrs) {
 +        return false;
 +    }
+     env->mstatus = mstatus;
--GEN_TRANS_WRS(wrs_nto)
+     riscv_cpu_set_mode(env, prev_priv);
--GEN_TRANS_WRS(wrs_sto)
 +    /*
 +     * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
 +     * should raise an exception when the implementation-specific bounded time
 +     * limit has expired. Our time limit is zero, so we either return
 +     * immediately, as does our implementation of wrs.sto, or raise an
 +     * exception, as handled by the wrs.nto helper.
 +     */
 +#ifndef CONFIG_USER_ONLY
 +    gen_helper_wrs_nto(tcg_env);
 +#endif
 +
 +    /* We only get here when helper_wrs_nto() doesn't raise an exception. */
 +    return trans_wrs_sto(ctx, NULL);
 +}
 --
-.45.1
+.38.1

-[PULL 16/28] riscv: thead: Add th.sxstatus CSR emulation
+[PULL v2 29/45] RISC-V: Add Zawrs ISA extension support
-From: Christoph Müllner <christoph.muellner@vrull.eu>
+From: Christoph Muellner <christoph.muellner@vrull.eu>
-The th.sxstatus CSR can be used to identify available custom extension
+This patch adds support for the Zawrs ISA extension.
-on T-Head CPUs. The CSR is documented here:
+Given the current (incomplete) implementation of reservation sets
-  https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc
+there seems to be no way to provide a full emulation of the WRS
 instruction (wake on reservation set invalidation or timeout or
 interrupt). Therefore, we just exit the TB and return to the main loop.
-An important property of this patch is, that the th.sxstatus MAEE field
+The specification can be found here:
-is not set (indicating that XTheadMae is not available).
+  https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc
 XTheadMae is a memory attribute extension (similar to Svpbmt) which is
 implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
 in PTEs that are marked as reserved. QEMU maintainers prefer to not
 implement XTheadMae, so we need give kernels a mechanism to identify
 if XTheadMae is available in a system or not. And this patch introduces
 this mechanism in QEMU in a way that's compatible with real HW
 (i.e., probing the th.sxstatus.MAEE bit).
-Further context can be found on the list:
+Note, that the Zawrs extension is frozen, but not ratified yet.
 https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html
-Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
+Changes since v3:
 * Remove "RFC" since the extension is frozen
 * Rebase on master and fix integration issues
 * Fix entry ordering in extension list
 Changes since v2:
 * Rebase on master and resolve conflicts
 * Adjustments according to a specification change
 * Inline REQUIRE_ZAWRS() since it has only one user
 Changes since v1:
 * Adding zawrs to the ISA string that is passed to the kernel
 Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
+Message-Id: <20221005144948.3421504-1-christoph.muellner@vrull.eu>
 Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- MAINTAINERS              |  1 +
+ target/riscv/cpu.h                          |  1 +
- target/riscv/cpu.h       |  3 ++
+ target/riscv/insn32.decode                  |  4 ++
- target/riscv/cpu.c       |  1 +
+ target/riscv/cpu.c                          |  7 +++
- target/riscv/th_csr.c    | 79 ++++++++++++++++++++++++++++++++++++++++
+ target/riscv/translate.c                    |  1 +
- target/riscv/meson.build |  1 +
+ target/riscv/insn_trans/trans_rvzawrs.c.inc | 51 +++++++++++++++++++++
-files changed, 85 insertions(+)
+files changed, 64 insertions(+)
- create mode 100644 target/riscv/th_csr.c
+ create mode 100644 target/riscv/insn_trans/trans_rvzawrs.c.inc
-diff --git a/MAINTAINERS b/MAINTAINERS
-index XXXXXXX..XXXXXXX 100644
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
- S: Supported
- F: target/riscv/insn_trans/trans_xthead.c.inc
- F: target/riscv/xthead*.decode
-+F: target/riscv/th_*
- F: disas/riscv-xthead*
- RISC-V XVentanaCondOps extension
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
- uint8_t satp_mode_max_from_map(uint32_t map);
+     bool ext_svnapot;
- const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
+     bool ext_svpbmt;
+     bool ext_zdinx;
-+/* Implemented in th_csr.c */
++    bool ext_zawrs;
-+void th_register_custom_csrs(RISCVCPU *cpu);
+     bool ext_zfh;
      bool ext_zfhmin;
      bool ext_zfinx;
 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn32.decode
 +++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm11
  vsetivli        11 .......... ..... 111 ..... 1010111  @r2_zimm10
  vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
 +# *** Zawrs Standard Extension ***
 +wrs_nto    000000001101 00000 000 00000 1110011
 +wrs_sto    000000011101 00000 000 00000 1110011
 +
- #endif /* RISCV_CPU_H */
+ # *** RV32 Zba Standard Extension ***
  sh1add     0010000 .......... 010 ..... 0110011 @r
  sh2add     0010000 .......... 100 ..... 0110011 @r
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
-     cpu->cfg.mvendorid = THEAD_VENDOR_ID;
+     ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr),
- #ifndef CONFIG_USER_ONLY
+     ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
-     set_satp_mode_max_supported(cpu, VM_1_10_SV39);
+     ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause),
-+    th_register_custom_csrs(cpu);
++    ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs),
- #endif
+     ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh),
+     ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
-     /* inherited from parent obj via riscv_cpu_init() */
+     ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
-diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
              return;
          }
 +        if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) {
 +            error_setg(errp, "Zawrs extension requires A extension");
 +            return;
 +        }
 +
          if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) {
              error_setg(errp, "Zfh/Zfhmin extensions require F extension");
              return;
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
      DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
      DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
      DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
 +    DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true),
      DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
      DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
      DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
  #include "insn_trans/trans_rvh.c.inc"
  #include "insn_trans/trans_rvv.c.inc"
  #include "insn_trans/trans_rvb.c.inc"
 +#include "insn_trans/trans_rvzawrs.c.inc"
  #include "insn_trans/trans_rvzfh.c.inc"
  #include "insn_trans/trans_rvk.c.inc"
  #include "insn_trans/trans_privileged.c.inc"
 diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/target/riscv/th_csr.c
++++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * T-Head-specific CSRs.
++ * RISC-V translation routines for the RISC-V Zawrs Extension.
 + *
-+ * Copyright (c) 2024 VRULL GmbH
++ * Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.io
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 ...
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
-+#include "qemu/osdep.h"
++static bool trans_wrs(DisasContext *ctx)
 +#include "cpu.h"
 +#include "cpu_vendorid.h"
 +
 +#define CSR_TH_SXSTATUS 0x5c0
 +
 +/* TH_SXSTATUS bits */
 +#define TH_SXSTATUS_UCME        BIT(16)
 +#define TH_SXSTATUS_MAEE        BIT(21)
 +#define TH_SXSTATUS_THEADISAEE  BIT(22)
 +
 +typedef struct {
 +    int csrno;
 +    int (*insertion_test)(RISCVCPU *cpu);
 +    riscv_csr_operations csr_ops;
 +} riscv_csr;
 +
 +static RISCVException smode(CPURISCVState *env, int csrno)
 +{
-+    if (riscv_has_ext(env, RVS)) {
++    if (!ctx->cfg_ptr->ext_zawrs) {
-+        return RISCV_EXCP_NONE;
++        return false;
 +    }
 +
-+    return RISCV_EXCP_ILLEGAL_INST;
++    /*
 +     * The specification says:
 +     * While stalled, an implementation is permitted to occasionally
 +     * terminate the stall and complete execution for any reason.
 +     *
 +     * So let's just exit TB and return to the main loop.
 +     */
 +
 +    /* Clear the load reservation  (if any).  */
 +    tcg_gen_movi_tl(load_res, -1);
 +
 +    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
 +    tcg_gen_exit_tb(NULL, 0);
 +    ctx->base.is_jmp = DISAS_NORETURN;
 +
 +    return true;
 +}
 +
-+static int test_thead_mvendorid(RISCVCPU *cpu)
++#define GEN_TRANS_WRS(insn)                                     \
-+{
++static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
-+    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
++{                                                               \
-+        return -1;
++    (void)a;                                                    \
-+    }
++    return trans_wrs(ctx);                                      \
 +
 +    return 0;
 +}
 +
-+static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
++GEN_TRANS_WRS(wrs_nto)
-+                                       target_ulong *val)
++GEN_TRANS_WRS(wrs_sto)
 +{
 +    /* We don't set MAEE here, because QEMU does not implement MAEE. */
 +    *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
 +    return RISCV_EXCP_NONE;
 +}
 +
 +static riscv_csr th_csr_list[] = {
 +    {
 +        .csrno = CSR_TH_SXSTATUS,
 +        .insertion_test = test_thead_mvendorid,
 +        .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
 +    }
 +};
 +
 +void th_register_custom_csrs(RISCVCPU *cpu)
 +{
 +    for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
 +        int csrno = th_csr_list[i].csrno;
 +        riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
 +        if (!th_csr_list[i].insertion_test(cpu)) {
 +            riscv_set_csr_ops(csrno, csr_ops);
 +        }
 +    }
 +}
 diff --git a/target/riscv/meson.build b/target/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/meson.build
 +++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
    'monitor.c',
    'machine.c',
    'pmu.c',
 +  'th_csr.c',
    'time_helper.c',
    'riscv-qmp-cmds.c',
  ))
 --
-.45.1
+.38.1

-New patch
+[PULL v2 30/45] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC
+From: Bin Meng <bmeng@tinylab.org>
+hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
+controllers regardless of how MSI is implemented. msi_nonbroken is
+initialized to true in sifive_plic_realize().
+Let SIFIVE_PLIC select MSI_NONBROKEN and drop the selection from
+RISC-V machines.
+Signed-off-by: Bin Meng <bmeng@tinylab.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+Message-Id: <20221211030829.802437-1-bmeng@tinylab.org>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/intc/Kconfig  | 1 +
+ hw/riscv/Kconfig | 5 -----
+files changed, 1 insertion(+), 5 deletions(-)
+diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/Kconfig
++++ b/hw/intc/Kconfig
+@@ -XXX,XX +XXX,XX @@ config RISCV_IMSIC
+ config SIFIVE_PLIC
+     bool
++    select MSI_NONBROKEN
+ config GOLDFISH_PIC
+     bool
+diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/Kconfig
++++ b/hw/riscv/Kconfig
+@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
+     select MCHP_PFSOC_IOSCB
+     select MCHP_PFSOC_MMUART
+     select MCHP_PFSOC_SYSREG
+-    select MSI_NONBROKEN
+     select RISCV_ACLINT
+     select SIFIVE_PDMA
+     select SIFIVE_PLIC
+@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
+     imply TPM_TIS_SYSBUS
+     select RISCV_NUMA
+     select GOLDFISH_RTC
+-    select MSI_NONBROKEN
+     select PCI
+     select PCI_EXPRESS_GENERIC_BRIDGE
+     select PFLASH_CFI01
+@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
+ config SIFIVE_E
+     bool
+-    select MSI_NONBROKEN
+     select RISCV_ACLINT
+     select SIFIVE_GPIO
+     select SIFIVE_PLIC
+@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
+ config SIFIVE_U
+     bool
+     select CADENCE
+-    select MSI_NONBROKEN
+     select RISCV_ACLINT
+     select SIFIVE_GPIO
+     select SIFIVE_PDMA
+@@ -XXX,XX +XXX,XX @@ config SPIKE
+     bool
+     select RISCV_NUMA
+     select HTIF
+-    select MSI_NONBROKEN
+     select RISCV_ACLINT
+     select SIFIVE_PLIC
+--
+.38.1

-[PULL 09/28] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
+[PULL v2 31/45] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Bin Meng <bmeng@tinylab.org>
-Privileged spec section 4.1.9 mentions:
+hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
 controllers regardless of how MSI is implemented. msi_nonbroken is
 initialized to true in both riscv_aplic_realize() and
 riscv_imsic_realize().
-"When a trap is taken into S-mode, stval is written with
+Select MSI_NONBROKEN in RISCV_APLIC and RISCV_IMSIC.
 exception-specific information to assist software in handling the trap.
 (...)
-If stval is written with a nonzero value when a breakpoint,
+Signed-off-by: Bin Meng <bmeng@tinylab.org>
 address-misaligned, access-fault, or page-fault exception occurs on an
 instruction fetch, load, or store, then stval will contain the faulting
 virtual address."
 A similar text is found for mtval in section 3.1.16.
 Setting mtval/stval in this scenario is optional, but some softwares read
 these regs when handling ebreaks.
 Write 'badaddr' in all ebreak breakpoints to write the appropriate
 'tval' during riscv_do_cpu_interrrupt().
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-Id: <20221211030829.802437-2-bmeng@tinylab.org>
 Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
+ hw/intc/Kconfig | 2 ++
 file changed, 2 insertions(+)
-diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
+diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_privileged.c.inc
+--- a/hw/intc/Kconfig
-+++ b/target/riscv/insn_trans/trans_privileged.c.inc
++++ b/hw/intc/Kconfig
-@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
+@@ -XXX,XX +XXX,XX @@ config RISCV_ACLINT
-     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
-         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
+ config RISCV_APLIC
-     } else {
+     bool
-+        tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
++    select MSI_NONBROKEN
-+                      offsetof(CPURISCVState, badaddr));
-         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
+ config RISCV_IMSIC
-     }
+     bool
-     return true;
++    select MSI_NONBROKEN
  config SIFIVE_PLIC
      bool
 --
-.45.1
+.38.1

-[PULL 19/28] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
+[PULL v2 32/45] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC
-From: Max Chou <max.chou@sifive.com>
+From: Bin Meng <bmeng@tinylab.org>
-The opfv_narrow_check needs to check the single width float operator by
+Since commit ef6310064820 ("hw/riscv: opentitan: Update to the latest build")
-require_rvf.
+the IBEX PLIC model was replaced with the SiFive PLIC model in the
 'opentitan' machine but we forgot the add the dependency there.
-Signed-off-by: Max Chou <max.chou@sifive.com>
+Signed-off-by: Bin Meng <bmeng@tinylab.org>
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
-Cc: qemu-stable <qemu-stable@nongnu.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20240322092600.1198921-4-max.chou@sifive.com>
+Message-Id: <20221211030829.802437-3-bmeng@tinylab.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvv.c.inc | 1 +
+ hw/riscv/Kconfig | 1 +
 file changed, 1 insertion(+)
-diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.c.inc
+--- a/hw/riscv/Kconfig
-+++ b/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/hw/riscv/Kconfig
-@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
+@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
- static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
+ config OPENTITAN
- {
+     bool
-     return opfv_narrow_check(s, a) &&
+     select IBEX
-+           require_rvf(s) &&
++    select SIFIVE_PLIC
-            require_scale_rvf(s) &&
+     select UNIMP
-            (s->sew != MO_8);
- }
+ config SHAKTI_C
 --
-.45.1
+.38.1

-New patch
+[PULL v2 33/45] hw/riscv: Sort machines Kconfig options in alphabetical order
+From: Bin Meng <bmeng@tinylab.org>
+SHAKTI_C machine Kconfig option was inserted in disorder. Fix it.
+Signed-off-by: Bin Meng <bmeng@tinylab.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+Message-Id: <20221211030829.802437-4-bmeng@tinylab.org>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/riscv/Kconfig | 16 +++++++++-------
+file changed, 9 insertions(+), 7 deletions(-)
+diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/Kconfig
++++ b/hw/riscv/Kconfig
+@@ -XXX,XX +XXX,XX @@ config RISCV_NUMA
+ config IBEX
+     bool
++# RISC-V machines in alphabetical order
++
+ config MICROCHIP_PFSOC
+     bool
+     select CADENCE_SDHCI
+@@ -XXX,XX +XXX,XX @@ config OPENTITAN
+     select SIFIVE_PLIC
+     select UNIMP
+-config SHAKTI_C
+-    bool
+-    select UNIMP
+-    select SHAKTI_UART
+-    select RISCV_ACLINT
+-    select SIFIVE_PLIC
+-
+ config RISCV_VIRT
+     bool
+     imply PCI_DEVICES
+@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
+     select FW_CFG_DMA
+     select PLATFORM_BUS
++config SHAKTI_C
++    bool
++    select RISCV_ACLINT
++    select SHAKTI_UART
++    select SIFIVE_PLIC
++    select UNIMP
++
+ config SIFIVE_E
+     bool
+     select RISCV_ACLINT
+--
+.38.1

-New patch
+[PULL v2 34/45] hw/riscv: spike: Remove misleading comments
+From: Bin Meng <bmeng@tinylab.org>
+PLIC is not included in the 'spike' machine.
+Signed-off-by: Bin Meng <bmeng@tinylab.org>
+Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <20221211030829.802437-5-bmeng@tinylab.org>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/riscv/spike.c | 1 -
+file changed, 1 deletion(-)
+diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/spike.c
++++ b/hw/riscv/spike.c
+@@ -XXX,XX +XXX,XX @@
+  *
+  * 0) HTIF Console and Poweroff
+  * 1) CLINT (Timer and IPI)
+- * 2) PLIC (Platform Level Interrupt Controller)
+  *
+  * This program is free software; you can redistribute it and/or modify it
+  * under the terms and conditions of the GNU General Public License,
+--
+.38.1

-New patch
+[PULL v2 35/45] hw/intc: sifive_plic: Drop PLICMode_H
+From: Bin Meng <bmeng@tinylab.org>
+H-mode has been removed since priv spec 1.10. Drop it.
+Signed-off-by: Bin Meng <bmeng@tinylab.org>
+Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <20221211030829.802437-6-bmeng@tinylab.org>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ include/hw/intc/sifive_plic.h | 1 -
+ hw/intc/sifive_plic.c         | 1 -
+files changed, 2 deletions(-)
+diff --git a/include/hw/intc/sifive_plic.h b/include/hw/intc/sifive_plic.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/intc/sifive_plic.h
++++ b/include/hw/intc/sifive_plic.h
+@@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(SiFivePLICState, SIFIVE_PLIC,
+ typedef enum PLICMode {
+     PLICMode_U,
+     PLICMode_S,
+-    PLICMode_H,
+     PLICMode_M
+ } PLICMode;
+diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/sifive_plic.c
++++ b/hw/intc/sifive_plic.c
+@@ -XXX,XX +XXX,XX @@ static PLICMode char_to_mode(char c)
+     switch (c) {
+     case 'U': return PLICMode_U;
+     case 'S': return PLICMode_S;
+-    case 'H': return PLICMode_H;
+     case 'M': return PLICMode_M;
+     default:
+         error_report("plic: invalid mode '%c'", c);
+--
+.38.1

-[PULL 07/28] target/riscv/kvm: tolerate KVM disable ext errors
+[PULL v2 36/45] hw/intc: sifive_plic: Improve robustness of the PLIC config parser
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Bin Meng <bmeng@tinylab.org>
-Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
+At present the PLIC config parser can only handle legal config string
-enabled, will fail with a kernel oops SIGILL right at the start. The
+like "MS,MS". However if a config string like ",MS,MS,,MS,MS,," is
-reason is that we can't expose zkr without implementing the SEED CSR.
+given the parser won't get the correct configuration.
 Disabling zkr in the guest would be a workaround, but if the KVM doesn't
 allow it we'll error out and never boot.
-In hindsight this is too strict. If we keep proceeding, despite not
+This commit improves the config parser to make it more robust.
 disabling the extension in the KVM vcpu, we'll not add the extension in
 the riscv,isa. The guest kernel will be unaware of the extension, i.e.
 it doesn't matter if the KVM vcpu has it enabled underneath or not. So
 it's ok to keep booting in this case.
-Change our current logic to not error out if we fail to disable an
+Signed-off-by: Bin Meng <bmeng@tinylab.org>
-extension in kvm_set_one_reg(), but show a warning and keep booting. It
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
-is important to throw a warning because we must make the user aware that
+Message-Id: <20221211030829.802437-7-bmeng@tinylab.org>
 the extension is still available in the vcpu, meaning that an
 ill-behaved guest can ignore the riscv,isa settings and  use the
 extension.
 The case we're handling happens with an EINVAL error code. If we fail to
 disable the extension in KVM for any other reason, error out.
 We'll also keep erroring out when we fail to enable an extension in KVM,
 since adding the extension in riscv,isa at this point will cause a guest
 malfunction because the extension isn't enabled in the vcpu.
 Suggested-by: Andrew Jones <ajones@ventanamicro.com>
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
+ hw/intc/sifive_plic.c | 24 ++++++++++++++++--------
-file changed, 8 insertions(+), 4 deletions(-)
+file changed, 16 insertions(+), 8 deletions(-)
-diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
+diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm/kvm-cpu.c
+--- a/hw/intc/sifive_plic.c
-+++ b/target/riscv/kvm/kvm-cpu.c
++++ b/hw/intc/sifive_plic.c
-@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
+@@ -XXX,XX +XXX,XX @@ static void sifive_plic_reset(DeviceState *dev)
-         reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
+  */
-         ret = kvm_set_one_reg(cs, id, &reg);
+ static void parse_hart_config(SiFivePLICState *plic)
-         if (ret != 0) {
+ {
--            error_report("Unable to %s extension %s in KVM, error %d",
+-    int addrid, hartid, modes;
--                         reg ? "enable" : "disable",
++    int addrid, hartid, modes, m;
--                         multi_ext_cfg->name, ret);
+     const char *p;
--            exit(EXIT_FAILURE);
+     char c;
-+            if (!reg && ret == -EINVAL) {
-+                warn_report("KVM cannot disable extension %s",
+@@ -XXX,XX +XXX,XX @@ static void parse_hart_config(SiFivePLICState *plic)
-+                            multi_ext_cfg->name);
+     p = plic->hart_config;
-+            } else {
+     while ((c = *p++)) {
-+                error_report("Unable to enable extension %s in KVM, error %d",
+         if (c == ',') {
-+                             multi_ext_cfg->name, ret);
+-            addrid += ctpop8(modes);
-+                exit(EXIT_FAILURE);
+-            modes = 0;
 -            hartid++;
 +            if (modes) {
 +                addrid += ctpop8(modes);
 +                hartid++;
 +                modes = 0;
 +            }
+         } else {
+-            int m = 1 << char_to_mode(c);
++            m = 1 << char_to_mode(c);
+             if (modes == (modes | m)) {
+                 error_report("plic: duplicate mode '%c' in config: %s",
+                              c, plic->hart_config);
+@@ -XXX,XX +XXX,XX @@ static void parse_hart_config(SiFivePLICState *plic)
+     }
+     if (modes) {
+         addrid += ctpop8(modes);
++        hartid++;
++        modes = 0;
+     }
+-    hartid++;
+     plic->num_addrs = addrid;
+     plic->num_harts = hartid;
+@@ -XXX,XX +XXX,XX @@ static void parse_hart_config(SiFivePLICState *plic)
+     p = plic->hart_config;
+     while ((c = *p++)) {
+         if (c == ',') {
+-            hartid++;
++            if (modes) {
++                hartid++;
++                modes = 0;
++            }
+         } else {
++            m = char_to_mode(c);
+             plic->addr_config[addrid].addrid = addrid;
+             plic->addr_config[addrid].hartid = hartid;
+-            plic->addr_config[addrid].mode = char_to_mode(c);
++            plic->addr_config[addrid].mode = m;
++            modes |= (1 << m);
+             addrid++;
          }
      }
- }
 --
-.45.1
+.38.1

-[PULL 25/28] target/riscv/kvm.c: Fix the hart bit setting of AIA
+[PULL v2 37/45] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize()
-From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
+From: Bin Meng <bmeng@tinylab.org>
-In AIA spec, each hart (or each hart within a group) has a unique hart
+The realize() callback has an errp for us to propagate the error up.
-number to locate the memory pages of interrupt files in the address
+While we are here, correct the wrong multi-line comment format.
 space. The number of bits required to represent any hart number is equal
 to ceil(log2(hmax + 1)), where hmax is the largest hart number among
 groups.
-However, if the largest hart number among groups is a power of 2, QEMU
+Signed-off-by: Bin Meng <bmeng@tinylab.org>
-will pass an inaccurate hart-index-bit setting to Linux. For example, when
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-to represent 4 harts, but we passes 3 to Linux. The code needs to be
+Message-Id: <20221211030829.802437-8-bmeng@tinylab.org>
 updated to ensure accurate hart-index-bit settings.
 Additionally, a Linux patch[1] is necessary to correctly recover the hart
 index when the guest OS has only 1 hart, where the hart-index-bit is 0.
 [1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/
 Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
+ hw/intc/sifive_plic.c | 7 ++++---
-file changed, 8 insertions(+), 1 deletion(-)
+file changed, 4 insertions(+), 3 deletions(-)
-diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
+diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm/kvm-cpu.c
+--- a/hw/intc/sifive_plic.c
-+++ b/target/riscv/kvm/kvm-cpu.c
++++ b/hw/intc/sifive_plic.c
-@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
+@@ -XXX,XX +XXX,XX @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
      s->m_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
      qdev_init_gpio_out(dev, s->m_external_irqs, s->num_harts);
 -    /* We can't allow the supervisor to control SEIP as this would allow the
 +    /*
 +     * We can't allow the supervisor to control SEIP as this would allow the
       * supervisor to clear a pending external interrupt which will result in
       * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
       * hardware controlled when a PLIC is attached.
@@ -XXX,XX +XXX,XX @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
      for (i = 0; i < s->num_harts; i++) {
          RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
          if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
 -            error_report("SEIP already claimed");
 -            exit(1);
 +            error_setg(errp, "SEIP already claimed");
 +            return;
          }
      }
--    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
-+
-+    if (max_hart_per_socket > 1) {
-+        max_hart_per_socket--;
-+        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
-+    } else {
-+        hart_bits = 0;
-+    }
-+
-     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
-                             KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
-                             &hart_bits, true, NULL);
 --
-.45.1
+.38.1

-[PULL 01/28] hw/intc/riscv_aplic: APLICs should add child earlier than realize
+[PULL v2 38/45] hw/intc: sifive_plic: Update "num-sources" property default value
-From: "yang.zhang" <yang.zhang@hexintek.com>
+From: Bin Meng <bmeng@tinylab.org>
-Since only root APLICs can have hw IRQ lines, aplic->parent should
+At present the default value of "num-sources" property is zero,
-be initialized first.
+which does not make a lot of sense, as in sifive_plic_realize()
 we see s->bitfield_words is calculated by:
-Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
+  s->bitfield_words = (s->num_sources + 31) >> 5;
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
+if the we don't configure "num-sources" property its default value
-Cc: qemu-stable <qemu-stable@nongnu.org>
+zero makes s->bitfield_words zero too, which isn't true because
-Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
+interrupt source 0 still occupies one word.
 Let's change the default value to 1 meaning that only interrupt
 source 0 is supported by default and a sanity check in realize().
 While we are here, add a comment to describe the exact meaning of
 this property that the number should include interrupt source 0.
 Signed-off-by: Bin Meng <bmeng@tinylab.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-Id: <20221211030829.802437-9-bmeng@tinylab.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/intc/riscv_aplic.c | 8 ++++----
+ hw/intc/sifive_plic.c | 8 +++++++-
-file changed, 4 insertions(+), 4 deletions(-)
+file changed, 7 insertions(+), 1 deletion(-)
-diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
+diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/riscv_aplic.c
+--- a/hw/intc/sifive_plic.c
-+++ b/hw/intc/riscv_aplic.c
++++ b/hw/intc/sifive_plic.c
-@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
+@@ -XXX,XX +XXX,XX @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
-     qdev_prop_set_bit(dev, "msimode", msimode);
-     qdev_prop_set_bit(dev, "mmode", mmode);
+     parse_hart_config(s);
-+    if (parent) {
++    if (!s->num_sources) {
-+        riscv_aplic_add_child(parent, dev);
++        error_setg(errp, "plic: invalid number of interrupt sources");
 +        return;
 +    }
 +
-     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+     s->bitfield_words = (s->num_sources + 31) >> 5;
+     s->num_enables = s->bitfield_words * s->num_addrs;
-     if (!is_kvm_aia(msimode)) {
+     s->source_priority = g_new0(uint32_t, s->num_sources);
-         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_sifive_plic = {
-     }
+ static Property sifive_plic_properties[] = {
+     DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
--    if (parent) {
+     DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
--        riscv_aplic_add_child(parent, dev);
+-    DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
--    }
++    /* number of interrupt sources including interrupt source 0 */
--
++    DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 1),
-     if (!msimode) {
+     DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
-         for (i = 0; i < num_harts; i++) {
+     DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
-             CPUState *cpu = cpu_by_arch_id(hartid_base + i);
+     DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
 --
-.45.1
+.38.1

-[PULL 12/28] target/riscv: Relax vector register check in RISCV gdbstub
+[PULL v2 39/45] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC
-From: Jason Chien <jason.chien@sifive.com>
+From: Bin Meng <bmeng@tinylab.org>
-In current implementation, the gdbstub allows reading vector registers
+Per chapter 6.5.2 in [1], the number of interupt sources including
-only if V extension is supported. However, all vector extensions and
+interrupt source 0 should be 187.
 vector crypto extensions have the vector registers and they all depend
 on Zve32x. The gdbstub should check for Zve32x instead.
-Signed-off-by: Jason Chien <jason.chien@sifive.com>
+[1] PolarFire SoC MSS TRM:
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
+https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/ReferenceManuals/PolarFire_SoC_FPGA_MSS_Technical_Reference_Manual_VC.pdf
-Reviewed-by: Max Chou <max.chou@sifive.com>
-Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
+Fixes: 56f6e31e7b7e ("hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board")
 Signed-off-by: Bin Meng <bmeng@tinylab.org>
 Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
 Message-Id: <20221211030829.802437-10-bmeng@tinylab.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/gdbstub.c | 2 +-
+ include/hw/riscv/microchip_pfsoc.h | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
+diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/gdbstub.c
+--- a/include/hw/riscv/microchip_pfsoc.h
-+++ b/target/riscv/gdbstub.c
++++ b/include/hw/riscv/microchip_pfsoc.h
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
+@@ -XXX,XX +XXX,XX @@ enum {
-                                  gdb_find_static_feature("riscv-32bit-fpu.xml"),
+ #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT    1
-);
+ #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT       4
-     }
--    if (env->misa_ext & RVV) {
+-#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES        185
-+    if (cpu->cfg.ext_zve32x) {
++#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES        187
-         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
+ #define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES     7
-                                  riscv_gdb_set_vector,
+ #define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE      0x04
-                                  ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
+ #define MICROCHIP_PFSOC_PLIC_PENDING_BASE       0x1000
 --
-.45.1
+.38.1

-New patch
+[PULL v2 40/45] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC
+From: Bin Meng <bmeng@tinylab.org>
+Per chapter 10 in Freedom E310 manuals [1][2][3], E310 G002 and G003
+supports 52 interrupt sources while G000 supports 51 interrupt sources.
+We use the value of G002 and G003, so it is 53 (including source 0).
+[1] G000 manual:
+https://sifive.cdn.prismic.io/sifive/4faf3e34-4a42-4c2f-be9e-c77baa4928c7_fe310-g000-manual-v3p2.pdf
+[2] G002 manual:
+https://sifive.cdn.prismic.io/sifive/034760b5-ac6a-4b1c-911c-f4148bb2c4a5_fe310-g002-v1p5.pdf
+[3] G003 manual:
+https://sifive.cdn.prismic.io/sifive/3af39c59-6498-471e-9dab-5355a0d539eb_fe310-g003-manual.pdf
+Fixes: eb637edb1241 ("SiFive Freedom E Series RISC-V Machine")
+Signed-off-by: Bin Meng <bmeng@tinylab.org>
+Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <20221211030829.802437-11-bmeng@tinylab.org>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ include/hw/riscv/sifive_e.h | 7 ++++++-
+file changed, 6 insertions(+), 1 deletion(-)
+diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/riscv/sifive_e.h
++++ b/include/hw/riscv/sifive_e.h
+@@ -XXX,XX +XXX,XX @@ enum {
+ };
+ #define SIFIVE_E_PLIC_HART_CONFIG "M"
+-#define SIFIVE_E_PLIC_NUM_SOURCES 127
++/*
++ * Freedom E310 G002 and G003 supports 52 interrupt sources while
++ * Freedom E310 G000 supports 51 interrupt sources. We use the value
++ * of G002 and G003, so it is 53 (including interrupt source 0).
++ */
++#define SIFIVE_E_PLIC_NUM_SOURCES 53
+ #define SIFIVE_E_PLIC_NUM_PRIORITIES 7
+ #define SIFIVE_E_PLIC_PRIORITY_BASE 0x04
+ #define SIFIVE_E_PLIC_PENDING_BASE 0x1000
+--
+.38.1

-New patch
+[PULL v2 41/45] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"
+From: Bin Meng <bmeng@tinylab.org>
+At present magic number is used to create "riscv,ndev" property
+in the dtb. Let's use the macro SIFIVE_U_PLIC_NUM_SOURCES that
+is used to instantiate the PLIC model instead.
+Signed-off-by: Bin Meng <bmeng@tinylab.org>
+Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <20221211030829.802437-12-bmeng@tinylab.org>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/riscv/sifive_u.c | 3 ++-
+file changed, 2 insertions(+), 1 deletion(-)
+diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/sifive_u.c
++++ b/hw/riscv/sifive_u.c
+@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
+     qemu_fdt_setprop_cells(fdt, nodename, "reg",
+x0, memmap[SIFIVE_U_DEV_PLIC].base,
+x0, memmap[SIFIVE_U_DEV_PLIC].size);
+-    qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
++    qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev",
++                          SIFIVE_U_PLIC_NUM_SOURCES - 1);
+     qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
+     plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
+     g_free(cells);
+--
+.38.1

-[PULL 23/28] target/riscv: Remove experimental prefix from "B" extension
+[PULL v2 42/45] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb
-From: Rob Bradford <rbradford@rivosinc.com>
+From: Bin Meng <bmeng@tinylab.org>
-This extension has now been ratified:
+Commit 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine")
-https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
+changed the value of VIRT_IRQCHIP_NUM_SOURCES from 127 to 53, which
-removed.
+is VIRTIO_NDEV and also used as the value of "riscv,ndev" property
 in the dtb. Unfortunately this is wrong as VIRT_IRQCHIP_NUM_SOURCES
 should include interrupt source 0 but "riscv,ndev" does not.
-Since this is now a ratified extension add it to the list of extensions
+While we are here, we also fix the comments of platform bus irq range
-included in the "max" CPU variant.
+which is now "64 to 96", but should be "64 to 95", introduced since
 commit 1832b7cb3f64 ("hw/riscv: virt: Create a platform bus").
-Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
+Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine")
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Signed-off-by: Bin Meng <bmeng@tinylab.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Message-Id: <20221211030829.802437-13-bmeng@tinylab.org>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.c         | 2 +-
+ include/hw/riscv/virt.h | 5 ++---
- target/riscv/tcg/tcg-cpu.c | 2 +-
+ hw/riscv/virt.c         | 3 ++-
-files changed, 2 insertions(+), 2 deletions(-)
+files changed, 4 insertions(+), 4 deletions(-)
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
+--- a/include/hw/riscv/virt.h
-+++ b/target/riscv/cpu.c
++++ b/include/hw/riscv/virt.h
-@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
+@@ -XXX,XX +XXX,XX @@ enum {
-     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
+     VIRTIO_IRQ = 1, /* 1 to 8 */
-     MISA_EXT_INFO(RVV, "v", "Vector operations"),
+     VIRTIO_COUNT = 8,
-     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
+     PCIE_IRQ = 0x20, /* 32 to 35 */
--    MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
+-    VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 96 */
-+    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
+-    VIRTIO_NDEV = 96 /* Arbitrary maximum number of interrupts */
 +    VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 95 */
  };
- static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
+ #define VIRT_PLATFORM_BUS_NUM_IRQS 32
-diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
  #define VIRT_IRQCHIP_NUM_MSIS 255
 -#define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV
 +#define VIRT_IRQCHIP_NUM_SOURCES 96
  #define VIRT_IRQCHIP_NUM_PRIO_BITS 3
  #define VIRT_IRQCHIP_MAX_GUESTS_BITS 3
  #define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U)
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/tcg/tcg-cpu.c
+--- a/hw/riscv/virt.c
-+++ b/target/riscv/tcg/tcg-cpu.c
++++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
-     const RISCVCPUMultiExtConfig *prop;
+         plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
+     qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg",
-     /* Enable RVG, RVJ and RVV that are disabled by default */
+x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
--    riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
+-    qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
-+    riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
++    qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev",
++                          VIRT_IRQCHIP_NUM_SOURCES - 1);
-     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
+     riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket);
-         isa_ext_update_enabled(cpu, prop->offset, true);
+     qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
          plic_phandles[socket]);
 --
-.45.1
+.38.1

-[PULL 27/28] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
+[PULL v2 43/45] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0
-From: Alistair Francis <alistair23@gmail.com>
+From: Bin Meng <bmeng@tinylab.org>
-Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
+At present the SiFive PLIC model "priority-base" expects interrupt
-CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
+priority register base starting from source 1 instead source 0,
-CSRs are part of the disassembly.
+that's why on most platforms "priority-base" is set to 0x04 except
 'opentitan' machine. 'opentitan' should have set "priority-base"
 to 0x04 too.
-Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
+Note the irq number calculation in sifive_plic_{read,write} is
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+correct as the codes make up for the irq number by adding 1.
-Fixes: ea10325917 ("RISC-V Disassembler")
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Let's simply update "priority-base" to start from interrupt source
-Cc: qemu-stable <qemu-stable@nongnu.org>
+and add a comment to make it crystal clear.
-Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
 Signed-off-by: Bin Meng <bmeng@tinylab.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
 Message-Id: <20221211030829.802437-14-bmeng@tinylab.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
+ include/hw/riscv/microchip_pfsoc.h | 2 +-
-file changed, 64 insertions(+), 1 deletion(-)
+ include/hw/riscv/shakti_c.h        | 2 +-
  include/hw/riscv/sifive_e.h        | 2 +-
  include/hw/riscv/sifive_u.h        | 2 +-
  include/hw/riscv/virt.h            | 2 +-
  hw/intc/sifive_plic.c              | 5 +++--
 files changed, 8 insertions(+), 7 deletions(-)
-diff --git a/disas/riscv.c b/disas/riscv.c
+diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
 index XXXXXXX..XXXXXXX 100644
---- a/disas/riscv.c
+--- a/include/hw/riscv/microchip_pfsoc.h
-+++ b/disas/riscv.c
++++ b/include/hw/riscv/microchip_pfsoc.h
-@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
+@@ -XXX,XX +XXX,XX @@ enum {
-     case 0x0383: return "mibound";
-     case 0x0384: return "mdbase";
+ #define MICROCHIP_PFSOC_PLIC_NUM_SOURCES        187
-     case 0x0385: return "mdbound";
+ #define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES     7
--    case 0x03a0: return "pmpcfg3";
+-#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE      0x04
-+    case 0x03a0: return "pmpcfg0";
++#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE      0x00
-+    case 0x03a1: return "pmpcfg1";
+ #define MICROCHIP_PFSOC_PLIC_PENDING_BASE       0x1000
-+    case 0x03a2: return "pmpcfg2";
+ #define MICROCHIP_PFSOC_PLIC_ENABLE_BASE        0x2000
-+    case 0x03a3: return "pmpcfg3";
+ #define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE      0x80
-+    case 0x03a4: return "pmpcfg4";
+diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
-+    case 0x03a5: return "pmpcfg5";
+index XXXXXXX..XXXXXXX 100644
-+    case 0x03a6: return "pmpcfg6";
+--- a/include/hw/riscv/shakti_c.h
-+    case 0x03a7: return "pmpcfg7";
++++ b/include/hw/riscv/shakti_c.h
-+    case 0x03a8: return "pmpcfg8";
+@@ -XXX,XX +XXX,XX @@ enum {
-+    case 0x03a9: return "pmpcfg9";
+ #define SHAKTI_C_PLIC_NUM_SOURCES 28
-+    case 0x03aa: return "pmpcfg10";
+ /* Excluding Priority 0 */
-+    case 0x03ab: return "pmpcfg11";
+ #define SHAKTI_C_PLIC_NUM_PRIORITIES 2
-+    case 0x03ac: return "pmpcfg12";
+-#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04
-+    case 0x03ad: return "pmpcfg13";
++#define SHAKTI_C_PLIC_PRIORITY_BASE 0x00
-+    case 0x03ae: return "pmpcfg14";
+ #define SHAKTI_C_PLIC_PENDING_BASE 0x1000
-+    case 0x03af: return "pmpcfg15";
+ #define SHAKTI_C_PLIC_ENABLE_BASE 0x2000
-     case 0x03b0: return "pmpaddr0";
+ #define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80
-     case 0x03b1: return "pmpaddr1";
+diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
-     case 0x03b2: return "pmpaddr2";
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
+--- a/include/hw/riscv/sifive_e.h
-     case 0x03bd: return "pmpaddr13";
++++ b/include/hw/riscv/sifive_e.h
-     case 0x03be: return "pmpaddr14";
+@@ -XXX,XX +XXX,XX @@ enum {
-     case 0x03bf: return "pmpaddr15";
+  */
-+    case 0x03c0: return "pmpaddr16";
+ #define SIFIVE_E_PLIC_NUM_SOURCES 53
-+    case 0x03c1: return "pmpaddr17";
+ #define SIFIVE_E_PLIC_NUM_PRIORITIES 7
-+    case 0x03c2: return "pmpaddr18";
+-#define SIFIVE_E_PLIC_PRIORITY_BASE 0x04
-+    case 0x03c3: return "pmpaddr19";
++#define SIFIVE_E_PLIC_PRIORITY_BASE 0x00
-+    case 0x03c4: return "pmpaddr20";
+ #define SIFIVE_E_PLIC_PENDING_BASE 0x1000
-+    case 0x03c5: return "pmpaddr21";
+ #define SIFIVE_E_PLIC_ENABLE_BASE 0x2000
-+    case 0x03c6: return "pmpaddr22";
+ #define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80
-+    case 0x03c7: return "pmpaddr23";
+diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
-+    case 0x03c8: return "pmpaddr24";
+index XXXXXXX..XXXXXXX 100644
-+    case 0x03c9: return "pmpaddr25";
+--- a/include/hw/riscv/sifive_u.h
-+    case 0x03ca: return "pmpaddr26";
++++ b/include/hw/riscv/sifive_u.h
-+    case 0x03cb: return "pmpaddr27";
+@@ -XXX,XX +XXX,XX @@ enum {
-+    case 0x03cc: return "pmpaddr28";
-+    case 0x03cd: return "pmpaddr29";
+ #define SIFIVE_U_PLIC_NUM_SOURCES 54
-+    case 0x03ce: return "pmpaddr30";
+ #define SIFIVE_U_PLIC_NUM_PRIORITIES 7
-+    case 0x03cf: return "pmpaddr31";
+-#define SIFIVE_U_PLIC_PRIORITY_BASE 0x04
-+    case 0x03d0: return "pmpaddr32";
++#define SIFIVE_U_PLIC_PRIORITY_BASE 0x00
-+    case 0x03d1: return "pmpaddr33";
+ #define SIFIVE_U_PLIC_PENDING_BASE 0x1000
-+    case 0x03d2: return "pmpaddr34";
+ #define SIFIVE_U_PLIC_ENABLE_BASE 0x2000
-+    case 0x03d3: return "pmpaddr35";
+ #define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80
-+    case 0x03d4: return "pmpaddr36";
+diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
-+    case 0x03d5: return "pmpaddr37";
+index XXXXXXX..XXXXXXX 100644
-+    case 0x03d6: return "pmpaddr38";
+--- a/include/hw/riscv/virt.h
-+    case 0x03d7: return "pmpaddr39";
++++ b/include/hw/riscv/virt.h
-+    case 0x03d8: return "pmpaddr40";
+@@ -XXX,XX +XXX,XX @@ enum {
-+    case 0x03d9: return "pmpaddr41";
+ #define VIRT_IRQCHIP_MAX_GUESTS_BITS 3
-+    case 0x03da: return "pmpaddr42";
+ #define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U)
-+    case 0x03db: return "pmpaddr43";
-+    case 0x03dc: return "pmpaddr44";
+-#define VIRT_PLIC_PRIORITY_BASE 0x04
-+    case 0x03dd: return "pmpaddr45";
++#define VIRT_PLIC_PRIORITY_BASE 0x00
-+    case 0x03de: return "pmpaddr46";
+ #define VIRT_PLIC_PENDING_BASE 0x1000
-+    case 0x03df: return "pmpaddr47";
+ #define VIRT_PLIC_ENABLE_BASE 0x2000
-+    case 0x03e0: return "pmpaddr48";
+ #define VIRT_PLIC_ENABLE_STRIDE 0x80
-+    case 0x03e1: return "pmpaddr49";
+diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
-+    case 0x03e2: return "pmpaddr50";
+index XXXXXXX..XXXXXXX 100644
-+    case 0x03e3: return "pmpaddr51";
+--- a/hw/intc/sifive_plic.c
-+    case 0x03e4: return "pmpaddr52";
++++ b/hw/intc/sifive_plic.c
-+    case 0x03e5: return "pmpaddr53";
+@@ -XXX,XX +XXX,XX @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
-+    case 0x03e6: return "pmpaddr54";
+     SiFivePLICState *plic = opaque;
-+    case 0x03e7: return "pmpaddr55";
-+    case 0x03e8: return "pmpaddr56";
+     if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
-+    case 0x03e9: return "pmpaddr57";
+-        uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
-+    case 0x03ea: return "pmpaddr58";
++        uint32_t irq = (addr - plic->priority_base) >> 2;
-+    case 0x03eb: return "pmpaddr59";
-+    case 0x03ec: return "pmpaddr60";
+         return plic->source_priority[irq];
-+    case 0x03ed: return "pmpaddr61";
+     } else if (addr_between(addr, plic->pending_base, plic->num_sources >> 3)) {
-+    case 0x03ee: return "pmpaddr62";
+@@ -XXX,XX +XXX,XX @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
-+    case 0x03ef: return "pmpaddr63";
+     SiFivePLICState *plic = opaque;
-     case 0x0780: return "mtohost";
-     case 0x0781: return "mfromhost";
+     if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
-     case 0x0782: return "mreset";
+-        uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
 +        uint32_t irq = (addr - plic->priority_base) >> 2;
          if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
              /*
@@ -XXX,XX +XXX,XX @@ static Property sifive_plic_properties[] = {
      /* number of interrupt sources including interrupt source 0 */
      DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 1),
      DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
 +    /* interrupt priority register base starting from source 0 */
      DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
      DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
      DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
 --
-.45.1
+.38.1

-[PULL 20/28] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
+[PULL v2 44/45] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization
-From: Max Chou <max.chou@sifive.com>
+From: Bin Meng <bmeng@tinylab.org>
-If the checking functions check both the single and double width
+"hartid-base" and "priority-base" are zero by default. There is no
-operators at the same time, then the single width operator checking
+need to initialize them to zero again.
 functions (require_rvf[min]) will check whether the SEW is 8.
-Signed-off-by: Max Chou <max.chou@sifive.com>
+Signed-off-by: Bin Meng <bmeng@tinylab.org>
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
-Cc: qemu-stable <qemu-stable@nongnu.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
+Message-Id: <20221211030829.802437-15-bmeng@tinylab.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
+ hw/riscv/opentitan.c | 2 --
-file changed, 4 insertions(+), 12 deletions(-)
+file changed, 2 deletions(-)
-diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.c.inc
+--- a/hw/riscv/opentitan.c
-+++ b/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/hw/riscv/opentitan.c
-@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
+@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
-     return require_rvv(s) &&
-            require_rvf(s) &&
+     /* PLIC */
-            require_scale_rvf(s) &&
+     qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M");
--           (s->sew != MO_8) &&
+-    qdev_prop_set_uint32(DEVICE(&s->plic), "hartid-base", 0);
-            vext_check_isa_ill(s) &&
+     qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180);
-            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
+     qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3);
- }
+-    qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
-@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
+     qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
-     return require_rvv(s) &&
+     qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
-            require_rvf(s) &&
+     qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32);
             require_scale_rvf(s) &&
 -           (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
             vext_check_ds(s, a->rd, a->rs2, a->vm);
  }
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
      return require_rvv(s) &&
             require_rvf(s) &&
             require_scale_rvf(s) &&
 -           (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
             vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
  }
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
      return require_rvv(s) &&
             require_rvf(s) &&
             require_scale_rvf(s) &&
 -           (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
             vext_check_dd(s, a->rd, a->rs2, a->vm);
  }
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
  {
      return opfv_widen_check(s, a) &&
             require_rvfmin(s) &&
 -           require_scale_rvfmin(s) &&
 -           (s->sew != MO_8);
 +           require_scale_rvfmin(s);
  }
  #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
  {
      return opfv_narrow_check(s, a) &&
             require_rvfmin(s) &&
 -           require_scale_rvfmin(s) &&
 -           (s->sew != MO_8);
 +           require_scale_rvfmin(s);
  }
  static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
  {
      return opfv_narrow_check(s, a) &&
             require_rvf(s) &&
 -           require_scale_rvf(s) &&
 -           (s->sew != MO_8);
 +           require_scale_rvf(s);
  }
  #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return reduction_widen_check(s, a) &&
             require_rvf(s) &&
 -           require_scale_rvf(s) &&
 -           (s->sew != MO_8);
 +           require_scale_rvf(s);
  }
  GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
 --
-.45.1
+.38.1

-[PULL 18/28] target/riscv: rvv: Check single width operator for vector fp widen instructions
+[PULL v2 45/45] hw/intc: sifive_plic: Fix the pending register range check
-From: Max Chou <max.chou@sifive.com>
+From: Bin Meng <bmeng@tinylab.org>
-The require_scale_rvf function only checks the double width operator for
+The pending register upper limit is currently set to
-the vector floating point widen instructions, so most of the widen
+plic->num_sources >> 3, which is wrong, e.g.: considering
-checking functions need to add require_rvf for single width operator.
+plic->num_sources is 7, the upper limit becomes 0 which fails
 the range check if reading the pending register at pending_base.
-The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
+Fixes: 1e24429e40df ("SiFive RISC-V PLIC Block")
-integer to double width float, so the opfxv_widen_check function doesn’t
+Signed-off-by: Bin Meng <bmeng@tinylab.org>
-need require_rvf for the single width operator(integer).
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-Id: <20221211030829.802437-16-bmeng@tinylab.org>
 Signed-off-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
+ hw/intc/sifive_plic.c | 5 +++--
-file changed, 5 insertions(+)
+file changed, 3 insertions(+), 2 deletions(-)
-diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvv.c.inc
+--- a/hw/intc/sifive_plic.c
-+++ b/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/hw/intc/sifive_plic.c
-@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_TRANS(vfrsub_vf,  opfvf_check)
+@@ -XXX,XX +XXX,XX @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
- static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
+         uint32_t irq = (addr - plic->priority_base) >> 2;
- {
-     return require_rvv(s) &&
+         return plic->source_priority[irq];
-+           require_rvf(s) &&
+-    } else if (addr_between(addr, plic->pending_base, plic->num_sources >> 3)) {
-            require_scale_rvf(s) &&
++    } else if (addr_between(addr, plic->pending_base,
-            (s->sew != MO_8) &&
++                            (plic->num_sources + 31) >> 3)) {
-            vext_check_isa_ill(s) &&
+         uint32_t word = (addr - plic->pending_base) >> 2;
-@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
- static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
+         return plic->pending[word];
- {
+@@ -XXX,XX +XXX,XX @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
-     return require_rvv(s) &&
+             sifive_plic_update(plic);
-+           require_rvf(s) &&
+         }
-            require_scale_rvf(s) &&
+     } else if (addr_between(addr, plic->pending_base,
-            (s->sew != MO_8) &&
+-                            plic->num_sources >> 3)) {
-            vext_check_isa_ill(s) &&
++                            (plic->num_sources + 31) >> 3)) {
-@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
+         qemu_log_mask(LOG_GUEST_ERROR,
- static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
+                       "%s: invalid pending write: 0x%" HWADDR_PRIx "",
- {
+                       __func__, addr);
      return require_rvv(s) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
  static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return require_rvv(s) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
  static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return reduction_widen_check(s, a) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8);
  }
 --
-.45.1
+.38.1

The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:

Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)

are available in the Git repository at:

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528

for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:

target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)

----------------------------------------------------------------
RISC-V PR for 9.1

* APLICs add child earlier than realize
* Fix exposure of Zkr
* Raise exceptions on wrs.nto
* Implement SBI debug console (DBCN) calls for KVM
* Support 64-bit addresses for initrd
* Change RISCV_EXCP_SEMIHOST exception number to 63
* Tolerate KVM disable ext errors
* Set tval in breakpoints
* Add support for Zve32x extension
* Add support for Zve64x extension
* Relax vector register check in RISCV gdbstub
* Fix the element agnostic Vector function problem
* Fix Zvkb extension config
* Implement dynamic establishment of custom decoder
* Add th.sxstatus CSR emulation
* Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
* Check single width operator for vector fp widen instructions
* Check single width operator for vfncvt.rod.f.f.w
* Remove redudant SEW checking for vector fp narrow/widen instructions
* Prioritize pmp errors in raise_mmu_exception()
* Do not set mtval2 for non guest-page faults
* Remove experimental prefix from "B" extension
* Fixup CBO extension register calculation
* Fix the hart bit setting of AIA
* Fix reg_width in ricsv_gen_dynamic_vector_feature()
* Decode all of the pmpcfg and pmpaddr CSRs
* Raise an exception when CSRRS/CSRRC writes a read-only CSR

----------------------------------------------------------------
Alexei Filippov (1):
      target/riscv: do not set mtval2 for non guest-page faults

Alistair Francis (2):
      target/riscv: rvzicbo: Fixup CBO extension register calculation
      disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs

Andrew Jones (2):
      target/riscv/kvm: Fix exposure of Zkr
      target/riscv: Raise exceptions on wrs.nto

Cheng Yang (1):
      hw/riscv/boot.c: Support 64-bit address for initrd

Christoph Müllner (1):
      riscv: thead: Add th.sxstatus CSR emulation

Clément Léger (1):
      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

Daniel Henrique Barboza (6):
      target/riscv/kvm: implement SBI debug console (DBCN) calls
      target/riscv/kvm: tolerate KVM disable ext errors
      target/riscv/debug: set tval=pc in breakpoint exceptions
      trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
      target/riscv: prioritize pmp errors in raise_mmu_exception()
      riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()

Huang Tao (2):
      target/riscv: Fix the element agnostic function problem
      target/riscv: Implement dynamic establishment of custom decoder

Jason Chien (3):
      target/riscv: Add support for Zve32x extension
      target/riscv: Add support for Zve64x extension
      target/riscv: Relax vector register check in RISCV gdbstub

Max Chou (4):
      target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
      target/riscv: rvv: Check single width operator for vector fp widen instructions
      target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
      target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions

Rob Bradford (1):
      target/riscv: Remove experimental prefix from "B" extension

Yangyu Chen (1):
      target/riscv/cpu.c: fix Zvkb extension config

Yong-Xuan Wang (1):
      target/riscv/kvm.c: Fix the hart bit setting of AIA

Yu-Ming Chang (1):
      target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

yang.zhang (1):
      hw/intc/riscv_aplic: APLICs should add child earlier than realize

From: "yang.zhang" <yang.zhang@hexintek.com>

Since only root APLICs can have hw IRQ lines, aplic->parent should
be initialized first.

Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/riscv_aplic.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
     qdev_prop_set_bit(dev, "msimode", msimode);
     qdev_prop_set_bit(dev, "mmode", mmode);
 
+    if (parent) {
+        riscv_aplic_add_child(parent, dev);
+    }
+
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 
     if (!is_kvm_aia(msimode)) {
         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
     }
 
-    if (parent) {
-        riscv_aplic_add_child(parent, dev);
-    }
-
     if (!msimode) {
         for (i = 0; i < num_harts; i++) {
             CPUState *cpu = cpu_by_arch_id(hartid_base + i);
-- 
2.45.1

From: Andrew Jones <ajones@ventanamicro.com>

The Zkr extension may only be exposed to KVM guests if the VMM
implements the SEED CSR. Use the same implementation as TCG.

Without this patch, running with a KVM which does not forward the
SEED CSR access to QEMU will result in an ILL exception being
injected into the guest (this results in Linux guests crashing on
boot). And, when running with a KVM which does forward the access,
QEMU will crash, since QEMU doesn't know what to do with the exit.

Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  3 +++
 target/riscv/csr.c         | 18 ++++++++++++++----
 target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
 3 files changed, 42 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 
 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+                                target_ulong write_mask);
+
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
 #endif
 
 /* Crypto Extension */
-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
-                               target_ulong *ret_value,
-                               target_ulong new_value,
-                               target_ulong write_mask)
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+                                target_ulong write_mask)
 {
     uint16_t random_v;
     Error *random_e = NULL;
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
         rval = random_v | SEED_OPST_ES16;
     }
 
+    return rval;
+}
+
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+                               target_ulong *ret_value,
+                               target_ulong new_value,
+                               target_ulong write_mask)
+{
+    target_ulong rval;
+
+    rval = riscv_new_csr_seed(new_value, write_mask);
+
     if (ret_value) {
         *ret_value = rval;
     }
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
     return ret;
 }
 
+static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
+{
+    target_ulong csr_num = run->riscv_csr.csr_num;
+    target_ulong new_value = run->riscv_csr.new_value;
+    target_ulong write_mask = run->riscv_csr.write_mask;
+    int ret = 0;
+
+    switch (csr_num) {
+    case CSR_SEED:
+        run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: un-handled CSR EXIT for CSR %lx\n",
+                      __func__, csr_num);
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
     case KVM_EXIT_RISCV_SBI:
         ret = kvm_riscv_handle_sbi(cs, run);
         break;
+    case KVM_EXIT_RISCV_CSR:
+        ret = kvm_riscv_handle_csr(cs, run);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
                       __func__, run->exit_reason);
-- 
2.45.1

From: Andrew Jones <ajones@ventanamicro.com>

Implementing wrs.nto to always just return is consistent with the
specification, as the instruction is permitted to terminate the
stall for any reason, but it's not useful for virtualization, where
we'd like the guest to trap to the hypervisor in order to allow
scheduling of the lock holding VCPU. Change to always immediately
raise exceptions when the appropriate conditions are present,
otherwise continue to just return. Note, immediately raising
exceptions is also consistent with the specification since the
time limit that should expire prior to the exception is
implementation-specific.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                       |  1 +
 target/riscv/op_helper.c                    | 11 ++++++++
 target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
 3 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
 DEF_HELPER_1(sret, tl, env)
 DEF_HELPER_1(mret, tl, env)
 DEF_HELPER_1(wfi, void, env)
+DEF_HELPER_1(wrs_nto, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
 DEF_HELPER_1(tlb_flush_all, void, env)
 /* Native Debug */
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
     }
 }
 
+void helper_wrs_nto(CPURISCVState *env)
+{
+    if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
+        get_field(env->hstatus, HSTATUS_VTW) &&
+        !get_field(env->mstatus, MSTATUS_TW)) {
+        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+    } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    }
+}
+
 void helper_tlb_flush(CPURISCVState *env)
 {
     CPUState *cs = env_cpu(env);
diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
@@ -XXX,XX +XXX,XX @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-static bool trans_wrs(DisasContext *ctx)
+static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
 {
     if (!ctx->cfg_ptr->ext_zawrs) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
     return true;
 }
 
-#define GEN_TRANS_WRS(insn)                                     \
-static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
-{                                                               \
-    (void)a;                                                    \
-    return trans_wrs(ctx);                                      \
-}
+static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
+{
+    if (!ctx->cfg_ptr->ext_zawrs) {
+        return false;
+    }
 
-GEN_TRANS_WRS(wrs_nto)
-GEN_TRANS_WRS(wrs_sto)
+    /*
+     * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
+     * should raise an exception when the implementation-specific bounded time
+     * limit has expired. Our time limit is zero, so we either return
+     * immediately, as does our implementation of wrs.sto, or raise an
+     * exception, as handled by the wrs.nto helper.
+     */
+#ifndef CONFIG_USER_ONLY
+    gen_helper_wrs_nto(tcg_env);
+#endif
+
+    /* We only get here when helper_wrs_nto() doesn't raise an exception. */
+    return trans_wrs_sto(ctx, NULL);
+}
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

SBI defines a Debug Console extension "DBCN" that will, in time, replace
the legacy console putchar and getchar SBI extensions.

The appeal of the DBCN extension is that it allows multiple bytes to be
read/written in the SBI console in a single SBI call.

As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
module to userspace. But this will only happens if the KVM module
actually supports this SBI extension and we activate it.

We'll check for DBCN support during init time, checking if get-reg-list
is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
kvm_set_one_reg() during kvm_arch_init_vcpu().

Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
SBI_EXT_DBCN, reading and writing as required.

A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
host, takes around 20 seconds to boot without using DBCN. With this
patch we're taking around 14 seconds to boot due to the speed-up in the
terminal output.  There's no change in boot time if the guest isn't
using earlycon.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/sbi_ecall_interface.h |  17 +++++
 target/riscv/kvm/kvm-cpu.c         | 111 +++++++++++++++++++++++++++++
 2 files changed, 128 insertions(+)

diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/sbi_ecall_interface.h
+++ b/target/riscv/sbi_ecall_interface.h
@@ -XXX,XX +XXX,XX @@
 
 /* clang-format off */
 
+#define SBI_SUCCESS                      0
+#define SBI_ERR_FAILED                  -1
+#define SBI_ERR_NOT_SUPPORTED           -2
+#define SBI_ERR_INVALID_PARAM           -3
+#define SBI_ERR_DENIED                  -4
+#define SBI_ERR_INVALID_ADDRESS         -5
+#define SBI_ERR_ALREADY_AVAILABLE       -6
+#define SBI_ERR_ALREADY_STARTED         -7
+#define SBI_ERR_ALREADY_STOPPED         -8
+#define SBI_ERR_NO_SHMEM                -9
+
 /* SBI Extension IDs */
 #define SBI_EXT_0_1_SET_TIMER           0x0
 #define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
@@ -XXX,XX +XXX,XX @@
 #define SBI_EXT_IPI                     0x735049
 #define SBI_EXT_RFENCE                  0x52464E43
 #define SBI_EXT_HSM                     0x48534D
+#define SBI_EXT_DBCN                    0x4442434E
 
 /* SBI function IDs for BASE extension */
 #define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
@@ -XXX,XX +XXX,XX @@
 #define SBI_EXT_HSM_HART_STOP           0x1
 #define SBI_EXT_HSM_HART_GET_STATUS     0x2
 
+/* SBI function IDs for DBCN extension */
+#define SBI_EXT_DBCN_CONSOLE_WRITE      0x0
+#define SBI_EXT_DBCN_CONSOLE_READ       0x1
+#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
+
 #define SBI_HSM_HART_STATUS_STARTED     0x0
 #define SBI_HSM_HART_STATUS_STOPPED     0x1
 #define SBI_HSM_HART_STATUS_START_PENDING   0x2
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
                    KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
 };
 
+static KVMCPUConfig kvm_sbi_dbcn = {
+    .name = "sbi_dbcn",
+    .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
+                  KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
+};
+
 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
 {
     CPURISCVState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
     return 0;
 }
 
+static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
+                                             KVMScratchCPU *kvmcpu,
+                                             struct kvm_reg_list *reglist)
+{
+    struct kvm_reg_list *reg_search;
+
+    reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
+                         sizeof(uint64_t), uint64_cmp);
+
+    if (reg_search) {
+        kvm_sbi_dbcn.supported = true;
+    }
+}
+
 static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
                                  struct kvm_reg_list *reglist)
 {
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
     if (riscv_has_ext(&cpu->env, RVV)) {
         kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
     }
+
+    kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
 }
 
 static void riscv_init_kvm_registers(Object *cpu_obj)
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
     return ret;
 }
 
+static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
+{
+    target_ulong reg = 1;
+
+    if (!kvm_sbi_dbcn.supported) {
+        return 0;
+    }
+
+    return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
+}
+
 int kvm_arch_init_vcpu(CPUState *cs)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
     kvm_riscv_update_cpu_misa_ext(cpu, cs);
     kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
 
+    ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
+
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
     return true;
 }
 
+static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
+{
+    g_autofree uint8_t *buf = NULL;
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    target_ulong num_bytes;
+    uint64_t addr;
+    unsigned char ch;
+    int ret;
+
+    switch (run->riscv_sbi.function_id) {
+    case SBI_EXT_DBCN_CONSOLE_READ:
+    case SBI_EXT_DBCN_CONSOLE_WRITE:
+        num_bytes = run->riscv_sbi.args[0];
+
+        if (num_bytes == 0) {
+            run->riscv_sbi.ret[0] = SBI_SUCCESS;
+            run->riscv_sbi.ret[1] = 0;
+            break;
+        }
+
+        addr = run->riscv_sbi.args[1];
+
+        /*
+         * Handle the case where a 32 bit CPU is running in a
+         * 64 bit addressing env.
+         */
+        if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
+            addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
+        }
+
+        buf = g_malloc0(num_bytes);
+
+        if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
+            ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
+            if (ret < 0) {
+                error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
+                             "reading chardev");
+                exit(1);
+            }
+
+            cpu_physical_memory_write(addr, buf, ret);
+        } else {
+            cpu_physical_memory_read(addr, buf, num_bytes);
+
+            ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
+            if (ret < 0) {
+                error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
+                             "writing chardev");
+                exit(1);
+            }
+        }
+
+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+        run->riscv_sbi.ret[1] = ret;
+        break;
+    case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
+        ch = run->riscv_sbi.args[0];
+        ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
+
+        if (ret < 0) {
+            error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
+                         "writing chardev");
+            exit(1);
+        }
+
+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+        run->riscv_sbi.ret[1] = 0;
+        break;
+    default:
+        run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
+    }
+}
+
 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
         }
         ret = 0;
         break;
+    case SBI_EXT_DBCN:
+        kvm_riscv_handle_sbi_dbcn(cs, run);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP,
                       "%s: un-handled SBI EXIT, specific reasons is %lu\n",
-- 
2.45.1

From: Cheng Yang <yangcheng.work@foxmail.com>

Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
to set the address of initrd in FDT to support 64-bit address.

Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/boot.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
     if (fdt) {
         end = start + size;
-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
     }
 }
 
-- 
2.45.1

From: Clément Léger <cleger@rivosinc.com>

The current semihost exception number (16) is a reserved number (range
[16-17]). The upcoming double trap specification uses that number for
the double trap exception. Since the privileged spec (Table 22) defines
ranges for custom uses change the semihosting exception number to 63
which belongs to the range [48-63] in order to avoid any future
collisions with reserved exception.

Signed-off-by: Clément Léger <cleger@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
-    RISCV_EXCP_SEMIHOST = 0x10,
     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
+    RISCV_EXCP_SEMIHOST = 0x3f,
 } RISCVException;
 
 #define RISCV_EXCP_INT_FLAG                0x80000000
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
enabled, will fail with a kernel oops SIGILL right at the start. The
reason is that we can't expose zkr without implementing the SEED CSR.
Disabling zkr in the guest would be a workaround, but if the KVM doesn't
allow it we'll error out and never boot.

In hindsight this is too strict. If we keep proceeding, despite not
disabling the extension in the KVM vcpu, we'll not add the extension in
the riscv,isa. The guest kernel will be unaware of the extension, i.e.
it doesn't matter if the KVM vcpu has it enabled underneath or not. So
it's ok to keep booting in this case.

Change our current logic to not error out if we fail to disable an
extension in kvm_set_one_reg(), but show a warning and keep booting. It
is important to throw a warning because we must make the user aware that
the extension is still available in the vcpu, meaning that an
ill-behaved guest can ignore the riscv,isa settings and  use the
extension.

The case we're handling happens with an EINVAL error code. If we fail to
disable the extension in KVM for any other reason, error out.

We'll also keep erroring out when we fail to enable an extension in KVM,
since adding the extension in riscv,isa at this point will cause a guest
malfunction because the extension isn't enabled in the vcpu.

Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
         reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
         ret = kvm_set_one_reg(cs, id, &reg);
         if (ret != 0) {
-            error_report("Unable to %s extension %s in KVM, error %d",
-                         reg ? "enable" : "disable",
-                         multi_ext_cfg->name, ret);
-            exit(EXIT_FAILURE);
+            if (!reg && ret == -EINVAL) {
+                warn_report("KVM cannot disable extension %s",
+                            multi_ext_cfg->name);
+            } else {
+                error_report("Unable to enable extension %s in KVM, error %d",
+                             multi_ext_cfg->name, ret);
+                exit(EXIT_FAILURE);
+            }
         }
     }
 }
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We're not setting (s/m)tval when triggering breakpoints of type 2
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5.7.12, "Match Control Type 6":

"The Privileged Spec says that breakpoint exceptions that occur on
instruction fetches, loads, or stores update the tval CSR with either
zero or the faulting virtual address. The faulting virtual address for
an mcontrol6 trigger with action = 0 is the address being accessed and
which caused that trigger to fire."

A similar text is also found in the Debug spec section 5.7.11 w.r.t.
mcontrol.

Note that what we're doing ATM is not violating the spec, but it's
simple enough to set mtval/stval and it makes life easier for any
software that relies on this info.

Given that we always use action = 0, save the faulting address for the
mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
used as as scratch area for traps with address information. 'tval' is
then set during riscv_cpu_do_interrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 1 +
 target/riscv/debug.c      | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
             tval = env->bins;
             break;
         case RISCV_EXCP_BREAKPOINT:
+            tval = env->badaddr;
             if (cs->watchpoint_hit) {
                 tval = cs->watchpoint_hit->hitaddr;
                 cs->watchpoint_hit = NULL;
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
                     /* check U/S/M bit against current privilege level */
                     if ((ctrl >> 3) & BIT(env->priv)) {
+                        env->badaddr = pc;
                         return true;
                     }
                 }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                     if (env->virt_enabled) {
                         /* check VU/VS bit against current privilege level */
                         if ((ctrl >> 23) & BIT(env->priv)) {
+                            env->badaddr = pc;
                             return true;
                         }
                     } else {
                         /* check U/S/M bit against current privilege level */
                         if ((ctrl >> 3) & BIT(env->priv)) {
+                            env->badaddr = pc;
                             return true;
                         }
                     }
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Privileged spec section 4.1.9 mentions:

"When a trap is taken into S-mode, stval is written with
exception-specific information to assist software in handling the trap.
(...)

If stval is written with a nonzero value when a breakpoint,
address-misaligned, access-fault, or page-fault exception occurs on an
instruction fetch, load, or store, then stval will contain the faulting
virtual address."

A similar text is found for mtval in section 3.1.16.

Setting mtval/stval in this scenario is optional, but some softwares read
these regs when handling ebreaks.

Write 'badaddr' in all ebreak breakpoints to write the appropriate
'tval' during riscv_do_cpu_interrrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
     } else {
+        tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
+                      offsetof(CPURISCVState, badaddr));
         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
     }
     return true;
-- 
2.45.1

From: Jason Chien <jason.chien@sifive.com>

Add support for Zve32x extension and replace some checks for Zve32f with
Zve32x, since Zve32f depends on Zve32x.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h                  |  1 +
 target/riscv/cpu.c                      |  2 ++
 target/riscv/cpu_helper.c               |  2 +-
 target/riscv/csr.c                      |  2 +-
 target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
 target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
 6 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_zhinx;
     bool ext_zhinxmin;
     bool ext_zve32f;
+    bool ext_zve32x;
     bool ext_zve64f;
     bool ext_zve64d;
     bool ext_zvbb;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
+    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
     MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
     MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
+    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
     MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
     *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
     *cs_base = 0;
 
-    if (cpu->cfg.ext_zve32f) {
+    if (cpu->cfg.ext_zve32x) {
         /*
          * If env->vl equals to VLMAX, we can use generic vector operation
          * expanders (GVEC) to accerlate the vector operations.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
 
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
-    if (riscv_cpu_cfg(env)->ext_zve32f) {
+    if (riscv_cpu_cfg(env)->ext_zve32x) {
 #if !defined(CONFIG_USER_ONLY)
         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
-    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
-        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-        return;
+    /* The Zve32f extension depends on the Zve32x extension */
+    if (cpu->cfg.ext_zve32f) {
+        if (!riscv_has_ext(env, RVF)) {
+            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
+            return;
+        }
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
     }
 
     if (cpu->cfg.ext_zvfh) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
     }
 
-    /*
-     * In principle Zve*x would also suffice here, were they supported
-     * in qemu
-     */
     if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
          cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
-         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
+         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
         error_setg(errp,
                    "Vector crypto extensions require V or Zve* extensions");
         return;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
 {
     TCGv s1, dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
 {
     TCGv dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
-- 
2.45.1

From: Jason Chien <jason.chien@sifive.com>

Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
enabling Zve64x enables Zve32x according to their dependency.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h     |  1 +
 target/riscv/cpu.c         |  2 ++
 target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
 3 files changed, 14 insertions(+), 6 deletions(-)

From: Jason Chien <jason.chien@sifive.com>

In current implementation, the gdbstub allows reading vector registers
only if V extension is supported. However, all vector extensions and
vector crypto extensions have the vector registers and they all depend
on Zve32x. The gdbstub should check for Zve32x instead.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
                                  gdb_find_static_feature("riscv-32bit-fpu.xml"),
                                  0);
     }
-    if (env->misa_ext & RVV) {
+    if (cpu->cfg.ext_zve32x) {
         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
                                  riscv_gdb_set_vector,
                                  ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
-- 
2.45.1

From: Huang Tao <eric.huang@linux.alibaba.com>

In RVV and vcrypto instructions, the masked and tail elements are set to 1s
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
agnostic policy.

However, this function can't deal the big endian situation. This patch fixes
the problem by adding handling of such case.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_internals.c
+++ b/target/riscv/vector_internals.c
@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
     if (tot - cnt == 0) {
         return ;
     }
+
+    if (HOST_BIG_ENDIAN) {
+        /*
+         * Deal the situation when the elements are insdie
+         * only one uint64 block including setting the
+         * masked-off element.
+         */
+        if (((tot - 1) ^ cnt) < 8) {
+            memset(base + H1(tot - 1), -1, tot - cnt);
+            return;
+        }
+        /*
+         * Otherwise, at least cross two uint64_t blocks.
+         * Set first unaligned block.
+         */
+        if (cnt % 8 != 0) {
+            uint32_t j = ROUND_UP(cnt, 8);
+            memset(base + H1(j - 1), -1, j - cnt);
+            cnt = j;
+        }
+        /* Set other 64bit aligend blocks */
+    }
     memset(base + cnt, -1, tot - cnt);
 }
 
-- 
2.45.1

From: Yangyu Chen <cyy@cyyself.name>

This code has a typo that writes zvkb to zvkg, causing users can't
enable zvkb through the config. This patch gets this fixed.

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Vector cryptography extensions */
     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
-    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
+    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
-- 
2.45.1

From: Huang Tao <eric.huang@linux.alibaba.com>

In this patch, we modify the decoder to be a freely composable data
structure instead of a hardcoded one. It can be dynamically builded up
according to the extensions.
This approach has several benefits:
1. Provides support for heterogeneous cpu architectures. As we add decoder in
   RISCVCPU, each cpu can have their own decoder, and the decoders can be
   different due to cpu's features.
2. Improve the decoding efficiency. We run the guard_func to see if the decoder
   can be added to the dynamic_decoder when building up the decoder. Therefore,
   there is no need to run the guard_func when decoding each instruction. It can
   improve the decoding efficiency
3. For vendor or dynamic cpus, it allows them to customize their own decoder
   functions to improve decoding efficiency, especially when vendor-defined
   instruction sets increase. Because of dynamic building up, it can skip the other
   decoder guard functions when decoding.
4. Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
   overhead for users that don't need this particular vendor decoder.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  1 +
 target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
 target/riscv/cpu.c         |  1 +
 target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
 target/riscv/translate.c   | 31 +++++++++++++++----------------
 5 files changed, 47 insertions(+), 16 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
     uint32_t pmu_avail_ctrs;
     /* Mapping of events to counters */
     GHashTable *pmu_event_ctr_map;
+    const GPtrArray *decoders;
 };
 
 /**
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.h
+++ b/target/riscv/tcg/tcg-cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
 
+struct DisasContext;
+struct RISCVCPUConfig;
+typedef struct RISCVDecoder {
+    bool (*guard_func)(const struct RISCVCPUConfig *);
+    bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+} RISCVDecoder;
+
+typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+
+extern const size_t decoder_table_size;
+
+extern const RISCVDecoder decoder_table[];
+
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
+
 #endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
             error_propagate(errp, local_err);
             return;
         }
+        riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
     } else if (kvm_enabled()) {
         riscv_kvm_cpu_finalize_features(cpu, &local_err);
         if (local_err != NULL) {
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
     }
 }
 
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
+{
+    GPtrArray *dynamic_decoders;
+    dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
+    for (size_t i = 0; i < decoder_table_size; ++i) {
+        if (decoder_table[i].guard_func &&
+            decoder_table[i].guard_func(&cpu->cfg)) {
+            g_ptr_array_add(dynamic_decoders,
+                            (gpointer)decoder_table[i].riscv_cpu_decode_fn);
+        }
+    }
+
+    cpu->decoders = dynamic_decoders;
+}
+
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
 {
     return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-info.c.inc"
 #undef  HELPER_H
 
+#include "tcg/tcg-cpu.h"
+
 /* global register indices */
 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     /* FRM is known to contain a valid value. */
     bool frm_valid;
     bool insn_start_updated;
+    const GPtrArray *decoders;
 } DisasContext;
 
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
     return (first_word & 3) == 3 ? 4 : 2;
 }
 
+const RISCVDecoder decoder_table[] = {
+    { always_true_p, decode_insn32 },
+    { has_xthead_p, decode_xthead},
+    { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
+};
+
+const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
+
 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 {
-    /*
-     * A table with predicate (i.e., guard) functions and decoder functions
-     * that are tested in-order until a decoder matches onto the opcode.
-     */
-    static const struct {
-        bool (*guard_func)(const RISCVCPUConfig *);
-        bool (*decode_func)(DisasContext *, uint32_t);
-    } decoders[] = {
-        { always_true_p,  decode_insn32 },
-        { has_xthead_p, decode_xthead },
-        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
-    };
-
     ctx->virt_inst_excp = false;
     ctx->cur_insn_len = insn_len(opcode);
     /* Check for compressed insn */
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
                                              ctx->base.pc_next + 2));
         ctx->opcode = opcode32;
 
-        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
-            if (decoders[i].guard_func(ctx->cfg_ptr) &&
-                decoders[i].decode_func(ctx, opcode32)) {
+        for (guint i = 0; i < ctx->decoders->len; ++i) {
+            riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
+            if (func(ctx, opcode32)) {
                 return;
             }
         }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
     ctx->zero = tcg_constant_tl(0);
     ctx->virt_inst_excp = false;
+    ctx->decoders = cpu->decoders;
 }
 
 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
-- 
2.45.1

From: Christoph Müllner <christoph.muellner@vrull.eu>

The th.sxstatus CSR can be used to identify available custom extension
on T-Head CPUs. The CSR is documented here:
  https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc

An important property of this patch is, that the th.sxstatus MAEE field
is not set (indicating that XTheadMae is not available).
XTheadMae is a memory attribute extension (similar to Svpbmt) which is
implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
in PTEs that are marked as reserved. QEMU maintainers prefer to not
implement XTheadMae, so we need give kernels a mechanism to identify
if XTheadMae is available in a system or not. And this patch introduces
this mechanism in QEMU in a way that's compatible with real HW
(i.e., probing the th.sxstatus.MAEE bit).

Further context can be found on the list:
https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html

Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 MAINTAINERS              |  1 +
 target/riscv/cpu.h       |  3 ++
 target/riscv/cpu.c       |  1 +
 target/riscv/th_csr.c    | 79 ++++++++++++++++++++++++++++++++++++++++
 target/riscv/meson.build |  1 +
 5 files changed, 85 insertions(+)
 create mode 100644 target/riscv/th_csr.c

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
 S: Supported
 F: target/riscv/insn_trans/trans_xthead.c.inc
 F: target/riscv/xthead*.decode
+F: target/riscv/th_*
 F: disas/riscv-xthead*
 
 RISC-V XVentanaCondOps extension
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
+/* Implemented in th_csr.c */
+void th_register_custom_csrs(RISCVCPU *cpu);
+
 #endif /* RISCV_CPU_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
     cpu->cfg.mvendorid = THEAD_VENDOR_ID;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_SV39);
+    th_register_custom_csrs(cpu);
 #endif
 
     /* inherited from parent obj via riscv_cpu_init() */
diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/th_csr.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * T-Head-specific CSRs.
+ *
+ * Copyright (c) 2024 VRULL GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "cpu_vendorid.h"
+
+#define CSR_TH_SXSTATUS 0x5c0
+
+/* TH_SXSTATUS bits */
+#define TH_SXSTATUS_UCME        BIT(16)
+#define TH_SXSTATUS_MAEE        BIT(21)
+#define TH_SXSTATUS_THEADISAEE  BIT(22)
+
+typedef struct {
+    int csrno;
+    int (*insertion_test)(RISCVCPU *cpu);
+    riscv_csr_operations csr_ops;
+} riscv_csr;
+
+static RISCVException smode(CPURISCVState *env, int csrno)
+{
+    if (riscv_has_ext(env, RVS)) {
+        return RISCV_EXCP_NONE;
+    }
+
+    return RISCV_EXCP_ILLEGAL_INST;
+}
+
+static int test_thead_mvendorid(RISCVCPU *cpu)
+{
+    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
+        return -1;
+    }
+
+    return 0;
+}
+
+static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
+                                       target_ulong *val)
+{
+    /* We don't set MAEE here, because QEMU does not implement MAEE. */
+    *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
+    return RISCV_EXCP_NONE;
+}
+
+static riscv_csr th_csr_list[] = {
+    {
+        .csrno = CSR_TH_SXSTATUS,
+        .insertion_test = test_thead_mvendorid,
+        .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
+    }
+};
+
+void th_register_custom_csrs(RISCVCPU *cpu)
+{
+    for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
+        int csrno = th_csr_list[i].csrno;
+        riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
+        if (!th_csr_list[i].insertion_test(cpu)) {
+            riscv_set_csr_ops(csrno, csr_ops);
+        }
+    }
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
   'monitor.c',
   'machine.c',
   'pmu.c',
+  'th_csr.c',
   'time_helper.c',
   'riscv-qmp-cmds.c',
 ))
-- 
2.45.1

From: Max Chou <max.chou@sifive.com>

According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
instructions will be affected by Zvfhmin extension.
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
conversions of

* From 1*SEW(16/32) to 2*SEW(32/64)
* From 2*SEW(32/64) to 1*SEW(16/32)

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

From: Max Chou <max.chou@sifive.com>

The require_scale_rvf function only checks the double width operator for
the vector floating point widen instructions, so most of the widen
checking functions need to add require_rvf for single width operator.

The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
integer to double width float, so the opfxv_widen_check function doesn’t
need require_rvf for the single width operator(integer).

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
 1 file changed, 5 insertions(+)

From: Max Chou <max.chou@sifive.com>

If the checking functions check both the single and double width
operators at the same time, then the single width operator checking
functions (require_rvf[min]) will check whether the SEW is 8.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_ds(s, a->rd, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dd(s, a->rd, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
            require_rvfmin(s) &&
-           require_scale_rvfmin(s) &&
-           (s->sew != MO_8);
+           require_scale_rvfmin(s);
 }
 
 #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvfmin(s) &&
-           require_scale_rvfmin(s) &&
-           (s->sew != MO_8);
+           require_scale_rvfmin(s);
 }
 
 static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvf(s) &&
-           require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           require_scale_rvf(s);
 }
 
 #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
 {
     return reduction_widen_check(s, a) &&
            require_rvf(s) &&
-           require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           require_scale_rvf(s);
 }
 
 GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

raise_mmu_exception(), as is today, is prioritizing guest page faults by
checking first if virt_enabled && !first_stage, and then considering the
regular inst/load/store faults.

There's no mention in the spec about guest page fault being a higher
priority that PMP faults. In fact, privileged spec section 3.7.1 says:

"Attempting to fetch an instruction from a PMP region that does not have
execute permissions raises an instruction access-fault exception.
Attempting to execute a load or load-reserved instruction which accesses
a physical address within a PMP region without read permissions raises a
load access-fault exception. Attempting to execute a store,
store-conditional, or AMO instruction which accesses a physical address
within a PMP region without write permissions raises a store
access-fault exception."

So, in fact, we're doing it wrong - PMP faults should always be thrown,
regardless of also being a first or second stage fault.

The way riscv_cpu_tlb_fill() and get_physical_address() work is
adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
reflected in the 'pmp_violation' flag. What we need is to change
raise_mmu_exception() to prioritize it.

Reported-by: Joseph Chan <jchan@ventanamicro.com>
Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
 
     switch (access_type) {
     case MMU_INST_FETCH:
-        if (env->virt_enabled && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
+        } else if (env->virt_enabled && !first_stage) {
             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
         }
         break;
     case MMU_DATA_LOAD:
-        if (two_stage && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
+        } else if (two_stage && !first_stage) {
             cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
         }
         break;
     case MMU_DATA_STORE:
-        if (two_stage && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
+        } else if (two_stage && !first_stage) {
             cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
-                RISCV_EXCP_STORE_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
         }
         break;
     default:
-- 
2.45.1

From: Alexei Filippov <alexei.filippov@syntacore.com>

Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
translation part, mtval2 will be set in case of successes 2 stage translation but
failed pmp check.

In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
page-fault is taken into M-mode, mtval2 is written with either zero or guest
physical address that faulted, shifted by 2 bits. *For other traps, mtval2
is set to zero...*

Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                               __func__, pa, ret, prot_pmp, tlb_size);
 
                 prot &= prot_pmp;
-            }
-
-            if (ret != TRANSLATE_SUCCESS) {
+            } else {
                 /*
                  * Guest physical address translation failed, this is a HS
                  * level exception
                  */
                 first_stage_error = false;
-                env->guest_phys_fault_addr = (im_address |
-                                              (address &
-                                               (TARGET_PAGE_SIZE - 1))) >> 2;
+                if (ret != TRANSLATE_PMP_FAIL) {
+                    env->guest_phys_fault_addr = (im_address |
+                                                  (address &
+                                                   (TARGET_PAGE_SIZE - 1))) >> 2;
+                }
             }
         }
     } else {
-- 
2.45.1

From: Rob Bradford <rbradford@rivosinc.com>

This extension has now been ratified:
https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
removed.

Since this is now a ratified extension add it to the list of extensions
included in the "max" CPU variant.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c         | 2 +-
 target/riscv/tcg/tcg-cpu.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
     MISA_EXT_INFO(RVV, "v", "Vector operations"),
     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
-    MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
+    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
 };
 
 static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
     const RISCVCPUMultiExtConfig *prop;
 
     /* Enable RVG, RVJ and RVV that are disabled by default */
-    riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
+    riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
 
     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
         isa_ext_update_enabled(cpu, prop->offset, true);
-- 
2.45.1

From: Alistair Francis <alistair23@gmail.com>

When running the instruction

```
    cbo.flush 0(x0)
```

QEMU would segfault.

The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
allocated.

In order to fix this let's use the existing get_address()
helper. This also has the benefit of performing pointer mask
calculations on the address specified in rs1.

The pointer masking specificiation specifically states:

"""
Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
"""

So this is the correct behaviour and we previously have been incorrectly
not masking the address.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
@@ -XXX,XX +XXX,XX @@
 static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_clean_flush(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_clean_flush(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_inval(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
 {
     REQUIRE_ZICBOZ(ctx);
-    gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_zero(tcg_env, src);
     return true;
 }
-- 
2.45.1

From: Yong-Xuan Wang <yongxuan.wang@sifive.com>

In AIA spec, each hart (or each hart within a group) has a unique hart
number to locate the memory pages of interrupt files in the address
space. The number of bits required to represent any hart number is equal
to ceil(log2(hmax + 1)), where hmax is the largest hart number among
groups.

However, if the largest hart number among groups is a power of 2, QEMU
will pass an inaccurate hart-index-bit setting to Linux. For example, when
the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
to represent 4 harts, but we passes 3 to Linux. The code needs to be
updated to ensure accurate hart-index-bit settings.

Additionally, a Linux patch[1] is necessary to correctly recover the hart
index when the guest OS has only 1 hart, where the hart-index-bit is 0.

[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
         }
     }
 
-    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+
+    if (max_hart_per_socket > 1) {
+        max_hart_per_socket--;
+        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+    } else {
+        hart_bits = 0;
+    }
+
     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
                             KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
                             &hart_bits, true, NULL);
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
in bytes, when in this context we want 'reg_width' as the length in
bits.

Fix 'reg_width' back to the value in bits like 7cb59921c05a
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
beforehand.

While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
clarity about what the variable represents. 'bitsize' is also used in
riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
gdb_feature_builder_append_reg().

Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
 static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
-    int reg_width = cpu->cfg.vlenb;
+    int bitsize = cpu->cfg.vlenb << 3;
     GDBFeatureBuilder builder;
     int i;
 
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 
     /* First define types and totals in a whole VL */
     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-        int count = reg_width / vec_lanes[i].size;
+        int count = bitsize / vec_lanes[i].size;
         gdb_feature_builder_append_tag(
             &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
             vec_lanes[i].id, vec_lanes[i].gdb_type, count);
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
     /* Define vector registers */
     for (i = 0; i < 32; i++) {
         gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
-                                       reg_width, i, "riscv_vector", "vector");
+                                       bitsize, i, "riscv_vector", "vector");
     }
 
     gdb_feature_builder_end(&builder);
-- 
2.45.1

From: Alistair Francis <alistair23@gmail.com>

Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
CSRs are part of the disassembly.

Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Fixes: ea10325917 ("RISC-V Disassembler")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 64 insertions(+), 1 deletion(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index XXXXXXX..XXXXXXX 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x0383: return "mibound";
     case 0x0384: return "mdbase";
     case 0x0385: return "mdbound";
-    case 0x03a0: return "pmpcfg3";
+    case 0x03a0: return "pmpcfg0";
+    case 0x03a1: return "pmpcfg1";
+    case 0x03a2: return "pmpcfg2";
+    case 0x03a3: return "pmpcfg3";
+    case 0x03a4: return "pmpcfg4";
+    case 0x03a5: return "pmpcfg5";
+    case 0x03a6: return "pmpcfg6";
+    case 0x03a7: return "pmpcfg7";
+    case 0x03a8: return "pmpcfg8";
+    case 0x03a9: return "pmpcfg9";
+    case 0x03aa: return "pmpcfg10";
+    case 0x03ab: return "pmpcfg11";
+    case 0x03ac: return "pmpcfg12";
+    case 0x03ad: return "pmpcfg13";
+    case 0x03ae: return "pmpcfg14";
+    case 0x03af: return "pmpcfg15";
     case 0x03b0: return "pmpaddr0";
     case 0x03b1: return "pmpaddr1";
     case 0x03b2: return "pmpaddr2";
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x03bd: return "pmpaddr13";
     case 0x03be: return "pmpaddr14";
     case 0x03bf: return "pmpaddr15";
+    case 0x03c0: return "pmpaddr16";
+    case 0x03c1: return "pmpaddr17";
+    case 0x03c2: return "pmpaddr18";
+    case 0x03c3: return "pmpaddr19";
+    case 0x03c4: return "pmpaddr20";
+    case 0x03c5: return "pmpaddr21";
+    case 0x03c6: return "pmpaddr22";
+    case 0x03c7: return "pmpaddr23";
+    case 0x03c8: return "pmpaddr24";
+    case 0x03c9: return "pmpaddr25";
+    case 0x03ca: return "pmpaddr26";
+    case 0x03cb: return "pmpaddr27";
+    case 0x03cc: return "pmpaddr28";
+    case 0x03cd: return "pmpaddr29";
+    case 0x03ce: return "pmpaddr30";
+    case 0x03cf: return "pmpaddr31";
+    case 0x03d0: return "pmpaddr32";
+    case 0x03d1: return "pmpaddr33";
+    case 0x03d2: return "pmpaddr34";
+    case 0x03d3: return "pmpaddr35";
+    case 0x03d4: return "pmpaddr36";
+    case 0x03d5: return "pmpaddr37";
+    case 0x03d6: return "pmpaddr38";
+    case 0x03d7: return "pmpaddr39";
+    case 0x03d8: return "pmpaddr40";
+    case 0x03d9: return "pmpaddr41";
+    case 0x03da: return "pmpaddr42";
+    case 0x03db: return "pmpaddr43";
+    case 0x03dc: return "pmpaddr44";
+    case 0x03dd: return "pmpaddr45";
+    case 0x03de: return "pmpaddr46";
+    case 0x03df: return "pmpaddr47";
+    case 0x03e0: return "pmpaddr48";
+    case 0x03e1: return "pmpaddr49";
+    case 0x03e2: return "pmpaddr50";
+    case 0x03e3: return "pmpaddr51";
+    case 0x03e4: return "pmpaddr52";
+    case 0x03e5: return "pmpaddr53";
+    case 0x03e6: return "pmpaddr54";
+    case 0x03e7: return "pmpaddr55";
+    case 0x03e8: return "pmpaddr56";
+    case 0x03e9: return "pmpaddr57";
+    case 0x03ea: return "pmpaddr58";
+    case 0x03eb: return "pmpaddr59";
+    case 0x03ec: return "pmpaddr60";
+    case 0x03ed: return "pmpaddr61";
+    case 0x03ee: return "pmpaddr62";
+    case 0x03ef: return "pmpaddr63";
     case 0x0780: return "mtohost";
     case 0x0781: return "mfromhost";
     case 0x0782: return "mreset";
-- 
2.45.1

From: Yu-Ming Chang <yumin686@andestech.com>

Both CSRRS and CSRRC always read the addressed CSR and cause any read side
effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
holding a zero value other than x0, the instruction will still attempt to write
the unmodified value back to the CSR and will cause any attendant side effects.

So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
a register holding a zero value, an illegal instruction exception should be
raised.

Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h       |  4 ++++
 target/riscv/csr.c       | 51 ++++++++++++++++++++++++++++++++++++----
 target/riscv/op_helper.c |  6 ++---
 3 files changed, 53 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
 void riscv_cpu_update_mask(CPURISCVState *env);
 bool riscv_cpu_is_32bit(RISCVCPU *cpu);
 
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+                          target_ulong *ret_value);
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask);
@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
                                           target_ulong new_value,
                                           target_ulong write_mask);
 
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                               Int128 *ret_value);
 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 *ret_value,
                                 Int128 new_value, Int128 write_mask);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
 
 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
                                                int csrno,
-                                               bool write_mask)
+                                               bool write)
 {
     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
     bool read_only = get_field(csrno, 0xC00) == 3;
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
     }
 
     /* read / write check */
-    if (write_mask && read_only) {
+    if (write && read_only) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+                           target_ulong *ret_value)
+{
+    RISCVException ret = riscv_csrrw_check(env, csrno, false);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
+}
+
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask)
 {
-    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
+    RISCVException ret = riscv_csrrw_check(env, csrno, true);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                               Int128 *ret_value)
+{
+    RISCVException ret;
+
+    ret = riscv_csrrw_check(env, csrno, false);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    if (csr_ops[csrno].read128) {
+        return riscv_csrrw_do128(env, csrno, ret_value,
+                                 int128_zero(), int128_zero());
+    }
+
+    /*
+     * Fall back to 64-bit version for now, if the 128-bit alternative isn't
+     * at all defined.
+     * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
+     * significant), for those, this fallback is correctly handling the
+     * accesses
+     */
+    target_ulong old_value;
+    ret = riscv_csrrw_do64(env, csrno, &old_value,
+                           (target_ulong)0,
+                           (target_ulong)0);
+    if (ret == RISCV_EXCP_NONE && ret_value) {
+        *ret_value = int128_make64(old_value);
+    }
+    return ret;
+}
+
 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 *ret_value,
                                 Int128 new_value, Int128 write_mask)
 {
     RISCVException ret;
 
-    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
+    ret = riscv_csrrw_check(env, csrno, true);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
     }
 
     target_ulong val = 0;
-    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
+    RISCVException ret = riscv_csrr(env, csr, &val);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
 target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
 {
     Int128 rv = int128_zero();
-    RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
-                                          int128_zero(),
-                                          int128_zero());
+    RISCVException ret = riscv_csrr_i128(env, csr, &rv);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
-- 
2.45.1

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 222059a0fccf4af3be776fe35a5ea2d6a68f9a0b:

Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into staging (2022-12-21 18:08:09 +0000)

are available in the Git repository at:

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20221222-1

for you to fetch changes up to 71a9bc59728a054036f3db7dd82dab8f8bd2baf9:

hw/intc: sifive_plic: Fix the pending register range check (2022-12-22 08:36:30 +1000)

----------------------------------------------------------------
First RISC-V PR for QEMU 8.0

* Fix PMP propagation for tlb
* Collection of bug fixes
* Add the `FIELDx_1CLEAR()` macro
* Bump the OpenTitan supported version
* Add smstateen support
* Support native debug icount trigger
* Remove the redundant ipi-id property in the virt machine
* Support cache-related PMU events in virtual mode
* Add some missing PolarFire SoC io regions
* Fix mret exception cause when no pmp rule is configured
* Fix bug where disabling compressed instructions would crash QEMU
* Add Zawrs ISA extension support
* A range of code refactoring and cleanups

----------------------------------------------------------------
Anup Patel (1):
      target/riscv: Typo fix in sstc() predicate

Atish Patra (1):
      hw/riscv: virt: Remove the redundant ipi-id property

Bin Meng (20):
      target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state()
      target/riscv: Fix mret exception cause when no pmp rule is configured
      target/riscv: Simplify helper_sret() a little bit
      target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+
      hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC
      hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers
      hw/riscv: Fix opentitan dependency to SIFIVE_PLIC
      hw/riscv: Sort machines Kconfig options in alphabetical order
      hw/riscv: spike: Remove misleading comments
      hw/intc: sifive_plic: Drop PLICMode_H
      hw/intc: sifive_plic: Improve robustness of the PLIC config parser
      hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize()
      hw/intc: sifive_plic: Update "num-sources" property default value
      hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC
      hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC
      hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"
      hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb
      hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0
      hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization
      hw/intc: sifive_plic: Fix the pending register range check

Christoph Muellner (1):
      RISC-V: Add Zawrs ISA extension support

Conor Dooley (3):
      hw/misc: pfsoc: add fabric clocks to ioscb
      hw/riscv: pfsoc: add missing FICs as unimplemented
      hw/{misc, riscv}: pfsoc: add system controller as unimplemented

Frédéric Pétrot (1):
      hw/intc: sifive_plic: Renumber the S irqs for numa support

Jim Shu (2):
      target/riscv: support cache-related PMU events in virtual mode
      hw/intc: sifive_plic: fix out-of-bound access of source_priority array

LIU Zhiwei (5):
      target/riscv: Fix PMP propagation for tlb
      target/riscv: Add itrigger support when icount is not enabled
      target/riscv: Add itrigger support when icount is enabled
      target/riscv: Enable native debug itrigger
      target/riscv: Add itrigger_enabled field to CPURISCVState

Mayuresh Chitale (3):
      target/riscv: Add smstateen support
      target/riscv: smstateen check for h/s/envcfg
      target/riscv: generate virtual instruction exception

Richard Henderson (4):
      tcg/riscv: Fix range matched by TCG_CT_CONST_M12
      tcg/riscv: Fix reg overlap case in tcg_out_addsub2
      tcg/riscv: Fix base register for user-only qemu_ld/st
      target/riscv: Set pc_succ_insn for !rvc illegal insn

Wilfred Mallawa (4):
      hw/registerfields: add `FIELDx_1CLEAR()` macro
      hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro
      hw/riscv/opentitan: bump opentitan
      hw/riscv/opentitan: add aon_timer base unimpl

From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Only the pmp index that be checked by pmp_hart_has_privs can be used
by pmp_get_tlb_size to avoid an error pmp index.

Before modification, we may use an error pmp index. For example,
we check address 0x4fc, and the size 0x4 in pmp_hart_has_privs. If there
is an pmp rule, valid range is [0x4fc, 0x500), then pmp_hart_has_privs
will return true;

However, this checked pmp index is discarded as pmp_hart_has_privs
return bool value. In pmp_is_range_in_tlb, it will traverse all pmp
rules. The tlb_sa will be 0x0, and tlb_ea will be 0xfff. If there is
a pmp rule [0x10, 0x14), it will be misused as it is legal in
pmp_get_tlb_size.

As we have already known the correct pmp index, just remove the
remove the pmp_is_range_in_tlb and get tlb size directly from
pmp_get_tlb_size.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221012060016.30856-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.h        |  6 +--
 target/riscv/cpu_helper.c | 16 ++++---
 target/riscv/pmp.c        | 90 +++++++++++++--------------------------
 3 files changed, 42 insertions(+), 70 deletions(-)

diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -XXX,XX +XXX,XX @@ target_ulong mseccfg_csr_read(CPURISCVState *env);
 void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
     target_ulong val);
 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
-bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
+int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
     target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
     target_ulong mode);
-bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
-                         target_ulong *tlb_size);
+target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
+                              target_ulong tlb_sa, target_ulong tlb_ea);
 void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
 void pmp_update_rule_nums(CPURISCVState *env);
 uint32_t pmp_get_num_rules(CPURISCVState *env);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
                                     int mode)
 {
     pmp_priv_t pmp_priv;
-    target_ulong tlb_size_pmp = 0;
+    int pmp_index = -1;
 
     if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
         return TRANSLATE_SUCCESS;
     }
 
-    if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv,
-                            mode)) {
+    pmp_index = pmp_hart_has_privs(env, addr, size, 1 << access_type,
+                                   &pmp_priv, mode);
+    if (pmp_index < 0) {
         *prot = 0;
         return TRANSLATE_PMP_FAIL;
     }
 
     *prot = pmp_priv_to_page_prot(pmp_priv);
-    if (tlb_size != NULL) {
-        if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) {
-            *tlb_size = tlb_size_pmp;
-        }
+    if ((tlb_size != NULL) && pmp_index != MAX_RISCV_PMPS) {
+        target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1);
+        target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1;
+
+        *tlb_size = pmp_get_tlb_size(env, pmp_index, tlb_sa, tlb_ea);
     }
 
     return TRANSLATE_SUCCESS;
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
 
 /*
  * Check if the address has required RWX privs to complete desired operation
+ * Return PMP rule index if a pmp rule match
+ * Return MAX_RISCV_PMPS if default match
+ * Return negtive value if no match
  */
-bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
+int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
     target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
     target_ulong mode)
 {
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
 
     /* Short cut if no rules */
     if (0 == pmp_get_num_rules(env)) {
-        return pmp_hart_has_privs_default(env, addr, size, privs,
-                                          allowed_privs, mode);
+        if (pmp_hart_has_privs_default(env, addr, size, privs,
+                                       allowed_privs, mode)) {
+            ret = MAX_RISCV_PMPS;
+        }
     }
 
     if (size == 0) {
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
         if ((s + e) == 1) {
             qemu_log_mask(LOG_GUEST_ERROR,
                           "pmp violation - access is partially inside\n");
-            ret = 0;
+            ret = -1;
             break;
         }
 
@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
                 }
             }
 
-            ret = ((privs & *allowed_privs) == privs);
+            if ((privs & *allowed_privs) == privs) {
+                ret = i;
+            }
             break;
         }
     }
 
     /* No rule matched */
     if (ret == -1) {
-        return pmp_hart_has_privs_default(env, addr, size, privs,
-                                          allowed_privs, mode);
+        if (pmp_hart_has_privs_default(env, addr, size, privs,
+                                       allowed_privs, mode)) {
+            ret = MAX_RISCV_PMPS;
+        }
     }
 
-    return ret == 1 ? true : false;
+    return ret;
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ target_ulong mseccfg_csr_read(CPURISCVState *env)
  * Calculate the TLB size if the start address or the end address of
  * PMP entry is presented in the TLB page.
  */
-static target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
-                                     target_ulong tlb_sa, target_ulong tlb_ea)
+target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
+                              target_ulong tlb_sa, target_ulong tlb_ea)
 {
     target_ulong pmp_sa = env->pmp_state.addr[pmp_index].sa;
     target_ulong pmp_ea = env->pmp_state.addr[pmp_index].ea;
 
-    if (pmp_sa >= tlb_sa && pmp_ea <= tlb_ea) {
-        return pmp_ea - pmp_sa + 1;
-    }
-
-    if (pmp_sa >= tlb_sa && pmp_sa <= tlb_ea && pmp_ea >= tlb_ea) {
-        return tlb_ea - pmp_sa + 1;
-    }
-
-    if (pmp_ea <= tlb_ea && pmp_ea >= tlb_sa && pmp_sa <= tlb_sa) {
-        return pmp_ea - tlb_sa + 1;
-    }
-
-    return 0;
-}
-
-/*
- * Check is there a PMP entry which range covers this page. If so,
- * try to find the minimum granularity for the TLB size.
- */
-bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
-                         target_ulong *tlb_size)
-{
-    int i;
-    target_ulong val;
-    target_ulong tlb_ea = (tlb_sa + TARGET_PAGE_SIZE - 1);
-
-    for (i = 0; i < MAX_RISCV_PMPS; i++) {
-        val = pmp_get_tlb_size(env, i, tlb_sa, tlb_ea);
-        if (val) {
-            if (*tlb_size == 0 || *tlb_size > val) {
-                *tlb_size = val;
-            }
-        }
-    }
-
-    if (*tlb_size != 0) {
+    if (pmp_sa <= tlb_sa && pmp_ea >= tlb_ea) {
+        return TARGET_PAGE_SIZE;
+    } else {
         /*
-         * At this point we have a tlb_size that is the smallest possible size
-         * That fits within a TARGET_PAGE_SIZE and the PMP region.
-         *
-         * If the size is less then TARGET_PAGE_SIZE we drop the size to 1.
-         * This means the result isn't cached in the TLB and is only used for
-         * a single translation.
-         */
-        if (*tlb_size < TARGET_PAGE_SIZE) {
-            *tlb_size = 1;
-        }
-
-        return true;
+        * At this point we have a tlb_size that is the smallest possible size
+        * That fits within a TARGET_PAGE_SIZE and the PMP region.
+        *
+        * If the size is less then TARGET_PAGE_SIZE we drop the size to 1.
+        * This means the result isn't cached in the TLB and is only used for
+        * a single translation.
+        */
+        return 1;
     }
-
-    return false;
 }
 
 /*
-- 
2.38.1

From: Wilfred Mallawa <wilfred.mallawa@wdc.com>

Adds a helper macro that implements the register `w1c`
functionality.

Ex:
  uint32_t data = FIELD32_1CLEAR(val, REG, FIELD);

If ANY bits of the specified `FIELD` is set
then the respective field is cleared and returned to `data`.

If the field is cleared (0), then no change and
val is returned.

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221017054950.317584-2-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/registerfields.h | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/registerfields.h
+++ b/include/hw/registerfields.h
@@ -XXX,XX +XXX,XX @@
                   R_ ## reg ## _ ## field ## _LENGTH, _v.v);              \
     _d; })
 
+/*
+ * Clear the specified field in storage if
+ * any field bits are set, else no changes made. Implements
+ * single/multi-bit `w1c`
+ *
+ */
+#define FIELD8_1CLEAR(storage, reg, field)                                \
+    (FIELD_EX8(storage, reg, field) ?                                     \
+    FIELD_DP8(storage, reg, field, 0x00) : storage)
+
+#define FIELD16_1CLEAR(storage, reg, field)                               \
+    (FIELD_EX16(storage, reg, field) ?                                    \
+    FIELD_DP16(storage, reg, field, 0x00) : storage)
+
+#define FIELD32_1CLEAR(storage, reg, field)                               \
+    (FIELD_EX32(storage, reg, field) ?                                    \
+    FIELD_DP32(storage, reg, field, 0x00) : storage)
+
+#define FIELD64_1CLEAR(storage, reg, field)                               \
+    (FIELD_EX64(storage, reg, field) ?                                    \
+    FIELD_DP64(storage, reg, field, 0x00) : storage)
+
 #define FIELD_SDP8(storage, reg, field, val) ({                           \
     struct {                                                              \
         signed int v:R_ ## reg ## _ ## field ## _LENGTH;                  \
-- 
2.38.1

From: Wilfred Mallawa <wilfred.mallawa@wdc.com>

use the `FIELD32_1CLEAR` macro to implement register
`rw1c` functionality to `ibex_spi`.

This change was tested by running the `SPI_HOST` from TockOS.

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221017054950.317584-3-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/ssi/ibex_spi_host.c | 21 +++++++++------------
 1 file changed, 9 insertions(+), 12 deletions(-)

diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/ibex_spi_host.c
+++ b/hw/ssi/ibex_spi_host.c
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
 {
     IbexSPIHostState *s = opaque;
     uint32_t val32 = val64;
-    uint32_t shift_mask = 0xff, status = 0, data = 0;
+    uint32_t shift_mask = 0xff, status = 0;
     uint8_t txqd_len;
 
     trace_ibex_spi_host_write(addr, size, val64);
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
     case IBEX_SPI_HOST_INTR_STATE:
         /* rw1c status register */
         if (FIELD_EX32(val32, INTR_STATE, ERROR)) {
-            data = FIELD_DP32(data, INTR_STATE, ERROR, 0);
+            s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], INTR_STATE, ERROR);
         }
         if (FIELD_EX32(val32, INTR_STATE, SPI_EVENT)) {
-            data = FIELD_DP32(data, INTR_STATE, SPI_EVENT, 0);
+            s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], INTR_STATE, SPI_EVENT);
         }
-        s->regs[addr] = data;
         break;
     case IBEX_SPI_HOST_INTR_ENABLE:
         s->regs[addr] = val32;
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
      *  When an error occurs, the corresponding bit must be cleared
      *  here before issuing any further commands
      */
-        status = s->regs[addr];
         /* rw1c status register */
         if (FIELD_EX32(val32, ERROR_STATUS, CMDBUSY)) {
-            status = FIELD_DP32(status, ERROR_STATUS, CMDBUSY, 0);
+            s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, CMDBUSY);
         }
         if (FIELD_EX32(val32, ERROR_STATUS, OVERFLOW)) {
-            status = FIELD_DP32(status, ERROR_STATUS, OVERFLOW, 0);
+            s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, OVERFLOW);
         }
         if (FIELD_EX32(val32, ERROR_STATUS, UNDERFLOW)) {
-            status = FIELD_DP32(status, ERROR_STATUS, UNDERFLOW, 0);
+            s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, UNDERFLOW);
         }
         if (FIELD_EX32(val32, ERROR_STATUS, CMDINVAL)) {
-            status = FIELD_DP32(status, ERROR_STATUS, CMDINVAL, 0);
+            s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, CMDINVAL);
         }
         if (FIELD_EX32(val32, ERROR_STATUS, CSIDINVAL)) {
-            status = FIELD_DP32(status, ERROR_STATUS, CSIDINVAL, 0);
+            s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, CSIDINVAL);
         }
         if (FIELD_EX32(val32, ERROR_STATUS, ACCESSINVAL)) {
-            status = FIELD_DP32(status, ERROR_STATUS, ACCESSINVAL, 0);
+            s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, ACCESSINVAL);
         }
-        s->regs[addr] = status;
         break;
     case IBEX_SPI_HOST_EVENT_ENABLE:
     /* Controls which classes of SPI events raise an interrupt. */
-- 
2.38.1

From: Richard Henderson <richard.henderson@linaro.org>

We were matching a signed 13-bit range, not a 12-bit range.
Expand the commentary within the function and be explicit
about all of the ranges.

Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221022095821.2441874-1-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 tcg/riscv/tcg-target.c.inc | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
     if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
         return 1;
     }
-    if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
+    /*
+     * Sign extended from 12 bits: [-0x800, 0x7ff].
+     * Used for most arithmetic, as this is the isa field.
+     */
+    if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) {
         return 1;
     }
-    if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) {
+    /*
+     * Sign extended from 12 bits, negated: [-0x7ff, 0x800].
+     * Used for subtraction, where a constant must be handled by ADDI.
+     */
+    if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) {
         return 1;
     }
-    if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) {
+    /*
+     * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff].
+     * Used by addsub2, which may need the negative operation,
+     * and requires the modified constant to be representable.
+     */
+    if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) {
         return 1;
     }
     return 0;
-- 
2.38.1

From: Richard Henderson <richard.henderson@linaro.org>

There was a typo using opc_addi instead of opc_add with the
two registers.  While we're at it, simplify the gating test
to al == bl to improve dynamic scheduling even when the
output register does not overlap the inputs.

Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221020233836.2341671-1-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 tcg/riscv/tcg-target.c.inc | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_addsub2(TCGContext *s,
         if (cbl) {
             tcg_out_opc_imm(s, opc_addi, rl, al, bl);
             tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl);
-        } else if (rl == al && rl == bl) {
+        } else if (al == bl) {
+            /*
+             * If the input regs overlap, this is a simple doubling
+             * and carry-out is the input msb.  This special case is
+             * required when the output reg overlaps the input,
+             * but we might as well use it always.
+             */
             tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0);
-            tcg_out_opc_reg(s, opc_addi, rl, al, bl);
+            tcg_out_opc_reg(s, opc_add, rl, al, al);
         } else {
             tcg_out_opc_reg(s, opc_add, rl, al, bl);
             tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0,
-- 
2.38.1

From: Richard Henderson <richard.henderson@linaro.org>

When guest_base != 0, we were not coordinating the usage of
TCG_REG_TMP0 as base properly, leading to a previous zero-extend
of the input address being discarded.

Shuffle the alignment check to the front, because that does not
depend on the zero-extend, and it keeps the register usage clear.
Set base after each step of the address arithmetic instead of before.

Return the base register used from tcg_out_tlb_load, so as to
keep that register choice localized to that function.

Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221023233337.2846860-1-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 tcg/riscv/tcg-target.c.inc | 39 +++++++++++++++++++++-----------------
 1 file changed, 22 insertions(+), 17 deletions(-)

diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target)
     tcg_debug_assert(ok);
 }
 
-static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
-                             TCGReg addrh, MemOpIdx oi,
-                             tcg_insn_unit **label_ptr, bool is_load)
+static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
+                               TCGReg addrh, MemOpIdx oi,
+                               tcg_insn_unit **label_ptr, bool is_load)
 {
     MemOp opc = get_memop(oi);
     unsigned s_bits = opc & MO_SIZE;
@@ -XXX,XX +XXX,XX @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
         addrl = TCG_REG_TMP0;
     }
     tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl);
+    return TCG_REG_TMP0;
 }
 
 static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi,
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
 #else
     unsigned a_bits;
 #endif
-    TCGReg base = TCG_REG_TMP0;
+    TCGReg base;
 
     data_regl = *args++;
     data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
     opc = get_memop(oi);
 
 #if defined(CONFIG_SOFTMMU)
-    tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1);
+    base = tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1);
     tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
     add_qemu_ldst_label(s, 1, oi,
                         (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
                         data_regl, data_regh, addr_regl, addr_regh,
                         s->code_ptr, label_ptr);
 #else
-    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
-        tcg_out_ext32u(s, base, addr_regl);
-        addr_regl = base;
-    }
     a_bits = get_alignment_bits(opc);
     if (a_bits) {
         tcg_out_test_alignment(s, true, addr_regl, a_bits);
     }
+    base = addr_regl;
+    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+        tcg_out_ext32u(s, TCG_REG_TMP0, base);
+        base = TCG_REG_TMP0;
+    }
     if (guest_base != 0) {
-        tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
+        tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base);
+        base = TCG_REG_TMP0;
     }
     tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
 #endif
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
 #else
     unsigned a_bits;
 #endif
-    TCGReg base = TCG_REG_TMP0;
+    TCGReg base;
 
     data_regl = *args++;
     data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
     opc = get_memop(oi);
 
 #if defined(CONFIG_SOFTMMU)
-    tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0);
+    base = tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0);
     tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
     add_qemu_ldst_label(s, 0, oi,
                         (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
                         data_regl, data_regh, addr_regl, addr_regh,
                         s->code_ptr, label_ptr);
 #else
-    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
-        tcg_out_ext32u(s, base, addr_regl);
-        addr_regl = base;
-    }
     a_bits = get_alignment_bits(opc);
     if (a_bits) {
         tcg_out_test_alignment(s, false, addr_regl, a_bits);
     }
+    base = addr_regl;
+    if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+        tcg_out_ext32u(s, TCG_REG_TMP0, base);
+        base = TCG_REG_TMP0;
+    }
     if (guest_base != 0) {
-        tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
+        tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base);
+        base = TCG_REG_TMP0;
     }
     tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
 #endif
-- 
2.38.1

From: Wilfred Mallawa <wilfred.mallawa@wdc.com>

This patch updates the OpenTitan model to match
the specified register layout as per [1]. Which is also the latest
commit of OpenTitan supported by TockOS.

Note: Pinmux and Padctrl has been merged into Pinmux [2][3], this patch removes
any references to Padctrl. Note: OpenTitan doc [2] has not yet specified
much detail regarding this, except for a note that states `TODO: this
section needs to be updated to reflect the pinmux/padctrl merger`

[1] https://github.com/lowRISC/opentitan/blob/d072ac505f82152678d6e04be95c72b728a347b8/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
[2] https://docs.opentitan.org/hw/top_earlgrey/doc/design/
[3] https://docs.opentitan.org/hw/ip/pinmux/doc/#overview

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20221025043335.339815-2-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/opentitan.h |  9 ++++-----
 hw/riscv/opentitan.c         | 21 +++++++++++++--------
 2 files changed, 17 insertions(+), 13 deletions(-)

diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -XXX,XX +XXX,XX @@ enum {
     IBEX_DEV_RSTMGR,
     IBEX_DEV_CLKMGR,
     IBEX_DEV_PINMUX,
-    IBEX_DEV_PADCTRL,
     IBEX_DEV_USBDEV,
     IBEX_DEV_FLASH_CTRL,
     IBEX_DEV_PLIC,
@@ -XXX,XX +XXX,XX @@ enum {
     IBEX_UART0_RX_TIMEOUT_IRQ     = 7,
     IBEX_UART0_RX_PARITY_ERR_IRQ  = 8,
     IBEX_TIMER_TIMEREXPIRED0_0    = 127,
-    IBEX_SPI_HOST0_ERR_IRQ        = 151,
-    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 152,
-    IBEX_SPI_HOST1_ERR_IRQ        = 153,
-    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 154,
+    IBEX_SPI_HOST0_ERR_IRQ        = 134,
+    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 135,
+    IBEX_SPI_HOST1_ERR_IRQ        = 136,
+    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 137,
 };
 
 #endif
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/units.h"
 #include "sysemu/sysemu.h"
 
+/*
+ * This version of the OpenTitan machine currently supports
+ * OpenTitan RTL version:
+ * <lowRISC/opentitan@d072ac505f82152678d6e04be95c72b728a347b8>
+ *
+ * MMIO mapping as per (specified commit):
+ * lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
+ */
 static const MemMapEntry ibex_memmap[] = {
-    [IBEX_DEV_ROM] =            {  0x00008000,   0x8000 },
+    [IBEX_DEV_ROM] =            {  0x00008000,  0x8000 },
     [IBEX_DEV_RAM] =            {  0x10000000,  0x20000 },
     [IBEX_DEV_FLASH] =          {  0x20000000,  0x100000 },
     [IBEX_DEV_UART] =           {  0x40000000,  0x1000  },
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = {
     [IBEX_DEV_I2C] =            {  0x40080000,  0x1000  },
     [IBEX_DEV_PATTGEN] =        {  0x400e0000,  0x1000  },
     [IBEX_DEV_TIMER] =          {  0x40100000,  0x1000  },
-    [IBEX_DEV_SENSOR_CTRL] =    {  0x40110000,  0x1000  },
     [IBEX_DEV_OTP_CTRL] =       {  0x40130000,  0x4000  },
     [IBEX_DEV_LC_CTRL] =        {  0x40140000,  0x1000  },
-    [IBEX_DEV_USBDEV] =         {  0x40150000,  0x1000  },
+    [IBEX_DEV_ALERT_HANDLER] =  {  0x40150000,  0x1000  },
     [IBEX_DEV_SPI_HOST0] =      {  0x40300000,  0x1000  },
     [IBEX_DEV_SPI_HOST1] =      {  0x40310000,  0x1000  },
+    [IBEX_DEV_USBDEV] =         {  0x40320000,  0x1000  },
     [IBEX_DEV_PWRMGR] =         {  0x40400000,  0x1000  },
     [IBEX_DEV_RSTMGR] =         {  0x40410000,  0x1000  },
     [IBEX_DEV_CLKMGR] =         {  0x40420000,  0x1000  },
     [IBEX_DEV_PINMUX] =         {  0x40460000,  0x1000  },
-    [IBEX_DEV_PADCTRL] =        {  0x40470000,  0x1000  },
+    [IBEX_DEV_SENSOR_CTRL] =    {  0x40490000,  0x1000  },
     [IBEX_DEV_FLASH_CTRL] =     {  0x41000000,  0x1000  },
     [IBEX_DEV_AES] =            {  0x41100000,  0x1000  },
     [IBEX_DEV_HMAC] =           {  0x41110000,  0x1000  },
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = {
     [IBEX_DEV_ENTROPY] =        {  0x41160000,  0x1000  },
     [IBEX_DEV_EDNO] =           {  0x41170000,  0x1000  },
     [IBEX_DEV_EDN1] =           {  0x41180000,  0x1000  },
-    [IBEX_DEV_ALERT_HANDLER] =  {  0x411b0000,  0x1000  },
     [IBEX_DEV_NMI_GEN] =        {  0x411c0000,  0x1000  },
     [IBEX_DEV_PERI] =           {  0x411f0000,  0x10000 },
-    [IBEX_DEV_PLIC] =           {  0x48000000,  0x4005000  },
+    [IBEX_DEV_PLIC] =           {  0x48000000,  0x4005000 },
     [IBEX_DEV_FLASH_VIRTUAL] =  {  0x80000000,  0x80000 },
 };
 
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
         memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
     create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
         memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
-    create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
-        memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size);
     create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
         memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
     create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
-- 
2.38.1

From: Wilfred Mallawa <wilfred.mallawa@wdc.com>

Adds the updated `aon_timer` base as an unimplemented device. This is
used by TockOS, patch ensures the guest doesn't hit load faults.

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221025043335.339815-3-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/opentitan.h | 1 +
 hw/riscv/opentitan.c         | 3 +++
 2 files changed, 4 insertions(+)

From: Mayuresh Chitale <mchitale@ventanamicro.com>

Smstateen extension specifies a mechanism to close
the potential covert channels that could cause security issues.

This patch adds the CSRs defined in the specification and
the corresponding predicates and read/write functions.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221016124726.102129-2-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h      |   4 +
 target/riscv/cpu_bits.h |  37 +++++
 target/riscv/csr.c      | 316 ++++++++++++++++++++++++++++++++++++++++
 target/riscv/machine.c  |  21 +++
 4 files changed, 378 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
 
     /* CSRs for execution enviornment configuration */
     uint64_t menvcfg;
+    uint64_t mstateen[SMSTATEEN_MAX_COUNT];
+    uint64_t hstateen[SMSTATEEN_MAX_COUNT];
+    uint64_t sstateen[SMSTATEEN_MAX_COUNT];
     target_ulong senvcfg;
     uint64_t henvcfg;
 #endif
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_ifencei;
     bool ext_icsr;
     bool ext_zihintpause;
+    bool ext_smstateen;
     bool ext_sstc;
     bool ext_svinval;
     bool ext_svnapot;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 /* Supervisor Configuration CSRs */
 #define CSR_SENVCFG         0x10A
 
+/* Supervisor state CSRs */
+#define CSR_SSTATEEN0       0x10C
+#define CSR_SSTATEEN1       0x10D
+#define CSR_SSTATEEN2       0x10E
+#define CSR_SSTATEEN3       0x10F
+
 /* Supervisor Trap Handling */
 #define CSR_SSCRATCH        0x140
 #define CSR_SEPC            0x141
@@ -XXX,XX +XXX,XX @@
 #define CSR_HENVCFG         0x60A
 #define CSR_HENVCFGH        0x61A
 
+/* Hypervisor state CSRs */
+#define CSR_HSTATEEN0       0x60C
+#define CSR_HSTATEEN0H      0x61C
+#define CSR_HSTATEEN1       0x60D
+#define CSR_HSTATEEN1H      0x61D
+#define CSR_HSTATEEN2       0x60E
+#define CSR_HSTATEEN2H      0x61E
+#define CSR_HSTATEEN3       0x60F
+#define CSR_HSTATEEN3H      0x61F
+
 /* Virtual CSRs */
 #define CSR_VSSTATUS        0x200
 #define CSR_VSIE            0x204
@@ -XXX,XX +XXX,XX @@
 #define CSR_MENVCFG         0x30A
 #define CSR_MENVCFGH        0x31A
 
+/* Machine state CSRs */
+#define CSR_MSTATEEN0       0x30C
+#define CSR_MSTATEEN0H      0x31C
+#define CSR_MSTATEEN1       0x30D
+#define CSR_MSTATEEN1H      0x31D
+#define CSR_MSTATEEN2       0x30E
+#define CSR_MSTATEEN2H      0x31E
+#define CSR_MSTATEEN3       0x30F
+#define CSR_MSTATEEN3H      0x31F
+
+/* Common defines for all smstateen */
+#define SMSTATEEN_MAX_COUNT 4
+#define SMSTATEEN0_CS       (1ULL << 0)
+#define SMSTATEEN0_FCSR     (1ULL << 1)
+#define SMSTATEEN0_HSCONTXT (1ULL << 57)
+#define SMSTATEEN0_IMSIC    (1ULL << 58)
+#define SMSTATEEN0_AIA      (1ULL << 59)
+#define SMSTATEEN0_SVSLCT   (1ULL << 60)
+#define SMSTATEEN0_HSENVCFG (1ULL << 62)
+#define SMSTATEEN_STATEEN   (1ULL << 63)
+
 /* Enhanced Physical Memory Protection (ePMP) */
 #define CSR_MSECCFG         0x747
 #define CSR_MSECCFGH        0x757
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException umode32(CPURISCVState *env, int csrno)
     return umode(env, csrno);
 }
 
+static RISCVException mstateen(CPURISCVState *env, int csrno)
+{
+    CPUState *cs = env_cpu(env);
+    RISCVCPU *cpu = RISCV_CPU(cs);
+
+    if (!cpu->cfg.ext_smstateen) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
+
+    return any(env, csrno);
+}
+
+static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
+{
+    CPUState *cs = env_cpu(env);
+    RISCVCPU *cpu = RISCV_CPU(cs);
+
+    if (!cpu->cfg.ext_smstateen) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
+
+    if (env->priv < PRV_M) {
+        if (!(env->mstateen[csrno - base] & SMSTATEEN_STATEEN)) {
+            return RISCV_EXCP_ILLEGAL_INST;
+        }
+    }
+
+    return hmode(env, csrno);
+}
+
+static RISCVException hstateen(CPURISCVState *env, int csrno)
+{
+    return hstateen_pred(env, csrno, CSR_HSTATEEN0);
+}
+
+static RISCVException hstateenh(CPURISCVState *env, int csrno)
+{
+    return hstateen_pred(env, csrno, CSR_HSTATEEN0H);
+}
+
+static RISCVException sstateen(CPURISCVState *env, int csrno)
+{
+    bool virt = riscv_cpu_virt_enabled(env);
+    int index = csrno - CSR_SSTATEEN0;
+    CPUState *cs = env_cpu(env);
+    RISCVCPU *cpu = RISCV_CPU(cs);
+
+    if (!cpu->cfg.ext_smstateen) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
+
+    if (env->priv < PRV_M) {
+        if (!(env->mstateen[index] & SMSTATEEN_STATEEN)) {
+            return RISCV_EXCP_ILLEGAL_INST;
+        }
+
+        if (virt) {
+            if (!(env->hstateen[index] & SMSTATEEN_STATEEN)) {
+                return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+            }
+        }
+    }
+
+    return smode(env, csrno);
+}
+
 /* Checks if PointerMasking registers could be accessed */
 static RISCVException pointer_masking(CPURISCVState *env, int csrno)
 {
@@ -XXX,XX +XXX,XX @@ static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+static RISCVException read_mstateen(CPURISCVState *env, int csrno,
+                                    target_ulong *val)
+{
+    *val = env->mstateen[csrno - CSR_MSTATEEN0];
+
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mstateen(CPURISCVState *env, int csrno,
+                                     uint64_t wr_mask, target_ulong new_val)
+{
+    uint64_t *reg;
+
+    reg = &env->mstateen[csrno - CSR_MSTATEEN0];
+    *reg = (*reg & ~wr_mask) | (new_val & wr_mask);
+
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
+                                      target_ulong new_val)
+{
+    uint64_t wr_mask = SMSTATEEN_STATEEN;
+
+    return write_mstateen(env, csrno, wr_mask, new_val);
+}
+
+static RISCVException write_mstateen_1_3(CPURISCVState *env, int csrno,
+                                      target_ulong new_val)
+{
+    return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
+}
+
+static RISCVException read_mstateenh(CPURISCVState *env, int csrno,
+                                      target_ulong *val)
+{
+    *val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32;
+
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mstateenh(CPURISCVState *env, int csrno,
+                                      uint64_t wr_mask, target_ulong new_val)
+{
+    uint64_t *reg, val;
+
+    reg = &env->mstateen[csrno - CSR_MSTATEEN0H];
+    val = (uint64_t)new_val << 32;
+    val |= *reg & 0xFFFFFFFF;
+    *reg = (*reg & ~wr_mask) | (val & wr_mask);
+
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
+                                      target_ulong new_val)
+{
+    uint64_t wr_mask = SMSTATEEN_STATEEN;
+
+    return write_mstateenh(env, csrno, wr_mask, new_val);
+}
+
+static RISCVException write_mstateenh_1_3(CPURISCVState *env, int csrno,
+                                      target_ulong new_val)
+{
+    return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
+}
+
+static RISCVException read_hstateen(CPURISCVState *env, int csrno,
+                                    target_ulong *val)
+{
+    int index = csrno - CSR_HSTATEEN0;
+
+    *val = env->hstateen[index] & env->mstateen[index];
+
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_hstateen(CPURISCVState *env, int csrno,
+                                     uint64_t mask, target_ulong new_val)
+{
+    int index = csrno - CSR_HSTATEEN0;
+    uint64_t *reg, wr_mask;
+
+    reg = &env->hstateen[index];
+    wr_mask = env->mstateen[index] & mask;
+    *reg = (*reg & ~wr_mask) | (new_val & wr_mask);
+
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
+                                      target_ulong new_val)
+{
+    uint64_t wr_mask = SMSTATEEN_STATEEN;
+
+    return write_hstateen(env, csrno, wr_mask, new_val);
+}
+
+static RISCVException write_hstateen_1_3(CPURISCVState *env, int csrno,
+                                      target_ulong new_val)
+{
+    return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
+}
+
+static RISCVException read_hstateenh(CPURISCVState *env, int csrno,
+                                     target_ulong *val)
+{
+    int index = csrno - CSR_HSTATEEN0H;
+
+    *val = (env->hstateen[index] >> 32) & (env->mstateen[index] >> 32);
+
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_hstateenh(CPURISCVState *env, int csrno,
+                                      uint64_t mask, target_ulong new_val)
+{
+    int index = csrno - CSR_HSTATEEN0H;
+    uint64_t *reg, wr_mask, val;
+
+    reg = &env->hstateen[index];
+    val = (uint64_t)new_val << 32;
+    val |= *reg & 0xFFFFFFFF;
+    wr_mask = env->mstateen[index] & mask;
+    *reg = (*reg & ~wr_mask) | (val & wr_mask);
+
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_hstateen0h(CPURISCVState *env, int csrno,
+                                       target_ulong new_val)
+{
+    uint64_t wr_mask = SMSTATEEN_STATEEN;
+
+    return write_hstateenh(env, csrno, wr_mask, new_val);
+}
+
+static RISCVException write_hstateenh_1_3(CPURISCVState *env, int csrno,
+                                       target_ulong new_val)
+{
+    return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
+}
+
+static RISCVException read_sstateen(CPURISCVState *env, int csrno,
+                                    target_ulong *val)
+{
+    bool virt = riscv_cpu_virt_enabled(env);
+    int index = csrno - CSR_SSTATEEN0;
+
+    *val = env->sstateen[index] & env->mstateen[index];
+    if (virt) {
+        *val &= env->hstateen[index];
+    }
+
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_sstateen(CPURISCVState *env, int csrno,
+                                     uint64_t mask, target_ulong new_val)
+{
+    bool virt = riscv_cpu_virt_enabled(env);
+    int index = csrno - CSR_SSTATEEN0;
+    uint64_t wr_mask;
+    uint64_t *reg;
+
+    wr_mask = env->mstateen[index] & mask;
+    if (virt) {
+        wr_mask &= env->hstateen[index];
+    }
+
+    reg = &env->sstateen[index];
+    *reg = (*reg & ~wr_mask) | (new_val & wr_mask);
+
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_sstateen0(CPURISCVState *env, int csrno,
+                                      target_ulong new_val)
+{
+    uint64_t wr_mask = SMSTATEEN_STATEEN;
+
+    return write_sstateen(env, csrno, wr_mask, new_val);
+}
+
+static RISCVException write_sstateen_1_3(CPURISCVState *env, int csrno,
+                                      target_ulong new_val)
+{
+    return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
+}
+
 static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
                                 uint64_t *ret_val,
                                 uint64_t new_val, uint64_t wr_mask)
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh,
                        .min_priv_ver = PRIV_VERSION_1_12_0              },
 
+    /* Smstateen extension CSRs */
+    [CSR_MSTATEEN0] = { "mstateen0", mstateen, read_mstateen, write_mstateen0,
+                        .min_priv_ver = PRIV_VERSION_1_12_0 },
+    [CSR_MSTATEEN0H] = { "mstateen0h", mstateen, read_mstateenh,
+                          write_mstateen0h,
+                         .min_priv_ver = PRIV_VERSION_1_12_0 },
+    [CSR_MSTATEEN1] = { "mstateen1", mstateen, read_mstateen,
+                        write_mstateen_1_3,
+                        .min_priv_ver = PRIV_VERSION_1_12_0 },
+    [CSR_MSTATEEN1H] = { "mstateen1h", mstateen, read_mstateenh,
+                         write_mstateenh_1_3,
+                         .min_priv_ver = PRIV_VERSION_1_12_0 },
+    [CSR_MSTATEEN2] = { "mstateen2", mstateen, read_mstateen,
+                        write_mstateen_1_3,
+                        .min_priv_ver = PRIV_VERSION_1_12_0 },
+    [CSR_MSTATEEN2H] = { "mstateen2h", mstateen, read_mstateenh,
+                         write_mstateenh_1_3,
+                         .min_priv_ver = PRIV_VERSION_1_12_0 },
+    [CSR_MSTATEEN3] = { "mstateen3", mstateen, read_mstateen,
+                        write_mstateen_1_3,
+                        .min_priv_ver = PRIV_VERSION_1_12_0 },
+    [CSR_MSTATEEN3H] = { "mstateen3h", mstateen, read_mstateenh,
+                         write_mstateenh_1_3,
+                         .min_priv_ver = PRIV_VERSION_1_12_0 },
+    [CSR_HSTATEEN0] = { "hstateen0", hstateen, read_hstateen, write_hstateen0,
+                        .min_priv_ver = PRIV_VERSION_1_12_0 },
+    [CSR_HSTATEEN0H] = { "hstateen0h", hstateenh, read_hstateenh,
+                         write_hstateen0h,
+                         .min_priv_ver = PRIV_VERSION_1_12_0 },
+    [CSR_HSTATEEN1] = { "hstateen1", hstateen, read_hstateen,
+                        write_hstateen_1_3,
+                        .min_priv_ver = PRIV_VERSION_1_12_0 },
+    [CSR_HSTATEEN1H] = { "hstateen1h", hstateenh, read_hstateenh,
+                         write_hstateenh_1_3,
+                         .min_priv_ver = PRIV_VERSION_1_12_0 },
+    [CSR_HSTATEEN2] = { "hstateen2", hstateen, read_hstateen,
+                        write_hstateen_1_3,
+                        .min_priv_ver = PRIV_VERSION_1_12_0 },
+    [CSR_HSTATEEN2H] = { "hstateen2h", hstateenh, read_hstateenh,
+                         write_hstateenh_1_3,
+                         .min_priv_ver = PRIV_VERSION_1_12_0 },
+    [CSR_HSTATEEN3] = { "hstateen3", hstateen, read_hstateen,
+                        write_hstateen_1_3,
+                        .min_priv_ver = PRIV_VERSION_1_12_0 },
+    [CSR_HSTATEEN3H] = { "hstateen3h", hstateenh, read_hstateenh,
+                         write_hstateenh_1_3,
+                         .min_priv_ver = PRIV_VERSION_1_12_0 },
+    [CSR_SSTATEEN0] = { "sstateen0", sstateen, read_sstateen, write_sstateen0,
+                        .min_priv_ver = PRIV_VERSION_1_12_0 },
+    [CSR_SSTATEEN1] = { "sstateen1", sstateen, read_sstateen,
+                        write_sstateen_1_3,
+                        .min_priv_ver = PRIV_VERSION_1_12_0 },
+    [CSR_SSTATEEN2] = { "sstateen2", sstateen, read_sstateen,
+                        write_sstateen_1_3,
+                        .min_priv_ver = PRIV_VERSION_1_12_0 },
+    [CSR_SSTATEEN3] = { "sstateen3", sstateen, read_sstateen,
+                        write_sstateen_1_3,
+                        .min_priv_ver = PRIV_VERSION_1_12_0 },
+
     /* Supervisor Trap Setup */
     [CSR_SSTATUS]    = { "sstatus",    smode, read_sstatus,    write_sstatus,
                          NULL,                read_sstatus_i128               },
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static int riscv_cpu_post_load(void *opaque, int version_id)
     return 0;
 }
 
+static bool smstateen_needed(void *opaque)
+{
+    RISCVCPU *cpu = opaque;
+
+    return cpu->cfg.ext_smstateen;
+}
+
+static const VMStateDescription vmstate_smstateen = {
+    .name = "cpu/smtateen",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = smstateen_needed,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4),
+        VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4),
+        VMSTATE_UINT64_ARRAY(env.sstateen, RISCVCPU, 4),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static bool envcfg_needed(void *opaque)
 {
     RISCVCPU *cpu = opaque;
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
         &vmstate_kvmtimer,
         &vmstate_envcfg,
         &vmstate_debug,
+        &vmstate_smstateen,
         NULL
     }
 };
-- 
2.38.1

From: Mayuresh Chitale <mchitale@ventanamicro.com>

Accesses to henvcfg, henvcfgh and senvcfg are allowed only if the corresponding
bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is
generated.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221016124726.102129-3-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 87 ++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 80 insertions(+), 7 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
 }
 
 /* Predicates */
+#if !defined(CONFIG_USER_ONLY)
+static RISCVException smstateen_acc_ok(CPURISCVState *env, int index,
+                                       uint64_t bit)
+{
+    bool virt = riscv_cpu_virt_enabled(env);
+    CPUState *cs = env_cpu(env);
+    RISCVCPU *cpu = RISCV_CPU(cs);
+
+    if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) {
+        return RISCV_EXCP_NONE;
+    }
+
+    if (!(env->mstateen[index] & bit)) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
+
+    if (virt) {
+        if (!(env->hstateen[index] & bit)) {
+            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+        }
+
+        if (env->priv == PRV_U && !(env->sstateen[index] & bit)) {
+            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+        }
+    }
+
+    if (env->priv == PRV_U && riscv_has_ext(env, RVS)) {
+        if (!(env->sstateen[index] & bit)) {
+            return RISCV_EXCP_ILLEGAL_INST;
+        }
+    }
+
+    return RISCV_EXCP_NONE;
+}
+#endif
+
 static RISCVException fs(CPURISCVState *env, int csrno)
 {
 #if !defined(CONFIG_USER_ONLY)
@@ -XXX,XX +XXX,XX @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
 static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
                                  target_ulong *val)
 {
+    RISCVException ret;
+
+    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
     *val = env->senvcfg;
     return RISCV_EXCP_NONE;
 }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
                                   target_ulong val)
 {
     uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE;
+    RISCVException ret;
 
-    env->senvcfg = (env->senvcfg & ~mask) | (val & mask);
+    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
 
+    env->senvcfg = (env->senvcfg & ~mask) | (val & mask);
     return RISCV_EXCP_NONE;
 }
 
 static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
                                  target_ulong *val)
 {
+    RISCVException ret;
+
+    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
     *val = env->henvcfg;
     return RISCV_EXCP_NONE;
 }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
                                   target_ulong val)
 {
     uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE;
+    RISCVException ret;
+
+    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
 
     if (riscv_cpu_mxl(env) == MXL_RV64) {
         mask |= HENVCFG_PBMTE | HENVCFG_STCE;
@@ -XXX,XX +XXX,XX @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
 static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
                                  target_ulong *val)
 {
+    RISCVException ret;
+
+    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
     *val = env->henvcfg >> 32;
     return RISCV_EXCP_NONE;
 }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
 {
     uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
     uint64_t valh = (uint64_t)val << 32;
+    RISCVException ret;
 
-    env->henvcfg = (env->henvcfg & ~mask) | (valh & mask);
+    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
 
+    env->henvcfg = (env->henvcfg & ~mask) | (valh & mask);
     return RISCV_EXCP_NONE;
 }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstateen(CPURISCVState *env, int csrno,
 static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
                                       target_ulong new_val)
 {
-    uint64_t wr_mask = SMSTATEEN_STATEEN;
+    uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
 
     return write_mstateen(env, csrno, wr_mask, new_val);
 }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstateenh(CPURISCVState *env, int csrno,
 static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
                                       target_ulong new_val)
 {
-    uint64_t wr_mask = SMSTATEEN_STATEEN;
+    uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
 
     return write_mstateenh(env, csrno, wr_mask, new_val);
 }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_hstateen(CPURISCVState *env, int csrno,
 static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
                                       target_ulong new_val)
 {
-    uint64_t wr_mask = SMSTATEEN_STATEEN;
+    uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
 
     return write_hstateen(env, csrno, wr_mask, new_val);
 }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_hstateenh(CPURISCVState *env, int csrno,
 static RISCVException write_hstateen0h(CPURISCVState *env, int csrno,
                                        target_ulong new_val)
 {
-    uint64_t wr_mask = SMSTATEEN_STATEEN;
+    uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
 
     return write_hstateenh(env, csrno, wr_mask, new_val);
 }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_sstateen(CPURISCVState *env, int csrno,
 static RISCVException write_sstateen0(CPURISCVState *env, int csrno,
                                       target_ulong new_val)
 {
-    uint64_t wr_mask = SMSTATEEN_STATEEN;
+    uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
 
     return write_sstateen(env, csrno, wr_mask, new_val);
 }
-- 
2.38.1

From: Mayuresh Chitale <mchitale@ventanamicro.com>

This patch adds a mechanism to generate a virtual instruction
instruction exception instead of an illegal instruction exception
during instruction decode when virt is enabled.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221016124726.102129-4-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
        to reset this known value.  */
     int frm;
     RISCVMXL ol;
+    bool virt_inst_excp;
     bool virt_enabled;
     const RISCVCPUConfig *cfg_ptr;
     bool hlsx;
@@ -XXX,XX +XXX,XX @@ static void gen_exception_illegal(DisasContext *ctx)
 {
     tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
                    offsetof(CPURISCVState, bins));
-    generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
+    if (ctx->virt_inst_excp) {
+        generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
+    } else {
+        generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
+    }
 }
 
 static void gen_exception_inst_addr_mis(DisasContext *ctx)
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
         { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
     };
 
+    ctx->virt_inst_excp = false;
     /* Check for compressed insn */
     if (insn_len(opcode) == 2) {
         if (!has_ext(ctx, RVC)) {
-- 
2.38.1

From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

When icount is not enabled, there is no API in QEMU that can get the
guest instruction number.

Translate the guest code in a way that each TB only has one instruction.
After executing the instruction, decrease the count by 1 until it reaches 0
where the itrigger fires.

Note that only when priviledge matches the itrigger configuration,
the count will decrease.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221013062946.7530-2-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h                            |  2 +
 target/riscv/debug.h                          | 12 ++++
 target/riscv/helper.h                         |  2 +
 target/riscv/cpu_helper.c                     |  6 ++
 target/riscv/debug.c                          | 71 +++++++++++++++++++
 target/riscv/translate.c                      | 33 ++++++++-
 .../riscv/insn_trans/trans_privileged.c.inc   |  4 +-
 target/riscv/insn_trans/trans_rvi.c.inc       |  8 +--
 target/riscv/insn_trans/trans_rvv.c.inc       |  4 +-
 9 files changed, 131 insertions(+), 11 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
 FIELD(TB_FLAGS, VTA, 24, 1)
 FIELD(TB_FLAGS, VMA, 25, 1)
+/* Native debug itrigger */
+FIELD(TB_FLAGS, ITRIGGER, 26, 1)
 
 #ifdef TARGET_RISCV32
 #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/debug.h
+++ b/target/riscv/debug.h
@@ -XXX,XX +XXX,XX @@ enum {
     SIZE_NUM = 16
 };
 
+/* itrigger filed masks */
+#define ITRIGGER_ACTION       0x3f
+#define ITRIGGER_U            BIT(6)
+#define ITRIGGER_S            BIT(7)
+#define ITRIGGER_PENDING      BIT(8)
+#define ITRIGGER_M            BIT(9)
+#define ITRIGGER_COUNT        (0x3fff << 10)
+#define ITRIGGER_HIT          BIT(24)
+#define ITRIGGER_VU           BIT(25)
+#define ITRIGGER_VS           BIT(26)
+
 bool tdata_available(CPURISCVState *env, int tdata_index);
 
 target_ulong tselect_csr_read(CPURISCVState *env);
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
 
 void riscv_trigger_init(CPURISCVState *env);
 
+bool riscv_itrigger_enabled(CPURISCVState *env);
 #endif /* RISCV_DEBUG_H */
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(sret, tl, env)
 DEF_HELPER_1(mret, tl, env)
 DEF_HELPER_1(wfi, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
+/* Native Debug */
+DEF_HELPER_1(itrigger_match, void, env)
 #endif
 
 /* Hypervisor functions */
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "tcg/tcg-op.h"
 #include "trace.h"
 #include "semihosting/common-semi.h"
+#include "sysemu/cpu-timers.h"
 #include "cpu_bits.h"
+#include "debug.h"
 
 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
 {
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
         flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
                            get_field(env->mstatus_hs, MSTATUS_VS));
     }
+    if (riscv_feature(env, RISCV_FEATURE_DEBUG) && !icount_enabled()) {
+        flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER,
+                           riscv_itrigger_enabled(env));
+    }
 #endif
 
     flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 #include "trace.h"
 #include "exec/exec-all.h"
+#include "exec/helper-proto.h"
 
 /*
  * The following M-mode trigger CSRs are implemented:
@@ -XXX,XX +XXX,XX @@ static void type6_reg_write(CPURISCVState *env, target_ulong index,
     return;
 }
 
+/* icount trigger type */
+static inline int
+itrigger_get_count(CPURISCVState *env, int index)
+{
+    return get_field(env->tdata1[index], ITRIGGER_COUNT);
+}
+
+static inline void
+itrigger_set_count(CPURISCVState *env, int index, int value)
+{
+    env->tdata1[index] = set_field(env->tdata1[index],
+                                   ITRIGGER_COUNT, value);
+}
+
+static bool check_itrigger_priv(CPURISCVState *env, int index)
+{
+    target_ulong tdata1 = env->tdata1[index];
+    if (riscv_cpu_virt_enabled(env)) {
+        /* check VU/VS bit against current privilege level */
+        return (get_field(tdata1, ITRIGGER_VS) == env->priv) ||
+               (get_field(tdata1, ITRIGGER_VU) == env->priv);
+    } else {
+        /* check U/S/M bit against current privilege level */
+        return (get_field(tdata1, ITRIGGER_M) == env->priv) ||
+               (get_field(tdata1, ITRIGGER_S) == env->priv) ||
+               (get_field(tdata1, ITRIGGER_U) == env->priv);
+    }
+}
+
+bool riscv_itrigger_enabled(CPURISCVState *env)
+{
+    int count;
+    for (int i = 0; i < RV_MAX_TRIGGERS; i++) {
+        if (get_trigger_type(env, i) != TRIGGER_TYPE_INST_CNT) {
+            continue;
+        }
+        if (check_itrigger_priv(env, i)) {
+            continue;
+        }
+        count = itrigger_get_count(env, i);
+        if (!count) {
+            continue;
+        }
+        return true;
+    }
+
+    return false;
+}
+
+void helper_itrigger_match(CPURISCVState *env)
+{
+    int count;
+    for (int i = 0; i < RV_MAX_TRIGGERS; i++) {
+        if (get_trigger_type(env, i) != TRIGGER_TYPE_INST_CNT) {
+            continue;
+        }
+        if (check_itrigger_priv(env, i)) {
+            continue;
+        }
+        count = itrigger_get_count(env, i);
+        if (!count) {
+            continue;
+        }
+        itrigger_set_count(env, i, count--);
+        if (!count) {
+            do_trigger_action(env, i);
+        }
+    }
+}
+
 target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
 {
     switch (tdata_index) {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     /* PointerMasking extension */
     bool pm_mask_enabled;
     bool pm_base_enabled;
+    /* Use icount trigger for native debug */
+    bool itrigger;
     /* TCG of the current insn_start */
     TCGOp *insn_start;
 } DisasContext;
@@ -XXX,XX +XXX,XX @@ static void gen_exception_inst_addr_mis(DisasContext *ctx)
     generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS);
 }
 
+static void lookup_and_goto_ptr(DisasContext *ctx)
+{
+#ifndef CONFIG_USER_ONLY
+    if (ctx->itrigger) {
+        gen_helper_itrigger_match(cpu_env);
+    }
+#endif
+    tcg_gen_lookup_and_goto_ptr();
+}
+
+static void exit_tb(DisasContext *ctx)
+{
+#ifndef CONFIG_USER_ONLY
+    if (ctx->itrigger) {
+        gen_helper_itrigger_match(cpu_env);
+    }
+#endif
+    tcg_gen_exit_tb(NULL, 0);
+}
+
 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
 {
-    if (translator_use_goto_tb(&ctx->base, dest)) {
+     /*
+      * Under itrigger, instruction executes one by one like singlestep,
+      * direct block chain benefits will be small.
+      */
+    if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) {
         tcg_gen_goto_tb(n);
         gen_set_pc_imm(ctx, dest);
         tcg_gen_exit_tb(ctx->base.tb, n);
     } else {
         gen_set_pc_imm(ctx, dest);
-        tcg_gen_lookup_and_goto_ptr();
+        lookup_and_goto_ptr(ctx);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     memset(ctx->ftemp, 0, sizeof(ctx->ftemp));
     ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
     ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
+    ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
     ctx->zero = tcg_constant_tl(0);
 }
 
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 
     /* Only the first insn within a TB is allowed to cross a page boundary. */
     if (ctx->base.is_jmp == DISAS_NEXT) {
-        if (!is_same_page(&ctx->base, ctx->base.pc_next)) {
+        if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) {
             ctx->base.is_jmp = DISAS_TOO_MANY;
         } else {
             unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK;
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
     if (has_ext(ctx, RVS)) {
         decode_save_opc(ctx);
         gen_helper_sret(cpu_pc, cpu_env);
-        tcg_gen_exit_tb(NULL, 0); /* no chaining */
+        exit_tb(ctx); /* no chaining */
         ctx->base.is_jmp = DISAS_NORETURN;
     } else {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
 #ifndef CONFIG_USER_ONLY
     decode_save_opc(ctx);
     gen_helper_mret(cpu_pc, cpu_env);
-    tcg_gen_exit_tb(NULL, 0); /* no chaining */
+    exit_tb(ctx); /* no chaining */
     ctx->base.is_jmp = DISAS_NORETURN;
     return true;
 #else
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
     }
 
     gen_set_gpri(ctx, a->rd, ctx->pc_succ_insn);
-    tcg_gen_lookup_and_goto_ptr();
+    lookup_and_goto_ptr(ctx);
 
     if (misaligned) {
         gen_set_label(misaligned);
@@ -XXX,XX +XXX,XX @@ static bool trans_pause(DisasContext *ctx, arg_pause *a)
      * end the TB and return to main loop
      */
     gen_set_pc_imm(ctx, ctx->pc_succ_insn);
-    tcg_gen_exit_tb(NULL, 0);
+    exit_tb(ctx);
     ctx->base.is_jmp = DISAS_NORETURN;
 
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
      * however we need to end the translation block
      */
     gen_set_pc_imm(ctx, ctx->pc_succ_insn);
-    tcg_gen_exit_tb(NULL, 0);
+    exit_tb(ctx);
     ctx->base.is_jmp = DISAS_NORETURN;
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool do_csr_post(DisasContext *ctx)
     decode_save_opc(ctx);
     /* We may have changed important cpu state -- exit to main loop. */
     gen_set_pc_imm(ctx, ctx->pc_succ_insn);
-    tcg_gen_exit_tb(NULL, 0);
+    exit_tb(ctx);
     ctx->base.is_jmp = DISAS_NORETURN;
     return true;
 }
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
     mark_vs_dirty(s);
 
     gen_set_pc_imm(s, s->pc_succ_insn);
-    tcg_gen_lookup_and_goto_ptr();
+    lookup_and_goto_ptr(s);
     s->base.is_jmp = DISAS_NORETURN;
 
     if (rd == 0 && rs1 == 0) {
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
     gen_set_gpr(s, rd, dst);
     mark_vs_dirty(s);
     gen_set_pc_imm(s, s->pc_succ_insn);
-    tcg_gen_lookup_and_goto_ptr();
+    lookup_and_goto_ptr(s);
     s->base.is_jmp = DISAS_NORETURN;
 
     return true;
-- 
2.38.1

From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

The max count in itrigger can be 0x3FFF, which will cause a no trivial
translation and execution overload.

When icount is enabled, QEMU provides API that can fetch guest
instruction number. Thus, we can set an timer for itrigger with
the count as deadline.

Only when timer expires or priviledge mode changes, do lazy update
to count.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221013062946.7530-3-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  2 ++
 target/riscv/debug.h      |  1 +
 target/riscv/cpu_helper.c |  3 ++
 target/riscv/debug.c      | 59 +++++++++++++++++++++++++++++++++++++++
 4 files changed, 65 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
     target_ulong tdata3[RV_MAX_TRIGGERS];
     struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS];
     struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS];
+    QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS];
+    int64_t last_icount;
 
     /* machine specific rdtime callback */
     uint64_t (*rdtime_fn)(void *);
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/debug.h
+++ b/target/riscv/debug.h
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
 void riscv_trigger_init(CPURISCVState *env);
 
 bool riscv_itrigger_enabled(CPURISCVState *env);
+void riscv_itrigger_update_priv(CPURISCVState *env);
 #endif /* RISCV_DEBUG_H */
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
     if (newpriv == PRV_H) {
         newpriv = PRV_U;
     }
+    if (icount_enabled() && newpriv != env->priv) {
+        riscv_itrigger_update_priv(env);
+    }
     /* tlb_flush is unnecessary as mode is contained in mmu_idx */
     env->priv = newpriv;
     env->xl = cpu_recompute_xl(env);
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -XXX,XX +XXX,XX @@
 #include "trace.h"
 #include "exec/exec-all.h"
 #include "exec/helper-proto.h"
+#include "sysemu/cpu-timers.h"
 
 /*
  * The following M-mode trigger CSRs are implemented:
@@ -XXX,XX +XXX,XX @@ void helper_itrigger_match(CPURISCVState *env)
     }
 }
 
+static void riscv_itrigger_update_count(CPURISCVState *env)
+{
+    int count, executed;
+    /*
+     * Record last icount, so that we can evaluate the executed instructions
+     * since last priviledge mode change or timer expire.
+     */
+    int64_t last_icount = env->last_icount, current_icount;
+    current_icount = env->last_icount = icount_get_raw();
+
+    for (int i = 0; i < RV_MAX_TRIGGERS; i++) {
+        if (get_trigger_type(env, i) != TRIGGER_TYPE_INST_CNT) {
+            continue;
+        }
+        count = itrigger_get_count(env, i);
+        if (!count) {
+            continue;
+        }
+        /*
+         * Only when priviledge is changed or itrigger timer expires,
+         * the count field in itrigger tdata1 register is updated.
+         * And the count field in itrigger only contains remaining value.
+         */
+        if (check_itrigger_priv(env, i)) {
+            /*
+             * If itrigger enabled in this priviledge mode, the number of
+             * executed instructions since last priviledge change
+             * should be reduced from current itrigger count.
+             */
+            executed = current_icount - last_icount;
+            itrigger_set_count(env, i, count - executed);
+            if (count == executed) {
+                do_trigger_action(env, i);
+            }
+        } else {
+            /*
+             * If itrigger is not enabled in this priviledge mode,
+             * the number of executed instructions will be discard and
+             * the count field in itrigger will not change.
+             */
+            timer_mod(env->itrigger_timer[i],
+                      current_icount + count);
+        }
+    }
+}
+
+static void riscv_itrigger_timer_cb(void *opaque)
+{
+    riscv_itrigger_update_count((CPURISCVState *)opaque);
+}
+
+void riscv_itrigger_update_priv(CPURISCVState *env)
+{
+    riscv_itrigger_update_count(env);
+}
+
 target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
 {
     switch (tdata_index) {
@@ -XXX,XX +XXX,XX @@ void riscv_trigger_init(CPURISCVState *env)
         env->tdata3[i] = 0;
         env->cpu_breakpoint[i] = NULL;
         env->cpu_watchpoint[i] = NULL;
+        env->itrigger_timer[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL,
+                                              riscv_itrigger_timer_cb, env);
     }
 }
-- 
2.38.1

From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

When QEMU is not in icount mode, execute instruction one by one. The
tdata1 can be read directly.

When QEMU is in icount mode, use a timer to simulate the itrigger. The
tdata1 may be not right because of lazy update of count in tdata1. Thus,
We should pack the adjusted count into tdata1 before read it back.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221013062946.7530-4-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/debug.c | 72 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -XXX,XX +XXX,XX @@ void riscv_itrigger_update_priv(CPURISCVState *env)
     riscv_itrigger_update_count(env);
 }
 
+static target_ulong itrigger_validate(CPURISCVState *env,
+                                      target_ulong ctrl)
+{
+    target_ulong val;
+
+    /* validate the generic part first */
+    val = tdata1_validate(env, ctrl, TRIGGER_TYPE_INST_CNT);
+
+    /* validate unimplemented (always zero) bits */
+    warn_always_zero_bit(ctrl, ITRIGGER_ACTION, "action");
+    warn_always_zero_bit(ctrl, ITRIGGER_HIT, "hit");
+    warn_always_zero_bit(ctrl, ITRIGGER_PENDING, "pending");
+
+    /* keep the mode and attribute bits */
+    val |= ctrl & (ITRIGGER_VU | ITRIGGER_VS | ITRIGGER_U | ITRIGGER_S |
+                   ITRIGGER_M | ITRIGGER_COUNT);
+
+    return val;
+}
+
+static void itrigger_reg_write(CPURISCVState *env, target_ulong index,
+                               int tdata_index, target_ulong val)
+{
+    target_ulong new_val;
+
+    switch (tdata_index) {
+    case TDATA1:
+        /* set timer for icount */
+        new_val = itrigger_validate(env, val);
+        if (new_val != env->tdata1[index]) {
+            env->tdata1[index] = new_val;
+            if (icount_enabled()) {
+                env->last_icount = icount_get_raw();
+                /* set the count to timer */
+                timer_mod(env->itrigger_timer[index],
+                          env->last_icount + itrigger_get_count(env, index));
+            }
+        }
+        break;
+    case TDATA2:
+        qemu_log_mask(LOG_UNIMP,
+                      "tdata2 is not supported for icount trigger\n");
+        break;
+    case TDATA3:
+        qemu_log_mask(LOG_UNIMP,
+                      "tdata3 is not supported for icount trigger\n");
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
+    return;
+}
+
+static int itrigger_get_adjust_count(CPURISCVState *env)
+{
+    int count = itrigger_get_count(env, env->trigger_cur), executed;
+    if ((count != 0) && check_itrigger_priv(env, env->trigger_cur)) {
+        executed = icount_get_raw() - env->last_icount;
+        count += executed;
+    }
+    return count;
+}
+
 target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
 {
+    int trigger_type;
     switch (tdata_index) {
     case TDATA1:
+        trigger_type = extract_trigger_type(env, env->tdata1[env->trigger_cur]);
+        if ((trigger_type == TRIGGER_TYPE_INST_CNT) && icount_enabled()) {
+            return deposit64(env->tdata1[env->trigger_cur], 10, 14,
+                             itrigger_get_adjust_count(env));
+        }
         return env->tdata1[env->trigger_cur];
     case TDATA2:
         return env->tdata2[env->trigger_cur];
@@ -XXX,XX +XXX,XX @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
         type6_reg_write(env, env->trigger_cur, tdata_index, val);
         break;
     case TRIGGER_TYPE_INST_CNT:
+        itrigger_reg_write(env, env->trigger_cur, tdata_index, val);
+        break;
     case TRIGGER_TYPE_INT:
     case TRIGGER_TYPE_EXCP:
     case TRIGGER_TYPE_EXT_SRC:
-- 
2.38.1

From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Avoid calling riscv_itrigger_enabled() when calculate the tbflags.
As the itrigger enable status can only be changed when write
tdata1, migration load or itrigger fire, update env->itrigger_enabled
at these places.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221013062946.7530-5-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  1 +
 target/riscv/cpu_helper.c |  3 +--
 target/riscv/debug.c      |  3 +++
 target/riscv/machine.c    | 15 +++++++++++++++
 4 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
     struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS];
     QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS];
     int64_t last_icount;
+    bool itrigger_enabled;
 
     /* machine specific rdtime callback */
     uint64_t (*rdtime_fn)(void *);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
                            get_field(env->mstatus_hs, MSTATUS_VS));
     }
     if (riscv_feature(env, RISCV_FEATURE_DEBUG) && !icount_enabled()) {
-        flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER,
-                           riscv_itrigger_enabled(env));
+        flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
     }
 #endif
 
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -XXX,XX +XXX,XX @@ void helper_itrigger_match(CPURISCVState *env)
         }
         itrigger_set_count(env, i, count--);
         if (!count) {
+            env->itrigger_enabled = riscv_itrigger_enabled(env);
             do_trigger_action(env, i);
         }
     }
@@ -XXX,XX +XXX,XX @@ static void itrigger_reg_write(CPURISCVState *env, target_ulong index,
                 /* set the count to timer */
                 timer_mod(env->itrigger_timer[index],
                           env->last_icount + itrigger_get_count(env, index));
+            } else {
+                env->itrigger_enabled = riscv_itrigger_enabled(env);
             }
         }
         break;
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/error-report.h"
 #include "sysemu/kvm.h"
 #include "migration/cpu.h"
+#include "sysemu/cpu-timers.h"
+#include "debug.h"
 
 static bool pmp_needed(void *opaque)
 {
@@ -XXX,XX +XXX,XX @@ static bool debug_needed(void *opaque)
     return riscv_feature(env, RISCV_FEATURE_DEBUG);
 }
 
+static int debug_post_load(void *opaque, int version_id)
+{
+    RISCVCPU *cpu = opaque;
+    CPURISCVState *env = &cpu->env;
+
+    if (icount_enabled()) {
+        env->itrigger_enabled = riscv_itrigger_enabled(env);
+    }
+
+    return 0;
+}
+
 static const VMStateDescription vmstate_debug = {
     .name = "cpu/debug",
     .version_id = 2,
     .minimum_version_id = 2,
     .needed = debug_needed,
+    .post_load = debug_post_load,
     .fields = (VMStateField[]) {
         VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
         VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS),
-- 
2.38.1

From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>

Commit 40244040a7a changed the way the S irqs are numbered. This breaks when
using numa configuration, e.g.:
./qemu-system-riscv64 -nographic -machine virt,dumpdtb=numa-tree.dtb \
                      -m 2G -smp cpus=16 \
		      -object memory-backend-ram,id=mem0,size=512M \
		      -object memory-backend-ram,id=mem1,size=512M \
		      -object memory-backend-ram,id=mem2,size=512M \
		      -object memory-backend-ram,id=mem3,size=512M \
		      -numa node,cpus=0-3,memdev=mem0,nodeid=0 \
		      -numa node,cpus=4-7,memdev=mem1,nodeid=1 \
		      -numa node,cpus=8-11,memdev=mem2,nodeid=2 \
		      -numa node,cpus=12-15,memdev=mem3,nodeid=3
leads to:
Unexpected error in object_property_find_err() at ../qom/object.c:1304:
qemu-system-riscv64: Property 'riscv.sifive.plic.unnamed-gpio-out[8]' not
found

This patch makes the nubering of the S irqs identical to what it was before.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Message-Id: <20221114135122.1668703-1-frederic.petrot@univ-grenoble-alpes.fr>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/sifive_plic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
         CPUState *cpu = qemu_get_cpu(cpu_num);
 
         if (plic->addr_config[i].mode == PLICMode_M) {
-            qdev_connect_gpio_out(dev, num_harts - plic->hartid_base + cpu_num,
+            qdev_connect_gpio_out(dev, cpu_num - hartid_base + num_harts,
                                   qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
         }
         if (plic->addr_config[i].mode == PLICMode_S) {
-            qdev_connect_gpio_out(dev, cpu_num,
+            qdev_connect_gpio_out(dev, cpu_num - hartid_base,
                                   qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
         }
     }
-- 
2.38.1

From: Anup Patel <apatel@ventanamicro.com>

We should use "&&" instead of "&" when checking hcounteren.TM and
henvcfg.STCE bits.

Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221108125703.1463577-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException sstc(CPURISCVState *env, int csrno)
     }
 
     if (riscv_cpu_virt_enabled(env)) {
-        if (!(get_field(env->hcounteren, COUNTEREN_TM) &
+        if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
               get_field(env->henvcfg, HENVCFG_STCE))) {
             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
         }
-- 
2.38.1

From: Atish Patra <atishp@rivosinc.com>

The imsic DT binding[1] has changed and no longer require an ipi-id.
The latest IMSIC driver dynamically allocates ipi id if slow-ipi
is not defined.

Get rid of the unused dt property which may lead to confusion.

[1] https://lore.kernel.org/lkml/20221111044207.1478350-5-apatel@ventanamicro.com/

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221122080529.1692533-1-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/virt.h | 1 -
 hw/riscv/virt.c         | 4 ----
 2 files changed, 5 deletions(-)

diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -XXX,XX +XXX,XX @@ enum {
 
 #define VIRT_PLATFORM_BUS_NUM_IRQS 32
 
-#define VIRT_IRQCHIP_IPI_MSI 1
 #define VIRT_IRQCHIP_NUM_MSIS 255
 #define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV
 #define VIRT_IRQCHIP_NUM_PRIO_BITS 3
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
         riscv_socket_count(mc) * sizeof(uint32_t) * 4);
     qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
         VIRT_IRQCHIP_NUM_MSIS);
-    qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id",
-        VIRT_IRQCHIP_IPI_MSI);
     if (riscv_socket_count(mc) > 1) {
         qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
             imsic_num_bits(imsic_max_hart_per_socket));
@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
         riscv_socket_count(mc) * sizeof(uint32_t) * 4);
     qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
         VIRT_IRQCHIP_NUM_MSIS);
-    qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id",
-        VIRT_IRQCHIP_IPI_MSI);
     if (imsic_guest_bits) {
         qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits",
             imsic_guest_bits);
-- 
2.38.1

From: Jim Shu <jim.shu@sifive.com>

let tlb_fill() function also increments PMU counter when it is from
two-stage translation, so QEMU could also monitor these PMU events when
CPU runs in VS/VU mode (like running guest OS).

Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221123090635.6574-1-jim.shu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
         }
     }
 
+    pmu_tlb_fill_incr_ctr(cpu, access_type);
     if (riscv_cpu_virt_enabled(env) ||
         ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
          access_type != MMU_INST_FETCH)) {
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
             }
         }
     } else {
-        pmu_tlb_fill_incr_ctr(cpu, access_type);
         /* Single stage lookup */
         ret = get_physical_address(env, &pa, &prot, address, NULL,
                                    access_type, mmu_idx, true, false, false);
-- 
2.38.1

From: Bin Meng <bmeng@tinylab.org>

sstatus register dump is currently missing in riscv_cpu_dump_state().
As sstatus is a copy of mstatus, which is described in the priv spec,
it seems redundant to print the same information twice.

Add some comments for this to let people know this is intentional.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221125050354.3166023-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
             CSR_MHARTID,
             CSR_MSTATUS,
             CSR_MSTATUSH,
+            /*
+             * CSR_SSTATUS is intentionally omitted here as its value
+             * can be figured out by looking at CSR_MSTATUS
+             */
             CSR_HSTATUS,
             CSR_VSSTATUS,
             CSR_MIP,
-- 
2.38.1

From: Conor Dooley <conor.dooley@microchip.com>

On PolarFire SoC, some peripherals (eg the PCI root port) are clocked by
"Clock Conditioning Circuitry" in the FPGA. The specific clock depends
on the FPGA bitstream & can be locked to one particular {D,P}LL - in the
Icicle Kit Reference Design v2022.09 or later this is/will be the case.

Linux v6.1+ will have a driver for this peripheral and devicetrees that
previously relied on "fixed-frequency" clock nodes have been switched
over to clock-controller nodes. The IOSCB region is represented in QEMU,
but the specific region of it that the CCCs occupy has not so v6.1-rcN
kernels fail to boot in QEMU.

Add the regions as unimplemented so that the status-quo in terms of boot
is maintained.

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Message-Id: <20221117225518.4102575-2-conor@kernel.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/misc/mchp_pfsoc_ioscb.h | 1 +
 hw/misc/mchp_pfsoc_ioscb.c         | 6 ++++++
 2 files changed, 7 insertions(+)

From: Conor Dooley <conor.dooley@microchip.com>

The Fabric Interconnect Controllers provide interfaces between the FPGA
fabric and the core complex. There are 5 FICs on PolarFire SoC, numbered
0 through 4. FIC2 is an AXI4 slave interface from the FPGA fabric and
does not show up on the MSS memory map. FIC4 is dedicated to the User
Crypto Processor and does not show up on the MSS memory map either.

FIC 0, 1 & 3 do show up in the MSS memory map and neither FICs 0 or 1
are represented in QEMU, leading to load access violations while booting
Linux for Icicle if PCIe is enabled as the root port is connected via
either FIC 0 or 1.

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Message-Id: <20221117225518.4102575-3-conor@kernel.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h |   2 +
 hw/riscv/microchip_pfsoc.c         | 115 ++++++++++++++++-------------
 2 files changed, 65 insertions(+), 52 deletions(-)

diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@ enum {
     MICROCHIP_PFSOC_USB,
     MICROCHIP_PFSOC_QSPI_XIP,
     MICROCHIP_PFSOC_IOSCB,
+    MICROCHIP_PFSOC_FABRIC_FIC0,
+    MICROCHIP_PFSOC_FABRIC_FIC1,
     MICROCHIP_PFSOC_FABRIC_FIC3,
     MICROCHIP_PFSOC_DRAM_LO,
     MICROCHIP_PFSOC_DRAM_LO_ALIAS,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
  *     describes the complete IOSCB modules memory maps
  */
 static const MemMapEntry microchip_pfsoc_memmap[] = {
-    [MICROCHIP_PFSOC_RSVD0] =           {        0x0,      0x100 },
-    [MICROCHIP_PFSOC_DEBUG] =           {      0x100,      0xf00 },
-    [MICROCHIP_PFSOC_E51_DTIM] =        {  0x1000000,     0x2000 },
-    [MICROCHIP_PFSOC_BUSERR_UNIT0] =    {  0x1700000,     0x1000 },
-    [MICROCHIP_PFSOC_BUSERR_UNIT1] =    {  0x1701000,     0x1000 },
-    [MICROCHIP_PFSOC_BUSERR_UNIT2] =    {  0x1702000,     0x1000 },
-    [MICROCHIP_PFSOC_BUSERR_UNIT3] =    {  0x1703000,     0x1000 },
-    [MICROCHIP_PFSOC_BUSERR_UNIT4] =    {  0x1704000,     0x1000 },
-    [MICROCHIP_PFSOC_CLINT] =           {  0x2000000,    0x10000 },
-    [MICROCHIP_PFSOC_L2CC] =            {  0x2010000,     0x1000 },
-    [MICROCHIP_PFSOC_DMA] =             {  0x3000000,   0x100000 },
-    [MICROCHIP_PFSOC_L2LIM] =           {  0x8000000,  0x2000000 },
-    [MICROCHIP_PFSOC_PLIC] =            {  0xc000000,  0x4000000 },
-    [MICROCHIP_PFSOC_MMUART0] =         { 0x20000000,     0x1000 },
-    [MICROCHIP_PFSOC_WDOG0] =           { 0x20001000,     0x1000 },
-    [MICROCHIP_PFSOC_SYSREG] =          { 0x20002000,     0x2000 },
-    [MICROCHIP_PFSOC_AXISW] =           { 0x20004000,     0x1000 },
-    [MICROCHIP_PFSOC_MPUCFG] =          { 0x20005000,     0x1000 },
-    [MICROCHIP_PFSOC_FMETER] =          { 0x20006000,     0x1000 },
-    [MICROCHIP_PFSOC_DDR_SGMII_PHY] =   { 0x20007000,     0x1000 },
-    [MICROCHIP_PFSOC_EMMC_SD] =         { 0x20008000,     0x1000 },
-    [MICROCHIP_PFSOC_DDR_CFG] =         { 0x20080000,    0x40000 },
-    [MICROCHIP_PFSOC_MMUART1] =         { 0x20100000,     0x1000 },
-    [MICROCHIP_PFSOC_MMUART2] =         { 0x20102000,     0x1000 },
-    [MICROCHIP_PFSOC_MMUART3] =         { 0x20104000,     0x1000 },
-    [MICROCHIP_PFSOC_MMUART4] =         { 0x20106000,     0x1000 },
-    [MICROCHIP_PFSOC_WDOG1] =           { 0x20101000,     0x1000 },
-    [MICROCHIP_PFSOC_WDOG2] =           { 0x20103000,     0x1000 },
-    [MICROCHIP_PFSOC_WDOG3] =           { 0x20105000,     0x1000 },
-    [MICROCHIP_PFSOC_WDOG4] =           { 0x20106000,     0x1000 },
-    [MICROCHIP_PFSOC_SPI0] =            { 0x20108000,     0x1000 },
-    [MICROCHIP_PFSOC_SPI1] =            { 0x20109000,     0x1000 },
-    [MICROCHIP_PFSOC_I2C0] =            { 0x2010a000,     0x1000 },
-    [MICROCHIP_PFSOC_I2C1] =            { 0x2010b000,     0x1000 },
-    [MICROCHIP_PFSOC_CAN0] =            { 0x2010c000,     0x1000 },
-    [MICROCHIP_PFSOC_CAN1] =            { 0x2010d000,     0x1000 },
-    [MICROCHIP_PFSOC_GEM0] =            { 0x20110000,     0x2000 },
-    [MICROCHIP_PFSOC_GEM1] =            { 0x20112000,     0x2000 },
-    [MICROCHIP_PFSOC_GPIO0] =           { 0x20120000,     0x1000 },
-    [MICROCHIP_PFSOC_GPIO1] =           { 0x20121000,     0x1000 },
-    [MICROCHIP_PFSOC_GPIO2] =           { 0x20122000,     0x1000 },
-    [MICROCHIP_PFSOC_RTC] =             { 0x20124000,     0x1000 },
-    [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,     0x1000 },
-    [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
-    [MICROCHIP_PFSOC_USB] =             { 0x20201000,     0x1000 },
-    [MICROCHIP_PFSOC_QSPI_XIP] =        { 0x21000000,  0x1000000 },
-    [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000, 0x10000000 },
-    [MICROCHIP_PFSOC_FABRIC_FIC3] =     { 0x40000000, 0x20000000 },
-    [MICROCHIP_PFSOC_DRAM_LO] =         { 0x80000000, 0x40000000 },
-    [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =   { 0xc0000000, 0x40000000 },
-    [MICROCHIP_PFSOC_DRAM_HI] =       { 0x1000000000,        0x0 },
-    [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000,        0x0 },
+    [MICROCHIP_PFSOC_RSVD0] =           {        0x0,        0x100 },
+    [MICROCHIP_PFSOC_DEBUG] =           {      0x100,        0xf00 },
+    [MICROCHIP_PFSOC_E51_DTIM] =        {  0x1000000,       0x2000 },
+    [MICROCHIP_PFSOC_BUSERR_UNIT0] =    {  0x1700000,       0x1000 },
+    [MICROCHIP_PFSOC_BUSERR_UNIT1] =    {  0x1701000,       0x1000 },
+    [MICROCHIP_PFSOC_BUSERR_UNIT2] =    {  0x1702000,       0x1000 },
+    [MICROCHIP_PFSOC_BUSERR_UNIT3] =    {  0x1703000,       0x1000 },
+    [MICROCHIP_PFSOC_BUSERR_UNIT4] =    {  0x1704000,       0x1000 },
+    [MICROCHIP_PFSOC_CLINT] =           {  0x2000000,      0x10000 },
+    [MICROCHIP_PFSOC_L2CC] =            {  0x2010000,       0x1000 },
+    [MICROCHIP_PFSOC_DMA] =             {  0x3000000,     0x100000 },
+    [MICROCHIP_PFSOC_L2LIM] =           {  0x8000000,    0x2000000 },
+    [MICROCHIP_PFSOC_PLIC] =            {  0xc000000,    0x4000000 },
+    [MICROCHIP_PFSOC_MMUART0] =         { 0x20000000,       0x1000 },
+    [MICROCHIP_PFSOC_WDOG0] =           { 0x20001000,       0x1000 },
+    [MICROCHIP_PFSOC_SYSREG] =          { 0x20002000,       0x2000 },
+    [MICROCHIP_PFSOC_AXISW] =           { 0x20004000,       0x1000 },
+    [MICROCHIP_PFSOC_MPUCFG] =          { 0x20005000,       0x1000 },
+    [MICROCHIP_PFSOC_FMETER] =          { 0x20006000,       0x1000 },
+    [MICROCHIP_PFSOC_DDR_SGMII_PHY] =   { 0x20007000,       0x1000 },
+    [MICROCHIP_PFSOC_EMMC_SD] =         { 0x20008000,       0x1000 },
+    [MICROCHIP_PFSOC_DDR_CFG] =         { 0x20080000,      0x40000 },
+    [MICROCHIP_PFSOC_MMUART1] =         { 0x20100000,       0x1000 },
+    [MICROCHIP_PFSOC_MMUART2] =         { 0x20102000,       0x1000 },
+    [MICROCHIP_PFSOC_MMUART3] =         { 0x20104000,       0x1000 },
+    [MICROCHIP_PFSOC_MMUART4] =         { 0x20106000,       0x1000 },
+    [MICROCHIP_PFSOC_WDOG1] =           { 0x20101000,       0x1000 },
+    [MICROCHIP_PFSOC_WDOG2] =           { 0x20103000,       0x1000 },
+    [MICROCHIP_PFSOC_WDOG3] =           { 0x20105000,       0x1000 },
+    [MICROCHIP_PFSOC_WDOG4] =           { 0x20106000,       0x1000 },
+    [MICROCHIP_PFSOC_SPI0] =            { 0x20108000,       0x1000 },
+    [MICROCHIP_PFSOC_SPI1] =            { 0x20109000,       0x1000 },
+    [MICROCHIP_PFSOC_I2C0] =            { 0x2010a000,       0x1000 },
+    [MICROCHIP_PFSOC_I2C1] =            { 0x2010b000,       0x1000 },
+    [MICROCHIP_PFSOC_CAN0] =            { 0x2010c000,       0x1000 },
+    [MICROCHIP_PFSOC_CAN1] =            { 0x2010d000,       0x1000 },
+    [MICROCHIP_PFSOC_GEM0] =            { 0x20110000,       0x2000 },
+    [MICROCHIP_PFSOC_GEM1] =            { 0x20112000,       0x2000 },
+    [MICROCHIP_PFSOC_GPIO0] =           { 0x20120000,       0x1000 },
+    [MICROCHIP_PFSOC_GPIO1] =           { 0x20121000,       0x1000 },
+    [MICROCHIP_PFSOC_GPIO2] =           { 0x20122000,       0x1000 },
+    [MICROCHIP_PFSOC_RTC] =             { 0x20124000,       0x1000 },
+    [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,       0x1000 },
+    [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,      0x20000 },
+    [MICROCHIP_PFSOC_USB] =             { 0x20201000,       0x1000 },
+    [MICROCHIP_PFSOC_QSPI_XIP] =        { 0x21000000,    0x1000000 },
+    [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000,   0x10000000 },
+    [MICROCHIP_PFSOC_FABRIC_FIC0] =   { 0x2000000000, 0x1000000000 },
+    [MICROCHIP_PFSOC_FABRIC_FIC1] =   { 0x3000000000, 0x1000000000 },
+    [MICROCHIP_PFSOC_FABRIC_FIC3] =     { 0x40000000,   0x20000000 },
+    [MICROCHIP_PFSOC_DRAM_LO] =         { 0x80000000,   0x40000000 },
+    [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =   { 0xc0000000,   0x40000000 },
+    [MICROCHIP_PFSOC_DRAM_HI] =       { 0x1000000000,          0x0 },
+    [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000,          0x0 },
+
 };
 
 static void microchip_pfsoc_soc_instance_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("microchip.pfsoc.fabricfic3",
         memmap[MICROCHIP_PFSOC_FABRIC_FIC3].base,
         memmap[MICROCHIP_PFSOC_FABRIC_FIC3].size);
+    /* FPGA Fabric */
+    create_unimplemented_device("microchip.pfsoc.fabricfic0",
+        memmap[MICROCHIP_PFSOC_FABRIC_FIC0].base,
+        memmap[MICROCHIP_PFSOC_FABRIC_FIC0].size);
+    /* FPGA Fabric */
+    create_unimplemented_device("microchip.pfsoc.fabricfic1",
+        memmap[MICROCHIP_PFSOC_FABRIC_FIC1].base,
+        memmap[MICROCHIP_PFSOC_FABRIC_FIC1].size);
 
     /* QSPI Flash */
     memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
-- 
2.38.1

From: Conor Dooley <conor.dooley@microchip.com>

The system controller on PolarFire SoC is access via a mailbox. The
control registers for this mailbox lie in the "IOSCB" region & the
interrupt is cleared via write to the "SYSREG" region. It also has a
QSPI controller, usually connected to a flash chip, that is used for
storing FPGA bitstreams and used for In-Application Programming (IAP).

Linux has an implementation of the system controller, through which the
hwrng is accessed, leading to load/store access faults.

Add the QSPI as unimplemented and a very basic (effectively
unimplemented) version of the system controller's mailbox. Rather than
purely marking the regions as unimplemented, service the mailbox
requests by reporting failures and raising the interrupt so a guest can
better handle the lack of support.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221117225518.4102575-4-conor@kernel.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/misc/mchp_pfsoc_ioscb.h  |  3 ++
 include/hw/misc/mchp_pfsoc_sysreg.h |  1 +
 include/hw/riscv/microchip_pfsoc.h  |  1 +
 hw/misc/mchp_pfsoc_ioscb.c          | 72 ++++++++++++++++++++++++++++-
 hw/misc/mchp_pfsoc_sysreg.c         | 18 ++++++--
 hw/riscv/microchip_pfsoc.c          |  6 +++
 6 files changed, 95 insertions(+), 6 deletions(-)

diff --git a/include/hw/misc/mchp_pfsoc_ioscb.h b/include/hw/misc/mchp_pfsoc_ioscb.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/mchp_pfsoc_ioscb.h
+++ b/include/hw/misc/mchp_pfsoc_ioscb.h
@@ -XXX,XX +XXX,XX @@ typedef struct MchpPfSoCIoscbState {
     MemoryRegion lane01;
     MemoryRegion lane23;
     MemoryRegion ctrl;
+    MemoryRegion qspixip;
+    MemoryRegion mailbox;
     MemoryRegion cfg;
     MemoryRegion ccc;
     MemoryRegion pll_mss;
@@ -XXX,XX +XXX,XX @@ typedef struct MchpPfSoCIoscbState {
     MemoryRegion cfm_sgmii;
     MemoryRegion bc_sgmii;
     MemoryRegion io_calib_sgmii;
+    qemu_irq irq;
 } MchpPfSoCIoscbState;
 
 #define TYPE_MCHP_PFSOC_IOSCB "mchp.pfsoc.ioscb"
diff --git a/include/hw/misc/mchp_pfsoc_sysreg.h b/include/hw/misc/mchp_pfsoc_sysreg.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/mchp_pfsoc_sysreg.h
+++ b/include/hw/misc/mchp_pfsoc_sysreg.h
@@ -XXX,XX +XXX,XX @@
 typedef struct MchpPfSoCSysregState {
     SysBusDevice parent;
     MemoryRegion sysreg;
+    qemu_irq irq;
 } MchpPfSoCSysregState;
 
 #define TYPE_MCHP_PFSOC_SYSREG "mchp.pfsoc.sysreg"
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@ enum {
     MICROCHIP_PFSOC_MMUART2_IRQ = 92,
     MICROCHIP_PFSOC_MMUART3_IRQ = 93,
     MICROCHIP_PFSOC_MMUART4_IRQ = 94,
+    MICROCHIP_PFSOC_MAILBOX_IRQ = 96,
 };
 
 #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT    1
diff --git a/hw/misc/mchp_pfsoc_ioscb.c b/hw/misc/mchp_pfsoc_ioscb.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/mchp_pfsoc_ioscb.c
+++ b/hw/misc/mchp_pfsoc_ioscb.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/bitops.h"
 #include "qemu/log.h"
 #include "qapi/error.h"
+#include "hw/irq.h"
 #include "hw/sysbus.h"
 #include "hw/misc/mchp_pfsoc_ioscb.h"
 
@@ -XXX,XX +XXX,XX @@
 #define IOSCB_WHOLE_REG_SIZE        0x10000000
 #define IOSCB_SUBMOD_REG_SIZE       0x1000
 #define IOSCB_CCC_REG_SIZE          0x2000000
+#define IOSCB_CTRL_REG_SIZE         0x800
+#define IOSCB_QSPIXIP_REG_SIZE      0x200
+
 
 /*
  * There are many sub-modules in the IOSCB module.
@@ -XXX,XX +XXX,XX @@
 #define IOSCB_LANE01_BASE           0x06500000
 #define IOSCB_LANE23_BASE           0x06510000
 #define IOSCB_CTRL_BASE             0x07020000
+#define IOSCB_QSPIXIP_BASE          0x07020100
+#define IOSCB_MAILBOX_BASE          0x07020800
 #define IOSCB_CFG_BASE              0x07080000
 #define IOSCB_CCC_BASE              0x08000000
 #define IOSCB_PLL_MSS_BASE          0x0E001000
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps mchp_pfsoc_io_calib_ddr_ops = {
     .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
+#define SERVICES_CR             0x50
+#define SERVICES_SR             0x54
+#define SERVICES_STATUS_SHIFT   16
+
+static uint64_t mchp_pfsoc_ctrl_read(void *opaque, hwaddr offset,
+                                     unsigned size)
+{
+    uint32_t val = 0;
+
+    switch (offset) {
+    case SERVICES_SR:
+        /*
+         * Although some services have no error codes, most do. All services
+         * that do implement errors, begin their error codes at 1. Treat all
+         * service requests as failures & return 1.
+         * See the "PolarFire® FPGA and PolarFire SoC FPGA System Services"
+         * user guide for more information on service error codes.
+         */
+        val = 1u << SERVICES_STATUS_SHIFT;
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
+                      "(size %d, offset 0x%" HWADDR_PRIx ")\n",
+                      __func__, size, offset);
+    }
+
+    return val;
+}
+
+static void mchp_pfsoc_ctrl_write(void *opaque, hwaddr offset,
+                                  uint64_t value, unsigned size)
+{
+    MchpPfSoCIoscbState *s = opaque;
+
+    switch (offset) {
+    case SERVICES_CR:
+        qemu_irq_raise(s->irq);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
+                      "(size %d, value 0x%" PRIx64
+                      ", offset 0x%" HWADDR_PRIx ")\n",
+                      __func__, size, value, offset);
+    }
+}
+
+static const MemoryRegionOps mchp_pfsoc_ctrl_ops = {
+    .read = mchp_pfsoc_ctrl_read,
+    .write = mchp_pfsoc_ctrl_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
 static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp)
 {
     MchpPfSoCIoscbState *s = MCHP_PFSOC_IOSCB(dev);
@@ -XXX,XX +XXX,XX @@ static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp)
                           "mchp.pfsoc.ioscb.lane23", IOSCB_SUBMOD_REG_SIZE);
     memory_region_add_subregion(&s->container, IOSCB_LANE23_BASE, &s->lane23);
 
-    memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
-                          "mchp.pfsoc.ioscb.ctrl", IOSCB_SUBMOD_REG_SIZE);
+    memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_ctrl_ops, s,
+                          "mchp.pfsoc.ioscb.ctrl", IOSCB_CTRL_REG_SIZE);
     memory_region_add_subregion(&s->container, IOSCB_CTRL_BASE, &s->ctrl);
 
+    memory_region_init_io(&s->qspixip, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+                          "mchp.pfsoc.ioscb.qspixip", IOSCB_QSPIXIP_REG_SIZE);
+    memory_region_add_subregion(&s->container, IOSCB_QSPIXIP_BASE, &s->qspixip);
+
+    memory_region_init_io(&s->mailbox, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+                          "mchp.pfsoc.ioscb.mailbox", IOSCB_SUBMOD_REG_SIZE);
+    memory_region_add_subregion(&s->container, IOSCB_MAILBOX_BASE, &s->mailbox);
+
     memory_region_init_io(&s->cfg, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
                           "mchp.pfsoc.ioscb.cfg", IOSCB_SUBMOD_REG_SIZE);
     memory_region_add_subregion(&s->container, IOSCB_CFG_BASE, &s->cfg);
@@ -XXX,XX +XXX,XX @@ static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp)
                           IOSCB_SUBMOD_REG_SIZE);
     memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_SGMII_BASE,
                                 &s->io_calib_sgmii);
+
+    sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
 }
 
 static void mchp_pfsoc_ioscb_class_init(ObjectClass *klass, void *data)
diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/mchp_pfsoc_sysreg.c
+++ b/hw/misc/mchp_pfsoc_sysreg.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/bitops.h"
 #include "qemu/log.h"
 #include "qapi/error.h"
+#include "hw/irq.h"
 #include "hw/sysbus.h"
 #include "hw/misc/mchp_pfsoc_sysreg.h"
 
 #define ENVM_CR         0xb8
+#define MESSAGE_INT     0x118c
 
 static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset,
                                        unsigned size)
@@ -XXX,XX +XXX,XX @@ static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset,
 static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset,
                                     uint64_t value, unsigned size)
 {
-    qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
-                  "(size %d, value 0x%" PRIx64
-                  ", offset 0x%" HWADDR_PRIx ")\n",
-                  __func__, size, value, offset);
+    MchpPfSoCSysregState *s = opaque;
+    switch (offset) {
+    case MESSAGE_INT:
+        qemu_irq_lower(s->irq);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
+                      "(size %d, value 0x%" PRIx64
+                      ", offset 0x%" HWADDR_PRIx ")\n",
+                      __func__, size, value, offset);
+    }
 }
 
 static const MemoryRegionOps mchp_pfsoc_sysreg_ops = {
@@ -XXX,XX +XXX,XX @@ static void mchp_pfsoc_sysreg_realize(DeviceState *dev, Error **errp)
                           "mchp.pfsoc.sysreg",
                           MCHP_PFSOC_SYSREG_REG_SIZE);
     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysreg);
+    sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
 }
 
 static void mchp_pfsoc_sysreg_class_init(ObjectClass *klass, void *data)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
     sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0,
                     memmap[MICROCHIP_PFSOC_SYSREG].base);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sysreg), 0,
+                       qdev_get_gpio_in(DEVICE(s->plic),
+                       MICROCHIP_PFSOC_MAILBOX_IRQ));
 
     /* AXISW */
     create_unimplemented_device("microchip.pfsoc.axisw",
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
     sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
                     memmap[MICROCHIP_PFSOC_IOSCB].base);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioscb), 0,
+                       qdev_get_gpio_in(DEVICE(s->plic),
+                       MICROCHIP_PFSOC_MAILBOX_IRQ));
 
     /* FPGA Fabric */
     create_unimplemented_device("microchip.pfsoc.fabricfic3",
-- 
2.38.1

From: Jim Shu <jim.shu@sifive.com>

If the number of interrupt is not multiple of 32, PLIC will have
out-of-bound access to source_priority array. Compute the number of
interrupt in the last word to avoid this out-of-bound access of array.

Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Message-Id: <20221127165753.30533-1-jim.shu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/sifive_plic.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -XXX,XX +XXX,XX @@ static uint32_t sifive_plic_claimed(SiFivePLICState *plic, uint32_t addrid)
     uint32_t max_irq = 0;
     uint32_t max_prio = plic->target_priority[addrid];
     int i, j;
+    int num_irq_in_word = 32;
 
     for (i = 0; i < plic->bitfield_words; i++) {
         uint32_t pending_enabled_not_claimed =
@@ -XXX,XX +XXX,XX @@ static uint32_t sifive_plic_claimed(SiFivePLICState *plic, uint32_t addrid)
             continue;
         }
 
-        for (j = 0; j < 32; j++) {
+        if (i == (plic->bitfield_words - 1)) {
+            /*
+             * If plic->num_sources is not multiple of 32, num-of-irq in last
+             * word is not 32. Compute the num-of-irq of last word to avoid
+             * out-of-bound access of source_priority array.
+             */
+            num_irq_in_word = plic->num_sources - ((plic->bitfield_words - 1) << 5);
+        }
+
+        for (j = 0; j < num_irq_in_word; j++) {
             int irq = (i << 5) + j;
             uint32_t prio = plic->source_priority[irq];
             int enabled = pending_enabled_not_claimed & (1 << j);
-- 
2.38.1

From: Bin Meng <bmeng@tinylab.org>

The priv spec v1.12 says:

If no PMP entry matches an M-mode access, the access succeeds. If
  no PMP entry matches an S-mode or U-mode access, but at least one
  PMP entry is implemented, the access fails. Failed accesses generate
  an instruction, load, or store access-fault exception.

At present the exception cause is set to 'illegal instruction' but
should have been 'instruction access fault'.

Fixes: d102f19a2085 ("target/riscv/pmp: Raise exception if no PMP entry is configured")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221205065303.204095-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/op_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_mret(CPURISCVState *env)
 
     if (riscv_feature(env, RISCV_FEATURE_PMP) &&
         !pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
-        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+        riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC());
     }
 
     target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
-- 
2.38.1

From: Richard Henderson <richard.henderson@linaro.org>

Failure to set pc_succ_insn may result in a TB covering zero bytes,
which triggers an assert within the code generator.

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1224
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221203175744.151365-1-richard.henderson@linaro.org>
[ Changes by AF:
 - Add missing run-plugin-test-noc-% line
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c          | 12 ++++--------
 tests/tcg/Makefile.target         |  2 ++
 tests/tcg/riscv64/Makefile.target |  6 ++++++
 tests/tcg/riscv64/test-noc.S      | 32 +++++++++++++++++++++++++++++++
 4 files changed, 44 insertions(+), 8 deletions(-)
 create mode 100644 tests/tcg/riscv64/test-noc.S

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
     ctx->virt_inst_excp = false;
     /* Check for compressed insn */
     if (insn_len(opcode) == 2) {
-        if (!has_ext(ctx, RVC)) {
-            gen_exception_illegal(ctx);
-        } else {
-            ctx->opcode = opcode;
-            ctx->pc_succ_insn = ctx->base.pc_next + 2;
-            if (decode_insn16(ctx, opcode)) {
-                return;
-            }
+        ctx->opcode = opcode;
+        ctx->pc_succ_insn = ctx->base.pc_next + 2;
+        if (has_ext(ctx, RVC) && decode_insn16(ctx, opcode)) {
+            return;
         }
     } else {
         uint32_t opcode32 = opcode;
diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target
index XXXXXXX..XXXXXXX 100644
--- a/tests/tcg/Makefile.target
+++ b/tests/tcg/Makefile.target
@@ -XXX,XX +XXX,XX @@ endif
 
 %: %.c
 	$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
+%: %.S
+	$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
 else
 # For softmmu targets we include a different Makefile fragement as the
 # build options for bare programs are usually pretty different. They
diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile.target
index XXXXXXX..XXXXXXX 100644
--- a/tests/tcg/riscv64/Makefile.target
+++ b/tests/tcg/riscv64/Makefile.target
@@ -XXX,XX +XXX,XX @@
 VPATH += $(SRC_PATH)/tests/tcg/riscv64
 TESTS += test-div
 TESTS += noexec
+
+# Disable compressed instructions for test-noc
+TESTS += test-noc
+test-noc: LDFLAGS = -nostdlib -static
+run-test-noc: QEMU_OPTS += -cpu rv64,c=false
+run-plugin-test-noc-%: QEMU_OPTS += -cpu rv64,c=false
diff --git a/tests/tcg/riscv64/test-noc.S b/tests/tcg/riscv64/test-noc.S
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/tcg/riscv64/test-noc.S
@@ -XXX,XX +XXX,XX @@
+#include <asm/unistd.h>
+
+	.text
+	.globl _start
+_start:
+	.option	norvc
+	li	a0, 4		/* SIGILL */
+	la	a1, sa
+	li	a2, 0
+	li	a3, 8
+	li	a7, __NR_rt_sigaction
+	scall
+
+	.option	rvc
+	li	a0, 1
+	j	exit
+	.option	norvc
+
+pass:
+	li	a0, 0
+exit:
+	li	a7, __NR_exit
+	scall
+
+	.data
+	/* struct kernel_sigaction sa = { .sa_handler = pass }; */
+	.type	sa, @object
+	.size	sa, 32
+sa:
+	.dword	pass
+	.zero	24
+
-- 
2.38.1

From: Bin Meng <bmeng@tinylab.org>

There are 2 paths in helper_sret() and the same mstatus update codes
are replicated. Extract the common parts to simplify it a little bit.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221207090037.281452-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/op_helper.c | 20 ++++++--------------
 1 file changed, 6 insertions(+), 14 deletions(-)

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_sret(CPURISCVState *env)
     }
 
     mstatus = env->mstatus;
+    prev_priv = get_field(mstatus, MSTATUS_SPP);
+    mstatus = set_field(mstatus, MSTATUS_SIE,
+                        get_field(mstatus, MSTATUS_SPIE));
+    mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
+    mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
+    env->mstatus = mstatus;
 
     if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
         /* We support Hypervisor extensions and virtulisation is disabled */
         target_ulong hstatus = env->hstatus;
 
-        prev_priv = get_field(mstatus, MSTATUS_SPP);
         prev_virt = get_field(hstatus, HSTATUS_SPV);
 
         hstatus = set_field(hstatus, HSTATUS_SPV, 0);
-        mstatus = set_field(mstatus, MSTATUS_SPP, 0);
-        mstatus = set_field(mstatus, SSTATUS_SIE,
-                            get_field(mstatus, SSTATUS_SPIE));
-        mstatus = set_field(mstatus, SSTATUS_SPIE, 1);
 
-        env->mstatus = mstatus;
         env->hstatus = hstatus;
 
         if (prev_virt) {
@@ -XXX,XX +XXX,XX @@ target_ulong helper_sret(CPURISCVState *env)
         }
 
         riscv_cpu_set_virt_enabled(env, prev_virt);
-    } else {
-        prev_priv = get_field(mstatus, MSTATUS_SPP);
-
-        mstatus = set_field(mstatus, MSTATUS_SIE,
-                            get_field(mstatus, MSTATUS_SPIE));
-        mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
-        mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
-        env->mstatus = mstatus;
     }
 
     riscv_cpu_set_mode(env, prev_priv);
-- 
2.38.1

From: Bin Meng <bmeng@tinylab.org>

Since priv spec v1.12, MRET and SRET now clear mstatus.MPRV when
leaving M-mode.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221207090037.281452-2-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/op_helper.c | 6 ++++++
 1 file changed, 6 insertions(+)

From: Christoph Muellner <christoph.muellner@vrull.eu>

This patch adds support for the Zawrs ISA extension.
Given the current (incomplete) implementation of reservation sets
there seems to be no way to provide a full emulation of the WRS
instruction (wake on reservation set invalidation or timeout or
interrupt). Therefore, we just exit the TB and return to the main loop.

The specification can be found here:
  https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc

Note, that the Zawrs extension is frozen, but not ratified yet.

Changes since v3:
* Remove "RFC" since the extension is frozen
* Rebase on master and fix integration issues
* Fix entry ordering in extension list

Changes since v2:
* Rebase on master and resolve conflicts
* Adjustments according to a specification change
* Inline REQUIRE_ZAWRS() since it has only one user

Changes since v1:
* Adding zawrs to the ISA string that is passed to the kernel

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221005144948.3421504-1-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h                          |  1 +
 target/riscv/insn32.decode                  |  4 ++
 target/riscv/cpu.c                          |  7 +++
 target/riscv/translate.c                    |  1 +
 target/riscv/insn_trans/trans_rvzawrs.c.inc | 51 +++++++++++++++++++++
 5 files changed, 64 insertions(+)
 create mode 100644 target/riscv/insn_trans/trans_rvzawrs.c.inc

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_svnapot;
     bool ext_svpbmt;
     bool ext_zdinx;
+    bool ext_zawrs;
     bool ext_zfh;
     bool ext_zfhmin;
     bool ext_zfinx;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm11
 vsetivli        11 .......... ..... 111 ..... 1010111  @r2_zimm10
 vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
 
+# *** Zawrs Standard Extension ***
+wrs_nto    000000001101 00000 000 00000 1110011
+wrs_sto    000000011101 00000 000 00000 1110011
+
 # *** RV32 Zba Standard Extension ***
 sh1add     0010000 .......... 010 ..... 0110011 @r
 sh2add     0010000 .......... 100 ..... 0110011 @r
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr),
     ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
     ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause),
+    ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs),
     ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh),
     ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
     ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             return;
         }
 
+        if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) {
+            error_setg(errp, "Zawrs extension requires A extension");
+            return;
+        }
+
         if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) {
             error_setg(errp, "Zfh/Zfhmin extensions require F extension");
             return;
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
     DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
+    DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true),
     DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
     DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
     DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
 #include "insn_trans/trans_rvh.c.inc"
 #include "insn_trans/trans_rvv.c.inc"
 #include "insn_trans/trans_rvb.c.inc"
+#include "insn_trans/trans_rvzawrs.c.inc"
 #include "insn_trans/trans_rvzfh.c.inc"
 #include "insn_trans/trans_rvk.c.inc"
 #include "insn_trans/trans_privileged.c.inc"
diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
@@ -XXX,XX +XXX,XX @@
+/*
+ * RISC-V translation routines for the RISC-V Zawrs Extension.
+ *
+ * Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.io
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_wrs(DisasContext *ctx)
+{
+    if (!ctx->cfg_ptr->ext_zawrs) {
+        return false;
+    }
+
+    /*
+     * The specification says:
+     * While stalled, an implementation is permitted to occasionally
+     * terminate the stall and complete execution for any reason.
+     *
+     * So let's just exit TB and return to the main loop.
+     */
+
+    /* Clear the load reservation  (if any).  */
+    tcg_gen_movi_tl(load_res, -1);
+
+    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+    tcg_gen_exit_tb(NULL, 0);
+    ctx->base.is_jmp = DISAS_NORETURN;
+
+    return true;
+}
+
+#define GEN_TRANS_WRS(insn)                                     \
+static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
+{                                                               \
+    (void)a;                                                    \
+    return trans_wrs(ctx);                                      \
+}
+
+GEN_TRANS_WRS(wrs_nto)
+GEN_TRANS_WRS(wrs_sto)
-- 
2.38.1

From: Bin Meng <bmeng@tinylab.org>

hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
controllers regardless of how MSI is implemented. msi_nonbroken is
initialized to true in sifive_plic_realize().

Let SIFIVE_PLIC select MSI_NONBROKEN and drop the selection from
RISC-V machines.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Message-Id: <20221211030829.802437-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/Kconfig  | 1 +
 hw/riscv/Kconfig | 5 -----
 2 files changed, 1 insertion(+), 5 deletions(-)

diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_IMSIC
 
 config SIFIVE_PLIC
     bool
+    select MSI_NONBROKEN
 
 config GOLDFISH_PIC
     bool
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
     select MCHP_PFSOC_IOSCB
     select MCHP_PFSOC_MMUART
     select MCHP_PFSOC_SYSREG
-    select MSI_NONBROKEN
     select RISCV_ACLINT
     select SIFIVE_PDMA
     select SIFIVE_PLIC
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     imply TPM_TIS_SYSBUS
     select RISCV_NUMA
     select GOLDFISH_RTC
-    select MSI_NONBROKEN
     select PCI
     select PCI_EXPRESS_GENERIC_BRIDGE
     select PFLASH_CFI01
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
 
 config SIFIVE_E
     bool
-    select MSI_NONBROKEN
     select RISCV_ACLINT
     select SIFIVE_GPIO
     select SIFIVE_PLIC
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
 config SIFIVE_U
     bool
     select CADENCE
-    select MSI_NONBROKEN
     select RISCV_ACLINT
     select SIFIVE_GPIO
     select SIFIVE_PDMA
@@ -XXX,XX +XXX,XX @@ config SPIKE
     bool
     select RISCV_NUMA
     select HTIF
-    select MSI_NONBROKEN
     select RISCV_ACLINT
     select SIFIVE_PLIC
-- 
2.38.1

From: Bin Meng <bmeng@tinylab.org>

SHAKTI_C machine Kconfig option was inserted in disorder. Fix it.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Message-Id: <20221211030829.802437-4-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/Kconfig | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_NUMA
 config IBEX
     bool
 
+# RISC-V machines in alphabetical order
+
 config MICROCHIP_PFSOC
     bool
     select CADENCE_SDHCI
@@ -XXX,XX +XXX,XX @@ config OPENTITAN
     select SIFIVE_PLIC
     select UNIMP
 
-config SHAKTI_C
-    bool
-    select UNIMP
-    select SHAKTI_UART
-    select RISCV_ACLINT
-    select SIFIVE_PLIC
-
 config RISCV_VIRT
     bool
     imply PCI_DEVICES
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     select FW_CFG_DMA
     select PLATFORM_BUS
 
+config SHAKTI_C
+    bool
+    select RISCV_ACLINT
+    select SHAKTI_UART
+    select SIFIVE_PLIC
+    select UNIMP
+
 config SIFIVE_E
     bool
     select RISCV_ACLINT
-- 
2.38.1

From: Bin Meng <bmeng@tinylab.org>

H-mode has been removed since priv spec 1.10. Drop it.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-6-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/intc/sifive_plic.h | 1 -
 hw/intc/sifive_plic.c         | 1 -
 2 files changed, 2 deletions(-)

diff --git a/include/hw/intc/sifive_plic.h b/include/hw/intc/sifive_plic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/sifive_plic.h
+++ b/include/hw/intc/sifive_plic.h
@@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(SiFivePLICState, SIFIVE_PLIC,
 typedef enum PLICMode {
     PLICMode_U,
     PLICMode_S,
-    PLICMode_H,
     PLICMode_M
 } PLICMode;
 
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -XXX,XX +XXX,XX @@ static PLICMode char_to_mode(char c)
     switch (c) {
     case 'U': return PLICMode_U;
     case 'S': return PLICMode_S;
-    case 'H': return PLICMode_H;
     case 'M': return PLICMode_M;
     default:
         error_report("plic: invalid mode '%c'", c);
-- 
2.38.1

From: Bin Meng <bmeng@tinylab.org>

At present the PLIC config parser can only handle legal config string
like "MS,MS". However if a config string like ",MS,MS,,MS,MS,," is
given the parser won't get the correct configuration.

This commit improves the config parser to make it more robust.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-7-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/sifive_plic.c | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -XXX,XX +XXX,XX @@ static void sifive_plic_reset(DeviceState *dev)
  */
 static void parse_hart_config(SiFivePLICState *plic)
 {
-    int addrid, hartid, modes;
+    int addrid, hartid, modes, m;
     const char *p;
     char c;
 
@@ -XXX,XX +XXX,XX @@ static void parse_hart_config(SiFivePLICState *plic)
     p = plic->hart_config;
     while ((c = *p++)) {
         if (c == ',') {
-            addrid += ctpop8(modes);
-            modes = 0;
-            hartid++;
+            if (modes) {
+                addrid += ctpop8(modes);
+                hartid++;
+                modes = 0;
+            }
         } else {
-            int m = 1 << char_to_mode(c);
+            m = 1 << char_to_mode(c);
             if (modes == (modes | m)) {
                 error_report("plic: duplicate mode '%c' in config: %s",
                              c, plic->hart_config);
@@ -XXX,XX +XXX,XX @@ static void parse_hart_config(SiFivePLICState *plic)
     }
     if (modes) {
         addrid += ctpop8(modes);
+        hartid++;
+        modes = 0;
     }
-    hartid++;
 
     plic->num_addrs = addrid;
     plic->num_harts = hartid;
@@ -XXX,XX +XXX,XX @@ static void parse_hart_config(SiFivePLICState *plic)
     p = plic->hart_config;
     while ((c = *p++)) {
         if (c == ',') {
-            hartid++;
+            if (modes) {
+                hartid++;
+                modes = 0;
+            }
         } else {
+            m = char_to_mode(c);
             plic->addr_config[addrid].addrid = addrid;
             plic->addr_config[addrid].hartid = hartid;
-            plic->addr_config[addrid].mode = char_to_mode(c);
+            plic->addr_config[addrid].mode = m;
+            modes |= (1 << m);
             addrid++;
         }
     }
-- 
2.38.1

From: Bin Meng <bmeng@tinylab.org>

The realize() callback has an errp for us to propagate the error up.
While we are here, correct the wrong multi-line comment format.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221211030829.802437-8-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/sifive_plic.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -XXX,XX +XXX,XX @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
     s->m_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
     qdev_init_gpio_out(dev, s->m_external_irqs, s->num_harts);
 
-    /* We can't allow the supervisor to control SEIP as this would allow the
+    /*
+     * We can't allow the supervisor to control SEIP as this would allow the
      * supervisor to clear a pending external interrupt which will result in
      * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
      * hardware controlled when a PLIC is attached.
@@ -XXX,XX +XXX,XX @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
     for (i = 0; i < s->num_harts; i++) {
         RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
         if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
-            error_report("SEIP already claimed");
-            exit(1);
+            error_setg(errp, "SEIP already claimed");
+            return;
         }
     }
 
-- 
2.38.1

From: Bin Meng <bmeng@tinylab.org>

At present the default value of "num-sources" property is zero,
which does not make a lot of sense, as in sifive_plic_realize()
we see s->bitfield_words is calculated by:

s->bitfield_words = (s->num_sources + 31) >> 5;

if the we don't configure "num-sources" property its default value
zero makes s->bitfield_words zero too, which isn't true because
interrupt source 0 still occupies one word.

Let's change the default value to 1 meaning that only interrupt
source 0 is supported by default and a sanity check in realize().

While we are here, add a comment to describe the exact meaning of
this property that the number should include interrupt source 0.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-9-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/sifive_plic.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -XXX,XX +XXX,XX @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
 
     parse_hart_config(s);
 
+    if (!s->num_sources) {
+        error_setg(errp, "plic: invalid number of interrupt sources");
+        return;
+    }
+
     s->bitfield_words = (s->num_sources + 31) >> 5;
     s->num_enables = s->bitfield_words * s->num_addrs;
     s->source_priority = g_new0(uint32_t, s->num_sources);
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_sifive_plic = {
 static Property sifive_plic_properties[] = {
     DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
     DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
-    DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
+    /* number of interrupt sources including interrupt source 0 */
+    DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 1),
     DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
     DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
     DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
-- 
2.38.1

From: Bin Meng <bmeng@tinylab.org>

Per chapter 6.5.2 in [1], the number of interupt sources including
interrupt source 0 should be 187.

[1] PolarFire SoC MSS TRM:
https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/ReferenceManuals/PolarFire_SoC_FPGA_MSS_Technical_Reference_Manual_VC.pdf

Fixes: 56f6e31e7b7e ("hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Message-Id: <20221211030829.802437-10-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

From: Bin Meng <bmeng@tinylab.org>

Per chapter 10 in Freedom E310 manuals [1][2][3], E310 G002 and G003
supports 52 interrupt sources while G000 supports 51 interrupt sources.

We use the value of G002 and G003, so it is 53 (including source 0).

[1] G000 manual:
https://sifive.cdn.prismic.io/sifive/4faf3e34-4a42-4c2f-be9e-c77baa4928c7_fe310-g000-manual-v3p2.pdf

[2] G002 manual:
https://sifive.cdn.prismic.io/sifive/034760b5-ac6a-4b1c-911c-f4148bb2c4a5_fe310-g002-v1p5.pdf

[3] G003 manual:
https://sifive.cdn.prismic.io/sifive/3af39c59-6498-471e-9dab-5355a0d539eb_fe310-g003-manual.pdf

Fixes: eb637edb1241 ("SiFive Freedom E Series RISC-V Machine")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-11-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/sifive_e.h | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -XXX,XX +XXX,XX @@ enum {
 };
 
 #define SIFIVE_E_PLIC_HART_CONFIG "M"
-#define SIFIVE_E_PLIC_NUM_SOURCES 127
+/*
+ * Freedom E310 G002 and G003 supports 52 interrupt sources while
+ * Freedom E310 G000 supports 51 interrupt sources. We use the value
+ * of G002 and G003, so it is 53 (including interrupt source 0).
+ */
+#define SIFIVE_E_PLIC_NUM_SOURCES 53
 #define SIFIVE_E_PLIC_NUM_PRIORITIES 7
 #define SIFIVE_E_PLIC_PRIORITY_BASE 0x04
 #define SIFIVE_E_PLIC_PENDING_BASE 0x1000
-- 
2.38.1

From: Bin Meng <bmeng@tinylab.org>

At present magic number is used to create "riscv,ndev" property
in the dtb. Let's use the macro SIFIVE_U_PLIC_NUM_SOURCES that
is used to instantiate the PLIC model instead.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-12-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_u.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
     qemu_fdt_setprop_cells(fdt, nodename, "reg",
         0x0, memmap[SIFIVE_U_DEV_PLIC].base,
         0x0, memmap[SIFIVE_U_DEV_PLIC].size);
-    qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
+    qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev",
+                          SIFIVE_U_PLIC_NUM_SOURCES - 1);
     qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
     plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
     g_free(cells);
-- 
2.38.1

From: Bin Meng <bmeng@tinylab.org>

Commit 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine")
changed the value of VIRT_IRQCHIP_NUM_SOURCES from 127 to 53, which
is VIRTIO_NDEV and also used as the value of "riscv,ndev" property
in the dtb. Unfortunately this is wrong as VIRT_IRQCHIP_NUM_SOURCES
should include interrupt source 0 but "riscv,ndev" does not.

While we are here, we also fix the comments of platform bus irq range
which is now "64 to 96", but should be "64 to 95", introduced since
commit 1832b7cb3f64 ("hw/riscv: virt: Create a platform bus").

Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-13-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/virt.h | 5 ++---
 hw/riscv/virt.c         | 3 ++-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -XXX,XX +XXX,XX @@ enum {
     VIRTIO_IRQ = 1, /* 1 to 8 */
     VIRTIO_COUNT = 8,
     PCIE_IRQ = 0x20, /* 32 to 35 */
-    VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 96 */
-    VIRTIO_NDEV = 96 /* Arbitrary maximum number of interrupts */
+    VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 95 */
 };
 
 #define VIRT_PLATFORM_BUS_NUM_IRQS 32
 
 #define VIRT_IRQCHIP_NUM_MSIS 255
-#define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV
+#define VIRT_IRQCHIP_NUM_SOURCES 96
 #define VIRT_IRQCHIP_NUM_PRIO_BITS 3
 #define VIRT_IRQCHIP_MAX_GUESTS_BITS 3
 #define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
         plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
     qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg",
         0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
-    qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
+    qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev",
+                          VIRT_IRQCHIP_NUM_SOURCES - 1);
     riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket);
     qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
         plic_phandles[socket]);
-- 
2.38.1

From: Bin Meng <bmeng@tinylab.org>

At present the SiFive PLIC model "priority-base" expects interrupt
priority register base starting from source 1 instead source 0,
that's why on most platforms "priority-base" is set to 0x04 except
'opentitan' machine. 'opentitan' should have set "priority-base"
to 0x04 too.

Note the irq number calculation in sifive_plic_{read,write} is
correct as the codes make up for the irq number by adding 1.

Let's simply update "priority-base" to start from interrupt source
0 and add a comment to make it crystal clear.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Message-Id: <20221211030829.802437-14-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h | 2 +-
 include/hw/riscv/shakti_c.h        | 2 +-
 include/hw/riscv/sifive_e.h        | 2 +-
 include/hw/riscv/sifive_u.h        | 2 +-
 include/hw/riscv/virt.h            | 2 +-
 hw/intc/sifive_plic.c              | 5 +++--
 6 files changed, 8 insertions(+), 7 deletions(-)

From: Bin Meng <bmeng@tinylab.org>

"hartid-base" and "priority-base" are zero by default. There is no
need to initialize them to zero again.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-15-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/opentitan.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
 
     /* PLIC */
     qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M");
-    qdev_prop_set_uint32(DEVICE(&s->plic), "hartid-base", 0);
     qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180);
     qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3);
-    qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
     qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
     qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
     qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32);
-- 
2.38.1

From: Bin Meng <bmeng@tinylab.org>

The pending register upper limit is currently set to
plic->num_sources >> 3, which is wrong, e.g.: considering
plic->num_sources is 7, the upper limit becomes 0 which fails
the range check if reading the pending register at pending_base.

Fixes: 1e24429e40df ("SiFive RISC-V PLIC Block")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-16-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/sifive_plic.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -XXX,XX +XXX,XX @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
         uint32_t irq = (addr - plic->priority_base) >> 2;
 
         return plic->source_priority[irq];
-    } else if (addr_between(addr, plic->pending_base, plic->num_sources >> 3)) {
+    } else if (addr_between(addr, plic->pending_base,
+                            (plic->num_sources + 31) >> 3)) {
         uint32_t word = (addr - plic->pending_base) >> 2;
 
         return plic->pending[word];
@@ -XXX,XX +XXX,XX @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
             sifive_plic_update(plic);
         }
     } else if (addr_between(addr, plic->pending_base,
-                            plic->num_sources >> 3)) {
+                            (plic->num_sources + 31) >> 3)) {
         qemu_log_mask(LOG_GUEST_ERROR,
                       "%s: invalid pending write: 0x%" HWADDR_PRIx "",
                       __func__, addr);
-- 
2.38.1