Series comparison

-[PULL 0/5] tcg patch queue
+[PULL 0/4] tcg patch queue
-The following changes since commit 7e1c0047015ffbd408e1aa4a5ec1abe4751dbf7e:
+Pretty small still, but there are two patches that ought
 to get backported to stable, so no point in delaying.
-  Merge tag 'migration-20240522-pull-request' of https://gitlab.com/farosas/qemu into staging (2024-05-22 15:32:25 -0700)
+r~
 The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
   Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)
 are available in the Git repository at:
-  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240523
+  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241212
-for you to fetch changes up to bfd43cccab9fb77b8405ca556fc2f2ed3b2920a3:
+for you to fetch changes up to 7ac87b14a92234b6a89b701b4043ad6cf8bdcccf:
-  accel/tcg: Init tb size and icount before plugin_gen_tb_end (2024-05-22 19:05:26 -0700)
+  target/sparc: Use memcpy() and remove memcpy32() (2024-12-12 14:28:38 -0600)
 ----------------------------------------------------------------
-tcg: Introduce TCG_TARGET_HAS_tst_vec
+tcg: Reset free_temps before tcg_optimize
-accel/tcg: Init tb size and icount before plugin_gen_tb_end
+tcg/riscv: Fix StoreStore barrier generation
 include/exec: Introduce fpst alias in helper-head.h.inc
 target/sparc: Use memcpy() and remove memcpy32()
 ----------------------------------------------------------------
-Richard Henderson (5):
+Philippe Mathieu-Daudé (1):
-      tcg: Introduce TCG_TARGET_HAS_tst_vec
+      target/sparc: Use memcpy() and remove memcpy32()
       tcg: Expand TCG_COND_TST* if not TCG_TARGET_HAS_tst_vec
       tcg/aarch64: Support TCG_TARGET_HAS_tst_vec
       tcg/arm: Support TCG_TARGET_HAS_tst_vec
       accel/tcg: Init tb size and icount before plugin_gen_tb_end
- include/tcg/tcg.h            |  1 +
+Richard Henderson (2):
- tcg/aarch64/tcg-target.h     |  1 +
+      tcg: Reset free_temps before tcg_optimize
- tcg/arm/tcg-target.h         |  1 +
+      include/exec: Introduce fpst alias in helper-head.h.inc
- tcg/i386/tcg-target.h        |  1 +
- tcg/loongarch64/tcg-target.h |  1 +
+Roman Artemev (1):
- tcg/ppc/tcg-target.h         |  1 +
+      tcg/riscv: Fix StoreStore barrier generation
- tcg/s390x/tcg-target.h       |  1 +
- accel/tcg/translator.c       |  8 ++++----
+ include/tcg/tcg-temp-internal.h |  6 ++++++
- tcg/tcg-op-vec.c             | 18 ++++++++++++++++++
+ accel/tcg/plugin-gen.c          |  2 +-
- tcg/aarch64/tcg-target.c.inc | 26 ++++++++++++++++++++++++--
+ target/sparc/win_helper.c       | 26 ++++++++------------------
- tcg/arm/tcg-target.c.inc     | 23 ++++++++++++++++++++---
+ tcg/tcg.c                       |  5 ++++-
-files changed, 73 insertions(+), 9 deletions(-)
+ include/exec/helper-head.h.inc  |  3 +++
  tcg/riscv/tcg-target.c.inc      |  2 +-
 files changed, 23 insertions(+), 21 deletions(-)

-[PULL 5/5] accel/tcg: Init tb size and icount before plugin_gen_tb_end
+[PULL 1/4] tcg: Reset free_temps before tcg_optimize
-When passing disassembly data to plugin callbacks,
+When allocating new temps during tcg_optmize, do not re-use
-translator_st_len relies on db->tb->size having been set.
+any EBB temps that were used within the TB.  We do not have
 any idea what span of the TB in which the temp was live.
-Fixes: 4c833c60e047 ("disas: Use translator_st to get disassembly data")
+Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize,
-Reported-by: Bernhard Beschow <shentey@gmail.com>
+as well as replacing the equivalent in plugin_gen_inject and
 tcg_func_start.
 Cc: qemu-stable@nongnu.org
 Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported")
 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711
 Reported-by: wannacu <wannacu2049@gmail.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Tested-by: Bernhard Beschow <shentey@gmail.com>
 Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 ---
- accel/tcg/translator.c | 8 ++++----
+ include/tcg/tcg-temp-internal.h | 6 ++++++
-file changed, 4 insertions(+), 4 deletions(-)
+ accel/tcg/plugin-gen.c          | 2 +-
  tcg/tcg.c                       | 5 ++++-
 files changed, 11 insertions(+), 2 deletions(-)
-diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
+diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
 index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/translator.c
+--- a/include/tcg/tcg-temp-internal.h
-+++ b/accel/tcg/translator.c
++++ b/include/tcg/tcg-temp-internal.h
-@@ -XXX,XX +XXX,XX @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns,
+@@ -XXX,XX +XXX,XX @@ TCGv_i64 tcg_temp_ebb_new_i64(void);
-     set_can_do_io(db, true);
+ TCGv_ptr tcg_temp_ebb_new_ptr(void);
-     tcg_ctx->emit_before_op = NULL;
+ TCGv_i128 tcg_temp_ebb_new_i128(void);
-+    /* May be used by disas_log or plugin callbacks. */
++/* Forget all freed EBB temps, so that new allocations produce new temps. */
-+    tb->size = db->pc_next - db->pc_first;
++static inline void tcg_temp_ebb_reset_freed(TCGContext *s)
-+    tb->icount = db->num_insns;
++{
 +    memset(s->free_temps, 0, sizeof(s->free_temps));
 +}
 +
-     if (plugin_enabled) {
+ #endif /* TCG_TEMP_FREE_H */
-         plugin_gen_tb_end(cpu, db->num_insns);
+diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
 index XXXXXXX..XXXXXXX 100644
 --- a/accel/tcg/plugin-gen.c
 +++ b/accel/tcg/plugin-gen.c
@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
       * that might be live within the existing opcode stream.
       * The simplest solution is to release them all and create new.
       */
 -    memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps));
 +    tcg_temp_ebb_reset_freed(tcg_ctx);
      QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) {
          switch (op->opc) {
 diff --git a/tcg/tcg.c b/tcg/tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/tcg.c
 +++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
      s->nb_temps = s->nb_globals;
      /* No temps have been previously allocated for size or locality.  */
 -    memset(s->free_temps, 0, sizeof(s->free_temps));
 +    tcg_temp_ebb_reset_freed(s);
      /* No constant temps have been previously allocated. */
      for (int i = 0; i < TCG_TYPE_COUNT; ++i) {
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
      }
+ #endif
--    /* The disas_log hook may use these values rather than recompute.  */
--    tb->size = db->pc_next - db->pc_first;
++    /* Do not reuse any EBB that may be allocated within the TB. */
--    tb->icount = db->num_insns;
++    tcg_temp_ebb_reset_freed(s);
--
++
-     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
+     tcg_optimize(s);
-         && qemu_log_in_addr_range(db->pc_first)) {
-         FILE *logfile = qemu_log_trylock();
+     reachable_code_pass(s);
 --
-.34.1
+.43.0

-[PULL 4/5] tcg/arm: Support TCG_TARGET_HAS_tst_vec
+[PULL 2/4] tcg/riscv: Fix StoreStore barrier generation
+From: Roman Artemev <roman.artemev@syntacore.com>
+On RISC-V to StoreStore barrier corresponds
+`fence w, w` not `fence r, r`
+Cc: qemu-stable@nongnu.org
+Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
+Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
+Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/arm/tcg-target.h     |  2 +-
+ tcg/riscv/tcg-target.c.inc | 2 +-
- tcg/arm/tcg-target.c.inc | 23 ++++++++++++++++++++---
+file changed, 1 insertion(+), 1 deletion(-)
 files changed, 21 insertions(+), 4 deletions(-)
-diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
+diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.h
+--- a/tcg/riscv/tcg-target.c.inc
-+++ b/tcg/arm/tcg-target.h
++++ b/tcg/riscv/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
- #define TCG_TARGET_HAS_minmax_vec       1
+         insn |= 0x02100000;
- #define TCG_TARGET_HAS_bitsel_vec       1
+     }
- #define TCG_TARGET_HAS_cmpsel_vec       0
+     if (a0 & TCG_MO_ST_ST) {
--#define TCG_TARGET_HAS_tst_vec          0
+-        insn |= 0x02200000;
-+#define TCG_TARGET_HAS_tst_vec          1
++        insn |= 0x01100000;
+     }
- #define TCG_TARGET_DEFAULT_MO (0)
+     tcg_out32(s, insn);
- #define TCG_TARGET_NEED_LDST_LABELS
+ }
 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/arm/tcg-target.c.inc
 +++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
      case INDEX_op_cmp_vec:
          {
              TCGCond cond = args[3];
 +            ARMInsn insn;
 -            if (cond == TCG_COND_NE) {
 +            switch (cond) {
 +            case TCG_COND_NE:
                  if (const_args[2]) {
                      tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1);
                  } else {
                      tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2);
                      tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0);
                  }
 -            } else {
 -                ARMInsn insn;
 +                break;
 +            case TCG_COND_TSTNE:
 +            case TCG_COND_TSTEQ:
 +                if (const_args[2]) {
 +                    /* (x & 0) == 0 */
 +                    tcg_out_dupi_vec(s, type, MO_8, a0,
 +                                     -(cond == TCG_COND_TSTEQ));
 +                    break;
 +                }
 +                tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a2);
 +                if (cond == TCG_COND_TSTEQ) {
 +                    tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0);
 +                }
 +                break;
 +
 +            default:
                  if (const_args[2]) {
                      insn = vec_cmp0_insn[cond];
                      if (insn) {
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
                      tcg_debug_assert(insn != 0);
                  }
                  tcg_out_vreg3(s, insn, q, vece, a0, a1, a2);
 +                break;
              }
          }
          return;
 --
-.34.1
+.43.0

-[PULL 1/5] tcg: Introduce TCG_TARGET_HAS_tst_vec
+[PULL 3/4] include/exec: Introduce fpst alias in helper-head.h.inc
-Prelude to supporting TCG_COND_TST* in vector comparisons.
+This allows targets to declare that the helper requires a
 float_status pointer and instead of a generic void pointer.
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- include/tcg/tcg.h            | 1 +
+ include/exec/helper-head.h.inc | 3 +++
- tcg/aarch64/tcg-target.h     | 1 +
+file changed, 3 insertions(+)
  tcg/arm/tcg-target.h         | 1 +
  tcg/i386/tcg-target.h        | 1 +
  tcg/loongarch64/tcg-target.h | 1 +
  tcg/ppc/tcg-target.h         | 1 +
  tcg/s390x/tcg-target.h       | 1 +
 files changed, 7 insertions(+)
-diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
+diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc
 index XXXXXXX..XXXXXXX 100644
---- a/include/tcg/tcg.h
+--- a/include/exec/helper-head.h.inc
-+++ b/include/tcg/tcg.h
++++ b/include/exec/helper-head.h.inc
-@@ -XXX,XX +XXX,XX @@ typedef uint64_t TCGRegSet;
+@@ -XXX,XX +XXX,XX @@
- #define TCG_TARGET_HAS_minmax_vec       0
+ #define dh_alias_ptr ptr
- #define TCG_TARGET_HAS_bitsel_vec       0
+ #define dh_alias_cptr ptr
- #define TCG_TARGET_HAS_cmpsel_vec       0
+ #define dh_alias_env ptr
-+#define TCG_TARGET_HAS_tst_vec          0
++#define dh_alias_fpst ptr
- #else
+ #define dh_alias_void void
- #define TCG_TARGET_MAYBE_vec            1
+ #define dh_alias_noreturn noreturn
- #endif
+ #define dh_alias(t) glue(dh_alias_, t)
-diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
+@@ -XXX,XX +XXX,XX @@
-index XXXXXXX..XXXXXXX 100644
+ #define dh_ctype_ptr void *
---- a/tcg/aarch64/tcg-target.h
+ #define dh_ctype_cptr const void *
-+++ b/tcg/aarch64/tcg-target.h
+ #define dh_ctype_env CPUArchState *
-@@ -XXX,XX +XXX,XX @@ typedef enum {
++#define dh_ctype_fpst float_status *
- #define TCG_TARGET_HAS_minmax_vec       1
+ #define dh_ctype_void void
- #define TCG_TARGET_HAS_bitsel_vec       1
+ #define dh_ctype_noreturn G_NORETURN void
- #define TCG_TARGET_HAS_cmpsel_vec       0
+ #define dh_ctype(t) dh_ctype_##t
-+#define TCG_TARGET_HAS_tst_vec          0
+@@ -XXX,XX +XXX,XX @@
+ #define dh_typecode_f64 dh_typecode_i64
- #define TCG_TARGET_DEFAULT_MO (0)
+ #define dh_typecode_cptr dh_typecode_ptr
- #define TCG_TARGET_NEED_LDST_LABELS
+ #define dh_typecode_env dh_typecode_ptr
-diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
++#define dh_typecode_fpst dh_typecode_ptr
-index XXXXXXX..XXXXXXX 100644
+ #define dh_typecode(t) dh_typecode_##t
---- a/tcg/arm/tcg-target.h
-+++ b/tcg/arm/tcg-target.h
+ #define dh_callflag_i32  0
@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
  #define TCG_TARGET_HAS_minmax_vec       1
  #define TCG_TARGET_HAS_bitsel_vec       1
  #define TCG_TARGET_HAS_cmpsel_vec       0
 +#define TCG_TARGET_HAS_tst_vec          0
  #define TCG_TARGET_DEFAULT_MO (0)
  #define TCG_TARGET_NEED_LDST_LABELS
 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/i386/tcg-target.h
 +++ b/tcg/i386/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
  #define TCG_TARGET_HAS_minmax_vec       1
  #define TCG_TARGET_HAS_bitsel_vec       have_avx512vl
  #define TCG_TARGET_HAS_cmpsel_vec       -1
 +#define TCG_TARGET_HAS_tst_vec          0
  #define TCG_TARGET_deposit_i32_valid(ofs, len) \
      (((ofs) == 0 && ((len) == 8 || (len) == 16)) || \
 diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/loongarch64/tcg-target.h
 +++ b/tcg/loongarch64/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
  #define TCG_TARGET_HAS_minmax_vec       1
  #define TCG_TARGET_HAS_bitsel_vec       1
  #define TCG_TARGET_HAS_cmpsel_vec       0
 +#define TCG_TARGET_HAS_tst_vec          0
  #define TCG_TARGET_DEFAULT_MO (0)
 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/ppc/tcg-target.h
 +++ b/tcg/ppc/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
  #define TCG_TARGET_HAS_minmax_vec       1
  #define TCG_TARGET_HAS_bitsel_vec       have_vsx
  #define TCG_TARGET_HAS_cmpsel_vec       0
 +#define TCG_TARGET_HAS_tst_vec          0
  #define TCG_TARGET_DEFAULT_MO (0)
  #define TCG_TARGET_NEED_LDST_LABELS
 diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/s390x/tcg-target.h
 +++ b/tcg/s390x/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities[3];
  #define TCG_TARGET_HAS_minmax_vec     1
  #define TCG_TARGET_HAS_bitsel_vec     1
  #define TCG_TARGET_HAS_cmpsel_vec     0
 +#define TCG_TARGET_HAS_tst_vec        0
  /* used for function call generation */
  #define TCG_TARGET_STACK_ALIGN        8
 --
-.34.1
+.43.0

-[PULL 2/5] tcg: Expand TCG_COND_TST* if not TCG_TARGET_HAS_tst_vec
+Deleted patch
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/tcg-op-vec.c | 18 ++++++++++++++++++
-file changed, 18 insertions(+)
-diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg-op-vec.c
-+++ b/tcg/tcg-op-vec.c
-@@ -XXX,XX +XXX,XX @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece,
-     TCGTemp *rt = tcgv_vec_temp(r);
-     TCGTemp *at = tcgv_vec_temp(a);
-     TCGTemp *bt = tcgv_vec_temp(b);
-+    TCGTemp *tt = NULL;
-     TCGArg ri = temp_arg(rt);
-     TCGArg ai = temp_arg(at);
-     TCGArg bi = temp_arg(bt);
-+    TCGArg ti;
-     TCGType type = rt->base_type;
-     int can;
-@@ -XXX,XX +XXX,XX @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece,
-     tcg_debug_assert(bt->base_type >= type);
-     tcg_assert_listed_vecop(INDEX_op_cmp_vec);
-     can = tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece);
-+
-+    if (!TCG_TARGET_HAS_tst_vec && is_tst_cond(cond)) {
-+        tt = tcg_temp_new_internal(type, TEMP_EBB);
-+        ti = temp_arg(tt);
-+        vec_gen_3(INDEX_op_and_vec, type, 0, ti, ai, bi);
-+        at = tt;
-+        ai = ti;
-+        bt = tcg_constant_internal(type, 0);
-+        bi = temp_arg(bt);
-+        cond = tcg_tst_eqne_cond(cond);
-+    }
-+
-     if (can > 0) {
-         vec_gen_4(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond);
-     } else {
-@@ -XXX,XX +XXX,XX @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece,
-         tcg_expand_vec_op(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond);
-         tcg_swap_vecop_list(hold_list);
-     }
-+
-+    if (tt) {
-+        tcg_temp_free_internal(tt);
-+    }
- }
- static bool do_op3(unsigned vece, TCGv_vec r, TCGv_vec a,
---
-.34.1

-[PULL 3/5] tcg/aarch64: Support TCG_TARGET_HAS_tst_vec
+[PULL 4/4] target/sparc: Use memcpy() and remove memcpy32()
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Rather than manually copying each register, use
+the libc memcpy(), which is well optimized nowadays.
+Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
+Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-ID: <20241205205418.67613-1-philmd@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/aarch64/tcg-target.h     |  2 +-
+ target/sparc/win_helper.c | 26 ++++++++------------------
- tcg/aarch64/tcg-target.c.inc | 26 ++++++++++++++++++++++++--
+file changed, 8 insertions(+), 18 deletions(-)
 files changed, 25 insertions(+), 3 deletions(-)
-diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
+diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/aarch64/tcg-target.h
+--- a/target/sparc/win_helper.c
-+++ b/tcg/aarch64/tcg-target.h
++++ b/target/sparc/win_helper.c
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@
- #define TCG_TARGET_HAS_minmax_vec       1
+ #include "exec/helper-proto.h"
- #define TCG_TARGET_HAS_bitsel_vec       1
+ #include "trace.h"
- #define TCG_TARGET_HAS_cmpsel_vec       0
--#define TCG_TARGET_HAS_tst_vec          0
+-static inline void memcpy32(target_ulong *dst, const target_ulong *src)
-+#define TCG_TARGET_HAS_tst_vec          1
+-{
+-    dst[0] = src[0];
- #define TCG_TARGET_DEFAULT_MO (0)
+-    dst[1] = src[1];
- #define TCG_TARGET_NEED_LDST_LABELS
+-    dst[2] = src[2];
-diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
+-    dst[3] = src[3];
-index XXXXXXX..XXXXXXX 100644
+-    dst[4] = src[4];
---- a/tcg/aarch64/tcg-target.c.inc
+-    dst[5] = src[5];
-+++ b/tcg/aarch64/tcg-target.c.inc
+-    dst[6] = src[6];
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+-    dst[7] = src[7];
-             TCGCond cond = args[3];
+-}
-             AArch64Insn insn;
+-
+ void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
--            if (cond == TCG_COND_NE) {
+ {
-+            switch (cond) {
+     /* put the modified wrap registers at their proper location */
-+            case TCG_COND_NE:
+     if (env->cwp == env->nwindows - 1) {
-                 if (const_args[2]) {
+-        memcpy32(env->regbase, env->regbase + env->nwindows * 16);
-                     if (is_scalar) {
++        memcpy(env->regbase, env->regbase + env->nwindows * 16,
-                         tcg_out_insn(s, 3611, CMTST, vece, a0, a1, a1);
++               sizeof(env->gregs));
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+     }
-                     }
+     env->cwp = new_cwp;
-                     tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0);
-                 }
+     /* put the wrap registers at their temporary location */
--            } else {
+     if (new_cwp == env->nwindows - 1) {
-+                break;
+-        memcpy32(env->regbase + env->nwindows * 16, env->regbase);
-+
++        memcpy(env->regbase + env->nwindows * 16, env->regbase,
-+            case TCG_COND_TSTNE:
++               sizeof(env->gregs));
-+            case TCG_COND_TSTEQ:
+     }
-+                if (const_args[2]) {
+     env->regwptr = env->regbase + (new_cwp * 16);
-+                    /* (x & 0) == 0 */
+ }
-+                    tcg_out_dupi_vec(s, type, MO_8, a0,
+@@ -XXX,XX +XXX,XX @@ void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl)
-+                                     -(cond == TCG_COND_TSTEQ));
+     dst = get_gl_gregset(env, env->gl);
-+                    break;
-+                }
+     if (src != dst) {
-+                if (is_scalar) {
+-        memcpy32(dst, env->gregs);
-+                    tcg_out_insn(s, 3611, CMTST, vece, a0, a1, a2);
+-        memcpy32(env->gregs, src);
-+                } else {
++        memcpy(dst, env->gregs, sizeof(env->gregs));
-+                    tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a2);
++        memcpy(env->gregs, src, sizeof(env->gregs));
-+                }
+     }
-+                if (cond == TCG_COND_TSTEQ) {
+ }
-+                    tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0);
-+                }
+@@ -XXX,XX +XXX,XX @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
-+                break;
+         /* Switch global register bank */
-+
+         src = get_gregset(env, new_pstate_regs);
-+            default:
+         dst = get_gregset(env, pstate_regs);
-                 if (const_args[2]) {
+-        memcpy32(dst, env->gregs);
-                     if (is_scalar) {
+-        memcpy32(env->gregs, src);
-                         insn = cmp0_scalar_insn[cond];
++        memcpy(dst, env->gregs, sizeof(env->gregs));
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
++        memcpy(env->gregs, src, sizeof(env->gregs));
-                     }
+     } else {
-                     tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2);
+         trace_win_helper_no_switch_pstate(new_pstate_regs);
-                 }
+     }
 +                break;
              }
          }
          break;
 --
-.34.1
+.43.0

The following changes since commit 7e1c0047015ffbd408e1aa4a5ec1abe4751dbf7e:

Merge tag 'migration-20240522-pull-request' of https://gitlab.com/farosas/qemu into staging (2024-05-22 15:32:25 -0700)

are available in the Git repository at:

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240523

for you to fetch changes up to bfd43cccab9fb77b8405ca556fc2f2ed3b2920a3:

accel/tcg: Init tb size and icount before plugin_gen_tb_end (2024-05-22 19:05:26 -0700)

----------------------------------------------------------------
tcg: Introduce TCG_TARGET_HAS_tst_vec
accel/tcg: Init tb size and icount before plugin_gen_tb_end

----------------------------------------------------------------
Richard Henderson (5):
      tcg: Introduce TCG_TARGET_HAS_tst_vec
      tcg: Expand TCG_COND_TST* if not TCG_TARGET_HAS_tst_vec
      tcg/aarch64: Support TCG_TARGET_HAS_tst_vec
      tcg/arm: Support TCG_TARGET_HAS_tst_vec
      accel/tcg: Init tb size and icount before plugin_gen_tb_end

Prelude to supporting TCG_COND_TST* in vector comparisons.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/tcg/tcg.h            | 1 +
 tcg/aarch64/tcg-target.h     | 1 +
 tcg/arm/tcg-target.h         | 1 +
 tcg/i386/tcg-target.h        | 1 +
 tcg/loongarch64/tcg-target.h | 1 +
 tcg/ppc/tcg-target.h         | 1 +
 tcg/s390x/tcg-target.h       | 1 +
 7 files changed, 7 insertions(+)

diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -XXX,XX +XXX,XX @@ typedef uint64_t TCGRegSet;
 #define TCG_TARGET_HAS_minmax_vec       0
 #define TCG_TARGET_HAS_bitsel_vec       0
 #define TCG_TARGET_HAS_cmpsel_vec       0
+#define TCG_TARGET_HAS_tst_vec          0
 #else
 #define TCG_TARGET_MAYBE_vec            1
 #endif
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
 #define TCG_TARGET_HAS_minmax_vec       1
 #define TCG_TARGET_HAS_bitsel_vec       1
 #define TCG_TARGET_HAS_cmpsel_vec       0
+#define TCG_TARGET_HAS_tst_vec          0
 
 #define TCG_TARGET_DEFAULT_MO (0)
 #define TCG_TARGET_NEED_LDST_LABELS
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
 #define TCG_TARGET_HAS_minmax_vec       1
 #define TCG_TARGET_HAS_bitsel_vec       1
 #define TCG_TARGET_HAS_cmpsel_vec       0
+#define TCG_TARGET_HAS_tst_vec          0
 
 #define TCG_TARGET_DEFAULT_MO (0)
 #define TCG_TARGET_NEED_LDST_LABELS
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
 #define TCG_TARGET_HAS_minmax_vec       1
 #define TCG_TARGET_HAS_bitsel_vec       have_avx512vl
 #define TCG_TARGET_HAS_cmpsel_vec       -1
+#define TCG_TARGET_HAS_tst_vec          0
 
 #define TCG_TARGET_deposit_i32_valid(ofs, len) \
     (((ofs) == 0 && ((len) == 8 || (len) == 16)) || \
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
 #define TCG_TARGET_HAS_minmax_vec       1
 #define TCG_TARGET_HAS_bitsel_vec       1
 #define TCG_TARGET_HAS_cmpsel_vec       0
+#define TCG_TARGET_HAS_tst_vec          0
 
 #define TCG_TARGET_DEFAULT_MO (0)
 
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
 #define TCG_TARGET_HAS_minmax_vec       1
 #define TCG_TARGET_HAS_bitsel_vec       have_vsx
 #define TCG_TARGET_HAS_cmpsel_vec       0
+#define TCG_TARGET_HAS_tst_vec          0
 
 #define TCG_TARGET_DEFAULT_MO (0)
 #define TCG_TARGET_NEED_LDST_LABELS
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/s390x/tcg-target.h
+++ b/tcg/s390x/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities[3];
 #define TCG_TARGET_HAS_minmax_vec     1
 #define TCG_TARGET_HAS_bitsel_vec     1
 #define TCG_TARGET_HAS_cmpsel_vec     0
+#define TCG_TARGET_HAS_tst_vec        0
 
 /* used for function call generation */
 #define TCG_TARGET_STACK_ALIGN		8
-- 
2.34.1

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tcg-op-vec.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -XXX,XX +XXX,XX @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece,
     TCGTemp *rt = tcgv_vec_temp(r);
     TCGTemp *at = tcgv_vec_temp(a);
     TCGTemp *bt = tcgv_vec_temp(b);
+    TCGTemp *tt = NULL;
     TCGArg ri = temp_arg(rt);
     TCGArg ai = temp_arg(at);
     TCGArg bi = temp_arg(bt);
+    TCGArg ti;
     TCGType type = rt->base_type;
     int can;
 
@@ -XXX,XX +XXX,XX @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece,
     tcg_debug_assert(bt->base_type >= type);
     tcg_assert_listed_vecop(INDEX_op_cmp_vec);
     can = tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece);
+
+    if (!TCG_TARGET_HAS_tst_vec && is_tst_cond(cond)) {
+        tt = tcg_temp_new_internal(type, TEMP_EBB);
+        ti = temp_arg(tt);
+        vec_gen_3(INDEX_op_and_vec, type, 0, ti, ai, bi);
+        at = tt;
+        ai = ti;
+        bt = tcg_constant_internal(type, 0);
+        bi = temp_arg(bt);
+        cond = tcg_tst_eqne_cond(cond);
+    }
+
     if (can > 0) {
         vec_gen_4(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond);
     } else {
@@ -XXX,XX +XXX,XX @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece,
         tcg_expand_vec_op(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond);
         tcg_swap_vecop_list(hold_list);
     }
+
+    if (tt) {
+        tcg_temp_free_internal(tt);
+    }
 }
 
 static bool do_op3(unsigned vece, TCGv_vec r, TCGv_vec a,
-- 
2.34.1

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/aarch64/tcg-target.h     |  2 +-
 tcg/aarch64/tcg-target.c.inc | 26 ++++++++++++++++++++++++--
 2 files changed, 25 insertions(+), 3 deletions(-)

diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
 #define TCG_TARGET_HAS_minmax_vec       1
 #define TCG_TARGET_HAS_bitsel_vec       1
 #define TCG_TARGET_HAS_cmpsel_vec       0
-#define TCG_TARGET_HAS_tst_vec          0
+#define TCG_TARGET_HAS_tst_vec          1
 
 #define TCG_TARGET_DEFAULT_MO (0)
 #define TCG_TARGET_NEED_LDST_LABELS
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
             TCGCond cond = args[3];
             AArch64Insn insn;
 
-            if (cond == TCG_COND_NE) {
+            switch (cond) {
+            case TCG_COND_NE:
                 if (const_args[2]) {
                     if (is_scalar) {
                         tcg_out_insn(s, 3611, CMTST, vece, a0, a1, a1);
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
                     }
                     tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0);
                 }
-            } else {
+                break;
+
+            case TCG_COND_TSTNE:
+            case TCG_COND_TSTEQ:
+                if (const_args[2]) {
+                    /* (x & 0) == 0 */
+                    tcg_out_dupi_vec(s, type, MO_8, a0,
+                                     -(cond == TCG_COND_TSTEQ));
+                    break;
+                }
+                if (is_scalar) {
+                    tcg_out_insn(s, 3611, CMTST, vece, a0, a1, a2);
+                } else {
+                    tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a2);
+                }
+                if (cond == TCG_COND_TSTEQ) {
+                    tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0);
+                }
+                break;
+
+            default:
                 if (const_args[2]) {
                     if (is_scalar) {
                         insn = cmp0_scalar_insn[cond];
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
                     }
                     tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2);
                 }
+                break;
             }
         }
         break;
-- 
2.34.1

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.h     |  2 +-
 tcg/arm/tcg-target.c.inc | 23 ++++++++++++++++++++---
 2 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
 #define TCG_TARGET_HAS_minmax_vec       1
 #define TCG_TARGET_HAS_bitsel_vec       1
 #define TCG_TARGET_HAS_cmpsel_vec       0
-#define TCG_TARGET_HAS_tst_vec          0
+#define TCG_TARGET_HAS_tst_vec          1
 
 #define TCG_TARGET_DEFAULT_MO (0)
 #define TCG_TARGET_NEED_LDST_LABELS
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_cmp_vec:
         {
             TCGCond cond = args[3];
+            ARMInsn insn;
 
-            if (cond == TCG_COND_NE) {
+            switch (cond) {
+            case TCG_COND_NE:
                 if (const_args[2]) {
                     tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1);
                 } else {
                     tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2);
                     tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0);
                 }
-            } else {
-                ARMInsn insn;
+                break;
 
+            case TCG_COND_TSTNE:
+            case TCG_COND_TSTEQ:
+                if (const_args[2]) {
+                    /* (x & 0) == 0 */
+                    tcg_out_dupi_vec(s, type, MO_8, a0,
+                                     -(cond == TCG_COND_TSTEQ));
+                    break;
+                }
+                tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a2);
+                if (cond == TCG_COND_TSTEQ) {
+                    tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0);
+                }
+                break;
+
+            default:
                 if (const_args[2]) {
                     insn = vec_cmp0_insn[cond];
                     if (insn) {
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
                     tcg_debug_assert(insn != 0);
                 }
                 tcg_out_vreg3(s, insn, q, vece, a0, a1, a2);
+                break;
             }
         }
         return;
-- 
2.34.1

When passing disassembly data to plugin callbacks,
translator_st_len relies on db->tb->size having been set.

Fixes: 4c833c60e047 ("disas: Use translator_st to get disassembly data")
Reported-by: Bernhard Beschow <shentey@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
 accel/tcg/translator.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -XXX,XX +XXX,XX @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns,
     set_can_do_io(db, true);
     tcg_ctx->emit_before_op = NULL;
 
+    /* May be used by disas_log or plugin callbacks. */
+    tb->size = db->pc_next - db->pc_first;
+    tb->icount = db->num_insns;
+
     if (plugin_enabled) {
         plugin_gen_tb_end(cpu, db->num_insns);
     }
 
-    /* The disas_log hook may use these values rather than recompute.  */
-    tb->size = db->pc_next - db->pc_first;
-    tb->icount = db->num_insns;
-
     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
         && qemu_log_in_addr_range(db->pc_first)) {
         FILE *logfile = qemu_log_trylock();
-- 
2.34.1

Pretty small still, but there are two patches that ought
to get backported to stable, so no point in delaying.

The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:

Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)

are available in the Git repository at:

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241212

for you to fetch changes up to 7ac87b14a92234b6a89b701b4043ad6cf8bdcccf:

target/sparc: Use memcpy() and remove memcpy32() (2024-12-12 14:28:38 -0600)

----------------------------------------------------------------
tcg: Reset free_temps before tcg_optimize
tcg/riscv: Fix StoreStore barrier generation
include/exec: Introduce fpst alias in helper-head.h.inc
target/sparc: Use memcpy() and remove memcpy32()

----------------------------------------------------------------
Philippe Mathieu-Daudé (1):
      target/sparc: Use memcpy() and remove memcpy32()

Richard Henderson (2):
      tcg: Reset free_temps before tcg_optimize
      include/exec: Introduce fpst alias in helper-head.h.inc

Roman Artemev (1):
      tcg/riscv: Fix StoreStore barrier generation

When allocating new temps during tcg_optmize, do not re-use
any EBB temps that were used within the TB.  We do not have
any idea what span of the TB in which the temp was live.

Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize,
as well as replacing the equivalent in plugin_gen_inject and
tcg_func_start.

Cc: qemu-stable@nongnu.org
Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711
Reported-by: wannacu <wannacu2049@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/tcg/tcg-temp-internal.h | 6 ++++++
 accel/tcg/plugin-gen.c          | 2 +-
 tcg/tcg.c                       | 5 ++++-
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-internal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg-temp-internal.h
+++ b/include/tcg/tcg-temp-internal.h
@@ -XXX,XX +XXX,XX @@ TCGv_i64 tcg_temp_ebb_new_i64(void);
 TCGv_ptr tcg_temp_ebb_new_ptr(void);
 TCGv_i128 tcg_temp_ebb_new_i128(void);
 
+/* Forget all freed EBB temps, so that new allocations produce new temps. */
+static inline void tcg_temp_ebb_reset_freed(TCGContext *s)
+{
+    memset(s->free_temps, 0, sizeof(s->free_temps));
+}
+
 #endif /* TCG_TEMP_FREE_H */
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/plugin-gen.c
+++ b/accel/tcg/plugin-gen.c
@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
      * that might be live within the existing opcode stream.
      * The simplest solution is to release them all and create new.
      */
-    memset(tcg_ctx->free_temps, 0, sizeof(tcg_ctx->free_temps));
+    tcg_temp_ebb_reset_freed(tcg_ctx);
 
     QTAILQ_FOREACH_SAFE(op, &tcg_ctx->ops, link, next) {
         switch (op->opc) {
diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
     s->nb_temps = s->nb_globals;
 
     /* No temps have been previously allocated for size or locality.  */
-    memset(s->free_temps, 0, sizeof(s->free_temps));
+    tcg_temp_ebb_reset_freed(s);
 
     /* No constant temps have been previously allocated. */
     for (int i = 0; i < TCG_TYPE_COUNT; ++i) {
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
     }
 #endif
 
+    /* Do not reuse any EBB that may be allocated within the TB. */
+    tcg_temp_ebb_reset_freed(s);
+
     tcg_optimize(s);
 
     reachable_code_pass(s);
-- 
2.43.0

From: Roman Artemev <roman.artemev@syntacore.com>

On RISC-V to StoreStore barrier corresponds
`fence w, w` not `fence r, r`

Cc: qemu-stable@nongnu.org
Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/riscv/tcg-target.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
         insn |= 0x02100000;
     }
     if (a0 & TCG_MO_ST_ST) {
-        insn |= 0x02200000;
+        insn |= 0x01100000;
     }
     tcg_out32(s, insn);
 }
-- 
2.43.0

This allows targets to declare that the helper requires a
float_status pointer and instead of a generic void pointer.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/helper-head.h.inc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/exec/helper-head.h.inc b/include/exec/helper-head.h.inc
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/helper-head.h.inc
+++ b/include/exec/helper-head.h.inc
@@ -XXX,XX +XXX,XX @@
 #define dh_alias_ptr ptr
 #define dh_alias_cptr ptr
 #define dh_alias_env ptr
+#define dh_alias_fpst ptr
 #define dh_alias_void void
 #define dh_alias_noreturn noreturn
 #define dh_alias(t) glue(dh_alias_, t)
@@ -XXX,XX +XXX,XX @@
 #define dh_ctype_ptr void *
 #define dh_ctype_cptr const void *
 #define dh_ctype_env CPUArchState *
+#define dh_ctype_fpst float_status *
 #define dh_ctype_void void
 #define dh_ctype_noreturn G_NORETURN void
 #define dh_ctype(t) dh_ctype_##t
@@ -XXX,XX +XXX,XX @@
 #define dh_typecode_f64 dh_typecode_i64
 #define dh_typecode_cptr dh_typecode_ptr
 #define dh_typecode_env dh_typecode_ptr
+#define dh_typecode_fpst dh_typecode_ptr
 #define dh_typecode(t) dh_typecode_##t
 
 #define dh_callflag_i32  0
-- 
2.43.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Rather than manually copying each register, use
the libc memcpy(), which is well optimized nowadays.

Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20241205205418.67613-1-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/win_helper.c | 26 ++++++++------------------
 1 file changed, 8 insertions(+), 18 deletions(-)

diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/sparc/win_helper.c
+++ b/target/sparc/win_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-proto.h"
 #include "trace.h"
 
-static inline void memcpy32(target_ulong *dst, const target_ulong *src)
-{
-    dst[0] = src[0];
-    dst[1] = src[1];
-    dst[2] = src[2];
-    dst[3] = src[3];
-    dst[4] = src[4];
-    dst[5] = src[5];
-    dst[6] = src[6];
-    dst[7] = src[7];
-}
-
 void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
 {
     /* put the modified wrap registers at their proper location */
     if (env->cwp == env->nwindows - 1) {
-        memcpy32(env->regbase, env->regbase + env->nwindows * 16);
+        memcpy(env->regbase, env->regbase + env->nwindows * 16,
+               sizeof(env->gregs));
     }
     env->cwp = new_cwp;
 
     /* put the wrap registers at their temporary location */
     if (new_cwp == env->nwindows - 1) {
-        memcpy32(env->regbase + env->nwindows * 16, env->regbase);
+        memcpy(env->regbase + env->nwindows * 16, env->regbase,
+               sizeof(env->gregs));
     }
     env->regwptr = env->regbase + (new_cwp * 16);
 }
@@ -XXX,XX +XXX,XX @@ void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl)
     dst = get_gl_gregset(env, env->gl);
 
     if (src != dst) {
-        memcpy32(dst, env->gregs);
-        memcpy32(env->gregs, src);
+        memcpy(dst, env->gregs, sizeof(env->gregs));
+        memcpy(env->gregs, src, sizeof(env->gregs));
     }
 }
 
@@ -XXX,XX +XXX,XX @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
         /* Switch global register bank */
         src = get_gregset(env, new_pstate_regs);
         dst = get_gregset(env, pstate_regs);
-        memcpy32(dst, env->gregs);
-        memcpy32(env->gregs, src);
+        memcpy(dst, env->gregs, sizeof(env->gregs));
+        memcpy(env->gregs, src, sizeof(env->gregs));
     } else {
         trace_win_helper_no_switch_pstate(new_pstate_regs);
     }
-- 
2.43.0