target/riscv: Support Zabha extension

[PATCH 2/6] target/riscv: Add AMO instructions for Zabha

Posted by LIU Zhiwei 6 months ago

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
 target/riscv/cpu_cfg.h                      |   1 +
 target/riscv/insn32.decode                  |  20 +++
 target/riscv/insn_trans/trans_rvzabha.c.inc | 131 ++++++++++++++++++++
 target/riscv/translate.c                    |   4 +-
 4 files changed, 155 insertions(+), 1 deletion(-)
 create mode 100644 target/riscv/insn_trans/trans_rvzabha.c.inc

diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index b327b144d7..f241b0b173 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -84,6 +84,7 @@ struct RISCVCPUConfig {
     bool ext_zaamo;
     bool ext_zacas;
     bool ext_zama16b;
+    bool ext_zabha;
     bool ext_zalrsc;
     bool ext_zawrs;
     bool ext_zfa;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 972a1e8fd1..8a4801d442 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1021,3 +1021,23 @@ amocas_q    00101 . . ..... ..... 100 ..... 0101111 @atom_st
 # *** Zimop may-be-operation extension ***
 mop_r_n     1 . 00 .. 0111 .. ..... 100 ..... 0111011 @mop5
 mop_rr_n    1 . 00 .. 1 ..... ..... 100 ..... 0111011 @mop3
+
+# *** Zabhb Standard Extension ***
+amoswap_b  00001 . . ..... ..... 000 ..... 0101111 @atom_st
+amoadd_b   00000 . . ..... ..... 000 ..... 0101111 @atom_st
+amoxor_b   00100 . . ..... ..... 000 ..... 0101111 @atom_st
+amoand_b   01100 . . ..... ..... 000 ..... 0101111 @atom_st
+amoor_b    01000 . . ..... ..... 000 ..... 0101111 @atom_st
+amomin_b   10000 . . ..... ..... 000 ..... 0101111 @atom_st
+amomax_b   10100 . . ..... ..... 000 ..... 0101111 @atom_st
+amominu_b  11000 . . ..... ..... 000 ..... 0101111 @atom_st
+amomaxu_b  11100 . . ..... ..... 000 ..... 0101111 @atom_st
+amoswap_h  00001 . . ..... ..... 001 ..... 0101111 @atom_st
+amoadd_h   00000 . . ..... ..... 001 ..... 0101111 @atom_st
+amoxor_h   00100 . . ..... ..... 001 ..... 0101111 @atom_st
+amoand_h   01100 . . ..... ..... 001 ..... 0101111 @atom_st
+amoor_h    01000 . . ..... ..... 001 ..... 0101111 @atom_st
+amomin_h   10000 . . ..... ..... 001 ..... 0101111 @atom_st
+amomax_h   10100 . . ..... ..... 001 ..... 0101111 @atom_st
+amominu_h  11000 . . ..... ..... 001 ..... 0101111 @atom_st
+amomaxu_h  11100 . . ..... ..... 001 ..... 0101111 @atom_st
diff --git a/target/riscv/insn_trans/trans_rvzabha.c.inc b/target/riscv/insn_trans/trans_rvzabha.c.inc
new file mode 100644
index 0000000000..9093a1cfc1
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvzabha.c.inc
@@ -0,0 +1,131 @@
+/*
+ * RISC-V translation routines for the Zabha Standard Extension.
+ *
+ * Copyright (c) 2024 Alibaba Group
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_ZABHA(ctx) do {           \
+    if (!ctx->cfg_ptr->ext_zabha) {       \
+        return false;                     \
+    }                                     \
+} while (0)
+
+static bool trans_amoswap_b(DisasContext *ctx, arg_amoswap_b *a)
+{
+    REQUIRE_ZABHA(ctx);
+    return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_SB);
+}
+
+static bool trans_amoadd_b(DisasContext *ctx, arg_amoadd_b *a)
+{
+    REQUIRE_ZABHA(ctx);
+    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_SB);
+}
+
+static bool trans_amoxor_b(DisasContext *ctx, arg_amoxor_b *a)
+{
+    REQUIRE_ZABHA(ctx);
+    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_SB);
+}
+
+static bool trans_amoand_b(DisasContext *ctx, arg_amoand_b *a)
+{
+    REQUIRE_ZABHA(ctx);
+    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_SB);
+}
+
+static bool trans_amoor_b(DisasContext *ctx, arg_amoor_b *a)
+{
+    REQUIRE_ZABHA(ctx);
+    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_SB);
+}
+
+static bool trans_amomin_b(DisasContext *ctx, arg_amomin_b *a)
+{
+    REQUIRE_ZABHA(ctx);
+    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_SB);
+}
+
+static bool trans_amomax_b(DisasContext *ctx, arg_amomax_b *a)
+{
+    REQUIRE_ZABHA(ctx);
+    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_SB);
+}
+
+static bool trans_amominu_b(DisasContext *ctx, arg_amominu_b *a)
+{
+    REQUIRE_ZABHA(ctx);
+    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_SB);
+}
+
+static bool trans_amomaxu_b(DisasContext *ctx, arg_amomaxu_b *a)
+{
+    REQUIRE_ZABHA(ctx);
+    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_SB);
+}
+
+static bool trans_amoswap_h(DisasContext *ctx, arg_amoswap_h *a)
+{
+    REQUIRE_ZABHA(ctx);
+    return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_TESW);
+}
+
+static bool trans_amoadd_h(DisasContext *ctx, arg_amoadd_h *a)
+{
+    REQUIRE_ZABHA(ctx);
+    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_TESW);
+}
+
+static bool trans_amoxor_h(DisasContext *ctx, arg_amoxor_h *a)
+{
+    REQUIRE_ZABHA(ctx);
+    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_TESW);
+}
+
+static bool trans_amoand_h(DisasContext *ctx, arg_amoand_h *a)
+{
+    REQUIRE_ZABHA(ctx);
+    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_TESW);
+}
+
+static bool trans_amoor_h(DisasContext *ctx, arg_amoor_h *a)
+{
+    REQUIRE_ZABHA(ctx);
+    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_TESW);
+}
+
+static bool trans_amomin_h(DisasContext *ctx, arg_amomin_h *a)
+{
+    REQUIRE_ZABHA(ctx);
+    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_TESW);
+}
+
+static bool trans_amomax_h(DisasContext *ctx, arg_amomax_h *a)
+{
+    REQUIRE_ZABHA(ctx);
+    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_TESW);
+}
+
+static bool trans_amominu_h(DisasContext *ctx, arg_amominu_h *a)
+{
+    REQUIRE_ZABHA(ctx);
+    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_TESW);
+}
+
+static bool trans_amomaxu_h(DisasContext *ctx, arg_amomaxu_h *a)
+{
+    REQUIRE_ZABHA(ctx);
+    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_TESW);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b160bcbfe0..f597542f1c 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1081,8 +1081,9 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
 {
     TCGv dest = dest_gpr(ctx, a->rd);
     TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+    MemOp size = mop & MO_SIZE;
 
-    if (ctx->cfg_ptr->ext_zama16b) {
+    if (ctx->cfg_ptr->ext_zama16b && size >= MO_32) {
         mop |= MO_ATOM_WITHIN16;
     } else {
         mop |= MO_ALIGN;
@@ -1116,6 +1117,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
 #include "insn_trans/trans_rvb.c.inc"
 #include "insn_trans/trans_rvzicond.c.inc"
 #include "insn_trans/trans_rvzacas.c.inc"
+#include "insn_trans/trans_rvzabha.c.inc"
 #include "insn_trans/trans_rvzawrs.c.inc"
 #include "insn_trans/trans_rvzicbo.c.inc"
 #include "insn_trans/trans_rvzimop.c.inc"
-- 
2.25.1

Re: [PATCH 2/6] target/riscv: Add AMO instructions for Zabha

Posted by Alistair Francis 5 months, 3 weeks ago

On Thu, May 23, 2024 at 10:44 PM LIU Zhiwei
<zhiwei_liu@linux.alibaba.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu_cfg.h                      |   1 +
>  target/riscv/insn32.decode                  |  20 +++
>  target/riscv/insn_trans/trans_rvzabha.c.inc | 131 ++++++++++++++++++++
>  target/riscv/translate.c                    |   4 +-
>  4 files changed, 155 insertions(+), 1 deletion(-)
>  create mode 100644 target/riscv/insn_trans/trans_rvzabha.c.inc
>
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index b327b144d7..f241b0b173 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -84,6 +84,7 @@ struct RISCVCPUConfig {
>      bool ext_zaamo;
>      bool ext_zacas;
>      bool ext_zama16b;
> +    bool ext_zabha;
>      bool ext_zalrsc;
>      bool ext_zawrs;
>      bool ext_zfa;
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 972a1e8fd1..8a4801d442 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -1021,3 +1021,23 @@ amocas_q    00101 . . ..... ..... 100 ..... 0101111 @atom_st
>  # *** Zimop may-be-operation extension ***
>  mop_r_n     1 . 00 .. 0111 .. ..... 100 ..... 0111011 @mop5
>  mop_rr_n    1 . 00 .. 1 ..... ..... 100 ..... 0111011 @mop3
> +
> +# *** Zabhb Standard Extension ***
> +amoswap_b  00001 . . ..... ..... 000 ..... 0101111 @atom_st
> +amoadd_b   00000 . . ..... ..... 000 ..... 0101111 @atom_st
> +amoxor_b   00100 . . ..... ..... 000 ..... 0101111 @atom_st
> +amoand_b   01100 . . ..... ..... 000 ..... 0101111 @atom_st
> +amoor_b    01000 . . ..... ..... 000 ..... 0101111 @atom_st
> +amomin_b   10000 . . ..... ..... 000 ..... 0101111 @atom_st
> +amomax_b   10100 . . ..... ..... 000 ..... 0101111 @atom_st
> +amominu_b  11000 . . ..... ..... 000 ..... 0101111 @atom_st
> +amomaxu_b  11100 . . ..... ..... 000 ..... 0101111 @atom_st
> +amoswap_h  00001 . . ..... ..... 001 ..... 0101111 @atom_st
> +amoadd_h   00000 . . ..... ..... 001 ..... 0101111 @atom_st
> +amoxor_h   00100 . . ..... ..... 001 ..... 0101111 @atom_st
> +amoand_h   01100 . . ..... ..... 001 ..... 0101111 @atom_st
> +amoor_h    01000 . . ..... ..... 001 ..... 0101111 @atom_st
> +amomin_h   10000 . . ..... ..... 001 ..... 0101111 @atom_st
> +amomax_h   10100 . . ..... ..... 001 ..... 0101111 @atom_st
> +amominu_h  11000 . . ..... ..... 001 ..... 0101111 @atom_st
> +amomaxu_h  11100 . . ..... ..... 001 ..... 0101111 @atom_st
> diff --git a/target/riscv/insn_trans/trans_rvzabha.c.inc b/target/riscv/insn_trans/trans_rvzabha.c.inc
> new file mode 100644
> index 0000000000..9093a1cfc1
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_rvzabha.c.inc
> @@ -0,0 +1,131 @@
> +/*
> + * RISC-V translation routines for the Zabha Standard Extension.
> + *
> + * Copyright (c) 2024 Alibaba Group
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#define REQUIRE_ZABHA(ctx) do {           \
> +    if (!ctx->cfg_ptr->ext_zabha) {       \
> +        return false;                     \
> +    }                                     \
> +} while (0)
> +
> +static bool trans_amoswap_b(DisasContext *ctx, arg_amoswap_b *a)
> +{
> +    REQUIRE_ZABHA(ctx);
> +    return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_SB);
> +}
> +
> +static bool trans_amoadd_b(DisasContext *ctx, arg_amoadd_b *a)
> +{
> +    REQUIRE_ZABHA(ctx);
> +    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_SB);
> +}
> +
> +static bool trans_amoxor_b(DisasContext *ctx, arg_amoxor_b *a)
> +{
> +    REQUIRE_ZABHA(ctx);
> +    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_SB);
> +}
> +
> +static bool trans_amoand_b(DisasContext *ctx, arg_amoand_b *a)
> +{
> +    REQUIRE_ZABHA(ctx);
> +    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_SB);
> +}
> +
> +static bool trans_amoor_b(DisasContext *ctx, arg_amoor_b *a)
> +{
> +    REQUIRE_ZABHA(ctx);
> +    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_SB);
> +}
> +
> +static bool trans_amomin_b(DisasContext *ctx, arg_amomin_b *a)
> +{
> +    REQUIRE_ZABHA(ctx);
> +    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_SB);
> +}
> +
> +static bool trans_amomax_b(DisasContext *ctx, arg_amomax_b *a)
> +{
> +    REQUIRE_ZABHA(ctx);
> +    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_SB);
> +}
> +
> +static bool trans_amominu_b(DisasContext *ctx, arg_amominu_b *a)
> +{
> +    REQUIRE_ZABHA(ctx);
> +    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_SB);
> +}
> +
> +static bool trans_amomaxu_b(DisasContext *ctx, arg_amomaxu_b *a)
> +{
> +    REQUIRE_ZABHA(ctx);
> +    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_SB);
> +}
> +
> +static bool trans_amoswap_h(DisasContext *ctx, arg_amoswap_h *a)
> +{
> +    REQUIRE_ZABHA(ctx);
> +    return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_TESW);
> +}
> +
> +static bool trans_amoadd_h(DisasContext *ctx, arg_amoadd_h *a)
> +{
> +    REQUIRE_ZABHA(ctx);
> +    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_TESW);
> +}
> +
> +static bool trans_amoxor_h(DisasContext *ctx, arg_amoxor_h *a)
> +{
> +    REQUIRE_ZABHA(ctx);
> +    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_TESW);
> +}
> +
> +static bool trans_amoand_h(DisasContext *ctx, arg_amoand_h *a)
> +{
> +    REQUIRE_ZABHA(ctx);
> +    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_TESW);
> +}
> +
> +static bool trans_amoor_h(DisasContext *ctx, arg_amoor_h *a)
> +{
> +    REQUIRE_ZABHA(ctx);
> +    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_TESW);
> +}
> +
> +static bool trans_amomin_h(DisasContext *ctx, arg_amomin_h *a)
> +{
> +    REQUIRE_ZABHA(ctx);
> +    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_TESW);
> +}
> +
> +static bool trans_amomax_h(DisasContext *ctx, arg_amomax_h *a)
> +{
> +    REQUIRE_ZABHA(ctx);
> +    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_TESW);
> +}
> +
> +static bool trans_amominu_h(DisasContext *ctx, arg_amominu_h *a)
> +{
> +    REQUIRE_ZABHA(ctx);
> +    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_TESW);
> +}
> +
> +static bool trans_amomaxu_h(DisasContext *ctx, arg_amomaxu_h *a)
> +{
> +    REQUIRE_ZABHA(ctx);
> +    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_TESW);
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index b160bcbfe0..f597542f1c 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1081,8 +1081,9 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
>  {
>      TCGv dest = dest_gpr(ctx, a->rd);
>      TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);
> +    MemOp size = mop & MO_SIZE;
>
> -    if (ctx->cfg_ptr->ext_zama16b) {
> +    if (ctx->cfg_ptr->ext_zama16b && size >= MO_32) {
>          mop |= MO_ATOM_WITHIN16;
>      } else {
>          mop |= MO_ALIGN;
> @@ -1116,6 +1117,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
>  #include "insn_trans/trans_rvb.c.inc"
>  #include "insn_trans/trans_rvzicond.c.inc"
>  #include "insn_trans/trans_rvzacas.c.inc"
> +#include "insn_trans/trans_rvzabha.c.inc"
>  #include "insn_trans/trans_rvzawrs.c.inc"
>  #include "insn_trans/trans_rvzicbo.c.inc"
>  #include "insn_trans/trans_rvzimop.c.inc"
> --
> 2.25.1
>
>

[PATCH 1/6] target/riscv: Move gen_amo before implement Zabha
[PATCH 2/6] target/riscv: Add AMO instructions for Zabha
[PATCH 3/6] target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
[PATCH 4/6] target/riscv: Add amocas.[b|h] for Zabha
[PATCH 5/6] target/riscv: Enable zabha for max cpu
[PATCH 6/6] disas/riscv: Support zabha disassemble