Series comparison

-[PULL 00/10] loongarch-to-apply queue
+[PULL 0/7] loongarch-to-apply queue
-The following changes since commit 6af8037c42fdc3d20d5aa2686799ab356a9ee1a9:
+The following changes since commit cf86770c7aa31ebd6e56f4eeb25c34107f92c51e:
-  Merge tag 'pull-vfio-20240522' of https://github.com/legoater/qemu into staging (2024-05-22 06:02:06 -0700)
+  Merge tag 'pull-request-2025-01-21v2' of https://gitlab.com/thuth/qemu into staging (2025-01-22 09:59:02 -0500)
 are available in the Git repository at:
-  https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240523
+  https://gitlab.com/bibo-mao/qemu.git tags/pull-loongarch-20250124
-for you to fetch changes up to 6204af704a071ea68d3af55c0502b112a7af9546:
+for you to fetch changes up to 3215fe8528de45a1794f0314623cc10bd8e8e19f:
-  hw/loongarch/virt: Fix FDT memory node address width (2024-05-23 09:30:41 +0800)
+  target/loongarch: Dump all generic CSR registers (2025-01-24 14:49:24 +0800)
 ----------------------------------------------------------------
-pull-loongarch-20240523
+pull-loongarch-20250124 queue
 ----------------------------------------------------------------
 Bibo Mao (7):
-      hw/loongarch: Add VM mode in IOCSR feature register in kvm mode
+      target/loongarch: Add dynamic function access with CSR register
-      hw/loongarch: Refine acpi srat table for numa memory
+      target/loongarch: Remove static CSR function setting
-      hw/loongarch: Refine fadt memory table for numa memory
+      target/loongarch: Add generic csr function type
-      hw/loongarch: Refine fwcfg memory map
+      target/loongarch: Add common header file for CSR registers
-      hw/loongarch: Refine system dram memory region
+      target/loongarch: Add common source file for CSR register
-      hw/loongarch: Remove minimum and default memory size
+      target/loongarch: Set unused flag with CSR registers
-      target/loongarch: Add loongarch vector property unconditionally
+      target/loongarch: Dump all generic CSR registers
-Jiaxun Yang (1):
+ target/loongarch/cpu.c                             |  96 +++++++++---
-      hw/loongarch/virt: Fix FDT memory node address width
+ target/loongarch/csr.c                             | 129 +++++++++++++++++
+ target/loongarch/csr.h                             |  29 ++++
-Song Gao (2):
+ target/loongarch/meson.build                       |   1 +
-      target/loongarch/kvm: Fix VM recovery from disk failures
+ .../tcg/insn_trans/trans_privileged.c.inc          | 161 +++++----------------
-      target/loongarch/kvm: fpu save the vreg registers high 192bit
+ target/loongarch/tcg/tcg_loongarch.h               |  12 ++
+ target/loongarch/tcg/translate.c                   |   5 +
- hw/loongarch/acpi-build.c  |  58 +++++++++------
+files changed, 294 insertions(+), 139 deletions(-)
- hw/loongarch/virt.c        | 179 ++++++++++++++++++++++++++++++++-------------
+ create mode 100644 target/loongarch/csr.c
- target/loongarch/cpu.c     |  14 +---
+ create mode 100644 target/loongarch/csr.h
- target/loongarch/kvm/kvm.c |   6 ++
+ create mode 100644 target/loongarch/tcg/tcg_loongarch.h
  target/loongarch/machine.c |   6 +-
 files changed, 176 insertions(+), 87 deletions(-)

-[PULL 01/10] target/loongarch/kvm: Fix VM recovery from disk failures
+Deleted patch
-vmstate does not save kvm_state_conter,
-which can cause VM recovery from disk to fail.
-Cc: qemu-stable@nongnu.org
-Signed-off-by: Song Gao <gaosong@loongson.cn>
-Acked-by: Peter Xu <peterx@redhat.com>
-Message-Id: <20240508024732.3127792-1-gaosong@loongson.cn>
----
- target/loongarch/machine.c | 6 ++++--
-file changed, 4 insertions(+), 2 deletions(-)
-diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/loongarch/machine.c
-+++ b/target/loongarch/machine.c
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_tlb = {
- /* LoongArch CPU state */
- const VMStateDescription vmstate_loongarch_cpu = {
-     .name = "cpu",
--    .version_id = 1,
--    .minimum_version_id = 1,
-+    .version_id = 2,
-+    .minimum_version_id = 2,
-     .fields = (const VMStateField[]) {
-         VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32),
-         VMSTATE_UINTTL(env.pc, LoongArchCPU),
-@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_loongarch_cpu = {
-         VMSTATE_UINT64(env.CSR_DERA, LoongArchCPU),
-         VMSTATE_UINT64(env.CSR_DSAVE, LoongArchCPU),
-+        VMSTATE_UINT64(kvm_state_counter, LoongArchCPU),
-+
-         VMSTATE_END_OF_LIST()
-     },
-     .subsections = (const VMStateDescription * const []) {
---
-.34.1

-[PULL 02/10] target/loongarch/kvm: fpu save the vreg registers high 192bit
+Deleted patch
-On kvm side, get_fpu/set_fpu save the vreg registers high 192bits,
-but QEMU missing.
-Cc: qemu-stable@nongnu.org
-Signed-off-by: Song Gao <gaosong@loongson.cn>
-Reviewed-by: Bibo Mao <maobibo@loongson.cn>
-Message-Id: <20240514110752.989572-1-gaosong@loongson.cn>
----
- target/loongarch/kvm/kvm.c | 6 ++++++
-file changed, 6 insertions(+)
-diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/loongarch/kvm/kvm.c
-+++ b/target/loongarch/kvm/kvm.c
-@@ -XXX,XX +XXX,XX @@ static int kvm_loongarch_get_regs_fp(CPUState *cs)
-     env->fcsr0 = fpu.fcsr;
-     for (i = 0; i < 32; i++) {
-         env->fpr[i].vreg.UD[0] = fpu.fpr[i].val64[0];
-+        env->fpr[i].vreg.UD[1] = fpu.fpr[i].val64[1];
-+        env->fpr[i].vreg.UD[2] = fpu.fpr[i].val64[2];
-+        env->fpr[i].vreg.UD[3] = fpu.fpr[i].val64[3];
-     }
-     for (i = 0; i < 8; i++) {
-         env->cf[i] = fpu.fcc & 0xFF;
-@@ -XXX,XX +XXX,XX @@ static int kvm_loongarch_put_regs_fp(CPUState *cs)
-     fpu.fcc = 0;
-     for (i = 0; i < 32; i++) {
-         fpu.fpr[i].val64[0] = env->fpr[i].vreg.UD[0];
-+        fpu.fpr[i].val64[1] = env->fpr[i].vreg.UD[1];
-+        fpu.fpr[i].val64[2] = env->fpr[i].vreg.UD[2];
-+        fpu.fpr[i].val64[3] = env->fpr[i].vreg.UD[3];
-     }
-     for (i = 0; i < 8; i++) {
---
-.34.1

-[PULL 06/10] hw/loongarch: Refine fwcfg memory map
+[PULL 1/7] target/loongarch: Add dynamic function access with CSR register
-From: Bibo Mao <maobibo@loongson.cn>
+With CSR register, dynamic function access is used for CSR register
+access in TCG mode, so that csr info can be used by other modules.
 Memory map table for fwcfg is used for UEFI BIOS, UEFI BIOS uses the first
 entry from fwcfg memory map as the first memory HOB, the second memory HOB
 will be used if the first memory HOB is used up.
 Memory map table for fwcfg does not care about numa node, however in
 generic the first memory HOB is part of numa node0, so that runtime
 memory of UEFI which is allocated from the first memory HOB is located
 at numa node0.
 Signed-off-by: Bibo Mao <maobibo@loongson.cn>
-Reviewed-by: Song Gao <gaosong@loongson.cn>
-Message-Id: <20240515093927.3453674-4-maobibo@loongson.cn>
-Signed-off-by: Song Gao <gaosong@loongson.cn>
 ---
- hw/loongarch/virt.c | 60 ++++++++++++++++++++++++++++++++++++++++++---
+ .../tcg/insn_trans/trans_privileged.c.inc     | 37 +++++++++++++++++--
-file changed, 57 insertions(+), 3 deletions(-)
+ target/loongarch/tcg/tcg_loongarch.h          | 12 ++++++
  target/loongarch/tcg/translate.c              |  5 +++
 files changed, 51 insertions(+), 3 deletions(-)
  create mode 100644 target/loongarch/tcg/tcg_loongarch.h
-diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
+diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/hw/loongarch/virt.c
+--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
-+++ b/hw/loongarch/virt.c
++++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
-@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps virt_iocsr_misc_ops = {
+@@ -XXX,XX +XXX,XX @@ enum {
-     },
+ #define CSR_OFF(NAME) \
- };
+     CSR_OFF_FLAGS(NAME, 0)
-+static void fw_cfg_add_memory(MachineState *ms)
+-static const CSRInfo csr_info[] = {
 +static CSRInfo csr_info[] = {
      CSR_OFF_FLAGS(CRMD, CSRFL_EXITTB),
      CSR_OFF(PRMD),
      CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB),
@@ -XXX,XX +XXX,XX @@ static bool check_plv(DisasContext *ctx)
      return false;
  }
 -static const CSRInfo *get_csr(unsigned csr_num)
 +static CSRInfo *get_csr(unsigned csr_num)
  {
 -    const CSRInfo *csr;
 +    CSRInfo *csr;
      if (csr_num >= ARRAY_SIZE(csr_info)) {
          return NULL;
@@ -XXX,XX +XXX,XX @@ static const CSRInfo *get_csr(unsigned csr_num)
      return csr;
  }
 +static bool set_csr_trans_func(unsigned int csr_num, GenCSRRead readfn,
 +                               GenCSRWrite writefn)
 +{
-+    hwaddr base, size, ram_size, gap;
++    CSRInfo *csr;
 +    int nb_numa_nodes, nodes;
 +    NodeInfo *numa_info;
 +
-+    ram_size = ms->ram_size;
++    csr = get_csr(csr_num);
-+    base = VIRT_LOWMEM_BASE;
++    if (!csr) {
-+    gap = VIRT_LOWMEM_SIZE;
++        return false;
 +    nodes = nb_numa_nodes = ms->numa_state->num_nodes;
 +    numa_info = ms->numa_state->nodes;
 +    if (!nodes) {
 +        nodes = 1;
 +    }
 +
-+    /* add fw_cfg memory map of node0 */
++    csr->readfn = readfn;
-+    if (nb_numa_nodes) {
++    csr->writefn = writefn;
-+        size = numa_info[0].node_mem;
++    return true;
 +    } else {
 +        size = ram_size;
 +    }
 +
 +    if (size >= gap) {
 +        memmap_add_entry(base, gap, 1);
 +        size -= gap;
 +        base = VIRT_HIGHMEM_BASE;
 +        gap = ram_size - VIRT_LOWMEM_SIZE;
 +    }
 +
 +    if (size) {
 +        memmap_add_entry(base, size, 1);
 +        base += size;
 +    }
 +
 +    if (nodes < 2) {
 +        return;
 +    }
 +
 +    /* add fw_cfg memory map of other nodes */
 +    size = ram_size - numa_info[0].node_mem;
 +    gap  = VIRT_LOWMEM_BASE + VIRT_LOWMEM_SIZE;
 +    if (base < gap && (base + size) > gap) {
 +        /*
 +         * memory map for the maining nodes splited into two part
 +         *   lowram:  [base, +(gap - base))
 +         *   highram: [VIRT_HIGHMEM_BASE, +(size - (gap - base)))
 +         */
 +        memmap_add_entry(base, gap - base, 1);
 +        size -= gap - base;
 +        base = VIRT_HIGHMEM_BASE;
 +    }
 +
 +   if (size)
 +        memmap_add_entry(base, size, 1);
 +}
 +
- static void virt_init(MachineState *machine)
++#define SET_CSR_FUNC(NAME, read, write)                 \
 +        set_csr_trans_func(LOONGARCH_CSR_##NAME, read, write)
 +
 +void loongarch_csr_translate_init(void)
 +{
 +    SET_CSR_FUNC(ESTAT, NULL, gen_helper_csrwr_estat);
 +    SET_CSR_FUNC(ASID,  NULL, gen_helper_csrwr_asid);
 +    SET_CSR_FUNC(PGD,   gen_helper_csrrd_pgd, NULL);
 +    SET_CSR_FUNC(PWCL,  NULL, gen_helper_csrwr_pwcl);
 +    SET_CSR_FUNC(CPUID, gen_helper_csrrd_cpuid, NULL);
 +    SET_CSR_FUNC(TCFG,  NULL, gen_helper_csrwr_tcfg);
 +    SET_CSR_FUNC(TVAL,  gen_helper_csrrd_tval, NULL);
 +    SET_CSR_FUNC(TICLR, NULL, gen_helper_csrwr_ticlr);
 +}
 +#undef SET_CSR_FUNC
 +
  static bool check_csr_flags(DisasContext *ctx, const CSRInfo *csr, bool write)
  {
-     LoongArchCPU *lacpu;
+     if ((csr->flags & CSRFL_READONLY) && write) {
-@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
+diff --git a/target/loongarch/tcg/tcg_loongarch.h b/target/loongarch/tcg/tcg_loongarch.h
-     }
+new file mode 100644
-     fdt_add_cpu_nodes(lvms);
+index XXXXXXX..XXXXXXX
-     fdt_add_memory_nodes(machine);
+--- /dev/null
-+    fw_cfg_add_memory(machine);
++++ b/target/loongarch/tcg/tcg_loongarch.h
+@@ -XXX,XX +XXX,XX @@
-     /* Node0 memory */
++/* SPDX-License-Identifier: GPL-2.0-or-later */
--    memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1);
++/*
-     memory_region_init_alias(&lvms->lowmem, NULL, "loongarch.node0.lowram",
++ * QEMU LoongArch TCG interface
-                              machine->ram, offset, VIRT_LOWMEM_SIZE);
++ *
-     memory_region_add_subregion(address_space_mem, phyAddr, &lvms->lowmem);
++ * Copyright (c) 2025 Loongson Technology Corporation Limited
-@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
++ */
-         highram_size = ram_size - VIRT_LOWMEM_SIZE;
++#ifndef TARGET_LOONGARCH_TCG_LOONGARCH_H
-     }
++#define TARGET_LOONGARCH_TCG_LOONGARCH_H
-     phyAddr = VIRT_HIGHMEM_BASE;
++
--    memmap_add_entry(phyAddr, highram_size, 1);
++void loongarch_csr_translate_init(void);
-     memory_region_init_alias(&lvms->highmem, NULL, "loongarch.node0.highram",
++
-                               machine->ram, offset, highram_size);
++#endif  /* TARGET_LOONGARCH_TCG_LOONGARCH_H */
-     memory_region_add_subregion(address_space_mem, phyAddr, &lvms->highmem);
+diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c
-@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
+index XXXXXXX..XXXXXXX 100644
-         memory_region_init_alias(nodemem, NULL, ramName, machine->ram,
+--- a/target/loongarch/tcg/translate.c
-                                  offset,  numa_info[i].node_mem);
++++ b/target/loongarch/tcg/translate.c
-         memory_region_add_subregion(address_space_mem, phyAddr, nodemem);
+@@ -XXX,XX +XXX,XX @@
--        memmap_add_entry(phyAddr, numa_info[i].node_mem, 1);
+ #include "exec/log.h"
-         offset += numa_info[i].node_mem;
+ #include "qemu/qemu-print.h"
-         phyAddr += numa_info[i].node_mem;
+ #include "fpu/softfloat.h"
-     }
++#include "tcg_loongarch.h"
  #include "translate.h"
  #include "internals.h"
  #include "vec.h"
@@ -XXX,XX +XXX,XX @@ void loongarch_translate_init(void)
                      offsetof(CPULoongArchState, lladdr), "lladdr");
      cpu_llval = tcg_global_mem_new(tcg_env,
                      offsetof(CPULoongArchState, llval), "llval");
 +
 +#ifndef CONFIG_USER_ONLY
 +    loongarch_csr_translate_init();
 +#endif
  }
 --
-.34.1
+.43.5

-[PULL 08/10] hw/loongarch: Remove minimum and default memory size
+[PULL 2/7] target/loongarch: Remove static CSR function setting
-From: Bibo Mao <maobibo@loongson.cn>
+Since CSR function setting is done dynamically in TCG mode, remove
+static CSR function setting here.
 Some qtest test cases such as numa use default memory size of generic
 machine class, which is 128M by fault.
 Here generic default memory size is used, and also remove minimum memory
 size which is 1G originally.
 Signed-off-by: Bibo Mao <maobibo@loongson.cn>
-Reviewed-by: Song Gao <gaosong@loongson.cn>
-Message-Id: <20240515093927.3453674-6-maobibo@loongson.cn>
-Signed-off-by: Song Gao <gaosong@loongson.cn>
 ---
- hw/loongarch/virt.c | 5 -----
+ .../tcg/insn_trans/trans_privileged.c.inc        | 16 ++++++++--------
-file changed, 5 deletions(-)
+file changed, 8 insertions(+), 8 deletions(-)
-diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
+diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/hw/loongarch/virt.c
+--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
-+++ b/hw/loongarch/virt.c
++++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
-@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ static CSRInfo csr_info[] = {
-         cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
+     CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB),
-     }
+     CSR_OFF_FLAGS(MISC, CSRFL_READONLY),
+     CSR_OFF(ECFG),
--    if (ram_size < 1 * GiB) {
+-    CSR_OFF_FUNCS(ESTAT, CSRFL_EXITTB, NULL, gen_helper_csrwr_estat),
--        error_report("ram_size must be greater than 1G.");
++    CSR_OFF_FLAGS(ESTAT, CSRFL_EXITTB),
--        exit(1);
+     CSR_OFF(ERA),
--    }
+     CSR_OFF(BADV),
-     create_fdt(lvms);
+     CSR_OFF_FLAGS(BADI, CSRFL_READONLY),
+@@ -XXX,XX +XXX,XX @@ static CSRInfo csr_info[] = {
-     /* Create IOCSR space */
+     CSR_OFF(TLBEHI),
-@@ -XXX,XX +XXX,XX @@ static void virt_class_init(ObjectClass *oc, void *data)
+     CSR_OFF(TLBELO0),
-     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
+     CSR_OFF(TLBELO1),
+-    CSR_OFF_FUNCS(ASID, CSRFL_EXITTB, NULL, gen_helper_csrwr_asid),
-     mc->init = virt_init;
++    CSR_OFF_FLAGS(ASID, CSRFL_EXITTB),
--    mc->default_ram_size = 1 * GiB;
+     CSR_OFF(PGDL),
-     mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464");
+     CSR_OFF(PGDH),
-     mc->default_ram_id = "loongarch.ram";
+-    CSR_OFF_FUNCS(PGD, CSRFL_READONLY, gen_helper_csrrd_pgd, NULL),
-     mc->max_cpus = LOONGARCH_MAX_CPUS;
+-    CSR_OFF_FUNCS(PWCL, 0, NULL, gen_helper_csrwr_pwcl),
 +    CSR_OFF_FLAGS(PGD, CSRFL_READONLY),
 +    CSR_OFF(PWCL),
      CSR_OFF(PWCH),
      CSR_OFF(STLBPS),
      CSR_OFF(RVACFG),
 -    CSR_OFF_FUNCS(CPUID, CSRFL_READONLY, gen_helper_csrrd_cpuid, NULL),
 +    CSR_OFF_FLAGS(CPUID, CSRFL_READONLY),
      CSR_OFF_FLAGS(PRCFG1, CSRFL_READONLY),
      CSR_OFF_FLAGS(PRCFG2, CSRFL_READONLY),
      CSR_OFF_FLAGS(PRCFG3, CSRFL_READONLY),
@@ -XXX,XX +XXX,XX @@ static CSRInfo csr_info[] = {
      CSR_OFF_ARRAY(SAVE, 14),
      CSR_OFF_ARRAY(SAVE, 15),
      CSR_OFF(TID),
 -    CSR_OFF_FUNCS(TCFG, CSRFL_IO, NULL, gen_helper_csrwr_tcfg),
 -    CSR_OFF_FUNCS(TVAL, CSRFL_READONLY | CSRFL_IO, gen_helper_csrrd_tval, NULL),
 +    CSR_OFF_FLAGS(TCFG, CSRFL_IO),
 +    CSR_OFF_FLAGS(TVAL, CSRFL_READONLY | CSRFL_IO),
      CSR_OFF(CNTC),
 -    CSR_OFF_FUNCS(TICLR, CSRFL_IO, NULL, gen_helper_csrwr_ticlr),
 +    CSR_OFF_FLAGS(TICLR, CSRFL_IO),
      CSR_OFF(LLBCTL),
      CSR_OFF(IMPCTL1),
      CSR_OFF(IMPCTL2),
 --
-.34.1
+.43.5

-[PULL 05/10] hw/loongarch: Refine fadt memory table for numa memory
+[PULL 3/7] target/loongarch: Add generic csr function type
-From: Bibo Mao <maobibo@loongson.cn>
+Parameter type TCGv and TCGv_ptr for function GenCSRRead and GenCSRWrite
+is not used in non-TCG mode. Generic csr function type is added here
-One LoongArch virt machine platform, there is limitation for memory
+with parameter void type, so that it passes to compile with non-TCG mode.
 map information. The minimum memory size is 256M and minimum memory
 size for numa node0 is 256M also. With qemu numa qtest, it is possible
 that memory size of numa node0 is 128M.
 Limitations for minimum memory size for both total memory and numa
 node0 is removed for fadt numa memory table creation.
 Signed-off-by: Bibo Mao <maobibo@loongson.cn>
-Reviewed-by: Song Gao <gaosong@loongson.cn>
-Message-Id: <20240515093927.3453674-3-maobibo@loongson.cn>
-Signed-off-by: Song Gao <gaosong@loongson.cn>
 ---
- hw/loongarch/virt.c | 46 ++++++++++++++++++++++++++++++++++++++++++---
+ .../tcg/insn_trans/trans_privileged.c.inc     | 27 ++++++++++++-------
-file changed, 43 insertions(+), 3 deletions(-)
+file changed, 17 insertions(+), 10 deletions(-)
-diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
+diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/hw/loongarch/virt.c
+--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
-+++ b/hw/loongarch/virt.c
++++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
-@@ -XXX,XX +XXX,XX @@ static void fdt_add_memory_node(MachineState *ms,
+@@ -XXX,XX +XXX,XX @@ GEN_FALSE_TRANS(idle)
-     g_free(nodename);
  typedef void (*GenCSRRead)(TCGv dest, TCGv_ptr env);
  typedef void (*GenCSRWrite)(TCGv dest, TCGv_ptr env, TCGv src);
 +typedef void (*GenCSRFunc)(void);
  typedef struct {
      int offset;
      int flags;
 -    GenCSRRead readfn;
 -    GenCSRWrite writefn;
 +    GenCSRFunc readfn;
 +    GenCSRFunc writefn;
  } CSRInfo;
  enum {
@@ -XXX,XX +XXX,XX @@ static bool set_csr_trans_func(unsigned int csr_num, GenCSRRead readfn,
          return false;
      }
 -    csr->readfn = readfn;
 -    csr->writefn = writefn;
 +    csr->readfn = (GenCSRFunc)readfn;
 +    csr->writefn = (GenCSRFunc)writefn;
      return true;
  }
-+static void fdt_add_memory_nodes(MachineState *ms)
+@@ -XXX,XX +XXX,XX @@ static bool trans_csrrd(DisasContext *ctx, arg_csrrd *a)
 +{
 +    hwaddr base, size, ram_size, gap;
 +    int i, nb_numa_nodes, nodes;
 +    NodeInfo *numa_info;
 +
 +    ram_size = ms->ram_size;
 +    base = VIRT_LOWMEM_BASE;
 +    gap = VIRT_LOWMEM_SIZE;
 +    nodes = nb_numa_nodes = ms->numa_state->num_nodes;
 +    numa_info = ms->numa_state->nodes;
 +    if (!nodes) {
 +        nodes = 1;
 +    }
 +
 +    for (i = 0; i < nodes; i++) {
 +        if (nb_numa_nodes) {
 +            size = numa_info[i].node_mem;
 +        } else {
 +            size = ram_size;
 +        }
 +
 +        /*
 +         * memory for the node splited into two part
 +         *   lowram:  [base, +gap)
 +         *   highram: [VIRT_HIGHMEM_BASE, +(len - gap))
 +         */
 +        if (size >= gap) {
 +            fdt_add_memory_node(ms, base, gap, i);
 +            size -= gap;
 +            base = VIRT_HIGHMEM_BASE;
 +            gap = ram_size - VIRT_LOWMEM_SIZE;
 +        }
 +
 +        if (size) {
 +            fdt_add_memory_node(ms, base, size, i);
 +            base += size;
 +            gap -= size;
 +        }
 +    }
 +}
 +
  static void virt_build_smbios(LoongArchVirtMachineState *lvms)
  {
-     MachineState *ms = MACHINE(lvms);
+     TCGv dest;
-@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
+     const CSRInfo *csr;
-         lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id;
++    GenCSRRead readfn;
      if (check_plv(ctx)) {
          return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_csrrd(DisasContext *ctx, arg_csrrd *a)
      } else {
          check_csr_flags(ctx, csr, false);
          dest = gpr_dst(ctx, a->rd, EXT_NONE);
 -        if (csr->readfn) {
 -            csr->readfn(dest, tcg_env);
 +        readfn = (GenCSRRead)csr->readfn;
 +        if (readfn) {
 +            readfn(dest, tcg_env);
          } else {
              tcg_gen_ld_tl(dest, tcg_env, csr->offset);
          }
@@ -XXX,XX +XXX,XX @@ static bool trans_csrwr(DisasContext *ctx, arg_csrwr *a)
  {
      TCGv dest, src1;
      const CSRInfo *csr;
 +    GenCSRWrite writefn;
      if (check_plv(ctx)) {
          return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_csrwr(DisasContext *ctx, arg_csrwr *a)
          return false;
      }
-     fdt_add_cpu_nodes(lvms);
+     src1 = gpr_src(ctx, a->rd, EXT_NONE);
-+    fdt_add_memory_nodes(machine);
+-    if (csr->writefn) {
++    writefn = (GenCSRWrite)csr->writefn;
-     /* Node0 memory */
++    if (writefn) {
-     memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1);
+         dest = gpr_dst(ctx, a->rd, EXT_NONE);
--    fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0);
+-        csr->writefn(dest, tcg_env, src1);
-     memory_region_init_alias(&lvms->lowmem, NULL, "loongarch.node0.lowram",
++        writefn(dest, tcg_env, src1);
-                              machine->ram, offset, VIRT_LOWMEM_SIZE);
+     } else {
-     memory_region_add_subregion(address_space_mem, phyAddr, &lvms->lowmem);
+         dest = tcg_temp_new();
-@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
+         tcg_gen_ld_tl(dest, tcg_env, csr->offset);
-     }
+@@ -XXX,XX +XXX,XX @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxchg *a)
-     phyAddr = VIRT_HIGHMEM_BASE;
+ {
-     memmap_add_entry(phyAddr, highram_size, 1);
+     TCGv src1, mask, oldv, newv, temp;
--    fdt_add_memory_node(machine, phyAddr, highram_size, 0);
+     const CSRInfo *csr;
-     memory_region_init_alias(&lvms->highmem, NULL, "loongarch.node0.highram",
++    GenCSRWrite writefn;
-                               machine->ram, offset, highram_size);
-     memory_region_add_subregion(address_space_mem, phyAddr, &lvms->highmem);
+     if (check_plv(ctx)) {
-@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
+         return false;
-                                  offset,  numa_info[i].node_mem);
+@@ -XXX,XX +XXX,XX @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxchg *a)
-         memory_region_add_subregion(address_space_mem, phyAddr, nodemem);
+     tcg_gen_andc_tl(temp, oldv, mask);
-         memmap_add_entry(phyAddr, numa_info[i].node_mem, 1);
+     tcg_gen_or_tl(newv, newv, temp);
--        fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i);
-         offset += numa_info[i].node_mem;
+-    if (csr->writefn) {
-         phyAddr += numa_info[i].node_mem;
+-        csr->writefn(oldv, tcg_env, newv);
 +    writefn = (GenCSRWrite)csr->writefn;
 +    if (writefn) {
 +        writefn(oldv, tcg_env, newv);
      } else {
          tcg_gen_st_tl(newv, tcg_env, csr->offset);
      }
 --
-.34.1
+.43.5

-[PULL 07/10] hw/loongarch: Refine system dram memory region
+[PULL 4/7] target/loongarch: Add common header file for CSR registers
-From: Bibo Mao <maobibo@loongson.cn>
+Common header file csr.h is added here, it can be used by both
+TCG mode and kvm mode.
 For system dram memory region, it is not necessary to use numa node
 information. There is only low memory region and high memory region.
 Remove numa node information for ddr memory region here, it can reduce
 memory region number on LoongArch virt machine.
 Signed-off-by: Bibo Mao <maobibo@loongson.cn>
-Reviewed-by: Song Gao <gaosong@loongson.cn>
-Message-Id: <20240515093927.3453674-5-maobibo@loongson.cn>
-Signed-off-by: Song Gao <gaosong@loongson.cn>
 ---
- hw/loongarch/virt.c | 53 +++++++++++++++------------------------------
+ target/loongarch/csr.h                        | 25 +++++++++++++++++++
-file changed, 17 insertions(+), 36 deletions(-)
+ .../tcg/insn_trans/trans_privileged.c.inc     | 16 +-----------
 files changed, 26 insertions(+), 15 deletions(-)
  create mode 100644 target/loongarch/csr.h
-diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
+diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/loongarch/csr.h
@@ -XXX,XX +XXX,XX @@
 +/* SPDX-License-Identifier: GPL-2.0-or-later */
 +/*
 + * Copyright (c) 2025 Loongson Technology Corporation Limited
 + */
 +
 +#ifndef TARGET_LOONGARCH_CSR_H
 +#define TARGET_LOONGARCH_CSR_H
 +
 +#include "cpu-csr.h"
 +
 +typedef void (*GenCSRFunc)(void);
 +enum {
 +    CSRFL_READONLY = (1 << 0),
 +    CSRFL_EXITTB   = (1 << 1),
 +    CSRFL_IO       = (1 << 2),
 +};
 +
 +typedef struct {
 +    int offset;
 +    int flags;
 +    GenCSRFunc readfn;
 +    GenCSRFunc writefn;
 +} CSRInfo;
 +
 +#endif /* TARGET_LOONGARCH_CSR_H */
 diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/hw/loongarch/virt.c
+--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
-+++ b/hw/loongarch/virt.c
++++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
-@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@
- {
+  * LoongArch translation routines for the privileged instructions.
-     LoongArchCPU *lacpu;
+  */
-     const char *cpu_model = machine->cpu_type;
--    ram_addr_t offset = 0;
+-#include "cpu-csr.h"
--    ram_addr_t ram_size = machine->ram_size;
++#include "csr.h"
--    uint64_t highram_size = 0, phyAddr = 0;
-     MemoryRegion *address_space_mem = get_system_memory();
+ #ifdef CONFIG_USER_ONLY
-     LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(machine);
--    int nb_numa_nodes = machine->numa_state->num_nodes;
+@@ -XXX,XX +XXX,XX @@ GEN_FALSE_TRANS(idle)
--    NodeInfo *numa_info = machine->numa_state->nodes;
-     int i;
+ typedef void (*GenCSRRead)(TCGv dest, TCGv_ptr env);
-+    hwaddr base, size, ram_size = machine->ram_size;
+ typedef void (*GenCSRWrite)(TCGv dest, TCGv_ptr env, TCGv src);
-     const CPUArchIdList *possible_cpus;
+-typedef void (*GenCSRFunc)(void);
      MachineClass *mc = MACHINE_GET_CLASS(machine);
      CPUState *cpu;
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
      fw_cfg_add_memory(machine);
      /* Node0 memory */
 -    memory_region_init_alias(&lvms->lowmem, NULL, "loongarch.node0.lowram",
 -                             machine->ram, offset, VIRT_LOWMEM_SIZE);
 -    memory_region_add_subregion(address_space_mem, phyAddr, &lvms->lowmem);
 -
--    offset += VIRT_LOWMEM_SIZE;
+-typedef struct {
--    if (nb_numa_nodes > 0) {
+-    int offset;
--        assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE);
+-    int flags;
--        highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE;
+-    GenCSRFunc readfn;
--    } else {
+-    GenCSRFunc writefn;
--        highram_size = ram_size - VIRT_LOWMEM_SIZE;
+-} CSRInfo;
 +    size = ram_size;
 +    base = VIRT_LOWMEM_BASE;
 +    if (size > VIRT_LOWMEM_SIZE) {
 +        size = VIRT_LOWMEM_SIZE;
      }
 -    phyAddr = VIRT_HIGHMEM_BASE;
 -    memory_region_init_alias(&lvms->highmem, NULL, "loongarch.node0.highram",
 -                              machine->ram, offset, highram_size);
 -    memory_region_add_subregion(address_space_mem, phyAddr, &lvms->highmem);
 -
--    /* Node1 - Nodemax memory */
+-enum {
--    offset += highram_size;
+-    CSRFL_READONLY = (1 << 0),
--    phyAddr += highram_size;
+-    CSRFL_EXITTB   = (1 << 1),
--
+-    CSRFL_IO       = (1 << 2),
--    for (i = 1; i < nb_numa_nodes; i++) {
+-};
--        MemoryRegion *nodemem = g_new(MemoryRegion, 1);
--        g_autofree char *ramName = g_strdup_printf("loongarch.node%d.ram", i);
+ #define CSR_OFF_FUNCS(NAME, FL, RD, WR)                    \
--        memory_region_init_alias(nodemem, NULL, ramName, machine->ram,
+     [LOONGARCH_CSR_##NAME] = {                             \
 -                                 offset,  numa_info[i].node_mem);
 -        memory_region_add_subregion(address_space_mem, phyAddr, nodemem);
 -        offset += numa_info[i].node_mem;
 -        phyAddr += numa_info[i].node_mem;
 +
 +    memory_region_init_alias(&lvms->lowmem, NULL, "loongarch.lowram",
 +                              machine->ram, base, size);
 +    memory_region_add_subregion(address_space_mem, base, &lvms->lowmem);
 +    base += size;
 +    if (ram_size - size) {
 +        base = VIRT_HIGHMEM_BASE;
 +        memory_region_init_alias(&lvms->highmem, NULL, "loongarch.highram",
 +                machine->ram, VIRT_LOWMEM_BASE + size, ram_size - size);
 +        memory_region_add_subregion(address_space_mem, base, &lvms->highmem);
 +        base += ram_size - size;
      }
      /* initialize device memory address space */
      if (machine->ram_size < machine->maxram_size) {
          ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
 -        hwaddr device_mem_base;
          if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
              error_report("unsupported amount of memory slots: %"PRIu64,
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
                           "%d bytes", TARGET_PAGE_SIZE);
              exit(EXIT_FAILURE);
          }
 -        /* device memory base is the top of high memory address. */
 -        device_mem_base = ROUND_UP(VIRT_HIGHMEM_BASE + highram_size, 1 * GiB);
 -        machine_memory_devices_init(machine, device_mem_base, device_mem_size);
 +        machine_memory_devices_init(machine, base, device_mem_size);
      }
      /* load the BIOS image. */
 --
-.34.1
+.43.5

-[PULL 03/10] hw/loongarch: Add VM mode in IOCSR feature register in kvm mode
+[PULL 5/7] target/loongarch: Add common source file for CSR register
-From: Bibo Mao <maobibo@loongson.cn>
+Common source file csr.c is added here, it can be used by both
+TCG mode and kvm mode. The common code is removed from file
-If VM runs in kvm mode, VM mode is added in IOCSR feature register.
+tcg/insn_trans/trans_privileged.c.inc to csrc.c
 So guest can detect kvm hypervisor type and enable possible pv functions.
 Signed-off-by: Bibo Mao <maobibo@loongson.cn>
-Reviewed-by: Song Gao <gaosong@loongson.cn>
-Message-Id: <20240514025109.3238398-1-maobibo@loongson.cn>
-Signed-off-by: Song Gao <gaosong@loongson.cn>
 ---
- hw/loongarch/virt.c | 12 +++++++++---
+ target/loongarch/csr.c                        | 114 ++++++++++++++++++
-file changed, 9 insertions(+), 3 deletions(-)
+ target/loongarch/csr.h                        |   1 +
  target/loongarch/meson.build                  |   1 +
  .../tcg/insn_trans/trans_privileged.c.inc     | 107 ----------------
 files changed, 116 insertions(+), 107 deletions(-)
  create mode 100644 target/loongarch/csr.c
-diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
+diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/loongarch/csr.c
@@ -XXX,XX +XXX,XX @@
 +/* SPDX-License-Identifier: GPL-2.0-or-later */
 +/*
 + * Copyright (c) 2025 Loongson Technology Corporation Limited
 + */
 +#include <stddef.h>
 +#include "qemu/osdep.h"
 +#include "cpu.h"
 +#include "csr.h"
 +
 +#define CSR_OFF_FUNCS(NAME, FL, RD, WR)                    \
 +    [LOONGARCH_CSR_##NAME] = {                             \
 +        .offset = offsetof(CPULoongArchState, CSR_##NAME), \
 +        .flags = FL, .readfn = RD, .writefn = WR           \
 +    }
 +
 +#define CSR_OFF_ARRAY(NAME, N)                                \
 +    [LOONGARCH_CSR_##NAME(N)] = {                             \
 +        .offset = offsetof(CPULoongArchState, CSR_##NAME[N]), \
 +        .flags = 0, .readfn = NULL, .writefn = NULL           \
 +    }
 +
 +#define CSR_OFF_FLAGS(NAME, FL)   CSR_OFF_FUNCS(NAME, FL, NULL, NULL)
 +#define CSR_OFF(NAME)             CSR_OFF_FLAGS(NAME, 0)
 +
 +static CSRInfo csr_info[] = {
 +    CSR_OFF_FLAGS(CRMD, CSRFL_EXITTB),
 +    CSR_OFF(PRMD),
 +    CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB),
 +    CSR_OFF_FLAGS(MISC, CSRFL_READONLY),
 +    CSR_OFF(ECFG),
 +    CSR_OFF_FLAGS(ESTAT, CSRFL_EXITTB),
 +    CSR_OFF(ERA),
 +    CSR_OFF(BADV),
 +    CSR_OFF_FLAGS(BADI, CSRFL_READONLY),
 +    CSR_OFF(EENTRY),
 +    CSR_OFF(TLBIDX),
 +    CSR_OFF(TLBEHI),
 +    CSR_OFF(TLBELO0),
 +    CSR_OFF(TLBELO1),
 +    CSR_OFF_FLAGS(ASID, CSRFL_EXITTB),
 +    CSR_OFF(PGDL),
 +    CSR_OFF(PGDH),
 +    CSR_OFF_FLAGS(PGD, CSRFL_READONLY),
 +    CSR_OFF(PWCL),
 +    CSR_OFF(PWCH),
 +    CSR_OFF(STLBPS),
 +    CSR_OFF(RVACFG),
 +    CSR_OFF_FLAGS(CPUID, CSRFL_READONLY),
 +    CSR_OFF_FLAGS(PRCFG1, CSRFL_READONLY),
 +    CSR_OFF_FLAGS(PRCFG2, CSRFL_READONLY),
 +    CSR_OFF_FLAGS(PRCFG3, CSRFL_READONLY),
 +    CSR_OFF_ARRAY(SAVE, 0),
 +    CSR_OFF_ARRAY(SAVE, 1),
 +    CSR_OFF_ARRAY(SAVE, 2),
 +    CSR_OFF_ARRAY(SAVE, 3),
 +    CSR_OFF_ARRAY(SAVE, 4),
 +    CSR_OFF_ARRAY(SAVE, 5),
 +    CSR_OFF_ARRAY(SAVE, 6),
 +    CSR_OFF_ARRAY(SAVE, 7),
 +    CSR_OFF_ARRAY(SAVE, 8),
 +    CSR_OFF_ARRAY(SAVE, 9),
 +    CSR_OFF_ARRAY(SAVE, 10),
 +    CSR_OFF_ARRAY(SAVE, 11),
 +    CSR_OFF_ARRAY(SAVE, 12),
 +    CSR_OFF_ARRAY(SAVE, 13),
 +    CSR_OFF_ARRAY(SAVE, 14),
 +    CSR_OFF_ARRAY(SAVE, 15),
 +    CSR_OFF(TID),
 +    CSR_OFF_FLAGS(TCFG, CSRFL_IO),
 +    CSR_OFF_FLAGS(TVAL, CSRFL_READONLY | CSRFL_IO),
 +    CSR_OFF(CNTC),
 +    CSR_OFF_FLAGS(TICLR, CSRFL_IO),
 +    CSR_OFF(LLBCTL),
 +    CSR_OFF(IMPCTL1),
 +    CSR_OFF(IMPCTL2),
 +    CSR_OFF(TLBRENTRY),
 +    CSR_OFF(TLBRBADV),
 +    CSR_OFF(TLBRERA),
 +    CSR_OFF(TLBRSAVE),
 +    CSR_OFF(TLBRELO0),
 +    CSR_OFF(TLBRELO1),
 +    CSR_OFF(TLBREHI),
 +    CSR_OFF(TLBRPRMD),
 +    CSR_OFF(MERRCTL),
 +    CSR_OFF(MERRINFO1),
 +    CSR_OFF(MERRINFO2),
 +    CSR_OFF(MERRENTRY),
 +    CSR_OFF(MERRERA),
 +    CSR_OFF(MERRSAVE),
 +    CSR_OFF(CTAG),
 +    CSR_OFF_ARRAY(DMW, 0),
 +    CSR_OFF_ARRAY(DMW, 1),
 +    CSR_OFF_ARRAY(DMW, 2),
 +    CSR_OFF_ARRAY(DMW, 3),
 +    CSR_OFF(DBG),
 +    CSR_OFF(DERA),
 +    CSR_OFF(DSAVE),
 +};
 +
 +CSRInfo *get_csr(unsigned int csr_num)
 +{
 +    CSRInfo *csr;
 +
 +    if (csr_num >= ARRAY_SIZE(csr_info)) {
 +        return NULL;
 +    }
 +
 +    csr = &csr_info[csr_num];
 +    if (csr->offset == 0) {
 +        return NULL;
 +    }
 +
 +    return csr;
 +}
 diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/loongarch/virt.c
+--- a/target/loongarch/csr.h
-+++ b/hw/loongarch/virt.c
++++ b/target/loongarch/csr.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ typedef struct {
- #include "qapi/error.h"
+     GenCSRFunc writefn;
- #include "hw/boards.h"
+ } CSRInfo;
- #include "hw/char/serial.h"
-+#include "sysemu/kvm.h"
++CSRInfo *get_csr(unsigned int csr_num);
- #include "sysemu/sysemu.h"
+ #endif /* TARGET_LOONGARCH_CSR_H */
- #include "sysemu/qtest.h"
+diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
- #include "sysemu/runstate.h"
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ static void virt_iocsr_misc_write(void *opaque, hwaddr addr,
+--- a/target/loongarch/meson.build
++++ b/target/loongarch/meson.build
- static uint64_t virt_iocsr_misc_read(void *opaque, hwaddr addr, unsigned size)
+@@ -XXX,XX +XXX,XX @@ loongarch_system_ss = ss.source_set()
  loongarch_system_ss.add(files(
    'arch_dump.c',
    'cpu_helper.c',
 +  'csr.c',
    'loongarch-qmp-cmds.c',
    'machine.c',
  ))
 diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
 +++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ GEN_FALSE_TRANS(idle)
  typedef void (*GenCSRRead)(TCGv dest, TCGv_ptr env);
  typedef void (*GenCSRWrite)(TCGv dest, TCGv_ptr env, TCGv src);
 -#define CSR_OFF_FUNCS(NAME, FL, RD, WR)                    \
 -    [LOONGARCH_CSR_##NAME] = {                             \
 -        .offset = offsetof(CPULoongArchState, CSR_##NAME), \
 -        .flags = FL, .readfn = RD, .writefn = WR           \
 -    }
 -
 -#define CSR_OFF_ARRAY(NAME, N)                                \
 -    [LOONGARCH_CSR_##NAME(N)] = {                             \
 -        .offset = offsetof(CPULoongArchState, CSR_##NAME[N]), \
 -        .flags = 0, .readfn = NULL, .writefn = NULL           \
 -    }
 -
 -#define CSR_OFF_FLAGS(NAME, FL) \
 -    CSR_OFF_FUNCS(NAME, FL, NULL, NULL)
 -
 -#define CSR_OFF(NAME) \
 -    CSR_OFF_FLAGS(NAME, 0)
 -
 -static CSRInfo csr_info[] = {
 -    CSR_OFF_FLAGS(CRMD, CSRFL_EXITTB),
 -    CSR_OFF(PRMD),
 -    CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB),
 -    CSR_OFF_FLAGS(MISC, CSRFL_READONLY),
 -    CSR_OFF(ECFG),
 -    CSR_OFF_FLAGS(ESTAT, CSRFL_EXITTB),
 -    CSR_OFF(ERA),
 -    CSR_OFF(BADV),
 -    CSR_OFF_FLAGS(BADI, CSRFL_READONLY),
 -    CSR_OFF(EENTRY),
 -    CSR_OFF(TLBIDX),
 -    CSR_OFF(TLBEHI),
 -    CSR_OFF(TLBELO0),
 -    CSR_OFF(TLBELO1),
 -    CSR_OFF_FLAGS(ASID, CSRFL_EXITTB),
 -    CSR_OFF(PGDL),
 -    CSR_OFF(PGDH),
 -    CSR_OFF_FLAGS(PGD, CSRFL_READONLY),
 -    CSR_OFF(PWCL),
 -    CSR_OFF(PWCH),
 -    CSR_OFF(STLBPS),
 -    CSR_OFF(RVACFG),
 -    CSR_OFF_FLAGS(CPUID, CSRFL_READONLY),
 -    CSR_OFF_FLAGS(PRCFG1, CSRFL_READONLY),
 -    CSR_OFF_FLAGS(PRCFG2, CSRFL_READONLY),
 -    CSR_OFF_FLAGS(PRCFG3, CSRFL_READONLY),
 -    CSR_OFF_ARRAY(SAVE, 0),
 -    CSR_OFF_ARRAY(SAVE, 1),
 -    CSR_OFF_ARRAY(SAVE, 2),
 -    CSR_OFF_ARRAY(SAVE, 3),
 -    CSR_OFF_ARRAY(SAVE, 4),
 -    CSR_OFF_ARRAY(SAVE, 5),
 -    CSR_OFF_ARRAY(SAVE, 6),
 -    CSR_OFF_ARRAY(SAVE, 7),
 -    CSR_OFF_ARRAY(SAVE, 8),
 -    CSR_OFF_ARRAY(SAVE, 9),
 -    CSR_OFF_ARRAY(SAVE, 10),
 -    CSR_OFF_ARRAY(SAVE, 11),
 -    CSR_OFF_ARRAY(SAVE, 12),
 -    CSR_OFF_ARRAY(SAVE, 13),
 -    CSR_OFF_ARRAY(SAVE, 14),
 -    CSR_OFF_ARRAY(SAVE, 15),
 -    CSR_OFF(TID),
 -    CSR_OFF_FLAGS(TCFG, CSRFL_IO),
 -    CSR_OFF_FLAGS(TVAL, CSRFL_READONLY | CSRFL_IO),
 -    CSR_OFF(CNTC),
 -    CSR_OFF_FLAGS(TICLR, CSRFL_IO),
 -    CSR_OFF(LLBCTL),
 -    CSR_OFF(IMPCTL1),
 -    CSR_OFF(IMPCTL2),
 -    CSR_OFF(TLBRENTRY),
 -    CSR_OFF(TLBRBADV),
 -    CSR_OFF(TLBRERA),
 -    CSR_OFF(TLBRSAVE),
 -    CSR_OFF(TLBRELO0),
 -    CSR_OFF(TLBRELO1),
 -    CSR_OFF(TLBREHI),
 -    CSR_OFF(TLBRPRMD),
 -    CSR_OFF(MERRCTL),
 -    CSR_OFF(MERRINFO1),
 -    CSR_OFF(MERRINFO2),
 -    CSR_OFF(MERRENTRY),
 -    CSR_OFF(MERRERA),
 -    CSR_OFF(MERRSAVE),
 -    CSR_OFF(CTAG),
 -    CSR_OFF_ARRAY(DMW, 0),
 -    CSR_OFF_ARRAY(DMW, 1),
 -    CSR_OFF_ARRAY(DMW, 2),
 -    CSR_OFF_ARRAY(DMW, 3),
 -    CSR_OFF(DBG),
 -    CSR_OFF(DERA),
 -    CSR_OFF(DSAVE),
 -};
 -
  static bool check_plv(DisasContext *ctx)
  {
-+    uint64_t ret;
+     if (ctx->plv == MMU_PLV_USER) {
-+
+@@ -XXX,XX +XXX,XX @@ static bool check_plv(DisasContext *ctx)
-     switch (addr) {
+     return false;
      case VERSION_REG:
          return 0x11ULL;
      case FEATURE_REG:
 -        return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI |
 -               1ULL << IOCSRF_CSRIPI;
 +        ret = BIT(IOCSRF_MSI) | BIT(IOCSRF_EXTIOI) | BIT(IOCSRF_CSRIPI);
 +        if (kvm_enabled()) {
 +            ret |= BIT(IOCSRF_VM);
 +        }
 +        return ret;
      case VENDOR_REG:
          return 0x6e6f73676e6f6f4cULL; /* "Loongson" */
      case CPUNAME_REG:
          return 0x303030354133ULL;     /* "3A5000" */
      case MISC_FUNC_REG:
 -        return 1ULL << IOCSRM_EXTIOI_EN;
 +        return BIT_ULL(IOCSRM_EXTIOI_EN);
      }
      return 0ULL;
  }
+-static CSRInfo *get_csr(unsigned csr_num)
+-{
+-    CSRInfo *csr;
+-
+-    if (csr_num >= ARRAY_SIZE(csr_info)) {
+-        return NULL;
+-    }
+-    csr = &csr_info[csr_num];
+-    if (csr->offset == 0) {
+-        return NULL;
+-    }
+-    return csr;
+-}
+-
+ static bool set_csr_trans_func(unsigned int csr_num, GenCSRRead readfn,
+                                GenCSRWrite writefn)
+ {
 --
-.34.1
+.43.5

-[PULL 09/10] target/loongarch: Add loongarch vector property unconditionally
+[PULL 6/7] target/loongarch: Set unused flag with CSR registers
-From: Bibo Mao <maobibo@loongson.cn>
+On LA464, some CSR registers are not used such as CSR_SAVE8 -
 CSR_SAVE15, also CSR registers relative with MCE is not used now.
-Currently LSX/LASX vector property is decided by the default value.
+Flag CSRFL_UNUSED is added for these registers, so that it will
-Instead vector property should be added unconditionally, and it is
+not dumped. In order to keep compatiblity, these CSR registers are
-irrelative with its default value. If vector is disabled by default,
+not removed since it is used in vmstate already.
 vector also can be enabled from command line.
 Signed-off-by: Bibo Mao <maobibo@loongson.cn>
-Reviewed-by: Song Gao <gaosong@loongson.cn>
-Message-Id: <20240521080549.434197-2-maobibo@loongson.cn>
-Signed-off-by: Song Gao <gaosong@loongson.cn>
 ---
- target/loongarch/cpu.c | 14 ++++----------
+ target/loongarch/cpu.c | 30 +++++++++++++++++++++++++++++-
-file changed, 4 insertions(+), 10 deletions(-)
+ target/loongarch/csr.c | 13 +++++++++++++
  target/loongarch/csr.h |  2 ++
 files changed, 44 insertions(+), 1 deletion(-)
 diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/loongarch/cpu.c
 +++ b/target/loongarch/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void loongarch_set_lasx(Object *obj, bool value, Error **errp)
+@@ -XXX,XX +XXX,XX @@
+ #include "cpu.h"
- void loongarch_cpu_post_init(Object *obj)
+ #include "internals.h"
  #include "fpu/softfloat-helpers.h"
 -#include "cpu-csr.h"
 +#include "csr.h"
  #ifndef CONFIG_USER_ONLY
  #include "system/reset.h"
  #endif
@@ -XXX,XX +XXX,XX @@ static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch)
      return MMU_DA_IDX;
  }
 +static void loongarch_la464_init_csr(Object *obj)
 +{
 +#ifndef CONFIG_USER_ONLY
 +    static bool initialized;
 +    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
 +    CPULoongArchState *env = &cpu->env;
 +    int i, num;
 +
 +    if (!initialized) {
 +        initialized = true;
 +        num = FIELD_EX64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM);
 +        for (i = num; i < 16; i++) {
 +            set_csr_flag(LOONGARCH_CSR_SAVE(i), CSRFL_UNUSED);
 +        }
 +        set_csr_flag(LOONGARCH_CSR_IMPCTL1, CSRFL_UNUSED);
 +        set_csr_flag(LOONGARCH_CSR_IMPCTL2, CSRFL_UNUSED);
 +        set_csr_flag(LOONGARCH_CSR_MERRCTL, CSRFL_UNUSED);
 +        set_csr_flag(LOONGARCH_CSR_MERRINFO1, CSRFL_UNUSED);
 +        set_csr_flag(LOONGARCH_CSR_MERRINFO2, CSRFL_UNUSED);
 +        set_csr_flag(LOONGARCH_CSR_MERRENTRY, CSRFL_UNUSED);
 +        set_csr_flag(LOONGARCH_CSR_MERRERA, CSRFL_UNUSED);
 +        set_csr_flag(LOONGARCH_CSR_MERRSAVE, CSRFL_UNUSED);
 +        set_csr_flag(LOONGARCH_CSR_CTAG, CSRFL_UNUSED);
 +    }
 +#endif
 +}
 +
  static void loongarch_la464_initfn(Object *obj)
  {
--    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+     LoongArchCPU *cpu = LOONGARCH_CPU(obj);
--
+@@ -XXX,XX +XXX,XX @@ static void loongarch_la464_initfn(Object *obj)
--    if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) {
+     env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7);
--        object_property_add_bool(obj, "lsx", loongarch_get_lsx,
+     env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8);
--                                 loongarch_set_lsx);
--    }
++    loongarch_la464_init_csr(obj);
--    if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LASX)) {
+     loongarch_cpu_post_init(obj);
 -        object_property_add_bool(obj, "lasx", loongarch_get_lasx,
 -                                 loongarch_set_lasx);
 -    }
 +    object_property_add_bool(obj, "lsx", loongarch_get_lsx,
 +                             loongarch_set_lsx);
 +    object_property_add_bool(obj, "lasx", loongarch_get_lasx,
 +                             loongarch_set_lasx);
  }
- static void loongarch_cpu_init(Object *obj)
+diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/loongarch/csr.c
 +++ b/target/loongarch/csr.c
@@ -XXX,XX +XXX,XX @@ CSRInfo *get_csr(unsigned int csr_num)
      return csr;
  }
 +
 +bool set_csr_flag(unsigned int csr_num, int flag)
 +{
 +    CSRInfo *csr;
 +
 +    csr = get_csr(csr_num);
 +    if (!csr) {
 +        return false;
 +    }
 +
 +    csr->flags |= flag;
 +    return true;
 +}
 diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/loongarch/csr.h
 +++ b/target/loongarch/csr.h
@@ -XXX,XX +XXX,XX @@ enum {
      CSRFL_READONLY = (1 << 0),
      CSRFL_EXITTB   = (1 << 1),
      CSRFL_IO       = (1 << 2),
 +    CSRFL_UNUSED   = (1 << 3),
  };
  typedef struct {
@@ -XXX,XX +XXX,XX @@ typedef struct {
  } CSRInfo;
  CSRInfo *get_csr(unsigned int csr_num);
 +bool set_csr_flag(unsigned int csr_num, int flag);
  #endif /* TARGET_LOONGARCH_CSR_H */
 --
-.34.1
+.43.5

-[PULL 04/10] hw/loongarch: Refine acpi srat table for numa memory
+[PULL 7/7] target/loongarch: Dump all generic CSR registers
-From: Bibo Mao <maobibo@loongson.cn>
+CSR registers is import system control registers, it had better
 dump all CSR registers when VM is running in system mode.
-One LoongArch virt machine platform, there is limitation for memory
+Here is dump output example of CSR registers:
-map information. The minimum memory size is 256M and minimum memory
+ CSR000: CRMD   b4               PRMD   4                EUEN   0                MISC   0
-size for numa node0 is 256M also. With qemu numa qtest, it is possible
+ CSR004: ECFG   71c1c            ESTAT  0                ERA    9000000002c31300 BADV   12022c0e0
-that memory size of numa node0 is 128M.
+ CSR008: BADI   2b0000
+ CSR012: EENTRY 90000000046b0000
-Limitations for minimum memory size for both total memory and numa
+ CSR016: TLBIDX ffffffff8e000228 TLBEHI 120228000        TLBELO0 400000016f19001f TLBELO1 400000016f1a401f
-node0 is removed for acpi srat table creation.
+ CSR024: ASID   a0004            PGDL   90000001016f0000 PGDH   9000000004680000 PGD    0
  CSR028: PWCL   5e56e            PWCH   2e4              STLBPS e                RVACFG 0
  CSR032: CPUID  0                PRCFG1 72f8             PRCFG2 3ffff000         PRCFG3 8073f2
  CSR048: SAVE0  0                SAVE1  af9c             SAVE2  12010d6a8        SAVE3  8300000
  CSR052: SAVE4  0                SAVE5  0                SAVE6  0                SAVE7  0
  CSR064: TID    0                TCFG   8f0ca15          TVAL   4cefd8b          CNTC   fffffffffe688aaa
  CSR068: TICLR  0
  CSR096: LLBCTL 1
  CSR136: TLBRENTRY 46ba000       TLBRBADV ffff8000130d81e2 TLBRERA 9000000003585cb8 TLBRSAVE ffff8000130d81e0
  CSR140: TLBRELO0 1fe00043       TLBRELO1 40             TLBREHI ffff8000130d800e TLBRPRMD 0
  CSR384: DMW0   8000000000000001 DMW1   9000000000000011 DMW2   0                DMW3   0
 Signed-off-by: Bibo Mao <maobibo@loongson.cn>
-Reviewed-by: Song Gao <gaosong@loongson.cn>
-Message-Id: <20240515093927.3453674-2-maobibo@loongson.cn>
-Signed-off-by: Song Gao <gaosong@loongson.cn>
 ---
- hw/loongarch/acpi-build.c | 58 +++++++++++++++++++++++----------------
+ target/loongarch/cpu.c | 66 ++++++++++++++++++++++++++++++++----------
-file changed, 34 insertions(+), 24 deletions(-)
+ target/loongarch/csr.c |  2 ++
  target/loongarch/csr.h |  1 +
 files changed, 53 insertions(+), 16 deletions(-)
-diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
+diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/loongarch/acpi-build.c
+--- a/target/loongarch/cpu.c
-+++ b/hw/loongarch/acpi-build.c
++++ b/target/loongarch/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void
+@@ -XXX,XX +XXX,XX @@ static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model)
- build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
+     return oc;
- {
+ }
-     int i, arch_id, node_id;
--    uint64_t mem_len, mem_base;
++static void loongarch_cpu_dump_csr(CPUState *cs, FILE *f)
--    int nb_numa_nodes = machine->numa_state->num_nodes;
++{
-+    hwaddr len, base, gap;
++#ifndef CONFIG_USER_ONLY
-+    NodeInfo *numa_info;
++    CPULoongArchState *env = cpu_env(cs);
-+    int nodes, nb_numa_nodes = machine->numa_state->num_nodes;
++    CSRInfo *csr_info;
-     LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(machine);
++    int64_t *addr;
-     MachineClass *mc = MACHINE_GET_CLASS(lvms);
++    int i, j, len, col = 0;
      const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(machine);
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
          build_append_int_noprefix(table_data, 0, 4); /* Reserved */
      }
 -    /* Node0 */
 -    build_srat_memory(table_data, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE,
 -                      0, MEM_AFFINITY_ENABLED);
 -    mem_base = VIRT_HIGHMEM_BASE;
 -    if (!nb_numa_nodes) {
 -        mem_len = machine->ram_size - VIRT_LOWMEM_SIZE;
 -    } else {
 -        mem_len = machine->numa_state->nodes[0].node_mem - VIRT_LOWMEM_SIZE;
 +    base = VIRT_LOWMEM_BASE;
 +    gap = VIRT_LOWMEM_SIZE;
 +    numa_info = machine->numa_state->nodes;
 +    nodes = nb_numa_nodes;
 +    if (!nodes) {
 +        nodes = 1;
      }
 -    if (mem_len)
 -        build_srat_memory(table_data, mem_base, mem_len, 0, MEM_AFFINITY_ENABLED);
 -
 -    /* Node1 - Nodemax */
 -    if (nb_numa_nodes) {
 -        mem_base += mem_len;
 -        for (i = 1; i < nb_numa_nodes; ++i) {
 -            if (machine->numa_state->nodes[i].node_mem > 0) {
 -                build_srat_memory(table_data, mem_base,
 -                                  machine->numa_state->nodes[i].node_mem, i,
 -                                  MEM_AFFINITY_ENABLED);
 -                mem_base += machine->numa_state->nodes[i].node_mem;
 -            }
 +
-+    for (i = 0; i < nodes; i++) {
++    qemu_fprintf(f, "\n");
-+        if (nb_numa_nodes) {
++
-+            len = numa_info[i].node_mem;
++    /* Dump all generic CSR register */
-+        } else {
++    for (i = 0; i < LOONGARCH_CSR_DBG; i++) {
-+            len = machine->ram_size;
++        csr_info = get_csr(i);
 +        if (!csr_info || (csr_info->flags & CSRFL_UNUSED)) {
 +            if (i == (col + 3)) {
 +                qemu_fprintf(f, "\n");
 +            }
 +
 +            continue;
 +        }
 +
-+        /*
++        if ((i >  (col + 3)) || (i == col)) {
-+         * memory for the node splited into two part
++            col = i & ~3;
-+         *   lowram:  [base, +gap)
++            qemu_fprintf(f, " CSR%03d:", col);
 +         *   highram: [VIRT_HIGHMEM_BASE, +(len - gap))
 +         */
 +        if (len >= gap) {
 +            build_srat_memory(table_data, base, len, i, MEM_AFFINITY_ENABLED);
 +            len -= gap;
 +            base = VIRT_HIGHMEM_BASE;
 +            gap = machine->ram_size - VIRT_LOWMEM_SIZE;
 +        }
 +
-+        if (len) {
++        addr = (void *)env + csr_info->offset;
-+            build_srat_memory(table_data, base, len, i, MEM_AFFINITY_ENABLED);
++        qemu_fprintf(f, " %s ", csr_info->name);
-+            base += len;
++        len = strlen(csr_info->name);
-+            gap  -= len;
++        for (; len < 6; len++) {
 +            qemu_fprintf(f, " ");
 +        }
 +
 +        qemu_fprintf(f, "%" PRIx64, *addr);
 +        j = find_last_bit((void *)addr, BITS_PER_LONG) & (BITS_PER_LONG - 1);
 +        len += j / 4 + 1;
 +        for (; len < 22; len++) {
 +                qemu_fprintf(f, " ");
 +        }
 +
 +        if (i == (col + 3)) {
 +            qemu_fprintf(f, "\n");
 +        }
 +    }
 +    qemu_fprintf(f, "\n");
 +#endif
 +}
 +
  static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
  {
      CPULoongArchState *env = cpu_env(cs);
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
          }
      }
-     if (machine->device_memory) {
+-    qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD);
-         build_srat_memory(table_data, machine->device_memory->base,
+-    qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD);
-                           memory_region_size(&machine->device_memory->mr),
+-    qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN);
--                          nb_numa_nodes - 1,
+-    qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT);
-+                          nodes - 1,
+-    qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA);
-                           MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
+-    qemu_fprintf(f, "BADV=%016" PRIx64 "\n", env->CSR_BADV);
 -    qemu_fprintf(f, "BADI=%016" PRIx64 "\n", env->CSR_BADI);
 -    qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY);
 -    qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 ","
 -                 " PRCFG3=%016" PRIx64 "\n",
 -                 env->CSR_PRCFG1, env->CSR_PRCFG2, env->CSR_PRCFG3);
 -    qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY);
 -    qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV);
 -    qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA);
 -    qemu_fprintf(f, "TCFG=%016" PRIx64 "\n", env->CSR_TCFG);
 -    qemu_fprintf(f, "TVAL=%016" PRIx64 "\n", env->CSR_TVAL);
 +    /* csr */
 +    loongarch_cpu_dump_csr(cs, f);
      /* fpr */
      if (flags & CPU_DUMP_FPU) {
 diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/loongarch/csr.c
 +++ b/target/loongarch/csr.c
@@ -XXX,XX +XXX,XX @@
  #define CSR_OFF_FUNCS(NAME, FL, RD, WR)                    \
      [LOONGARCH_CSR_##NAME] = {                             \
 +        .name   = (stringify(NAME)),                       \
          .offset = offsetof(CPULoongArchState, CSR_##NAME), \
          .flags = FL, .readfn = RD, .writefn = WR           \
      }
+ #define CSR_OFF_ARRAY(NAME, N)                                \
+     [LOONGARCH_CSR_##NAME(N)] = {                             \
++        .name   = (stringify(NAME##N)),                       \
+         .offset = offsetof(CPULoongArchState, CSR_##NAME[N]), \
+         .flags = 0, .readfn = NULL, .writefn = NULL           \
+     }
+diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/loongarch/csr.h
++++ b/target/loongarch/csr.h
+@@ -XXX,XX +XXX,XX @@ enum {
+ };
+ typedef struct {
++    const char *name;
+     int offset;
+     int flags;
+     GenCSRFunc readfn;
 --
-.34.1
+.43.5

-[PULL 10/10] hw/loongarch/virt: Fix FDT memory node address width
+Deleted patch
-From: Jiaxun Yang <jiaxun.yang@flygoat.com>
-Higher bits for memory nodes were omitted at qemu_fdt_setprop_cells.
-Cc: qemu-stable@nongnu.org
-Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
-Reviewed-by: Song Gao <gaosong@loongson.cn>
-Message-Id: <20240520-loongarch-fdt-memnode-v1-1-5ea9be93911e@flygoat.com>
-Signed-off-by: Song Gao <gaosong@loongson.cn>
----
- hw/loongarch/virt.c | 3 ++-
-file changed, 2 insertions(+), 1 deletion(-)
-diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/loongarch/virt.c
-+++ b/hw/loongarch/virt.c
-@@ -XXX,XX +XXX,XX @@ static void fdt_add_memory_node(MachineState *ms,
-     char *nodename = g_strdup_printf("/memory@%" PRIx64, base);
-     qemu_fdt_add_subnode(ms->fdt, nodename);
--    qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, base, 0, size);
-+    qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", base >> 32, base,
-+                           size >> 32, size);
-     qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
-     if (ms->numa_state && ms->numa_state->num_nodes) {
---
-.34.1

The following changes since commit 6af8037c42fdc3d20d5aa2686799ab356a9ee1a9:

Merge tag 'pull-vfio-20240522' of https://github.com/legoater/qemu into staging (2024-05-22 06:02:06 -0700)

are available in the Git repository at:

https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240523

for you to fetch changes up to 6204af704a071ea68d3af55c0502b112a7af9546:

hw/loongarch/virt: Fix FDT memory node address width (2024-05-23 09:30:41 +0800)

----------------------------------------------------------------
pull-loongarch-20240523

----------------------------------------------------------------
Bibo Mao (7):
      hw/loongarch: Add VM mode in IOCSR feature register in kvm mode
      hw/loongarch: Refine acpi srat table for numa memory
      hw/loongarch: Refine fadt memory table for numa memory
      hw/loongarch: Refine fwcfg memory map
      hw/loongarch: Refine system dram memory region
      hw/loongarch: Remove minimum and default memory size
      target/loongarch: Add loongarch vector property unconditionally

Jiaxun Yang (1):
      hw/loongarch/virt: Fix FDT memory node address width

Song Gao (2):
      target/loongarch/kvm: Fix VM recovery from disk failures
      target/loongarch/kvm: fpu save the vreg registers high 192bit

hw/loongarch/acpi-build.c  |  58 +++++++++------
 hw/loongarch/virt.c        | 179 ++++++++++++++++++++++++++++++++-------------
 target/loongarch/cpu.c     |  14 +---
 target/loongarch/kvm/kvm.c |   6 ++
 target/loongarch/machine.c |   6 +-
 5 files changed, 176 insertions(+), 87 deletions(-)

vmstate does not save kvm_state_conter,
which can cause VM recovery from disk to fail.

Cc: qemu-stable@nongnu.org
Signed-off-by: Song Gao <gaosong@loongson.cn>
Acked-by: Peter Xu <peterx@redhat.com>
Message-Id: <20240508024732.3127792-1-gaosong@loongson.cn>
---
 target/loongarch/machine.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/machine.c
+++ b/target/loongarch/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_tlb = {
 /* LoongArch CPU state */
 const VMStateDescription vmstate_loongarch_cpu = {
     .name = "cpu",
-    .version_id = 1,
-    .minimum_version_id = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
     .fields = (const VMStateField[]) {
         VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32),
         VMSTATE_UINTTL(env.pc, LoongArchCPU),
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_loongarch_cpu = {
         VMSTATE_UINT64(env.CSR_DERA, LoongArchCPU),
         VMSTATE_UINT64(env.CSR_DSAVE, LoongArchCPU),
 
+        VMSTATE_UINT64(kvm_state_counter, LoongArchCPU),
+
         VMSTATE_END_OF_LIST()
     },
     .subsections = (const VMStateDescription * const []) {
-- 
2.34.1

On kvm side, get_fpu/set_fpu save the vreg registers high 192bits,
but QEMU missing.

Cc: qemu-stable@nongnu.org
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Message-Id: <20240514110752.989572-1-gaosong@loongson.cn>
---
 target/loongarch/kvm/kvm.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/kvm/kvm.c
+++ b/target/loongarch/kvm/kvm.c
@@ -XXX,XX +XXX,XX @@ static int kvm_loongarch_get_regs_fp(CPUState *cs)
     env->fcsr0 = fpu.fcsr;
     for (i = 0; i < 32; i++) {
         env->fpr[i].vreg.UD[0] = fpu.fpr[i].val64[0];
+        env->fpr[i].vreg.UD[1] = fpu.fpr[i].val64[1];
+        env->fpr[i].vreg.UD[2] = fpu.fpr[i].val64[2];
+        env->fpr[i].vreg.UD[3] = fpu.fpr[i].val64[3];
     }
     for (i = 0; i < 8; i++) {
         env->cf[i] = fpu.fcc & 0xFF;
@@ -XXX,XX +XXX,XX @@ static int kvm_loongarch_put_regs_fp(CPUState *cs)
     fpu.fcc = 0;
     for (i = 0; i < 32; i++) {
         fpu.fpr[i].val64[0] = env->fpr[i].vreg.UD[0];
+        fpu.fpr[i].val64[1] = env->fpr[i].vreg.UD[1];
+        fpu.fpr[i].val64[2] = env->fpr[i].vreg.UD[2];
+        fpu.fpr[i].val64[3] = env->fpr[i].vreg.UD[3];
     }
 
     for (i = 0; i < 8; i++) {
-- 
2.34.1

From: Bibo Mao <maobibo@loongson.cn>

If VM runs in kvm mode, VM mode is added in IOCSR feature register.
So guest can detect kvm hypervisor type and enable possible pv functions.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20240514025109.3238398-1-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 hw/loongarch/virt.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "hw/boards.h"
 #include "hw/char/serial.h"
+#include "sysemu/kvm.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/qtest.h"
 #include "sysemu/runstate.h"
@@ -XXX,XX +XXX,XX @@ static void virt_iocsr_misc_write(void *opaque, hwaddr addr,
 
 static uint64_t virt_iocsr_misc_read(void *opaque, hwaddr addr, unsigned size)
 {
+    uint64_t ret;
+
     switch (addr) {
     case VERSION_REG:
         return 0x11ULL;
     case FEATURE_REG:
-        return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI |
-               1ULL << IOCSRF_CSRIPI;
+        ret = BIT(IOCSRF_MSI) | BIT(IOCSRF_EXTIOI) | BIT(IOCSRF_CSRIPI);
+        if (kvm_enabled()) {
+            ret |= BIT(IOCSRF_VM);
+        }
+        return ret;
     case VENDOR_REG:
         return 0x6e6f73676e6f6f4cULL; /* "Loongson" */
     case CPUNAME_REG:
         return 0x303030354133ULL;     /* "3A5000" */
     case MISC_FUNC_REG:
-        return 1ULL << IOCSRM_EXTIOI_EN;
+        return BIT_ULL(IOCSRM_EXTIOI_EN);
     }
     return 0ULL;
 }
-- 
2.34.1

From: Bibo Mao <maobibo@loongson.cn>

One LoongArch virt machine platform, there is limitation for memory
map information. The minimum memory size is 256M and minimum memory
size for numa node0 is 256M also. With qemu numa qtest, it is possible
that memory size of numa node0 is 128M.

Limitations for minimum memory size for both total memory and numa
node0 is removed for acpi srat table creation.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20240515093927.3453674-2-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 hw/loongarch/acpi-build.c | 58 +++++++++++++++++++++++----------------
 1 file changed, 34 insertions(+), 24 deletions(-)

diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/acpi-build.c
+++ b/hw/loongarch/acpi-build.c
@@ -XXX,XX +XXX,XX @@ static void
 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
 {
     int i, arch_id, node_id;
-    uint64_t mem_len, mem_base;
-    int nb_numa_nodes = machine->numa_state->num_nodes;
+    hwaddr len, base, gap;
+    NodeInfo *numa_info;
+    int nodes, nb_numa_nodes = machine->numa_state->num_nodes;
     LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(machine);
     MachineClass *mc = MACHINE_GET_CLASS(lvms);
     const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(machine);
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
         build_append_int_noprefix(table_data, 0, 4); /* Reserved */
     }
 
-    /* Node0 */
-    build_srat_memory(table_data, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE,
-                      0, MEM_AFFINITY_ENABLED);
-    mem_base = VIRT_HIGHMEM_BASE;
-    if (!nb_numa_nodes) {
-        mem_len = machine->ram_size - VIRT_LOWMEM_SIZE;
-    } else {
-        mem_len = machine->numa_state->nodes[0].node_mem - VIRT_LOWMEM_SIZE;
+    base = VIRT_LOWMEM_BASE;
+    gap = VIRT_LOWMEM_SIZE;
+    numa_info = machine->numa_state->nodes;
+    nodes = nb_numa_nodes;
+    if (!nodes) {
+        nodes = 1;
     }
-    if (mem_len)
-        build_srat_memory(table_data, mem_base, mem_len, 0, MEM_AFFINITY_ENABLED);
-
-    /* Node1 - Nodemax */
-    if (nb_numa_nodes) {
-        mem_base += mem_len;
-        for (i = 1; i < nb_numa_nodes; ++i) {
-            if (machine->numa_state->nodes[i].node_mem > 0) {
-                build_srat_memory(table_data, mem_base,
-                                  machine->numa_state->nodes[i].node_mem, i,
-                                  MEM_AFFINITY_ENABLED);
-                mem_base += machine->numa_state->nodes[i].node_mem;
-            }
+
+    for (i = 0; i < nodes; i++) {
+        if (nb_numa_nodes) {
+            len = numa_info[i].node_mem;
+        } else {
+            len = machine->ram_size;
+        }
+
+        /*
+         * memory for the node splited into two part
+         *   lowram:  [base, +gap)
+         *   highram: [VIRT_HIGHMEM_BASE, +(len - gap))
+         */
+        if (len >= gap) {
+            build_srat_memory(table_data, base, len, i, MEM_AFFINITY_ENABLED);
+            len -= gap;
+            base = VIRT_HIGHMEM_BASE;
+            gap = machine->ram_size - VIRT_LOWMEM_SIZE;
+        }
+
+        if (len) {
+            build_srat_memory(table_data, base, len, i, MEM_AFFINITY_ENABLED);
+            base += len;
+            gap  -= len;
         }
     }
 
     if (machine->device_memory) {
         build_srat_memory(table_data, machine->device_memory->base,
                           memory_region_size(&machine->device_memory->mr),
-                          nb_numa_nodes - 1,
+                          nodes - 1,
                           MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
     }
 
-- 
2.34.1

From: Bibo Mao <maobibo@loongson.cn>

Limitations for minimum memory size for both total memory and numa
node0 is removed for fadt numa memory table creation.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20240515093927.3453674-3-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 hw/loongarch/virt.c | 46 ++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 43 insertions(+), 3 deletions(-)

diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@ static void fdt_add_memory_node(MachineState *ms,
     g_free(nodename);
 }
 
+static void fdt_add_memory_nodes(MachineState *ms)
+{
+    hwaddr base, size, ram_size, gap;
+    int i, nb_numa_nodes, nodes;
+    NodeInfo *numa_info;
+
+    ram_size = ms->ram_size;
+    base = VIRT_LOWMEM_BASE;
+    gap = VIRT_LOWMEM_SIZE;
+    nodes = nb_numa_nodes = ms->numa_state->num_nodes;
+    numa_info = ms->numa_state->nodes;
+    if (!nodes) {
+        nodes = 1;
+    }
+
+    for (i = 0; i < nodes; i++) {
+        if (nb_numa_nodes) {
+            size = numa_info[i].node_mem;
+        } else {
+            size = ram_size;
+        }
+
+        /*
+         * memory for the node splited into two part
+         *   lowram:  [base, +gap)
+         *   highram: [VIRT_HIGHMEM_BASE, +(len - gap))
+         */
+        if (size >= gap) {
+            fdt_add_memory_node(ms, base, gap, i);
+            size -= gap;
+            base = VIRT_HIGHMEM_BASE;
+            gap = ram_size - VIRT_LOWMEM_SIZE;
+        }
+
+        if (size) {
+            fdt_add_memory_node(ms, base, size, i);
+            base += size;
+            gap -= size;
+        }
+    }
+}
+
 static void virt_build_smbios(LoongArchVirtMachineState *lvms)
 {
     MachineState *ms = MACHINE(lvms);
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
         lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id;
     }
     fdt_add_cpu_nodes(lvms);
+    fdt_add_memory_nodes(machine);
 
     /* Node0 memory */
     memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1);
-    fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0);
     memory_region_init_alias(&lvms->lowmem, NULL, "loongarch.node0.lowram",
                              machine->ram, offset, VIRT_LOWMEM_SIZE);
     memory_region_add_subregion(address_space_mem, phyAddr, &lvms->lowmem);
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
     }
     phyAddr = VIRT_HIGHMEM_BASE;
     memmap_add_entry(phyAddr, highram_size, 1);
-    fdt_add_memory_node(machine, phyAddr, highram_size, 0);
     memory_region_init_alias(&lvms->highmem, NULL, "loongarch.node0.highram",
                               machine->ram, offset, highram_size);
     memory_region_add_subregion(address_space_mem, phyAddr, &lvms->highmem);
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
                                  offset,  numa_info[i].node_mem);
         memory_region_add_subregion(address_space_mem, phyAddr, nodemem);
         memmap_add_entry(phyAddr, numa_info[i].node_mem, 1);
-        fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i);
         offset += numa_info[i].node_mem;
         phyAddr += numa_info[i].node_mem;
     }
-- 
2.34.1

From: Bibo Mao <maobibo@loongson.cn>

Memory map table for fwcfg is used for UEFI BIOS, UEFI BIOS uses the first
entry from fwcfg memory map as the first memory HOB, the second memory HOB
will be used if the first memory HOB is used up.

Memory map table for fwcfg does not care about numa node, however in
generic the first memory HOB is part of numa node0, so that runtime
memory of UEFI which is allocated from the first memory HOB is located
at numa node0.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20240515093927.3453674-4-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 hw/loongarch/virt.c | 60 ++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 57 insertions(+), 3 deletions(-)

diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps virt_iocsr_misc_ops = {
     },
 };
 
+static void fw_cfg_add_memory(MachineState *ms)
+{
+    hwaddr base, size, ram_size, gap;
+    int nb_numa_nodes, nodes;
+    NodeInfo *numa_info;
+
+    ram_size = ms->ram_size;
+    base = VIRT_LOWMEM_BASE;
+    gap = VIRT_LOWMEM_SIZE;
+    nodes = nb_numa_nodes = ms->numa_state->num_nodes;
+    numa_info = ms->numa_state->nodes;
+    if (!nodes) {
+        nodes = 1;
+    }
+
+    /* add fw_cfg memory map of node0 */
+    if (nb_numa_nodes) {
+        size = numa_info[0].node_mem;
+    } else {
+        size = ram_size;
+    }
+
+    if (size >= gap) {
+        memmap_add_entry(base, gap, 1);
+        size -= gap;
+        base = VIRT_HIGHMEM_BASE;
+        gap = ram_size - VIRT_LOWMEM_SIZE;
+    }
+
+    if (size) {
+        memmap_add_entry(base, size, 1);
+        base += size;
+    }
+
+    if (nodes < 2) {
+        return;
+    }
+
+    /* add fw_cfg memory map of other nodes */
+    size = ram_size - numa_info[0].node_mem;
+    gap  = VIRT_LOWMEM_BASE + VIRT_LOWMEM_SIZE;
+    if (base < gap && (base + size) > gap) {
+        /*
+         * memory map for the maining nodes splited into two part
+         *   lowram:  [base, +(gap - base))
+         *   highram: [VIRT_HIGHMEM_BASE, +(size - (gap - base)))
+         */
+        memmap_add_entry(base, gap - base, 1);
+        size -= gap - base;
+        base = VIRT_HIGHMEM_BASE;
+    }
+
+   if (size)
+        memmap_add_entry(base, size, 1);
+}
+
 static void virt_init(MachineState *machine)
 {
     LoongArchCPU *lacpu;
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
     }
     fdt_add_cpu_nodes(lvms);
     fdt_add_memory_nodes(machine);
+    fw_cfg_add_memory(machine);
 
     /* Node0 memory */
-    memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1);
     memory_region_init_alias(&lvms->lowmem, NULL, "loongarch.node0.lowram",
                              machine->ram, offset, VIRT_LOWMEM_SIZE);
     memory_region_add_subregion(address_space_mem, phyAddr, &lvms->lowmem);
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
         highram_size = ram_size - VIRT_LOWMEM_SIZE;
     }
     phyAddr = VIRT_HIGHMEM_BASE;
-    memmap_add_entry(phyAddr, highram_size, 1);
     memory_region_init_alias(&lvms->highmem, NULL, "loongarch.node0.highram",
                               machine->ram, offset, highram_size);
     memory_region_add_subregion(address_space_mem, phyAddr, &lvms->highmem);
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
         memory_region_init_alias(nodemem, NULL, ramName, machine->ram,
                                  offset,  numa_info[i].node_mem);
         memory_region_add_subregion(address_space_mem, phyAddr, nodemem);
-        memmap_add_entry(phyAddr, numa_info[i].node_mem, 1);
         offset += numa_info[i].node_mem;
         phyAddr += numa_info[i].node_mem;
     }
-- 
2.34.1

From: Bibo Mao <maobibo@loongson.cn>

For system dram memory region, it is not necessary to use numa node
information. There is only low memory region and high memory region.

Remove numa node information for ddr memory region here, it can reduce
memory region number on LoongArch virt machine.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20240515093927.3453674-5-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 hw/loongarch/virt.c | 53 +++++++++++++++------------------------------
 1 file changed, 17 insertions(+), 36 deletions(-)

diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
 {
     LoongArchCPU *lacpu;
     const char *cpu_model = machine->cpu_type;
-    ram_addr_t offset = 0;
-    ram_addr_t ram_size = machine->ram_size;
-    uint64_t highram_size = 0, phyAddr = 0;
     MemoryRegion *address_space_mem = get_system_memory();
     LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(machine);
-    int nb_numa_nodes = machine->numa_state->num_nodes;
-    NodeInfo *numa_info = machine->numa_state->nodes;
     int i;
+    hwaddr base, size, ram_size = machine->ram_size;
     const CPUArchIdList *possible_cpus;
     MachineClass *mc = MACHINE_GET_CLASS(machine);
     CPUState *cpu;
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
     fw_cfg_add_memory(machine);
 
     /* Node0 memory */
-    memory_region_init_alias(&lvms->lowmem, NULL, "loongarch.node0.lowram",
-                             machine->ram, offset, VIRT_LOWMEM_SIZE);
-    memory_region_add_subregion(address_space_mem, phyAddr, &lvms->lowmem);
-
-    offset += VIRT_LOWMEM_SIZE;
-    if (nb_numa_nodes > 0) {
-        assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE);
-        highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE;
-    } else {
-        highram_size = ram_size - VIRT_LOWMEM_SIZE;
+    size = ram_size;
+    base = VIRT_LOWMEM_BASE;
+    if (size > VIRT_LOWMEM_SIZE) {
+        size = VIRT_LOWMEM_SIZE;
     }
-    phyAddr = VIRT_HIGHMEM_BASE;
-    memory_region_init_alias(&lvms->highmem, NULL, "loongarch.node0.highram",
-                              machine->ram, offset, highram_size);
-    memory_region_add_subregion(address_space_mem, phyAddr, &lvms->highmem);
-
-    /* Node1 - Nodemax memory */
-    offset += highram_size;
-    phyAddr += highram_size;
-
-    for (i = 1; i < nb_numa_nodes; i++) {
-        MemoryRegion *nodemem = g_new(MemoryRegion, 1);
-        g_autofree char *ramName = g_strdup_printf("loongarch.node%d.ram", i);
-        memory_region_init_alias(nodemem, NULL, ramName, machine->ram,
-                                 offset,  numa_info[i].node_mem);
-        memory_region_add_subregion(address_space_mem, phyAddr, nodemem);
-        offset += numa_info[i].node_mem;
-        phyAddr += numa_info[i].node_mem;
+
+    memory_region_init_alias(&lvms->lowmem, NULL, "loongarch.lowram",
+                              machine->ram, base, size);
+    memory_region_add_subregion(address_space_mem, base, &lvms->lowmem);
+    base += size;
+    if (ram_size - size) {
+        base = VIRT_HIGHMEM_BASE;
+        memory_region_init_alias(&lvms->highmem, NULL, "loongarch.highram",
+                machine->ram, VIRT_LOWMEM_BASE + size, ram_size - size);
+        memory_region_add_subregion(address_space_mem, base, &lvms->highmem);
+        base += ram_size - size;
     }
 
     /* initialize device memory address space */
     if (machine->ram_size < machine->maxram_size) {
         ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
-        hwaddr device_mem_base;
 
         if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
             error_report("unsupported amount of memory slots: %"PRIu64,
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
                          "%d bytes", TARGET_PAGE_SIZE);
             exit(EXIT_FAILURE);
         }
-        /* device memory base is the top of high memory address. */
-        device_mem_base = ROUND_UP(VIRT_HIGHMEM_BASE + highram_size, 1 * GiB);
-        machine_memory_devices_init(machine, device_mem_base, device_mem_size);
+        machine_memory_devices_init(machine, base, device_mem_size);
     }
 
     /* load the BIOS image. */
-- 
2.34.1

From: Bibo Mao <maobibo@loongson.cn>

Some qtest test cases such as numa use default memory size of generic
machine class, which is 128M by fault.

Here generic default memory size is used, and also remove minimum memory
size which is 1G originally.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20240515093927.3453674-6-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 hw/loongarch/virt.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
         cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
     }
 
-    if (ram_size < 1 * GiB) {
-        error_report("ram_size must be greater than 1G.");
-        exit(1);
-    }
     create_fdt(lvms);
 
     /* Create IOCSR space */
@@ -XXX,XX +XXX,XX @@ static void virt_class_init(ObjectClass *oc, void *data)
     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
 
     mc->init = virt_init;
-    mc->default_ram_size = 1 * GiB;
     mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464");
     mc->default_ram_id = "loongarch.ram";
     mc->max_cpus = LOONGARCH_MAX_CPUS;
-- 
2.34.1

From: Bibo Mao <maobibo@loongson.cn>

Currently LSX/LASX vector property is decided by the default value.
Instead vector property should be added unconditionally, and it is
irrelative with its default value. If vector is disabled by default,
vector also can be enabled from command line.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20240521080549.434197-2-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 target/loongarch/cpu.c | 14 ++++----------
 1 file changed, 4 insertions(+), 10 deletions(-)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -XXX,XX +XXX,XX @@ static void loongarch_set_lasx(Object *obj, bool value, Error **errp)
 
 void loongarch_cpu_post_init(Object *obj)
 {
-    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
-
-    if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) {
-        object_property_add_bool(obj, "lsx", loongarch_get_lsx,
-                                 loongarch_set_lsx);
-    }
-    if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LASX)) {
-        object_property_add_bool(obj, "lasx", loongarch_get_lasx,
-                                 loongarch_set_lasx);
-    }
+    object_property_add_bool(obj, "lsx", loongarch_get_lsx,
+                             loongarch_set_lsx);
+    object_property_add_bool(obj, "lasx", loongarch_get_lasx,
+                             loongarch_set_lasx);
 }
 
 static void loongarch_cpu_init(Object *obj)
-- 
2.34.1

From: Jiaxun Yang <jiaxun.yang@flygoat.com>

Higher bits for memory nodes were omitted at qemu_fdt_setprop_cells.

Cc: qemu-stable@nongnu.org
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20240520-loongarch-fdt-memnode-v1-1-5ea9be93911e@flygoat.com>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 hw/loongarch/virt.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@ static void fdt_add_memory_node(MachineState *ms,
     char *nodename = g_strdup_printf("/memory@%" PRIx64, base);
 
     qemu_fdt_add_subnode(ms->fdt, nodename);
-    qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, base, 0, size);
+    qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", base >> 32, base,
+                           size >> 32, size);
     qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
 
     if (ms->numa_state && ms->numa_state->num_nodes) {
-- 
2.34.1

The following changes since commit cf86770c7aa31ebd6e56f4eeb25c34107f92c51e:

Merge tag 'pull-request-2025-01-21v2' of https://gitlab.com/thuth/qemu into staging (2025-01-22 09:59:02 -0500)

are available in the Git repository at:

https://gitlab.com/bibo-mao/qemu.git tags/pull-loongarch-20250124

for you to fetch changes up to 3215fe8528de45a1794f0314623cc10bd8e8e19f:

target/loongarch: Dump all generic CSR registers (2025-01-24 14:49:24 +0800)

----------------------------------------------------------------
pull-loongarch-20250124 queue

----------------------------------------------------------------
Bibo Mao (7):
      target/loongarch: Add dynamic function access with CSR register
      target/loongarch: Remove static CSR function setting
      target/loongarch: Add generic csr function type
      target/loongarch: Add common header file for CSR registers
      target/loongarch: Add common source file for CSR register
      target/loongarch: Set unused flag with CSR registers
      target/loongarch: Dump all generic CSR registers

target/loongarch/cpu.c                             |  96 +++++++++---
 target/loongarch/csr.c                             | 129 +++++++++++++++++
 target/loongarch/csr.h                             |  29 ++++
 target/loongarch/meson.build                       |   1 +
 .../tcg/insn_trans/trans_privileged.c.inc          | 161 +++++----------------
 target/loongarch/tcg/tcg_loongarch.h               |  12 ++
 target/loongarch/tcg/translate.c                   |   5 +
 7 files changed, 294 insertions(+), 139 deletions(-)
 create mode 100644 target/loongarch/csr.c
 create mode 100644 target/loongarch/csr.h
 create mode 100644 target/loongarch/tcg/tcg_loongarch.h

With CSR register, dynamic function access is used for CSR register
access in TCG mode, so that csr info can be used by other modules.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 .../tcg/insn_trans/trans_privileged.c.inc     | 37 +++++++++++++++++--
 target/loongarch/tcg/tcg_loongarch.h          | 12 ++++++
 target/loongarch/tcg/translate.c              |  5 +++
 3 files changed, 51 insertions(+), 3 deletions(-)
 create mode 100644 target/loongarch/tcg/tcg_loongarch.h

diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ enum {
 #define CSR_OFF(NAME) \
     CSR_OFF_FLAGS(NAME, 0)
 
-static const CSRInfo csr_info[] = {
+static CSRInfo csr_info[] = {
     CSR_OFF_FLAGS(CRMD, CSRFL_EXITTB),
     CSR_OFF(PRMD),
     CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB),
@@ -XXX,XX +XXX,XX @@ static bool check_plv(DisasContext *ctx)
     return false;
 }
 
-static const CSRInfo *get_csr(unsigned csr_num)
+static CSRInfo *get_csr(unsigned csr_num)
 {
-    const CSRInfo *csr;
+    CSRInfo *csr;
 
     if (csr_num >= ARRAY_SIZE(csr_info)) {
         return NULL;
@@ -XXX,XX +XXX,XX @@ static const CSRInfo *get_csr(unsigned csr_num)
     return csr;
 }
 
+static bool set_csr_trans_func(unsigned int csr_num, GenCSRRead readfn,
+                               GenCSRWrite writefn)
+{
+    CSRInfo *csr;
+
+    csr = get_csr(csr_num);
+    if (!csr) {
+        return false;
+    }
+
+    csr->readfn = readfn;
+    csr->writefn = writefn;
+    return true;
+}
+
+#define SET_CSR_FUNC(NAME, read, write)                 \
+        set_csr_trans_func(LOONGARCH_CSR_##NAME, read, write)
+
+void loongarch_csr_translate_init(void)
+{
+    SET_CSR_FUNC(ESTAT, NULL, gen_helper_csrwr_estat);
+    SET_CSR_FUNC(ASID,  NULL, gen_helper_csrwr_asid);
+    SET_CSR_FUNC(PGD,   gen_helper_csrrd_pgd, NULL);
+    SET_CSR_FUNC(PWCL,  NULL, gen_helper_csrwr_pwcl);
+    SET_CSR_FUNC(CPUID, gen_helper_csrrd_cpuid, NULL);
+    SET_CSR_FUNC(TCFG,  NULL, gen_helper_csrwr_tcfg);
+    SET_CSR_FUNC(TVAL,  gen_helper_csrrd_tval, NULL);
+    SET_CSR_FUNC(TICLR, NULL, gen_helper_csrwr_ticlr);
+}
+#undef SET_CSR_FUNC
+
 static bool check_csr_flags(DisasContext *ctx, const CSRInfo *csr, bool write)
 {
     if ((csr->flags & CSRFL_READONLY) && write) {
diff --git a/target/loongarch/tcg/tcg_loongarch.h b/target/loongarch/tcg/tcg_loongarch.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/loongarch/tcg/tcg_loongarch.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch TCG interface
+ *
+ * Copyright (c) 2025 Loongson Technology Corporation Limited
+ */
+#ifndef TARGET_LOONGARCH_TCG_LOONGARCH_H
+#define TARGET_LOONGARCH_TCG_LOONGARCH_H
+
+void loongarch_csr_translate_init(void);
+
+#endif  /* TARGET_LOONGARCH_TCG_LOONGARCH_H */
diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/tcg/translate.c
+++ b/target/loongarch/tcg/translate.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/log.h"
 #include "qemu/qemu-print.h"
 #include "fpu/softfloat.h"
+#include "tcg_loongarch.h"
 #include "translate.h"
 #include "internals.h"
 #include "vec.h"
@@ -XXX,XX +XXX,XX @@ void loongarch_translate_init(void)
                     offsetof(CPULoongArchState, lladdr), "lladdr");
     cpu_llval = tcg_global_mem_new(tcg_env,
                     offsetof(CPULoongArchState, llval), "llval");
+
+#ifndef CONFIG_USER_ONLY
+    loongarch_csr_translate_init();
+#endif
 }
-- 
2.43.5

Since CSR function setting is done dynamically in TCG mode, remove
static CSR function setting here.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 .../tcg/insn_trans/trans_privileged.c.inc        | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

Parameter type TCGv and TCGv_ptr for function GenCSRRead and GenCSRWrite
is not used in non-TCG mode. Generic csr function type is added here
with parameter void type, so that it passes to compile with non-TCG mode.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 .../tcg/insn_trans/trans_privileged.c.inc     | 27 ++++++++++++-------
 1 file changed, 17 insertions(+), 10 deletions(-)

diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ GEN_FALSE_TRANS(idle)
 
 typedef void (*GenCSRRead)(TCGv dest, TCGv_ptr env);
 typedef void (*GenCSRWrite)(TCGv dest, TCGv_ptr env, TCGv src);
+typedef void (*GenCSRFunc)(void);
 
 typedef struct {
     int offset;
     int flags;
-    GenCSRRead readfn;
-    GenCSRWrite writefn;
+    GenCSRFunc readfn;
+    GenCSRFunc writefn;
 } CSRInfo;
 
 enum {
@@ -XXX,XX +XXX,XX @@ static bool set_csr_trans_func(unsigned int csr_num, GenCSRRead readfn,
         return false;
     }
 
-    csr->readfn = readfn;
-    csr->writefn = writefn;
+    csr->readfn = (GenCSRFunc)readfn;
+    csr->writefn = (GenCSRFunc)writefn;
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_csrrd(DisasContext *ctx, arg_csrrd *a)
 {
     TCGv dest;
     const CSRInfo *csr;
+    GenCSRRead readfn;
 
     if (check_plv(ctx)) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_csrrd(DisasContext *ctx, arg_csrrd *a)
     } else {
         check_csr_flags(ctx, csr, false);
         dest = gpr_dst(ctx, a->rd, EXT_NONE);
-        if (csr->readfn) {
-            csr->readfn(dest, tcg_env);
+        readfn = (GenCSRRead)csr->readfn;
+        if (readfn) {
+            readfn(dest, tcg_env);
         } else {
             tcg_gen_ld_tl(dest, tcg_env, csr->offset);
         }
@@ -XXX,XX +XXX,XX @@ static bool trans_csrwr(DisasContext *ctx, arg_csrwr *a)
 {
     TCGv dest, src1;
     const CSRInfo *csr;
+    GenCSRWrite writefn;
 
     if (check_plv(ctx)) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_csrwr(DisasContext *ctx, arg_csrwr *a)
         return false;
     }
     src1 = gpr_src(ctx, a->rd, EXT_NONE);
-    if (csr->writefn) {
+    writefn = (GenCSRWrite)csr->writefn;
+    if (writefn) {
         dest = gpr_dst(ctx, a->rd, EXT_NONE);
-        csr->writefn(dest, tcg_env, src1);
+        writefn(dest, tcg_env, src1);
     } else {
         dest = tcg_temp_new();
         tcg_gen_ld_tl(dest, tcg_env, csr->offset);
@@ -XXX,XX +XXX,XX @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxchg *a)
 {
     TCGv src1, mask, oldv, newv, temp;
     const CSRInfo *csr;
+    GenCSRWrite writefn;
 
     if (check_plv(ctx)) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxchg *a)
     tcg_gen_andc_tl(temp, oldv, mask);
     tcg_gen_or_tl(newv, newv, temp);
 
-    if (csr->writefn) {
-        csr->writefn(oldv, tcg_env, newv);
+    writefn = (GenCSRWrite)csr->writefn;
+    if (writefn) {
+        writefn(oldv, tcg_env, newv);
     } else {
         tcg_gen_st_tl(newv, tcg_env, csr->offset);
     }
-- 
2.43.5

Common header file csr.h is added here, it can be used by both
TCG mode and kvm mode.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/csr.h                        | 25 +++++++++++++++++++
 .../tcg/insn_trans/trans_privileged.c.inc     | 16 +-----------
 2 files changed, 26 insertions(+), 15 deletions(-)
 create mode 100644 target/loongarch/csr.h

diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/loongarch/csr.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2025 Loongson Technology Corporation Limited
+ */
+
+#ifndef TARGET_LOONGARCH_CSR_H
+#define TARGET_LOONGARCH_CSR_H
+
+#include "cpu-csr.h"
+
+typedef void (*GenCSRFunc)(void);
+enum {
+    CSRFL_READONLY = (1 << 0),
+    CSRFL_EXITTB   = (1 << 1),
+    CSRFL_IO       = (1 << 2),
+};
+
+typedef struct {
+    int offset;
+    int flags;
+    GenCSRFunc readfn;
+    GenCSRFunc writefn;
+} CSRInfo;
+
+#endif /* TARGET_LOONGARCH_CSR_H */
diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@
  * LoongArch translation routines for the privileged instructions.
  */
 
-#include "cpu-csr.h"
+#include "csr.h"
 
 #ifdef CONFIG_USER_ONLY
 
@@ -XXX,XX +XXX,XX @@ GEN_FALSE_TRANS(idle)
 
 typedef void (*GenCSRRead)(TCGv dest, TCGv_ptr env);
 typedef void (*GenCSRWrite)(TCGv dest, TCGv_ptr env, TCGv src);
-typedef void (*GenCSRFunc)(void);
-
-typedef struct {
-    int offset;
-    int flags;
-    GenCSRFunc readfn;
-    GenCSRFunc writefn;
-} CSRInfo;
-
-enum {
-    CSRFL_READONLY = (1 << 0),
-    CSRFL_EXITTB   = (1 << 1),
-    CSRFL_IO       = (1 << 2),
-};
 
 #define CSR_OFF_FUNCS(NAME, FL, RD, WR)                    \
     [LOONGARCH_CSR_##NAME] = {                             \
-- 
2.43.5

Common source file csr.c is added here, it can be used by both
TCG mode and kvm mode. The common code is removed from file
tcg/insn_trans/trans_privileged.c.inc to csrc.c

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/csr.c                        | 114 ++++++++++++++++++
 target/loongarch/csr.h                        |   1 +
 target/loongarch/meson.build                  |   1 +
 .../tcg/insn_trans/trans_privileged.c.inc     | 107 ----------------
 4 files changed, 116 insertions(+), 107 deletions(-)
 create mode 100644 target/loongarch/csr.c

diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/loongarch/csr.c
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2025 Loongson Technology Corporation Limited
+ */
+#include <stddef.h>
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "csr.h"
+
+#define CSR_OFF_FUNCS(NAME, FL, RD, WR)                    \
+    [LOONGARCH_CSR_##NAME] = {                             \
+        .offset = offsetof(CPULoongArchState, CSR_##NAME), \
+        .flags = FL, .readfn = RD, .writefn = WR           \
+    }
+
+#define CSR_OFF_ARRAY(NAME, N)                                \
+    [LOONGARCH_CSR_##NAME(N)] = {                             \
+        .offset = offsetof(CPULoongArchState, CSR_##NAME[N]), \
+        .flags = 0, .readfn = NULL, .writefn = NULL           \
+    }
+
+#define CSR_OFF_FLAGS(NAME, FL)   CSR_OFF_FUNCS(NAME, FL, NULL, NULL)
+#define CSR_OFF(NAME)             CSR_OFF_FLAGS(NAME, 0)
+
+static CSRInfo csr_info[] = {
+    CSR_OFF_FLAGS(CRMD, CSRFL_EXITTB),
+    CSR_OFF(PRMD),
+    CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB),
+    CSR_OFF_FLAGS(MISC, CSRFL_READONLY),
+    CSR_OFF(ECFG),
+    CSR_OFF_FLAGS(ESTAT, CSRFL_EXITTB),
+    CSR_OFF(ERA),
+    CSR_OFF(BADV),
+    CSR_OFF_FLAGS(BADI, CSRFL_READONLY),
+    CSR_OFF(EENTRY),
+    CSR_OFF(TLBIDX),
+    CSR_OFF(TLBEHI),
+    CSR_OFF(TLBELO0),
+    CSR_OFF(TLBELO1),
+    CSR_OFF_FLAGS(ASID, CSRFL_EXITTB),
+    CSR_OFF(PGDL),
+    CSR_OFF(PGDH),
+    CSR_OFF_FLAGS(PGD, CSRFL_READONLY),
+    CSR_OFF(PWCL),
+    CSR_OFF(PWCH),
+    CSR_OFF(STLBPS),
+    CSR_OFF(RVACFG),
+    CSR_OFF_FLAGS(CPUID, CSRFL_READONLY),
+    CSR_OFF_FLAGS(PRCFG1, CSRFL_READONLY),
+    CSR_OFF_FLAGS(PRCFG2, CSRFL_READONLY),
+    CSR_OFF_FLAGS(PRCFG3, CSRFL_READONLY),
+    CSR_OFF_ARRAY(SAVE, 0),
+    CSR_OFF_ARRAY(SAVE, 1),
+    CSR_OFF_ARRAY(SAVE, 2),
+    CSR_OFF_ARRAY(SAVE, 3),
+    CSR_OFF_ARRAY(SAVE, 4),
+    CSR_OFF_ARRAY(SAVE, 5),
+    CSR_OFF_ARRAY(SAVE, 6),
+    CSR_OFF_ARRAY(SAVE, 7),
+    CSR_OFF_ARRAY(SAVE, 8),
+    CSR_OFF_ARRAY(SAVE, 9),
+    CSR_OFF_ARRAY(SAVE, 10),
+    CSR_OFF_ARRAY(SAVE, 11),
+    CSR_OFF_ARRAY(SAVE, 12),
+    CSR_OFF_ARRAY(SAVE, 13),
+    CSR_OFF_ARRAY(SAVE, 14),
+    CSR_OFF_ARRAY(SAVE, 15),
+    CSR_OFF(TID),
+    CSR_OFF_FLAGS(TCFG, CSRFL_IO),
+    CSR_OFF_FLAGS(TVAL, CSRFL_READONLY | CSRFL_IO),
+    CSR_OFF(CNTC),
+    CSR_OFF_FLAGS(TICLR, CSRFL_IO),
+    CSR_OFF(LLBCTL),
+    CSR_OFF(IMPCTL1),
+    CSR_OFF(IMPCTL2),
+    CSR_OFF(TLBRENTRY),
+    CSR_OFF(TLBRBADV),
+    CSR_OFF(TLBRERA),
+    CSR_OFF(TLBRSAVE),
+    CSR_OFF(TLBRELO0),
+    CSR_OFF(TLBRELO1),
+    CSR_OFF(TLBREHI),
+    CSR_OFF(TLBRPRMD),
+    CSR_OFF(MERRCTL),
+    CSR_OFF(MERRINFO1),
+    CSR_OFF(MERRINFO2),
+    CSR_OFF(MERRENTRY),
+    CSR_OFF(MERRERA),
+    CSR_OFF(MERRSAVE),
+    CSR_OFF(CTAG),
+    CSR_OFF_ARRAY(DMW, 0),
+    CSR_OFF_ARRAY(DMW, 1),
+    CSR_OFF_ARRAY(DMW, 2),
+    CSR_OFF_ARRAY(DMW, 3),
+    CSR_OFF(DBG),
+    CSR_OFF(DERA),
+    CSR_OFF(DSAVE),
+};
+
+CSRInfo *get_csr(unsigned int csr_num)
+{
+    CSRInfo *csr;
+
+    if (csr_num >= ARRAY_SIZE(csr_info)) {
+        return NULL;
+    }
+
+    csr = &csr_info[csr_num];
+    if (csr->offset == 0) {
+        return NULL;
+    }
+
+    return csr;
+}
diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/csr.h
+++ b/target/loongarch/csr.h
@@ -XXX,XX +XXX,XX @@ typedef struct {
     GenCSRFunc writefn;
 } CSRInfo;
 
+CSRInfo *get_csr(unsigned int csr_num);
 #endif /* TARGET_LOONGARCH_CSR_H */
diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/meson.build
+++ b/target/loongarch/meson.build
@@ -XXX,XX +XXX,XX @@ loongarch_system_ss = ss.source_set()
 loongarch_system_ss.add(files(
   'arch_dump.c',
   'cpu_helper.c',
+  'csr.c',
   'loongarch-qmp-cmds.c',
   'machine.c',
 ))
diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ GEN_FALSE_TRANS(idle)
 typedef void (*GenCSRRead)(TCGv dest, TCGv_ptr env);
 typedef void (*GenCSRWrite)(TCGv dest, TCGv_ptr env, TCGv src);
 
-#define CSR_OFF_FUNCS(NAME, FL, RD, WR)                    \
-    [LOONGARCH_CSR_##NAME] = {                             \
-        .offset = offsetof(CPULoongArchState, CSR_##NAME), \
-        .flags = FL, .readfn = RD, .writefn = WR           \
-    }
-
-#define CSR_OFF_ARRAY(NAME, N)                                \
-    [LOONGARCH_CSR_##NAME(N)] = {                             \
-        .offset = offsetof(CPULoongArchState, CSR_##NAME[N]), \
-        .flags = 0, .readfn = NULL, .writefn = NULL           \
-    }
-
-#define CSR_OFF_FLAGS(NAME, FL) \
-    CSR_OFF_FUNCS(NAME, FL, NULL, NULL)
-
-#define CSR_OFF(NAME) \
-    CSR_OFF_FLAGS(NAME, 0)
-
-static CSRInfo csr_info[] = {
-    CSR_OFF_FLAGS(CRMD, CSRFL_EXITTB),
-    CSR_OFF(PRMD),
-    CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB),
-    CSR_OFF_FLAGS(MISC, CSRFL_READONLY),
-    CSR_OFF(ECFG),
-    CSR_OFF_FLAGS(ESTAT, CSRFL_EXITTB),
-    CSR_OFF(ERA),
-    CSR_OFF(BADV),
-    CSR_OFF_FLAGS(BADI, CSRFL_READONLY),
-    CSR_OFF(EENTRY),
-    CSR_OFF(TLBIDX),
-    CSR_OFF(TLBEHI),
-    CSR_OFF(TLBELO0),
-    CSR_OFF(TLBELO1),
-    CSR_OFF_FLAGS(ASID, CSRFL_EXITTB),
-    CSR_OFF(PGDL),
-    CSR_OFF(PGDH),
-    CSR_OFF_FLAGS(PGD, CSRFL_READONLY),
-    CSR_OFF(PWCL),
-    CSR_OFF(PWCH),
-    CSR_OFF(STLBPS),
-    CSR_OFF(RVACFG),
-    CSR_OFF_FLAGS(CPUID, CSRFL_READONLY),
-    CSR_OFF_FLAGS(PRCFG1, CSRFL_READONLY),
-    CSR_OFF_FLAGS(PRCFG2, CSRFL_READONLY),
-    CSR_OFF_FLAGS(PRCFG3, CSRFL_READONLY),
-    CSR_OFF_ARRAY(SAVE, 0),
-    CSR_OFF_ARRAY(SAVE, 1),
-    CSR_OFF_ARRAY(SAVE, 2),
-    CSR_OFF_ARRAY(SAVE, 3),
-    CSR_OFF_ARRAY(SAVE, 4),
-    CSR_OFF_ARRAY(SAVE, 5),
-    CSR_OFF_ARRAY(SAVE, 6),
-    CSR_OFF_ARRAY(SAVE, 7),
-    CSR_OFF_ARRAY(SAVE, 8),
-    CSR_OFF_ARRAY(SAVE, 9),
-    CSR_OFF_ARRAY(SAVE, 10),
-    CSR_OFF_ARRAY(SAVE, 11),
-    CSR_OFF_ARRAY(SAVE, 12),
-    CSR_OFF_ARRAY(SAVE, 13),
-    CSR_OFF_ARRAY(SAVE, 14),
-    CSR_OFF_ARRAY(SAVE, 15),
-    CSR_OFF(TID),
-    CSR_OFF_FLAGS(TCFG, CSRFL_IO),
-    CSR_OFF_FLAGS(TVAL, CSRFL_READONLY | CSRFL_IO),
-    CSR_OFF(CNTC),
-    CSR_OFF_FLAGS(TICLR, CSRFL_IO),
-    CSR_OFF(LLBCTL),
-    CSR_OFF(IMPCTL1),
-    CSR_OFF(IMPCTL2),
-    CSR_OFF(TLBRENTRY),
-    CSR_OFF(TLBRBADV),
-    CSR_OFF(TLBRERA),
-    CSR_OFF(TLBRSAVE),
-    CSR_OFF(TLBRELO0),
-    CSR_OFF(TLBRELO1),
-    CSR_OFF(TLBREHI),
-    CSR_OFF(TLBRPRMD),
-    CSR_OFF(MERRCTL),
-    CSR_OFF(MERRINFO1),
-    CSR_OFF(MERRINFO2),
-    CSR_OFF(MERRENTRY),
-    CSR_OFF(MERRERA),
-    CSR_OFF(MERRSAVE),
-    CSR_OFF(CTAG),
-    CSR_OFF_ARRAY(DMW, 0),
-    CSR_OFF_ARRAY(DMW, 1),
-    CSR_OFF_ARRAY(DMW, 2),
-    CSR_OFF_ARRAY(DMW, 3),
-    CSR_OFF(DBG),
-    CSR_OFF(DERA),
-    CSR_OFF(DSAVE),
-};
-
 static bool check_plv(DisasContext *ctx)
 {
     if (ctx->plv == MMU_PLV_USER) {
@@ -XXX,XX +XXX,XX @@ static bool check_plv(DisasContext *ctx)
     return false;
 }
 
-static CSRInfo *get_csr(unsigned csr_num)
-{
-    CSRInfo *csr;
-
-    if (csr_num >= ARRAY_SIZE(csr_info)) {
-        return NULL;
-    }
-    csr = &csr_info[csr_num];
-    if (csr->offset == 0) {
-        return NULL;
-    }
-    return csr;
-}
-
 static bool set_csr_trans_func(unsigned int csr_num, GenCSRRead readfn,
                                GenCSRWrite writefn)
 {
-- 
2.43.5

On LA464, some CSR registers are not used such as CSR_SAVE8 -
CSR_SAVE15, also CSR registers relative with MCE is not used now.

Flag CSRFL_UNUSED is added for these registers, so that it will
not dumped. In order to keep compatiblity, these CSR registers are
not removed since it is used in vmstate already.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/cpu.c | 30 +++++++++++++++++++++++++++++-
 target/loongarch/csr.c | 13 +++++++++++++
 target/loongarch/csr.h |  2 ++
 3 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 #include "internals.h"
 #include "fpu/softfloat-helpers.h"
-#include "cpu-csr.h"
+#include "csr.h"
 #ifndef CONFIG_USER_ONLY
 #include "system/reset.h"
 #endif
@@ -XXX,XX +XXX,XX @@ static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch)
     return MMU_DA_IDX;
 }
 
+static void loongarch_la464_init_csr(Object *obj)
+{
+#ifndef CONFIG_USER_ONLY
+    static bool initialized;
+    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+    CPULoongArchState *env = &cpu->env;
+    int i, num;
+
+    if (!initialized) {
+        initialized = true;
+        num = FIELD_EX64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM);
+        for (i = num; i < 16; i++) {
+            set_csr_flag(LOONGARCH_CSR_SAVE(i), CSRFL_UNUSED);
+        }
+        set_csr_flag(LOONGARCH_CSR_IMPCTL1, CSRFL_UNUSED);
+        set_csr_flag(LOONGARCH_CSR_IMPCTL2, CSRFL_UNUSED);
+        set_csr_flag(LOONGARCH_CSR_MERRCTL, CSRFL_UNUSED);
+        set_csr_flag(LOONGARCH_CSR_MERRINFO1, CSRFL_UNUSED);
+        set_csr_flag(LOONGARCH_CSR_MERRINFO2, CSRFL_UNUSED);
+        set_csr_flag(LOONGARCH_CSR_MERRENTRY, CSRFL_UNUSED);
+        set_csr_flag(LOONGARCH_CSR_MERRERA, CSRFL_UNUSED);
+        set_csr_flag(LOONGARCH_CSR_MERRSAVE, CSRFL_UNUSED);
+        set_csr_flag(LOONGARCH_CSR_CTAG, CSRFL_UNUSED);
+    }
+#endif
+}
+
 static void loongarch_la464_initfn(Object *obj)
 {
     LoongArchCPU *cpu = LOONGARCH_CPU(obj);
@@ -XXX,XX +XXX,XX @@ static void loongarch_la464_initfn(Object *obj)
     env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7);
     env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8);
 
+    loongarch_la464_init_csr(obj);
     loongarch_cpu_post_init(obj);
 }
 
diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/csr.c
+++ b/target/loongarch/csr.c
@@ -XXX,XX +XXX,XX @@ CSRInfo *get_csr(unsigned int csr_num)
 
     return csr;
 }
+
+bool set_csr_flag(unsigned int csr_num, int flag)
+{
+    CSRInfo *csr;
+
+    csr = get_csr(csr_num);
+    if (!csr) {
+        return false;
+    }
+
+    csr->flags |= flag;
+    return true;
+}
diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/csr.h
+++ b/target/loongarch/csr.h
@@ -XXX,XX +XXX,XX @@ enum {
     CSRFL_READONLY = (1 << 0),
     CSRFL_EXITTB   = (1 << 1),
     CSRFL_IO       = (1 << 2),
+    CSRFL_UNUSED   = (1 << 3),
 };
 
 typedef struct {
@@ -XXX,XX +XXX,XX @@ typedef struct {
 } CSRInfo;
 
 CSRInfo *get_csr(unsigned int csr_num);
+bool set_csr_flag(unsigned int csr_num, int flag);
 #endif /* TARGET_LOONGARCH_CSR_H */
-- 
2.43.5

CSR registers is import system control registers, it had better
dump all CSR registers when VM is running in system mode.

Here is dump output example of CSR registers:
 CSR000: CRMD   b4               PRMD   4                EUEN   0                MISC   0
 CSR004: ECFG   71c1c            ESTAT  0                ERA    9000000002c31300 BADV   12022c0e0
 CSR008: BADI   2b0000
 CSR012: EENTRY 90000000046b0000
 CSR016: TLBIDX ffffffff8e000228 TLBEHI 120228000        TLBELO0 400000016f19001f TLBELO1 400000016f1a401f
 CSR024: ASID   a0004            PGDL   90000001016f0000 PGDH   9000000004680000 PGD    0
 CSR028: PWCL   5e56e            PWCH   2e4              STLBPS e                RVACFG 0
 CSR032: CPUID  0                PRCFG1 72f8             PRCFG2 3ffff000         PRCFG3 8073f2
 CSR048: SAVE0  0                SAVE1  af9c             SAVE2  12010d6a8        SAVE3  8300000
 CSR052: SAVE4  0                SAVE5  0                SAVE6  0                SAVE7  0
 CSR064: TID    0                TCFG   8f0ca15          TVAL   4cefd8b          CNTC   fffffffffe688aaa
 CSR068: TICLR  0
 CSR096: LLBCTL 1
 CSR136: TLBRENTRY 46ba000       TLBRBADV ffff8000130d81e2 TLBRERA 9000000003585cb8 TLBRSAVE ffff8000130d81e0
 CSR140: TLBRELO0 1fe00043       TLBRELO1 40             TLBREHI ffff8000130d800e TLBRPRMD 0
 CSR384: DMW0   8000000000000001 DMW1   9000000000000011 DMW2   0                DMW3   0

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/cpu.c | 66 ++++++++++++++++++++++++++++++++----------
 target/loongarch/csr.c |  2 ++
 target/loongarch/csr.h |  1 +
 3 files changed, 53 insertions(+), 16 deletions(-)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -XXX,XX +XXX,XX @@ static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model)
     return oc;
 }
 
+static void loongarch_cpu_dump_csr(CPUState *cs, FILE *f)
+{
+#ifndef CONFIG_USER_ONLY
+    CPULoongArchState *env = cpu_env(cs);
+    CSRInfo *csr_info;
+    int64_t *addr;
+    int i, j, len, col = 0;
+
+    qemu_fprintf(f, "\n");
+
+    /* Dump all generic CSR register */
+    for (i = 0; i < LOONGARCH_CSR_DBG; i++) {
+        csr_info = get_csr(i);
+        if (!csr_info || (csr_info->flags & CSRFL_UNUSED)) {
+            if (i == (col + 3)) {
+                qemu_fprintf(f, "\n");
+            }
+
+            continue;
+        }
+
+        if ((i >  (col + 3)) || (i == col)) {
+            col = i & ~3;
+            qemu_fprintf(f, " CSR%03d:", col);
+        }
+
+        addr = (void *)env + csr_info->offset;
+        qemu_fprintf(f, " %s ", csr_info->name);
+        len = strlen(csr_info->name);
+        for (; len < 6; len++) {
+            qemu_fprintf(f, " ");
+        }
+
+        qemu_fprintf(f, "%" PRIx64, *addr);
+        j = find_last_bit((void *)addr, BITS_PER_LONG) & (BITS_PER_LONG - 1);
+        len += j / 4 + 1;
+        for (; len < 22; len++) {
+                qemu_fprintf(f, " ");
+        }
+
+        if (i == (col + 3)) {
+            qemu_fprintf(f, "\n");
+        }
+    }
+    qemu_fprintf(f, "\n");
+#endif
+}
+
 static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 {
     CPULoongArchState *env = cpu_env(cs);
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
         }
     }
 
-    qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD);
-    qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD);
-    qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN);
-    qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT);
-    qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA);
-    qemu_fprintf(f, "BADV=%016" PRIx64 "\n", env->CSR_BADV);
-    qemu_fprintf(f, "BADI=%016" PRIx64 "\n", env->CSR_BADI);
-    qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY);
-    qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 ","
-                 " PRCFG3=%016" PRIx64 "\n",
-                 env->CSR_PRCFG1, env->CSR_PRCFG2, env->CSR_PRCFG3);
-    qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY);
-    qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV);
-    qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA);
-    qemu_fprintf(f, "TCFG=%016" PRIx64 "\n", env->CSR_TCFG);
-    qemu_fprintf(f, "TVAL=%016" PRIx64 "\n", env->CSR_TVAL);
+    /* csr */
+    loongarch_cpu_dump_csr(cs, f);
 
     /* fpr */
     if (flags & CPU_DUMP_FPU) {
diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/csr.c
+++ b/target/loongarch/csr.c
@@ -XXX,XX +XXX,XX @@
 
 #define CSR_OFF_FUNCS(NAME, FL, RD, WR)                    \
     [LOONGARCH_CSR_##NAME] = {                             \
+        .name   = (stringify(NAME)),                       \
         .offset = offsetof(CPULoongArchState, CSR_##NAME), \
         .flags = FL, .readfn = RD, .writefn = WR           \
     }
 
 #define CSR_OFF_ARRAY(NAME, N)                                \
     [LOONGARCH_CSR_##NAME(N)] = {                             \
+        .name   = (stringify(NAME##N)),                       \
         .offset = offsetof(CPULoongArchState, CSR_##NAME[N]), \
         .flags = 0, .readfn = NULL, .writefn = NULL           \
     }
diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/csr.h
+++ b/target/loongarch/csr.h
@@ -XXX,XX +XXX,XX @@ enum {
 };
 
 typedef struct {
+    const char *name;
     int offset;
     int flags;
     GenCSRFunc readfn;
-- 
2.43.5