[v1] target/riscv: Support RISC-V privilege 1.13 spec

[PATCH 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32

Posted by Fea.Wang 1 year, 9 months ago

Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH
and HEDELEGH for exception codes 32-47 for reserving and exception codes
48-63 for custom use. Add the CSR number though the implementation is
just reading zero and writing ignore. Besides, for accessing HEDELEGH, it
should be controlled by mstateen0 'P1P13' bit.

Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/cpu_bits.h |  2 ++
 target/riscv/csr.c      | 31 +++++++++++++++++++++++++++++++
 2 files changed, 33 insertions(+)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 28bd3fb0b4..f888025c59 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -156,6 +156,8 @@
 
 /* 32-bit only */
 #define CSR_MSTATUSH        0x310
+#define CSR_MEDELEGH        0x312
+#define CSR_HEDELEGH        0x612
 
 /* Machine Trap Handling */
 #define CSR_MSCRATCH        0x340
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d844ce770e..4d7313f456 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3227,6 +3227,33 @@ static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+static RISCVException read_hedelegh(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
+{
+    RISCVException ret;
+    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    /* Reserved, now read zero */
+    *val = 0;
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_hedelegh(CPURISCVState *env, int csrno,
+                                    target_ulong val)
+{
+    RISCVException ret;
+    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    /* Reserved, now write ignore */
+    return RISCV_EXCP_NONE;
+}
+
 static RISCVException rmw_hvien64(CPURISCVState *env, int csrno,
                                     uint64_t *ret_val,
                                     uint64_t new_val, uint64_t wr_mask)
@@ -4674,6 +4701,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
 
     [CSR_MSTATUSH]    = { "mstatush",   any32, read_mstatush,
                           write_mstatush                                   },
+    [CSR_MEDELEGH]    = { "medelegh",   any32, read_zero, write_ignore,
+                          .min_priv_ver = PRIV_VERSION_1_13_0              },
+    [CSR_HEDELEGH]    = { "hedelegh",   any32, read_hedelegh, write_hedelegh,
+                          .min_priv_ver = PRIV_VERSION_1_13_0              },
 
     /* Machine Trap Handling */
     [CSR_MSCRATCH] = { "mscratch", any,  read_mscratch, write_mscratch,
-- 
2.34.1

Re: [PATCH 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32

Posted by LIU Zhiwei 1 year, 9 months ago

On 2024/5/10 14:58, Fea.Wang wrote:
> Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH
> and HEDELEGH for exception codes 32-47 for reserving and exception codes
> 48-63 for custom use. Add the CSR number though the implementation is
> just reading zero and writing ignore. Besides, for accessing HEDELEGH, it
> should be controlled by mstateen0 'P1P13' bit.
>
> Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
>   target/riscv/cpu_bits.h |  2 ++
>   target/riscv/csr.c      | 31 +++++++++++++++++++++++++++++++
>   2 files changed, 33 insertions(+)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 28bd3fb0b4..f888025c59 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -156,6 +156,8 @@
>   
>   /* 32-bit only */
>   #define CSR_MSTATUSH        0x310
> +#define CSR_MEDELEGH        0x312
> +#define CSR_HEDELEGH        0x612
>   
>   /* Machine Trap Handling */
>   #define CSR_MSCRATCH        0x340
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index d844ce770e..4d7313f456 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3227,6 +3227,33 @@ static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
>       return RISCV_EXCP_NONE;
>   }
>   
> +static RISCVException read_hedelegh(CPURISCVState *env, int csrno,
> +                                   target_ulong *val)
> +{
> +    RISCVException ret;
> +    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13);
> +    if (ret != RISCV_EXCP_NONE) {
> +        return ret;
> +    }
> +
> +    /* Reserved, now read zero */
> +    *val = 0;
> +    return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_hedelegh(CPURISCVState *env, int csrno,
> +                                    target_ulong val)
> +{
> +    RISCVException ret;
> +    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13);
> +    if (ret != RISCV_EXCP_NONE) {
> +        return ret;
> +    }
> +
> +    /* Reserved, now write ignore */
> +    return RISCV_EXCP_NONE;
> +}
> +
>   static RISCVException rmw_hvien64(CPURISCVState *env, int csrno,
>                                       uint64_t *ret_val,
>                                       uint64_t new_val, uint64_t wr_mask)
> @@ -4674,6 +4701,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>   
>       [CSR_MSTATUSH]    = { "mstatush",   any32, read_mstatush,
>                             write_mstatush                                   },
> +    [CSR_MEDELEGH]    = { "medelegh",   any32, read_zero, write_ignore,
> +                          .min_priv_ver = PRIV_VERSION_1_13_0              },
> +    [CSR_HEDELEGH]    = { "hedelegh",   any32, read_hedelegh, write_hedelegh,

Using hmode32 instead of any32.

Otherwise,

Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

> +                          .min_priv_ver = PRIV_VERSION_1_13_0              },
>   
>       /* Machine Trap Handling */
>       [CSR_MSCRATCH] = { "mscratch", any,  read_mscratch, write_mscratch,

Re: [PATCH 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32

Posted by Fea Wang 1 year, 9 months ago

OK, I will correct it in the patch v2. Thank you.

Sincerely,
Fea

LIU Zhiwei <zhiwei_liu@linux.alibaba.com> 於 2024年5月13日 週一 上午10:49寫道：

>
> On 2024/5/10 14:58, Fea.Wang wrote:
> > Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH
> > and HEDELEGH for exception codes 32-47 for reserving and exception codes
> > 48-63 for custom use. Add the CSR number though the implementation is
> > just reading zero and writing ignore. Besides, for accessing HEDELEGH, it
> > should be controlled by mstateen0 'P1P13' bit.
> >
> > Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> > Reviewed-by: Frank Chang <frank.chang@sifive.com>
> > ---
> >   target/riscv/cpu_bits.h |  2 ++
> >   target/riscv/csr.c      | 31 +++++++++++++++++++++++++++++++
> >   2 files changed, 33 insertions(+)
> >
> > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > index 28bd3fb0b4..f888025c59 100644
> > --- a/target/riscv/cpu_bits.h
> > +++ b/target/riscv/cpu_bits.h
> > @@ -156,6 +156,8 @@
> >
> >   /* 32-bit only */
> >   #define CSR_MSTATUSH        0x310
> > +#define CSR_MEDELEGH        0x312
> > +#define CSR_HEDELEGH        0x612
> >
> >   /* Machine Trap Handling */
> >   #define CSR_MSCRATCH        0x340
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index d844ce770e..4d7313f456 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -3227,6 +3227,33 @@ static RISCVException write_hedeleg(CPURISCVState
> *env, int csrno,
> >       return RISCV_EXCP_NONE;
> >   }
> >
> > +static RISCVException read_hedelegh(CPURISCVState *env, int csrno,
> > +                                   target_ulong *val)
> > +{
> > +    RISCVException ret;
> > +    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13);
> > +    if (ret != RISCV_EXCP_NONE) {
> > +        return ret;
> > +    }
> > +
> > +    /* Reserved, now read zero */
> > +    *val = 0;
> > +    return RISCV_EXCP_NONE;
> > +}
> > +
> > +static RISCVException write_hedelegh(CPURISCVState *env, int csrno,
> > +                                    target_ulong val)
> > +{
> > +    RISCVException ret;
> > +    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13);
> > +    if (ret != RISCV_EXCP_NONE) {
> > +        return ret;
> > +    }
> > +
> > +    /* Reserved, now write ignore */
> > +    return RISCV_EXCP_NONE;
> > +}
> > +
> >   static RISCVException rmw_hvien64(CPURISCVState *env, int csrno,
> >                                       uint64_t *ret_val,
> >                                       uint64_t new_val, uint64_t wr_mask)
> > @@ -4674,6 +4701,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> >
> >       [CSR_MSTATUSH]    = { "mstatush",   any32, read_mstatush,
> >                             write_mstatush
>      },
> > +    [CSR_MEDELEGH]    = { "medelegh",   any32, read_zero, write_ignore,
> > +                          .min_priv_ver = PRIV_VERSION_1_13_0
>     },
> > +    [CSR_HEDELEGH]    = { "hedelegh",   any32, read_hedelegh,
> write_hedelegh,
>
> Using hmode32 instead of any32.
>
> Otherwise,
>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
>
> > +                          .min_priv_ver = PRIV_VERSION_1_13_0
>     },
> >
> >       /* Machine Trap Handling */
> >       [CSR_MSCRATCH] = { "mscratch", any,  read_mscratch, write_mscratch,
>

[PATCH 1/5] target/riscv: Reuse the conversion function of priv_spec and string
[PATCH 2/5] target/riscv: Support the version for ss1p13
[PATCH 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0
[PATCH 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32
[PATCH 5/5] target/riscv: Reserve exception codes for sw-check and hw-err