[v1] target/riscv: Support RISC-V privilege 1.13 spec

[PATCH 1/5] target/riscv: Reuse the conversion function of priv_spec and string

Posted by Fea.Wang 1 year, 9 months ago

From: Jim Shu <jim.shu@sifive.com>

Public the conversion function of priv_spec and string in cpu.h, so that
tcg-cpu.c could also use it.

Signed-off-by: Jim Shu <jim.shu@sifive.com>
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/cpu.c         |  4 ++--
 target/riscv/cpu.h         |  3 +++
 target/riscv/tcg/tcg-cpu.c | 13 +++++--------
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a74f0eb29c..b6b48e5620 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1769,7 +1769,7 @@ static const PropertyInfo prop_pmp = {
     .set = prop_pmp_set,
 };
 
-static int priv_spec_from_str(const char *priv_spec_str)
+int priv_spec_from_str(const char *priv_spec_str)
 {
     int priv_version = -1;
 
@@ -1784,7 +1784,7 @@ static int priv_spec_from_str(const char *priv_spec_str)
     return priv_version;
 }
 
-static const char *priv_spec_to_str(int priv_version)
+const char *priv_spec_to_str(int priv_version)
 {
     switch (priv_version) {
     case PRIV_VERSION_1_10_0:
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index e0dd1828b5..7696102697 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -829,4 +829,7 @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
+const char *priv_spec_to_str(int priv_version);
+int priv_spec_from_str(const char *priv_spec_str);
+
 #endif /* RISCV_CPU_H */
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 4ebebebe09..faa8de9b83 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -76,16 +76,13 @@ static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit,
 
 static const char *cpu_priv_ver_to_str(int priv_ver)
 {
-    switch (priv_ver) {
-    case PRIV_VERSION_1_10_0:
-        return "v1.10.0";
-    case PRIV_VERSION_1_11_0:
-        return "v1.11.0";
-    case PRIV_VERSION_1_12_0:
-        return "v1.12.0";
+    const char *priv_spec_str = priv_spec_to_str(priv_ver);
+
+    if (priv_spec_str == NULL) {
+        g_assert_not_reached();
     }
 
-    g_assert_not_reached();
+    return priv_spec_str;
 }
 
 static void riscv_cpu_synchronize_from_tb(CPUState *cs,
-- 
2.34.1

Re: [PATCH 1/5] target/riscv: Reuse the conversion function of priv_spec and string

Posted by LIU Zhiwei 1 year, 9 months ago

On 2024/5/10 14:58, Fea.Wang wrote:
> From: Jim Shu <jim.shu@sifive.com>
>
> Public the conversion function of priv_spec and string in cpu.h, so that
> tcg-cpu.c could also use it.
>
> Signed-off-by: Jim Shu <jim.shu@sifive.com>
> Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
>   target/riscv/cpu.c         |  4 ++--
>   target/riscv/cpu.h         |  3 +++
>   target/riscv/tcg/tcg-cpu.c | 13 +++++--------
>   3 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index a74f0eb29c..b6b48e5620 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1769,7 +1769,7 @@ static const PropertyInfo prop_pmp = {
>       .set = prop_pmp_set,
>   };
>   
> -static int priv_spec_from_str(const char *priv_spec_str)
> +int priv_spec_from_str(const char *priv_spec_str)
>   {
>       int priv_version = -1;
>   
> @@ -1784,7 +1784,7 @@ static int priv_spec_from_str(const char *priv_spec_str)
>       return priv_version;
>   }
>   
> -static const char *priv_spec_to_str(int priv_version)
> +const char *priv_spec_to_str(int priv_version)
>   {
>       switch (priv_version) {
>       case PRIV_VERSION_1_10_0:
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index e0dd1828b5..7696102697 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -829,4 +829,7 @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
>   uint8_t satp_mode_max_from_map(uint32_t map);
>   const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
>   
> +const char *priv_spec_to_str(int priv_version);
> +int priv_spec_from_str(const char *priv_spec_str);
> +
>   #endif /* RISCV_CPU_H */
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 4ebebebe09..faa8de9b83 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -76,16 +76,13 @@ static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit,
>   
>   static const char *cpu_priv_ver_to_str(int priv_ver)
>   {
> -    switch (priv_ver) {
> -    case PRIV_VERSION_1_10_0:
> -        return "v1.10.0";
> -    case PRIV_VERSION_1_11_0:
> -        return "v1.11.0";
> -    case PRIV_VERSION_1_12_0:
> -        return "v1.12.0";
> +    const char *priv_spec_str = priv_spec_to_str(priv_ver);
> +
> +    if (priv_spec_str == NULL) {
> +        g_assert_not_reached();
>       }

g_assert(priv_spec_str != NULL) or g_assert(priv_spec_str)

Otherwise,

Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Zhiwei

>   
> -    g_assert_not_reached();
> +    return priv_spec_str;
>   }
>   
>   static void riscv_cpu_synchronize_from_tb(CPUState *cs,

Re: [PATCH 1/5] target/riscv: Reuse the conversion function of priv_spec and string

Posted by Fea Wang 1 year, 9 months ago

Thank you, I will correct it in the patch v2.

Sincerely,
Fea

LIU Zhiwei <zhiwei_liu@linux.alibaba.com> 於 2024年5月13日 週一 上午10:55寫道：

>
> On 2024/5/10 14:58, Fea.Wang wrote:
> > From: Jim Shu <jim.shu@sifive.com>
> >
> > Public the conversion function of priv_spec and string in cpu.h, so that
> > tcg-cpu.c could also use it.
> >
> > Signed-off-by: Jim Shu <jim.shu@sifive.com>
> > Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> > Reviewed-by: Frank Chang <frank.chang@sifive.com>
> > ---
> >   target/riscv/cpu.c         |  4 ++--
> >   target/riscv/cpu.h         |  3 +++
> >   target/riscv/tcg/tcg-cpu.c | 13 +++++--------
> >   3 files changed, 10 insertions(+), 10 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index a74f0eb29c..b6b48e5620 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -1769,7 +1769,7 @@ static const PropertyInfo prop_pmp = {
> >       .set = prop_pmp_set,
> >   };
> >
> > -static int priv_spec_from_str(const char *priv_spec_str)
> > +int priv_spec_from_str(const char *priv_spec_str)
> >   {
> >       int priv_version = -1;
> >
> > @@ -1784,7 +1784,7 @@ static int priv_spec_from_str(const char
> *priv_spec_str)
> >       return priv_version;
> >   }
> >
> > -static const char *priv_spec_to_str(int priv_version)
> > +const char *priv_spec_to_str(int priv_version)
> >   {
> >       switch (priv_version) {
> >       case PRIV_VERSION_1_10_0:
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index e0dd1828b5..7696102697 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -829,4 +829,7 @@ target_ulong riscv_new_csr_seed(target_ulong
> new_value,
> >   uint8_t satp_mode_max_from_map(uint32_t map);
> >   const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
> >
> > +const char *priv_spec_to_str(int priv_version);
> > +int priv_spec_from_str(const char *priv_spec_str);
> > +
> >   #endif /* RISCV_CPU_H */
> > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> > index 4ebebebe09..faa8de9b83 100644
> > --- a/target/riscv/tcg/tcg-cpu.c
> > +++ b/target/riscv/tcg/tcg-cpu.c
> > @@ -76,16 +76,13 @@ static void riscv_cpu_write_misa_bit(RISCVCPU *cpu,
> uint32_t bit,
> >
> >   static const char *cpu_priv_ver_to_str(int priv_ver)
> >   {
> > -    switch (priv_ver) {
> > -    case PRIV_VERSION_1_10_0:
> > -        return "v1.10.0";
> > -    case PRIV_VERSION_1_11_0:
> > -        return "v1.11.0";
> > -    case PRIV_VERSION_1_12_0:
> > -        return "v1.12.0";
> > +    const char *priv_spec_str = priv_spec_to_str(priv_ver);
> > +
> > +    if (priv_spec_str == NULL) {
> > +        g_assert_not_reached();
> >       }
>
> g_assert(priv_spec_str != NULL) or g_assert(priv_spec_str)
>
> Otherwise,
>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
>
> Zhiwei
>
> >
> > -    g_assert_not_reached();
> > +    return priv_spec_str;
> >   }
> >
> >   static void riscv_cpu_synchronize_from_tb(CPUState *cs,
>

Re: [PATCH 1/5] target/riscv: Reuse the conversion function of priv_spec and string

Posted by liwei 1 year, 9 months ago

On 2024/5/10 14:58, Fea.Wang wrote:
> From: Jim Shu <jim.shu@sifive.com>
>
> Public the conversion function of priv_spec and string in cpu.h, so that
> tcg-cpu.c could also use it.
>
> Signed-off-by: Jim Shu <jim.shu@sifive.com>
> Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
>   target/riscv/cpu.c         |  4 ++--
>   target/riscv/cpu.h         |  3 +++
>   target/riscv/tcg/tcg-cpu.c | 13 +++++--------
>   3 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index a74f0eb29c..b6b48e5620 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1769,7 +1769,7 @@ static const PropertyInfo prop_pmp = {
>       .set = prop_pmp_set,
>   };
>   
> -static int priv_spec_from_str(const char *priv_spec_str)
> +int priv_spec_from_str(const char *priv_spec_str)

This change seems unnecessary in this patch.

Regards,

Weiwei Li

>   {
>       int priv_version = -1;
>   
> @@ -1784,7 +1784,7 @@ static int priv_spec_from_str(const char *priv_spec_str)
>       return priv_version;
>   }
>   
> -static const char *priv_spec_to_str(int priv_version)
> +const char *priv_spec_to_str(int priv_version)
>   {
>       switch (priv_version) {
>       case PRIV_VERSION_1_10_0:
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index e0dd1828b5..7696102697 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -829,4 +829,7 @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
>   uint8_t satp_mode_max_from_map(uint32_t map);
>   const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
>   
> +const char *priv_spec_to_str(int priv_version);
> +int priv_spec_from_str(const char *priv_spec_str);
> +
>   #endif /* RISCV_CPU_H */
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 4ebebebe09..faa8de9b83 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -76,16 +76,13 @@ static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit,
>   
>   static const char *cpu_priv_ver_to_str(int priv_ver)
>   {
> -    switch (priv_ver) {
> -    case PRIV_VERSION_1_10_0:
> -        return "v1.10.0";
> -    case PRIV_VERSION_1_11_0:
> -        return "v1.11.0";
> -    case PRIV_VERSION_1_12_0:
> -        return "v1.12.0";
> +    const char *priv_spec_str = priv_spec_to_str(priv_ver);
> +
> +    if (priv_spec_str == NULL) {
> +        g_assert_not_reached();
>       }
>   
> -    g_assert_not_reached();
> +    return priv_spec_str;
>   }
>   
>   static void riscv_cpu_synchronize_from_tb(CPUState *cs,

[PATCH 1/5] target/riscv: Reuse the conversion function of priv_spec and string
[PATCH 2/5] target/riscv: Support the version for ss1p13
[PATCH 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0
[PATCH 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32
[PATCH 5/5] target/riscv: Reserve exception codes for sw-check and hw-err