Fix fp16 checking in vector fp widen/narrow instructions

[PATCH v2 0/4] Fix fp16 checking in vector fp widen/narrow instructions

Max Chou posted 4 patches 1 year, 10 months ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20240322092600.1198921-1-max.chou@sifive.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/insn_trans/trans_rvv.c.inc | 42 ++++++++++++++++---------
1 file changed, 28 insertions(+), 14 deletions(-)

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[PATCH v2 0/4] Fix fp16 checking in vector fp widen/narrow instructions

Posted by Max Chou 1 year, 10 months ago

When SEW is 16, we need to check whether the Zvfhmin is enabled for the
single width operator for vector floating point widen/narrow
instructions. 

The commits in this patchset fix the single width operator checking and
remove the redudant SEW checking for vector floating point widen/narrow
instructions.

v2:
  Group patchset and rebase to the riscv-to-apply.next branch(commit 385e575)


Thanks to those who have already reviewed:

    Daniel Henrique Barboza dbarboza@ventanamicro.com
        [PATCH] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
        [PATCH] target/riscv: rvv: Check single width operator for vector fp widen instructions
        [PATCH] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
        [PATCH] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions


Max Chou (4):
  target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and
    vfncvt.f.f.w instructions
  target/riscv: rvv: Check single width operator for vector fp widen
    instructions
  target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
  target/riscv: rvv: Remove redudant SEW checking for vector fp
    narrow/widen instructions

 target/riscv/insn_trans/trans_rvv.c.inc | 42 ++++++++++++++++---------
 1 file changed, 28 insertions(+), 14 deletions(-)

-- 
2.34.1

Re: [PATCH v2 0/4] Fix fp16 checking in vector fp widen/narrow instructions

Posted by Alistair Francis 1 year, 9 months ago

On Fri, Mar 22, 2024 at 7:33 PM Max Chou <max.chou@sifive.com> wrote:
>
> When SEW is 16, we need to check whether the Zvfhmin is enabled for the
> single width operator for vector floating point widen/narrow
> instructions.
>
> The commits in this patchset fix the single width operator checking and
> remove the redudant SEW checking for vector floating point widen/narrow
> instructions.
>
> v2:
>   Group patchset and rebase to the riscv-to-apply.next branch(commit 385e575)
>
>
> Thanks to those who have already reviewed:
>
>     Daniel Henrique Barboza dbarboza@ventanamicro.com
>         [PATCH] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
>         [PATCH] target/riscv: rvv: Check single width operator for vector fp widen instructions
>         [PATCH] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
>         [PATCH] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
>
>
> Max Chou (4):
>   target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and
>     vfncvt.f.f.w instructions
>   target/riscv: rvv: Check single width operator for vector fp widen
>     instructions
>   target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
>   target/riscv: rvv: Remove redudant SEW checking for vector fp
>     narrow/widen instructions

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/insn_trans/trans_rvv.c.inc | 42 ++++++++++++++++---------
>  1 file changed, 28 insertions(+), 14 deletions(-)
>
> --
> 2.34.1
>
>