Add a method to reset the value of LSI Source-ID.
Mask off LSI source-id based on number of interrupts in the big/small PHB.
Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com>
---
hw/pci-host/pnv_phb4.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index f48750ee54..8fbaf6512e 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -489,6 +489,7 @@ static void pnv_phb4_update_xsrc(PnvPHB4 *phb)
lsi_base = GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3]);
lsi_base <<= 3;
+ lsi_base &= (xsrc->nr_irqs - 1);
/* TODO: handle reset values of PHB_LSI_SRC_ID */
if (!lsi_base) {
@@ -1966,6 +1967,12 @@ static void pnv_phb4_ro_mask_init(PnvPHB4 *phb)
/* TODO: Add more RO-masks as regs are implemented in the model */
}
+static void pnv_phb4_fund_A_reset(PnvPHB4 *phb)
+{
+ phb->regs[PHB_LSI_SOURCE_ID >> 3] = PPC_BITMASK(4, 12);
+ pnv_phb4_update_xsrc(phb);
+}
+
static void pnv_phb4_err_reg_reset(PnvPHB4 *phb)
{
STICKY_RST(PHB_ERR_STATUS, 0, PPC_BITMASK(0, 33));
@@ -2023,6 +2030,7 @@ static void pnv_phb4_reset(void *dev)
pnv_phb4_cfg_core_reset(phb);
pnv_phb4_pbl_core_reset(phb);
+ pnv_phb4_fund_A_reset(phb);
pnv_phb4_err_reg_reset(phb);
pnv_phb4_pcie_stack_reg_reset(phb);
pnv_phb4_regb_err_reg_reset(phb);
@@ -2102,8 +2110,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
return;
}
- pnv_phb4_update_xsrc(phb);
-
phb->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);
pnv_phb4_xscom_realize(phb);
--
2.39.3
On 3/21/24 11:04, Saif Abrar wrote:
> Add a method to reset the value of LSI Source-ID.
> Mask off LSI source-id based on number of interrupts in the big/small PHB.
Looks ok.
> Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com>
> ---
> hw/pci-host/pnv_phb4.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
> index f48750ee54..8fbaf6512e 100644
> --- a/hw/pci-host/pnv_phb4.c
> +++ b/hw/pci-host/pnv_phb4.c
> @@ -489,6 +489,7 @@ static void pnv_phb4_update_xsrc(PnvPHB4 *phb)
>
> lsi_base = GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3]);
> lsi_base <<= 3;
> + lsi_base &= (xsrc->nr_irqs - 1);
>
> /* TODO: handle reset values of PHB_LSI_SRC_ID */
> if (!lsi_base) {
> @@ -1966,6 +1967,12 @@ static void pnv_phb4_ro_mask_init(PnvPHB4 *phb)
> /* TODO: Add more RO-masks as regs are implemented in the model */
> }
>
> +static void pnv_phb4_fund_A_reset(PnvPHB4 *phb)
What is fund_A ?
> +{
> + phb->regs[PHB_LSI_SOURCE_ID >> 3] = PPC_BITMASK(4, 12);
Is this mask the default value for HW ?
Thanks,
C.
> + pnv_phb4_update_xsrc(phb);
> +}
> +
> static void pnv_phb4_err_reg_reset(PnvPHB4 *phb)
> {
> STICKY_RST(PHB_ERR_STATUS, 0, PPC_BITMASK(0, 33));
> @@ -2023,6 +2030,7 @@ static void pnv_phb4_reset(void *dev)
> pnv_phb4_cfg_core_reset(phb);
> pnv_phb4_pbl_core_reset(phb);
>
> + pnv_phb4_fund_A_reset(phb);
> pnv_phb4_err_reg_reset(phb);
> pnv_phb4_pcie_stack_reg_reset(phb);
> pnv_phb4_regb_err_reg_reset(phb);
> @@ -2102,8 +2110,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
> return;
> }
>
> - pnv_phb4_update_xsrc(phb);
> -
> phb->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);
>
> pnv_phb4_xscom_realize(phb);
Hello Cedric,
> }
> +static void pnv_phb4_fund_A_reset(PnvPHB4 *phb)
>
> What is fund_A ?
I used 'fund_A' as an abbreviation to "Fundamental Register Set A".
Please let know if you suggest another abbreviation to name this method.
>> +{
>> + phb->regs[PHB_LSI_SOURCE_ID >> 3] = PPC_BITMASK(4, 12);
>
> Is this mask the default value for HW ?
Yes, the spec defines the bits[04:12] of LSI Source ID having reset
value: 0x1FF
Regards,
Saif
On 25-03-2024 07:04 pm, Cédric Le Goater wrote:
> On 3/21/24 11:04, Saif Abrar wrote:
>> Add a method to reset the value of LSI Source-ID.
>> Mask off LSI source-id based on number of interrupts in the big/small
>> PHB.
>
> Looks ok.
>
>
>> Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com>
>> ---
>> hw/pci-host/pnv_phb4.c | 10 ++++++++--
>> 1 file changed, 8 insertions(+), 2 deletions(-)
>>
>> diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
>> index f48750ee54..8fbaf6512e 100644
>> --- a/hw/pci-host/pnv_phb4.c
>> +++ b/hw/pci-host/pnv_phb4.c
>> @@ -489,6 +489,7 @@ static void pnv_phb4_update_xsrc(PnvPHB4 *phb)
>> lsi_base = GETFIELD(PHB_LSI_SRC_ID,
>> phb->regs[PHB_LSI_SOURCE_ID >> 3]);
>> lsi_base <<= 3;
>> + lsi_base &= (xsrc->nr_irqs - 1);
>> /* TODO: handle reset values of PHB_LSI_SRC_ID */
>> if (!lsi_base) {
>> @@ -1966,6 +1967,12 @@ static void pnv_phb4_ro_mask_init(PnvPHB4 *phb)
>> /* TODO: Add more RO-masks as regs are implemented in the model */
>> }
>> +static void pnv_phb4_fund_A_reset(PnvPHB4 *phb)
>
> What is fund_A ?
>
>> +{
>> + phb->regs[PHB_LSI_SOURCE_ID >> 3] = PPC_BITMASK(4, 12);
>
> Is this mask the default value for HW ?
>
>
> Thanks,
>
> C.
>
>
>> + pnv_phb4_update_xsrc(phb);
>> +}
>> +
>> static void pnv_phb4_err_reg_reset(PnvPHB4 *phb)
>> {
>> STICKY_RST(PHB_ERR_STATUS, 0, PPC_BITMASK(0, 33));
>> @@ -2023,6 +2030,7 @@ static void pnv_phb4_reset(void *dev)
>> pnv_phb4_cfg_core_reset(phb);
>> pnv_phb4_pbl_core_reset(phb);
>> + pnv_phb4_fund_A_reset(phb);
>> pnv_phb4_err_reg_reset(phb);
>> pnv_phb4_pcie_stack_reg_reset(phb);
>> pnv_phb4_regb_err_reg_reset(phb);
>> @@ -2102,8 +2110,6 @@ static void pnv_phb4_realize(DeviceState *dev,
>> Error **errp)
>> return;
>> }
>> - pnv_phb4_update_xsrc(phb);
>> -
>> phb->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc,
>> xsrc->nr_irqs);
>> pnv_phb4_xscom_realize(phb);
>
Hello Cedric,
> }
> +static void pnv_phb4_fund_A_reset(PnvPHB4 *phb)
>
> What is fund_A ?
I used 'fund_A' as an abbreviation to "Fundamental Register Set A".
Please let know if you suggest another abbreviation to name this method.
>> +{
>> + phb->regs[PHB_LSI_SOURCE_ID >> 3] = PPC_BITMASK(4, 12);
>
> Is this mask the default value for HW ?
Yes, the spec defines the bits[04:12] of LSI Source ID having reset
value: 0x1FF
Regards,
Saif
On 25-03-2024 07:04 pm, Cédric Le Goater wrote:
> On 3/21/24 11:04, Saif Abrar wrote:
>> Add a method to reset the value of LSI Source-ID.
>> Mask off LSI source-id based on number of interrupts in the big/small
>> PHB.
>
> Looks ok.
>
>
>> Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com>
>> ---
>> hw/pci-host/pnv_phb4.c | 10 ++++++++--
>> 1 file changed, 8 insertions(+), 2 deletions(-)
>>
>> diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
>> index f48750ee54..8fbaf6512e 100644
>> --- a/hw/pci-host/pnv_phb4.c
>> +++ b/hw/pci-host/pnv_phb4.c
>> @@ -489,6 +489,7 @@ static void pnv_phb4_update_xsrc(PnvPHB4 *phb)
>> lsi_base = GETFIELD(PHB_LSI_SRC_ID,
>> phb->regs[PHB_LSI_SOURCE_ID >> 3]);
>> lsi_base <<= 3;
>> + lsi_base &= (xsrc->nr_irqs - 1);
>> /* TODO: handle reset values of PHB_LSI_SRC_ID */
>> if (!lsi_base) {
>> @@ -1966,6 +1967,12 @@ static void pnv_phb4_ro_mask_init(PnvPHB4 *phb)
>> /* TODO: Add more RO-masks as regs are implemented in the model */
>> }
>> +static void pnv_phb4_fund_A_reset(PnvPHB4 *phb)
>
> What is fund_A ?
>
>> +{
>> + phb->regs[PHB_LSI_SOURCE_ID >> 3] = PPC_BITMASK(4, 12);
>
> Is this mask the default value for HW ?
>
>
> Thanks,
>
> C.
>
>
>> + pnv_phb4_update_xsrc(phb);
>> +}
>> +
>> static void pnv_phb4_err_reg_reset(PnvPHB4 *phb)
>> {
>> STICKY_RST(PHB_ERR_STATUS, 0, PPC_BITMASK(0, 33));
>> @@ -2023,6 +2030,7 @@ static void pnv_phb4_reset(void *dev)
>> pnv_phb4_cfg_core_reset(phb);
>> pnv_phb4_pbl_core_reset(phb);
>> + pnv_phb4_fund_A_reset(phb);
>> pnv_phb4_err_reg_reset(phb);
>> pnv_phb4_pcie_stack_reg_reset(phb);
>> pnv_phb4_regb_err_reg_reset(phb);
>> @@ -2102,8 +2110,6 @@ static void pnv_phb4_realize(DeviceState *dev,
>> Error **errp)
>> return;
>> }
>> - pnv_phb4_update_xsrc(phb);
>> -
>> phb->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc,
>> xsrc->nr_irqs);
>> pnv_phb4_xscom_realize(phb);
>
On 3/27/24 10:59, Saif Abrar wrote:
> Hello Cedric,
>
>> }
>> +static void pnv_phb4_fund_A_reset(PnvPHB4 *phb)
>>
>> What is fund_A ?
>
> I used 'fund_A' as an abbreviation to "Fundamental Register Set A".
>
> Please let know if you suggest another abbreviation to name this method.
pnv_phb4_reset_xsrc may be ?
Thanks,
C.
>
>>> +{
>>> + phb->regs[PHB_LSI_SOURCE_ID >> 3] = PPC_BITMASK(4, 12);
>>
>> Is this mask the default value for HW ?
> Yes, the spec defines the bits[04:12] of LSI Source ID having reset value: 0x1FF
>
>
> Regards,
>
> Saif
>
>
> On 25-03-2024 07:04 pm, Cédric Le Goater wrote:
>> On 3/21/24 11:04, Saif Abrar wrote:
>>> Add a method to reset the value of LSI Source-ID.
>>> Mask off LSI source-id based on number of interrupts in the big/small PHB.
>>
>> Looks ok.
>>
>>
>>> Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com>
>>> ---
>>> hw/pci-host/pnv_phb4.c | 10 ++++++++--
>>> 1 file changed, 8 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
>>> index f48750ee54..8fbaf6512e 100644
>>> --- a/hw/pci-host/pnv_phb4.c
>>> +++ b/hw/pci-host/pnv_phb4.c
>>> @@ -489,6 +489,7 @@ static void pnv_phb4_update_xsrc(PnvPHB4 *phb)
>>> lsi_base = GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3]);
>>> lsi_base <<= 3;
>>> + lsi_base &= (xsrc->nr_irqs - 1);
>>> /* TODO: handle reset values of PHB_LSI_SRC_ID */
>>> if (!lsi_base) {
>>> @@ -1966,6 +1967,12 @@ static void pnv_phb4_ro_mask_init(PnvPHB4 *phb)
>>> /* TODO: Add more RO-masks as regs are implemented in the model */
>>> }
>>> +static void pnv_phb4_fund_A_reset(PnvPHB4 *phb)
>>
>> What is fund_A ?
>>
>>> +{
>>> + phb->regs[PHB_LSI_SOURCE_ID >> 3] = PPC_BITMASK(4, 12);
>>
>> Is this mask the default value for HW ?
>>
>>
>> Thanks,
>>
>> C.
>>
>>
>>> + pnv_phb4_update_xsrc(phb);
>>> +}
>>> +
>>> static void pnv_phb4_err_reg_reset(PnvPHB4 *phb)
>>> {
>>> STICKY_RST(PHB_ERR_STATUS, 0, PPC_BITMASK(0, 33));
>>> @@ -2023,6 +2030,7 @@ static void pnv_phb4_reset(void *dev)
>>> pnv_phb4_cfg_core_reset(phb);
>>> pnv_phb4_pbl_core_reset(phb);
>>> + pnv_phb4_fund_A_reset(phb);
>>> pnv_phb4_err_reg_reset(phb);
>>> pnv_phb4_pcie_stack_reg_reset(phb);
>>> pnv_phb4_regb_err_reg_reset(phb);
>>> @@ -2102,8 +2110,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
>>> return;
>>> }
>>> - pnv_phb4_update_xsrc(phb);
>>> -
>>> phb->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);
>>> pnv_phb4_xscom_realize(phb);
>>
© 2016 - 2026 Red Hat, Inc.