pnv/phb4: Update PHB4 to the latest spec PH5

[PATCH 09/10] hw/pci: Set write-mask bits for PCIE Link-Control-2 register

Posted by Saif Abrar 1 year, 10 months ago

PHB updates the register PCIE Link-Control-2.
Set the write-mask bits for TLS, ENTER_COMP, TX_MARGIN,
HASD, MOD_COMP, COMP_SOS and COMP_P_DE.

Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com>
---
 hw/pci/pcie.c                             | 6 ++++++
 include/standard-headers/linux/pci_regs.h | 3 +++
 2 files changed, 9 insertions(+)

diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 4b2f0805c6..e3081f6b84 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -212,6 +212,12 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset,
 
     pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB);
 
+    pci_set_word(dev->wmask + pos + PCI_EXP_LNKCTL2,
+            PCI_EXP_LNKCTL2_TLS | PCI_EXP_LNKCTL2_ENTER_COMP |
+            PCI_EXP_LNKCTL2_TX_MARGIN | PCI_EXP_LNKCTL2_HASD |
+            PCI_EXP_LNKCTL2_MOD_COMP | PCI_EXP_LNKCTL2_COMP_SOS |
+            PCI_EXP_LNKCTL2_COMP_P_DE);
+
     if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) {
         /* read-only to behave like a 'NULL' Extended Capability Header */
         pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0);
diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h
index a39193213f..f743defe91 100644
--- a/include/standard-headers/linux/pci_regs.h
+++ b/include/standard-headers/linux/pci_regs.h
@@ -694,6 +694,9 @@
 #define  PCI_EXP_LNKCTL2_ENTER_COMP	0x0010 /* Enter Compliance */
 #define  PCI_EXP_LNKCTL2_TX_MARGIN	0x0380 /* Transmit Margin */
 #define  PCI_EXP_LNKCTL2_HASD		0x0020 /* HW Autonomous Speed Disable */
+#define  PCI_EXP_LNKCTL2_MOD_COMP	0x0400 /* Enter Modified Compliance */
+#define  PCI_EXP_LNKCTL2_COMP_SOS	0x0800 /* Compliance SOS */
+#define  PCI_EXP_LNKCTL2_COMP_P_DE	0xF000 /* Compliance Preset/De-emphasis */
 #define PCI_EXP_LNKSTA2		0x32	/* Link Status 2 */
 #define  PCI_EXP_LNKSTA2_FLIT		0x0400 /* Flit Mode Status */
 #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2	0x32	/* end of v2 EPs w/ link */
-- 
2.39.3

Re: [PATCH 09/10] hw/pci: Set write-mask bits for PCIE Link-Control-2 register

Posted by Cédric Le Goater 1 year, 10 months ago

On 3/21/24 11:04, Saif Abrar wrote:
> PHB updates the register PCIE Link-Control-2.
> Set the write-mask bits for TLS, ENTER_COMP, TX_MARGIN,
> HASD, MOD_COMP, COMP_SOS and COMP_P_DE.


You should resend this patch independently of the PowerNV PHB changes.


Thanks,

C.



> Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com>
> ---
>   hw/pci/pcie.c                             | 6 ++++++
>   include/standard-headers/linux/pci_regs.h | 3 +++
>   2 files changed, 9 insertions(+)
> 
> diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
> index 4b2f0805c6..e3081f6b84 100644
> --- a/hw/pci/pcie.c
> +++ b/hw/pci/pcie.c
> @@ -212,6 +212,12 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset,
>   
>       pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB);
>   
> +    pci_set_word(dev->wmask + pos + PCI_EXP_LNKCTL2,
> +            PCI_EXP_LNKCTL2_TLS | PCI_EXP_LNKCTL2_ENTER_COMP |
> +            PCI_EXP_LNKCTL2_TX_MARGIN | PCI_EXP_LNKCTL2_HASD |
> +            PCI_EXP_LNKCTL2_MOD_COMP | PCI_EXP_LNKCTL2_COMP_SOS |
> +            PCI_EXP_LNKCTL2_COMP_P_DE);
> +
>       if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) {
>           /* read-only to behave like a 'NULL' Extended Capability Header */
>           pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0);
> diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h
> index a39193213f..f743defe91 100644
> --- a/include/standard-headers/linux/pci_regs.h
> +++ b/include/standard-headers/linux/pci_regs.h
> @@ -694,6 +694,9 @@
>   #define  PCI_EXP_LNKCTL2_ENTER_COMP	0x0010 /* Enter Compliance */
>   #define  PCI_EXP_LNKCTL2_TX_MARGIN	0x0380 /* Transmit Margin */
>   #define  PCI_EXP_LNKCTL2_HASD		0x0020 /* HW Autonomous Speed Disable */
> +#define  PCI_EXP_LNKCTL2_MOD_COMP	0x0400 /* Enter Modified Compliance */
> +#define  PCI_EXP_LNKCTL2_COMP_SOS	0x0800 /* Compliance SOS */
> +#define  PCI_EXP_LNKCTL2_COMP_P_DE	0xF000 /* Compliance Preset/De-emphasis */
>   #define PCI_EXP_LNKSTA2		0x32	/* Link Status 2 */
>   #define  PCI_EXP_LNKSTA2_FLIT		0x0400 /* Flit Mode Status */
>   #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2	0x32	/* end of v2 EPs w/ link */

Re: [PATCH 09/10] hw/pci: Set write-mask bits for PCIE Link-Control-2 register

Posted by Cornelia Huck 1 year, 10 months ago

On Mon, Mar 25 2024, Cédric Le Goater <clg@kaod.org> wrote:

> On 3/21/24 11:04, Saif Abrar wrote:
>> PHB updates the register PCIE Link-Control-2.
>> Set the write-mask bits for TLS, ENTER_COMP, TX_MARGIN,
>> HASD, MOD_COMP, COMP_SOS and COMP_P_DE.
>
>
> You should resend this patch independently of the PowerNV PHB changes.
>
>
> Thanks,
>
> C.
>
>
>
>> Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com>
>> ---
>>   hw/pci/pcie.c                             | 6 ++++++
>>   include/standard-headers/linux/pci_regs.h | 3 +++
>>   2 files changed, 9 insertions(+)

This patch also needs to be split: the code under standard-headers/ is
updated via a Linux headers update, which should either be a full update
against a released kernel version (can be -rc), or a placeholder patch
if the changes have not yet been merged.