target/microblaze: Sprint housekeeping

[RFC PATCH-for-9.1 8/8] target/microblaze: Widen $ear to 64-bit

Posted by Philippe Mathieu-Daudé 1 year, 10 months ago

The Exception Address Register is 64-bit wide.
User emulation only access the 32 lower bits.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/microblaze/cpu.h       | 2 +-
 linux-user/elfload.c          | 2 +-
 target/microblaze/gdbstub.c   | 2 +-
 target/microblaze/translate.c | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index c3e2aba0ec..a9f93b37b7 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -251,7 +251,7 @@ struct CPUArchState {
     uint32_t pc;
     uint32_t msr;    /* All bits of MSR except MSR[C] and MSR[CC] */
     uint32_t msr_c;  /* MSR[C], in low bit; other bits must be 0 */
-    target_ulong ear;
+    uint64_t ear;
     uint32_t esr;
     uint32_t fsr;
     uint32_t btr;
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 60cf55b36c..4612aef95a 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1498,7 +1498,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUMBState *env
     (*regs)[pos++] = tswapreg(env->pc);
     (*regs)[pos++] = tswapreg(mb_cpu_read_msr(env));
     (*regs)[pos++] = 0;
-    (*regs)[pos++] = tswapreg(env->ear);
+    (*regs)[pos++] = tswapreg((uint32_t)env->ear);
     (*regs)[pos++] = 0;
     (*regs)[pos++] = tswapreg(env->esr);
 }
diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c
index 09d74e164d..147d20c3e4 100644
--- a/target/microblaze/gdbstub.c
+++ b/target/microblaze/gdbstub.c
@@ -63,7 +63,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
         val = mb_cpu_read_msr(env);
         break;
     case GDB_EAR:
-        val = env->ear;
+        val = (uint32_t)env->ear;
         break;
     case GDB_ESR:
         val = env->esr;
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 493850c544..19b180501f 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1835,7 +1835,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
     }
 
     qemu_fprintf(f, "\nesr=0x%04x fsr=0x%02x btr=0x%08x edr=0x%x\n"
-                 "ear=0x" TARGET_FMT_lx " slr=0x%x shr=0x%x\n",
+                 "ear=0x%" PRIx64 " slr=0x%x shr=0x%x\n",
                  env->esr, env->fsr, env->btr, env->edr,
                  env->ear, env->slr, env->shr);
 
-- 
2.41.0

Re: [RFC PATCH-for-9.1 8/8] target/microblaze: Widen $ear to 64-bit

Posted by Edgar E. Iglesias 1 year, 10 months ago

On Tue, Mar 19, 2024 at 07:28:55AM +0100, Philippe Mathieu-Daudé wrote:
> The Exception Address Register is 64-bit wide.
> User emulation only access the 32 lower bits.


Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>

> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/microblaze/cpu.h       | 2 +-
>  linux-user/elfload.c          | 2 +-
>  target/microblaze/gdbstub.c   | 2 +-
>  target/microblaze/translate.c | 2 +-
>  4 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index c3e2aba0ec..a9f93b37b7 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -251,7 +251,7 @@ struct CPUArchState {
>      uint32_t pc;
>      uint32_t msr;    /* All bits of MSR except MSR[C] and MSR[CC] */
>      uint32_t msr_c;  /* MSR[C], in low bit; other bits must be 0 */
> -    target_ulong ear;
> +    uint64_t ear;
>      uint32_t esr;
>      uint32_t fsr;
>      uint32_t btr;
> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> index 60cf55b36c..4612aef95a 100644
> --- a/linux-user/elfload.c
> +++ b/linux-user/elfload.c
> @@ -1498,7 +1498,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUMBState *env
>      (*regs)[pos++] = tswapreg(env->pc);
>      (*regs)[pos++] = tswapreg(mb_cpu_read_msr(env));
>      (*regs)[pos++] = 0;
> -    (*regs)[pos++] = tswapreg(env->ear);
> +    (*regs)[pos++] = tswapreg((uint32_t)env->ear);
>      (*regs)[pos++] = 0;
>      (*regs)[pos++] = tswapreg(env->esr);
>  }
> diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c
> index 09d74e164d..147d20c3e4 100644
> --- a/target/microblaze/gdbstub.c
> +++ b/target/microblaze/gdbstub.c
> @@ -63,7 +63,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
>          val = mb_cpu_read_msr(env);
>          break;
>      case GDB_EAR:
> -        val = env->ear;
> +        val = (uint32_t)env->ear;
>          break;
>      case GDB_ESR:
>          val = env->esr;
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 493850c544..19b180501f 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -1835,7 +1835,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>      }
>  
>      qemu_fprintf(f, "\nesr=0x%04x fsr=0x%02x btr=0x%08x edr=0x%x\n"
> -                 "ear=0x" TARGET_FMT_lx " slr=0x%x shr=0x%x\n",
> +                 "ear=0x%" PRIx64 " slr=0x%x shr=0x%x\n",
>                   env->esr, env->fsr, env->btr, env->edr,
>                   env->ear, env->slr, env->shr);
>  
> -- 
> 2.41.0
>

Re: [RFC PATCH-for-9.1 8/8] target/microblaze: Widen $ear to 64-bit

Posted by Anton Johansson via 1 year, 10 months ago

On 19/03/24, Philippe Mathieu-Daudé wrote:
> The Exception Address Register is 64-bit wide.
> User emulation only access the 32 lower bits.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/microblaze/cpu.h       | 2 +-
>  linux-user/elfload.c          | 2 +-
>  target/microblaze/gdbstub.c   | 2 +-
>  target/microblaze/translate.c | 2 +-
>  4 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index c3e2aba0ec..a9f93b37b7 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -251,7 +251,7 @@ struct CPUArchState {
>      uint32_t pc;
>      uint32_t msr;    /* All bits of MSR except MSR[C] and MSR[CC] */
>      uint32_t msr_c;  /* MSR[C], in low bit; other bits must be 0 */
> -    target_ulong ear;
> +    uint64_t ear;
>      uint32_t esr;
>      uint32_t fsr;
>      uint32_t btr;
> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> index 60cf55b36c..4612aef95a 100644
> --- a/linux-user/elfload.c
> +++ b/linux-user/elfload.c
> @@ -1498,7 +1498,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUMBState *env
>      (*regs)[pos++] = tswapreg(env->pc);
>      (*regs)[pos++] = tswapreg(mb_cpu_read_msr(env));
>      (*regs)[pos++] = 0;
> -    (*regs)[pos++] = tswapreg(env->ear);
> +    (*regs)[pos++] = tswapreg((uint32_t)env->ear);
As far as I can tell env->ear is never written to from TCG so we 
shouldn't have any problems w. endian mismatch between guest/host,
right?

Anyway,

Reviewed-by: Anton Johansson <anjo@rev.ng>