MMU helpers are only used during system emulation,
move them to sys_helper.c.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/microblaze/op_helper.c | 48 ----------------------------------
target/microblaze/sys_helper.c | 47 +++++++++++++++++++++++++++++++++
2 files changed, 47 insertions(+), 48 deletions(-)
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
index f6378030b7..45dbed4aaa 100644
--- a/target/microblaze/op_helper.c
+++ b/target/microblaze/op_helper.c
@@ -381,51 +381,3 @@ void helper_stackprot(CPUMBState *env, target_ulong addr)
cpu_loop_exit_restore(cs, GETPC());
}
}
-
-#if !defined(CONFIG_USER_ONLY)
-/* Writes/reads to the MMU's special regs end up here. */
-uint32_t helper_mmu_read(CPUMBState *env, uint32_t ext, uint32_t rn)
-{
- return mmu_read(env, ext, rn);
-}
-
-void helper_mmu_write(CPUMBState *env, uint32_t ext, uint32_t rn, uint32_t v)
-{
- mmu_write(env, ext, rn, v);
-}
-
-void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
- unsigned size, MMUAccessType access_type,
- int mmu_idx, MemTxAttrs attrs,
- MemTxResult response, uintptr_t retaddr)
-{
- MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
- CPUMBState *env = &cpu->env;
-
- qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx
- " physaddr 0x" HWADDR_FMT_plx " size %d access type %s\n",
- addr, physaddr, size,
- access_type == MMU_INST_FETCH ? "INST_FETCH" :
- (access_type == MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_STORE"));
-
- if (!(env->msr & MSR_EE)) {
- return;
- }
-
- if (access_type == MMU_INST_FETCH) {
- if (!cpu->cfg.iopb_bus_exception) {
- return;
- }
- env->esr = ESR_EC_INSN_BUS;
- } else {
- if (!cpu->cfg.dopb_bus_exception) {
- return;
- }
- env->esr = ESR_EC_DATA_BUS;
- }
-
- env->ear = addr;
- cs->exception_index = EXCP_HW_EXCP;
- cpu_loop_exit_restore(cs, retaddr);
-}
-#endif
diff --git a/target/microblaze/sys_helper.c b/target/microblaze/sys_helper.c
index 5180500354..7531f95ca7 100644
--- a/target/microblaze/sys_helper.c
+++ b/target/microblaze/sys_helper.c
@@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
#include "qemu/host-utils.h"
#include "exec/log.h"
@@ -292,3 +293,49 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
cs->exception_index = EXCP_HW_EXCP;
cpu_loop_exit(cs);
}
+
+/* Writes/reads to the MMU's special regs end up here. */
+uint32_t helper_mmu_read(CPUMBState *env, uint32_t ext, uint32_t rn)
+{
+ return mmu_read(env, ext, rn);
+}
+
+void helper_mmu_write(CPUMBState *env, uint32_t ext, uint32_t rn, uint32_t v)
+{
+ mmu_write(env, ext, rn, v);
+}
+
+void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
+ unsigned size, MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr)
+{
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+ CPUMBState *env = &cpu->env;
+
+ qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx
+ " physaddr 0x" HWADDR_FMT_plx " size %d access type %s\n",
+ addr, physaddr, size,
+ access_type == MMU_INST_FETCH ? "INST_FETCH" :
+ (access_type == MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_STORE"));
+
+ if (!(env->msr & MSR_EE)) {
+ return;
+ }
+
+ if (access_type == MMU_INST_FETCH) {
+ if (!cpu->cfg.iopb_bus_exception) {
+ return;
+ }
+ env->esr = ESR_EC_INSN_BUS;
+ } else {
+ if (!cpu->cfg.dopb_bus_exception) {
+ return;
+ }
+ env->esr = ESR_EC_DATA_BUS;
+ }
+
+ env->ear = addr;
+ cs->exception_index = EXCP_HW_EXCP;
+ cpu_loop_exit_restore(cs, retaddr);
+}
--
2.41.0
On Tue, Mar 19, 2024 at 07:28:54AM +0100, Philippe Mathieu-Daudé wrote:
> MMU helpers are only used during system emulation,
> move them to sys_helper.c.
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/microblaze/op_helper.c | 48 ----------------------------------
> target/microblaze/sys_helper.c | 47 +++++++++++++++++++++++++++++++++
> 2 files changed, 47 insertions(+), 48 deletions(-)
>
> diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
> index f6378030b7..45dbed4aaa 100644
> --- a/target/microblaze/op_helper.c
> +++ b/target/microblaze/op_helper.c
> @@ -381,51 +381,3 @@ void helper_stackprot(CPUMBState *env, target_ulong addr)
> cpu_loop_exit_restore(cs, GETPC());
> }
> }
> -
> -#if !defined(CONFIG_USER_ONLY)
> -/* Writes/reads to the MMU's special regs end up here. */
> -uint32_t helper_mmu_read(CPUMBState *env, uint32_t ext, uint32_t rn)
> -{
> - return mmu_read(env, ext, rn);
> -}
> -
> -void helper_mmu_write(CPUMBState *env, uint32_t ext, uint32_t rn, uint32_t v)
> -{
> - mmu_write(env, ext, rn, v);
> -}
> -
> -void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
> - unsigned size, MMUAccessType access_type,
> - int mmu_idx, MemTxAttrs attrs,
> - MemTxResult response, uintptr_t retaddr)
> -{
> - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
> - CPUMBState *env = &cpu->env;
> -
> - qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx
> - " physaddr 0x" HWADDR_FMT_plx " size %d access type %s\n",
> - addr, physaddr, size,
> - access_type == MMU_INST_FETCH ? "INST_FETCH" :
> - (access_type == MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_STORE"));
> -
> - if (!(env->msr & MSR_EE)) {
> - return;
> - }
> -
> - if (access_type == MMU_INST_FETCH) {
> - if (!cpu->cfg.iopb_bus_exception) {
> - return;
> - }
> - env->esr = ESR_EC_INSN_BUS;
> - } else {
> - if (!cpu->cfg.dopb_bus_exception) {
> - return;
> - }
> - env->esr = ESR_EC_DATA_BUS;
> - }
> -
> - env->ear = addr;
> - cs->exception_index = EXCP_HW_EXCP;
> - cpu_loop_exit_restore(cs, retaddr);
> -}
> -#endif
> diff --git a/target/microblaze/sys_helper.c b/target/microblaze/sys_helper.c
> index 5180500354..7531f95ca7 100644
> --- a/target/microblaze/sys_helper.c
> +++ b/target/microblaze/sys_helper.c
> @@ -21,6 +21,7 @@
> #include "qemu/osdep.h"
> #include "cpu.h"
> #include "exec/exec-all.h"
> +#include "exec/helper-proto.h"
> #include "qemu/host-utils.h"
> #include "exec/log.h"
>
> @@ -292,3 +293,49 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> cs->exception_index = EXCP_HW_EXCP;
> cpu_loop_exit(cs);
> }
> +
> +/* Writes/reads to the MMU's special regs end up here. */
> +uint32_t helper_mmu_read(CPUMBState *env, uint32_t ext, uint32_t rn)
> +{
> + return mmu_read(env, ext, rn);
> +}
> +
> +void helper_mmu_write(CPUMBState *env, uint32_t ext, uint32_t rn, uint32_t v)
> +{
> + mmu_write(env, ext, rn, v);
> +}
> +
> +void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
> + unsigned size, MMUAccessType access_type,
> + int mmu_idx, MemTxAttrs attrs,
> + MemTxResult response, uintptr_t retaddr)
> +{
> + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
> + CPUMBState *env = &cpu->env;
> +
> + qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx
> + " physaddr 0x" HWADDR_FMT_plx " size %d access type %s\n",
> + addr, physaddr, size,
> + access_type == MMU_INST_FETCH ? "INST_FETCH" :
> + (access_type == MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_STORE"));
> +
> + if (!(env->msr & MSR_EE)) {
> + return;
> + }
> +
> + if (access_type == MMU_INST_FETCH) {
> + if (!cpu->cfg.iopb_bus_exception) {
> + return;
> + }
> + env->esr = ESR_EC_INSN_BUS;
> + } else {
> + if (!cpu->cfg.dopb_bus_exception) {
> + return;
> + }
> + env->esr = ESR_EC_DATA_BUS;
> + }
> +
> + env->ear = addr;
> + cs->exception_index = EXCP_HW_EXCP;
> + cpu_loop_exit_restore(cs, retaddr);
> +}
> --
> 2.41.0
>
On 19/03/24, Philippe Mathieu-Daudé wrote:
> MMU helpers are only used during system emulation,
> move them to sys_helper.c.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/microblaze/op_helper.c | 48 ----------------------------------
> target/microblaze/sys_helper.c | 47 +++++++++++++++++++++++++++++++++
> 2 files changed, 47 insertions(+), 48 deletions(-)
>
> diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
> index f6378030b7..45dbed4aaa 100644
> --- a/target/microblaze/op_helper.c
> +++ b/target/microblaze/op_helper.c
> @@ -381,51 +381,3 @@ void helper_stackprot(CPUMBState *env, target_ulong addr)
> cpu_loop_exit_restore(cs, GETPC());
> }
> }
> -
> -#if !defined(CONFIG_USER_ONLY)
> -/* Writes/reads to the MMU's special regs end up here. */
> -uint32_t helper_mmu_read(CPUMBState *env, uint32_t ext, uint32_t rn)
> -{
> - return mmu_read(env, ext, rn);
> -}
> -
> -void helper_mmu_write(CPUMBState *env, uint32_t ext, uint32_t rn, uint32_t v)
> -{
> - mmu_write(env, ext, rn, v);
> -}
> -
> -void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
> - unsigned size, MMUAccessType access_type,
> - int mmu_idx, MemTxAttrs attrs,
> - MemTxResult response, uintptr_t retaddr)
> -{
> - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
> - CPUMBState *env = &cpu->env;
> -
> - qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx
> - " physaddr 0x" HWADDR_FMT_plx " size %d access type %s\n",
> - addr, physaddr, size,
> - access_type == MMU_INST_FETCH ? "INST_FETCH" :
> - (access_type == MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_STORE"));
> -
> - if (!(env->msr & MSR_EE)) {
> - return;
> - }
> -
> - if (access_type == MMU_INST_FETCH) {
> - if (!cpu->cfg.iopb_bus_exception) {
> - return;
> - }
> - env->esr = ESR_EC_INSN_BUS;
> - } else {
> - if (!cpu->cfg.dopb_bus_exception) {
> - return;
> - }
> - env->esr = ESR_EC_DATA_BUS;
> - }
> -
> - env->ear = addr;
> - cs->exception_index = EXCP_HW_EXCP;
> - cpu_loop_exit_restore(cs, retaddr);
> -}
> -#endif
> diff --git a/target/microblaze/sys_helper.c b/target/microblaze/sys_helper.c
> index 5180500354..7531f95ca7 100644
> --- a/target/microblaze/sys_helper.c
> +++ b/target/microblaze/sys_helper.c
> @@ -21,6 +21,7 @@
> #include "qemu/osdep.h"
> #include "cpu.h"
> #include "exec/exec-all.h"
> +#include "exec/helper-proto.h"
> #include "qemu/host-utils.h"
> #include "exec/log.h"
>
> @@ -292,3 +293,49 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> cs->exception_index = EXCP_HW_EXCP;
> cpu_loop_exit(cs);
> }
> +
> +/* Writes/reads to the MMU's special regs end up here. */
> +uint32_t helper_mmu_read(CPUMBState *env, uint32_t ext, uint32_t rn)
> +{
> + return mmu_read(env, ext, rn);
> +}
> +
> +void helper_mmu_write(CPUMBState *env, uint32_t ext, uint32_t rn, uint32_t v)
> +{
> + mmu_write(env, ext, rn, v);
> +}
> +
> +void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
> + unsigned size, MMUAccessType access_type,
> + int mmu_idx, MemTxAttrs attrs,
> + MemTxResult response, uintptr_t retaddr)
> +{
> + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
> + CPUMBState *env = &cpu->env;
> +
> + qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx
> + " physaddr 0x" HWADDR_FMT_plx " size %d access type %s\n",
> + addr, physaddr, size,
> + access_type == MMU_INST_FETCH ? "INST_FETCH" :
> + (access_type == MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_STORE"));
> +
> + if (!(env->msr & MSR_EE)) {
> + return;
> + }
> +
> + if (access_type == MMU_INST_FETCH) {
> + if (!cpu->cfg.iopb_bus_exception) {
> + return;
> + }
> + env->esr = ESR_EC_INSN_BUS;
> + } else {
> + if (!cpu->cfg.dopb_bus_exception) {
> + return;
> + }
> + env->esr = ESR_EC_DATA_BUS;
> + }
> +
> + env->ear = addr;
> + cs->exception_index = EXCP_HW_EXCP;
> + cpu_loop_exit_restore(cs, retaddr);
> +}
> --
> 2.41.0
>
Reviewed-by: Anton Johansson <anjo@rev.ng>
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